ANALOG DEVICES AD7995

4-Channel, 12-/10-/8-Bit ADC with 2 I C-Compatible Interface in 8-Lead SOT-23 AD7991/AD7995/AD7999 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD 12-/10-/8-bit ADCs with fast conversion time: 1 μs typical 4 analog input channels/3 analog input channels with reference input V IN0 Specified for V of 2.7 V to 5.5 V DD 12-/10-/8-BIT V I/P IN1 T/H SAR MUX Sequencer operation V ADC IN2 V /V Temperature range: −40°C to +125°C IN3 REF 2 I C-compatible serial interface supports standard, fast, CONTROL SCL and high speed modes LOGIC AND 2 I C 2 SDA 2 versions allow 2 I C addresses INTERFACE Low power consumption Shutdown mode: 1 μA maximum AD7991/AD7995/AD7999 8-lead SOT-23 package GND APPLICATIONS Figure 1. System monitoring Battery-powered systems Data acquisition Medical instruments GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power, 1. Four single-ended analog input channels, or three single- 2 successive approximation ADCs with an I C®-compatible interface. ended analog input channels and one reference input channel. 2 Each part operates from a single 2.7 V to 5.5 V power supply and 2. I C-compatible serial interface. Standard, fast, and high features a 1 μs conversion time. The track-and-hold amplifier speed modes. allows each part to handle input frequencies of up to 14 MHz, 3. Automatic shutdown. and a multiplexer allows taking samples from four channels. 4. Reference derived from the power supply or external reference. Each AD7991/AD7995/AD7999 provides a 2-wire serial 5. 8-lead SOT-23 package. 2 interface compatible with I C interfaces. The AD7991 and AD7995 come in two versions and each version has an Table 1. Related Devices 2 individual I C address. This allows two of the same devices to be Device Resolution Input Channels 2 connected to the same I C bus. Both versions support standard, AD7998 12 8 2 fast, and high speed I C interface modes. The AD7999 comes in AD7997 10 8 one version. AD7994 12 4 The AD7991/AD7995/AD7999 normally remain in a shutdown AD7993 10 4 state, powering up only for conversions. The conversion process AD7992 12 2 2 is controlled by a command mode, during which each I C read operation initiates a conversion and returns the result over the 2 I C bus. When four channels are used as analog inputs, the reference for the part is taken from V ; this allows the widest dynamic input DD range to the ADC. Therefore, the analog input range to the ADC is 0 V to V . An external reference, applied through the DD V /V input, can also be used with this part. IN3 REF Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06461-001 AD7991/AD7995/AD7999 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 17 Applications....................................................................................... 1 Typical Connection Diagram ................................................... 18 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 18 General Description ......................................................................... 1 Internal Register Structure............................................................ 20 Product Highlights ........................................................................... 1 Configuration Register .............................................................. 20 Revision History ............................................................................... 2 Sample Delay and Bit Trial Delay............................................. 21 Specifications..................................................................................... 3 Conversion Result Register....................................................... 21 AD7991.......................................................................................... 3 Serial Interface ................................................................................ 22 AD7995.......................................................................................... 5 Serial Bus Address...................................................................... 22 AD7999.......................................................................................... 7 Writing to the AD7991/AD7995/AD7999.................................. 23 2 I C Timing Specifications............................................................ 9 Reading from the AD7991/AD7995/AD7999............................ 24 Absolute Maximum Ratings.......................................................... 11 Placing the AD7991/AD7995/AD7999 into High Speed Mode................................................................................. 25 ESD Caution................................................................................ 11 Mode of Operation......................................................................... 26 Pin Configuration and Function Descriptions........................... 12 Outline Dimensions....................................................................... 27 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 27 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 REVISION HISTORY 10/10—Rev. A to Rev. B Changes to Max Offset Error Parameter in Table 2..................... 3 Changes to Max Offset Error Parameter (Y Version) in Table 3 ......5 Changes to Max Offset Error Parameter (Y Version) in Table 4 ......7 Changes to Ordering Guide...................................................................27 10/09—Rev. 0 to Rev. A Changes to Table 3............................................................................ 5 Changes to Table 4............................................................................ 7 Updated Ordering Guide............................................................... 27 12/07—Revision 0: Initial Version Rev. B | Page 2 of 28 AD7991/AD7995/AD7999 SPECIFICATIONS 1 AD7991 The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, V = 2.7 V to 5.5 V, V = 2.5 V, f = 3.4 MHz, DD REF SCL and T = T to T . A MIN MAX Table 2. Y Version Parameter Min Typ Max Unit Test Conditions/Comments 2, 3 DYNAMIC PERFORMANCE See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz 4 Signal-to-Noise and Distortion (SINAD) 69.5 70 dB 4 Signal-to-Noise Ratio (SNR) 70 71 dB 4 Total Harmonic Distortion (THD) −75.5 dB 4 Peak Harmonic or Spurious Noise (SFDR) −77.5 dB 4 Intermodulation Distortion (IMD) fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for f up SCL to 400 kHz Second-Order Terms −92 dB Third-Order Terms −88 dB 4 Channel-to-Channel Isolation −90 dB fIN = 10 kHz 4 Full-Power Bandwidth 14 MHz @ 3 dB 1.5 MHz @ 0.1 dB 2, 5 DC ACCURACY Resolution 12 Bits 4 Integral Nonlinearity ±1 LSB ±0.5 LSB 4 Differential Nonlinearity ±0.9 LSB Guaranteed no missed codes to 12 bits ±0.5 LSB 4 Offset Error ±1 ±7 LSB Offset Error Matching ±0.5 LSB Offset Temperature Drift 4.43 ppm/°C 4 Gain Error ±2 LSB Gain Error Matching ±0.7 LSB Gain Temperature Drift 0.69 ppm/°C ANALOG INPUT Input Voltage Range 0 VREF V VREF = VIN3/VREF or VDD DC Leakage Current ±1 μA Input Capacitance 34 pF Channel 0 to Channel 2—during acquisition phase 4 pF Channel 0 to Channel 2—outside acquisition phase 35 pF Channel 3—during acquisition phase 5 pF Channel 3—outside acquisition phase REFERENCE INPUT VREF Input Voltage Range 1.2 VDD V DC Leakage Current ±1 μA V Input Capacitance 5 pF Outside conversion phase REF 35 pF During conversion phase Input Impedance 69 kΩ Rev. B | Page 3 of 28 AD7991/AD7995/AD7999 Y Version Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS (SDA, SCL) Input High Voltage, V 0.7 (V ) V V = 2.7 V to 5.5 V INH DD DD 0.9 (V) V V = 2.35 V to 2.7 V DD DD Input Low Voltage, V 0.3 (V) V V = 2.7 V to 5.5 V INL DD DD 0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 μA VIN = 0 V or VDD 6 Input Capacitance, CIN 10 pF Input Hysteresis, V 0.1 (V ) V HYST DD LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.4 V ISINK = 3 mA 0.6 V I = 6 mA SINK Floating-State Leakage Current ±1 μA 6 Floating-State Output Capacitance 10 pF Output Coding Straight (natural) binary THROUGHPUT RATE 18 × (1/f ) f ≤ 1.7 MHz; see the Serial Interface SCL SCL section 17.5 × (1/fSCL) fSCL > 1.7 MHz; see the Serial Interface + 2 μs section 2 POWER REQUIREMENTS VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented VDD 2.7 5.5 V I Digital inputs = 0 V or V DD DD ADC Operating, Interface Active 0.09/0.25 mA V = 3.3 V/5.5 V, 400 kHz f DD SCL (Fully Operational) 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 7 Power-Down, Interface Active 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.26/0.85 mA V = 3.3 V/5.5 V, 3.4 MHz f DD SCL 7 Power-Down, Interface Inactive 1/1.6 μA V = 3.3 V/5.5 V DD Power Dissipation ADC Operating, Interface Active 0.3/1.38 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL (Fully Operational) 0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 7 Power-Down, Interface Active 0.24/0.88 mW V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.86/4.68 mW V = 3.3 V/5.5 V, 3.4 MHz f DD SCL 7 Power-Down, Interface Inactive 3.3/8.8 μW V = 3.3 V/5.5 V DD 1 Functional from V = 2.35 V. DD 2 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 3 For f up to 400 kHz, clock stretching is not implemented. Above f = 400 kHz, clock stretching is implemented. SCL SCL 4 See the Terminology section. 5 For f ≤ 1.7 MHz, clock stretching is not implemented; for f > 1.7 MHz, clock stretching is implemented. SCL SCL 6 Guaranteed by initial characterization. 7 See the Reading from the AD7991/AD7995/AD7999 section. Rev. B | Page 4 of 28 AD7991/AD7995/AD7999 1 AD7995 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 3. 2 A Version Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 3 , 4 DYNAMIC PERFORMANCE See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz f = 1 kHz sine wave for f up to 400 kHz IN SCL Signal-to-Noise and 61.5 61 dB 5 Distortion (SINAD) Total Harmonic Distortion −85 −75 dB 5 (THD) Peak Harmonic or Spurious −85 −76 dB 5 Noise (SFDR) Intermodulation fa = 11 kHz, fb = 9 kHz for f from 1.7 MHz to SCL 5 Distortion (IMD) 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms −90 −90 dB Third-Order Terms −86 −86 dB Channel-to-Channel −90 −90 dB fIN = 10 kHz 5 Isolation 5 Full-Power Bandwidth 14 14 MHz @ 3 dB 1.5 1.5 MHz @ 0.1 dB 3, 6 DC ACCURACY Resolution 10 10 Bits 5 Integral Nonlinearity ±0.4 ±0.4 LSB 5 Differential Nonlinearity ±0.4 ±0.4 LSB Guaranteed no missed codes to 10 bits 5 Offset Error ±1 ±2.25 LSB Offset Error Matching ±0.04 ±0.2 LSB Offset Temperature Drift 4.13 4.13 ppm/°C 5 Gain Error ±0.15 ±0.5 LSB Gain Error Matching ±0.06 ±0.25 LSB Gain Temperature Drift 0.50 0.50 ppm/°C ANALOG INPUT Input Voltage Range 0 VREF 0 VREF V VREF = VIN3/VREF or VDD DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase REFERENCE INPUT VREF Input Voltage Range 1.2 VDD 1.2 VDD V DC Leakage Current ±1 ±1 μA VREF Input Capacitance 5 5 pF Outside conversion phase 35 35 pF During conversion phase Input Impedance 69 69 kΩ Rev. B | Page 5 of 28 AD7991/AD7995/AD7999 2 A Version Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V 0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, VINL 0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V 0.1 (V) V V = 2.35 V to 2.7 V DD DD Input Leakage Current, I ±1 ±1 μA V = 0 V or V IN IN DD 7 Input Capacitance, C 10 10 pF IN Input Hysteresis, V 0.1 (V ) 0.1 (V ) V HYST DD DD LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Floating-State Leakage ±1 ±1 μA Current Floating-State Output 10 10 pF 7 Capacitance Output Coding Straight (natural) binary Straight (natural) binary THROUGHPUT RATE 18 × (1/fSCL) 18 × (1/fSCL) f ≤ 1.7 MHz; see the Serial Interface SCL section 17.5 × (1/fSCL) + 17.5 × (1/fSCL) + fSCL > 1.7 MHz; see the Serial Interface 2 μs 2 μs section 3 POWER REQUIREMENTS VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD ADC Operating, 0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL Interface Active (Fully Operational) 0.25 0.25/0.8 mA V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Power-Down, Interface 0.07/0.16 mA V = 3.3 V/5.5 V, 400 kHz f DD SCL 8 Active 0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface 1 1/1.6 μA VDD = 3.3 V/5.5 V 8 Inactive Power Dissipation ADC Operating, 0.3/1.38 mW V = 3.3 V/5.5 V, 400 kHz f DD SCL Interface Active 0.83 0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL (Fully Operational) Power-Down, Interface 0.24/0.88 mW V = 3.3 V/5.5 V, 400 kHz f DD SCL 8 Active 0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface 3.3 3.3/8.8 μW VDD = 3.3 V/5.5 V 8 Inactive 1 Functional from V = 2.35 V. DD 2 A Version tested at VDD = 3.3 V and fSCL = 3.4 MHz. Functionality tested at fSCL = 400 kHz. 3 Sample delay and bit trial delay enabled, t = t = 0.5/f . 1 2 SCL 4 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 5 See the Terminology section. 6 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section. Rev. B | Page 6 of 28 AD7991/AD7995/AD7999 1 AD7999 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 4. 2 A Version Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 3 , 4 DYNAMIC PERFORMANCE See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz f = 1 kHz sine wave for f up to 400 kHz IN SCL Signal-to-Noise and 49.5 49.5 dB 5 Distortion (SINAD) Total Harmonic −65 −65 dB 5 Distortion (THD) Peak Harmonic or −65 −65 dB 5 Spurious Noise (SFDR) Intermodulation fa = 11 kHz, fb = 9 kHz for f from 1.7 MHz to SCL 5 Distortion (IMD) 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms −83 −83 dB Third-Order Terms −75 −75 dB Channel-to-Channel −90 −90 dB fIN = 10 kHz 5 Isolation 5 Full-Power Bandwidth 14 14 MHz @ 3 dB 1.5 1.5 MHz @ 0.1 dB 3, 6 DC ACCURACY Resolution 8 8 Bits 5 Integral Nonlinearity ±0.04 ±0.1 LSB 5 Differential Nonlinearity ±0.05 ±0.1 LSB Guaranteed no missed codes to eight bits 5 Offset Error ±0.3 ±0.5 LSB Offset Error Matching ±0.02 ±0.05 LSB Offset Temperature Drift 4.26 4.26 ppm/°C 5 Gain Error ±0.06 ±0.175 LSB Gain Error Matching ±0.03 ±0.06 LSB Gain Temperature Drift 0.59 0.59 ppm/°C ANALOG INPUT Input Voltage Range 0 V 0 V V V = V /V or V REF REF REF IN3 REF DD DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase REFERENCE INPUT V Input Voltage Range 1.2 V 1.2 V V REF DD DD DC Leakage Current ±1 ±1 μA V Input Capacitance 5 5 pF Outside conversion phase REF 35 35 pF During conversion phase Input Impedance 69 69 kΩ Rev. B | Page 7 of 28 AD7991/AD7995/AD7999 2 A Version Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V 0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, VINL 0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V 0.1 (V) V V = 2.35 V to 2.7 V DD DD Input Leakage Current, I ±1 ±1 μA V = 0 V or V IN IN DD 7 Input Capacitance, C 10 10 pF IN Input Hysteresis, V 0.1 (V ) 0.1 (V ) V HYST DD DD LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Floating-State Leakage ±1 ±1 μA Current Floating-State Output 10 10 pF 7 Capacitance Output Coding Straight (natural) binary Straight (natural) binary THROUGHPUT RATE 18×(1/fSCL) 18×(1/fSCL) f ≤ 1.7 MHz; see the Serial Interface section SCL 17.5×(1/fSCL) 17.5×(1/fSCL) fSCL > 1.7 MHz; see the Serial Interface section + 2 μs + 2 μs 3 POWER REQUIREMENTS V = V ; for f = 3.4 MHz, REF DD SCL clock stretching is implemented VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD ADC Operating, 0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL Interface Active 0.25 0.25/0.8 mA V = 3.3 V/5.5 V, 3.4 MHz f DD SCL (Fully Operational) Power-Down, 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL 8 Interface Active 0.26 0.26/0.85 mA V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Power-Down , 1 1/1.6 μA V = 3.3 V/5.5 V DD 8 Interface Inactive Power Dissipation 0.3/1.38 mW V = 3.3 V/5.5 V, 400 kHz f DD SCL ADC Operating, 0.83 0.83/4.4 mW V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Interface Active (Fully Operational) Power-Down, 0.24/0.88 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL 8 Interface Active 0.86 0.86/4.68 mW V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Power-Down , 3.3 3.3/8.8 μW V = 3.3 V/5.5 V DD 8 Interface Inactive 1 Functional from VDD = 2.35 V. 2 A Version tested at V =3.3 V and f = 3.4 MHz. Functionality tested at f = 400 kHz. DD SCL SCL 3 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 4 For f up to 400 kHz, clock stretching is not implemented. Above f = 400 kHz, clock stretching is implemented. SCL SCL 5 See the Terminology section. 6 For f ≤ 1.7 MHz, clock stretching is not implemented; for f > 1.7 MHz, clock stretching is implemented. SCL SCL 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section. Rev. B | Page 8 of 28 AD7991/AD7995/AD7999 2 I C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tr and tf measured between 0.3 VDD and 0.7 VDD (see Figure 2). Unless otherwise noted, VDD = 2.7 V to 5.5 V and TA = TMIN to TMAX. Table 5. Limit at tMIN, tMAX Parameter Conditions Min Typ Max Unit Description 1 fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode C = 100 pF maximum 3.4 MHz B CB = 400 pF maximum 1.7 MHz 1 t Standard mode 4 μs t , SCL high time 1 HIGH Fast mode 0.6 μs High speed mode CB = 100 pF maximum 60 ns CB = 400 pF maximum 120 ns 1 t2 Standard mode 4.7 μs tLOW, SCL low time Fast mode 1.3 μs High speed mode C = 100 pF maximum 160 ns B C = 400 pF maximum 320 ns B 1 t Standard mode 250 ns t , data setup time 3 SU;DAT Fast mode 100 ns High speed mode 10 ns 1, 2 t Standard mode 0 3.45 μs t , data hold time 4 HD;DAT Fast mode 0 0.9 μs High Speed mode 3 CB = 100 pF maximum 0 70 ns CB = 400 pF maximum 0 150 ns 1 t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition Fast mode 0.6 μs High Speed mode 160 ns 1 t6 Standard mode 4 μs tHD;STA, hold time for a repeated start condition Fast mode 0.6 μs High speed mode 160 ns 1 t7 Standard mode 4.7 μs tBUF, bus-free time between a stop and a start condition Fast mode 1.3 μs 1 t Standard mode 4 μs t , setup time for a stop condition 8 SU;STO Fast mode 0.6 μs High speed mode 160 ns t Standard mode 1000 ns t , rise time of the SDA signal 9 RDA Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF maximum 10 80 ns C = 400 pF maximum 20 160 ns B Rev. B | Page 9 of 28 AD7991/AD7995/AD7999 Limit at tMIN, tMAX Parameter Conditions Min Typ Max Unit Description t10 Standard mode 300 ns tFDA, fall time of the SDA signal Fast mode 20 + 0.1 C 300 ns B High speed mode C = 100 pF maximum 10 80 ns B CB = 400 pF maximum 20 160 ns t Standard mode 1000 ns t , rise time of the SCL signal 11 RCL Fast mode 20 + 0.1 C 300 ns B High speed mode CB = 100 pF maximum 10 40 ns CB = 400 pF maximum 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of the SCL signal after a repeated start condition and after an acknowledge bit Fast mode 20 + 0.1 C 300 ns B High speed mode C = 100 pF maximum 10 80 ns B CB = 400 pF maximum 20 160 ns t Standard mode 300 ns t , fall time of the SCL signal 12 FCL Fast mode 20 + 0.1 C 300 ns B High speed mode CB = 100 pF maximum 10 40 ns CB = 400 pF maximum 20 80 ns 1 tSP Fast mode 0 50 ns Pulse width of the suppressed spike High speed mode 0 10 ns tPOWER-UP 0.6 μs Power-up and acquisition time 1 Functionality is tested during production. 2 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 3 For 3 V supplies, the maximum hold time with C = 100 pF maximum is 100 ns maximum. B t 11 t 12 t t 2 6 SCL t t t t t 6 4 3 5 8 t 1 t t 10 9 SDA t 7 S P S P S = START CONDITION P = STOP CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. B | Page 10 of 28 06461-002 AD7991/AD7995/AD7999 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to 7 V DD rating only; functional operation of the device at these or any Analog Input Voltage to GND −0.3 V to V + 0.3 V DD other conditions above those indicated in the operational Reference Input Voltage to GND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to VDD + 0.3 V 1 device reliability. Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Ranges ESD CAUTION Industrial (Y Version) Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 8-Lead SOT-23 Package θ Thermal Impedance 170°C/W JA θ Thermal Impedance 90°C/W JC RoHS Compliant Temperature, 260 + 0°C Soldering Reflow ESD 1 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 11 of 28 AD7991/AD7995/AD7999 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCL 1 8 V DD AD7991/ AD7995/ SDA 2 7 GND AD7999 V 3 6 V /V IN0 TOP VIEW IN3 REF (Not to Scale) V 4 5 V IN1 IN2 Figure 3. SOT-23 Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 SCL Digital Input. Serial bus clock. External pull-up resistor required. 2 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 3 V Analog Input 1. Single-ended analog input channel. The input range is 0 V to V . IN0 REF 4 V Analog Input 2. Single-ended analog input channel. The input range is 0 V to V . IN1 REF 5 V Analog Input 3. Single-ended analog input channel. The input range is 0 V to V . IN2 REF 6 VIN3/VREF Analog Input 4. Single-ended analog input channel. The input range is 0 V to VREF. Can also be used to input an external VREF signal. 7 GND Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input signals should be referred to this AGND voltage. 8 V Power Supply Input. The V range for the AD7991/AD7995/AD7999 is from 2.7 V to 5.5 V. DD DD 2 Table 8. I C Address Selection 2 Part Number I C Address AD7991-0 010 1000 AD7991-1 010 1001 AD7995-0 010 1000 AD7995-1 010 1001 AD7999-1 010 1001 Rev. B | Page 12 of 28 06461-003 AD7991/AD7995/AD7999 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 V = 2.7V DD 0.8 0.8 V = 2.35V REF f = 1.7MHz SCL 0.6 0.6 POSITIVE INL 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 NEGATIVE INL –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 CODE REFERENCE VOLTAGE (V) Figure 4. DNL Error, VDD = 2.7 V, VREF = 2.35 V, fSCL = 1.7 MHz Figure 7. INL Error vs. Reference Voltage , fSCL = 1.7 MHz Without Clock Stretching Without Clock Stretching 1.0 1.0 V = 2.7V DD 0.8 0.8 V = 2.35V REF f = 1.7MHz SCL 0.6 0.6 POSITIVE DNL 0.4 0.4 0.2 0.2 0 0 NEGATIVE DNL –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 CODE REFERENCE VOLTAGE (V) Figure 5. INL Error, VDD = 2.7 V, VREF = 2.35 V, fSCL = 1.7 MHz Figure 8. DNL Error vs. Reference Voltage, fSCL = 1.7 MHz Without Clock Stretching Without Clock Stretching 12.0 74 1.0 ENOB V = 5V DD 0.8 11.5 ENOB V = 3V DD 72 SINAD V = 5V DD 0.6 11.0 70 0.4 10.5 0.2 68 SINAD V = 3V DD 10.0 0 66 –0.2 9.5 –0.4 64 9.0 –0.6 V = 5V DD 62 8.5 V = 2.5V –0.8 REF f = 1.7MHz SCL 8.0 60 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 06 123 45 CODE REFERENCE VOLTAGE (V) Figure 6. ENOB/SINAD vs. Reference Voltage, f = 1.7 MHz Figure 9. INL Error, V = 5 V, V = 2.5 V, f = 1.7 MHz SCL DD REF SCL Without Clock Stretching Without Clock Stretching Rev. B | Page 13 of 28 ENOB (Bits) INL ERROR (LSB) DNL ERROR (LSB) 06461-036 06461-006 06461-005 SINAD (dB) INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 06461-037 06461-033 06461-013 AD7991/AD7995/AD7999 1.0 –70 f = 1.7MHz SCL 0.8 0.6 0.4 –80 V = 5V 0.2 DD 0 V = 3V DD –0.2 –90 –0.4 –0.6 V = 5V DD –0.8 V = 2.5V REF f = 1.7MHz SCL –1.0 –100 0 500 1000 1500 2000 2500 3000 3500 4000 1 10 100 CODE INPUT FREQUENCY (kHz) Figure 10. DNL Error, V = 5 V, V = 2.5 V, f = 1.7 MHz Figure 13. THD vs. Input Frequency, V = 2.5 V, f = 1.7 MHz DD REF SCL REF SCL Without Clock Stretching Without Clock Stretching 800 96 f = 1.7MHz SCL 95 +125°C V = 3V +85°C DD 600 +25°C 94 –40°C 93 400 92 V = 5V DD 91 200 90 V = V REF DD f = 1.7MHz SCL TEMPERATURE = T A 89 0 0 102030405060 70 80 90 100 26 34 5 f (kHz) NOISE V (V) DD Figure 11. IDD Supply Current vs. Supply Voltage, fSCL = 1.7 MHz Figure 14. AD7991 Channel-to-Channel Isolation , fSCL = 1.7 MHz Without Clock Stretching, −40°C to +125°C Without Clock Stretching 1000 0 16384 POINT FFT f = 3.4MHz SCL f = 22.5kSPS +125°C S f = 405kHz +85°C SCL –20 f = 5.13kHz 800 +25°C IN SNR = 71.83dB –40°C SINAD = 71.39dB –40 THD = –81.26dB SFDR = –93.71dB 600 –60 400 –80 200 –100 0 –120 02 46 8 10 26 34 5 FREQUENCY (kHz) V (V) DD Figure 12. IDD Supply Current vs. Supply Voltage, f SCL = 3.4 MHz Figure 15. Dynamic Performance, fSCL = 405 kHz with Clock Stretching, −40°C to +125°C Without Clock Stretching, VDD = 5 V, Full-Scale Input, Seven-Term Blackman-Harris Window Rev. B | Page 14 of 28 DNL ERROR (LSB) I (μA) I (μA) DD DD 06461-034 06461-035 06461-014 CHANNEL-TO-CHANNEL ISOLATION (dB) SINAD (dB) THD (dB) 06461-018 06461-031 06461-017 AD7991/AD7995/AD7999 3 0 16384 POINT FFT f = 95kSPS S f = 1.71MHz –20 SCL f = 10.13kHz IN SNR = 71.77dB SINAD = 71.45dB –40 2 THD = –82.43dB SFDR = –95.02dB V = 5V DD –60 –80 1 V = 3V DD –100 –120 0 0 5 10 15 20 25 30 35 40 45 0 500 1000 1500 FREQUENCY (kHz) SCL FREQUENCY (kHz) Figure 16. Dynamic Performance, fSCL = 1.71 MHz Figure 17. Power vs. SCL Frequency, V = 2.5 V REF Without Clock Stretching, VDD = 5 V, Full-Scale Input, Seven-Term Blackman-Harris Window Rev. B | Page 15 of 28 SINAD (dB) 06461-019 POWER (mW) 06461-032 AD7991/AD7995/AD7999 TERMINOLOGY in frequency from the original sine waves, and the third-order Signal-to-Noise and Distortion (SINAD) Ratio terms are usually at a frequency close to the input frequencies. As a The measured ratio of signal-to-noise and distortion at the output result, the second- and third-order terms are specified separately. of the ADC. The signal is the rms amplitude of the fundamental. The calculation of intermodulation distortion is, like the THD Noise is the sum of the nonfundamental signals excluding dc, specification, the ratio of the rms sum of the individual distortion up to half the sampling frequency (f /2). The ratio is dependent S products to the rms amplitude of the sum of the fundamentals, on the number of quantization levels in the digitization process: expressed in decibels. the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input Channel-to-Channel Isolation is given by Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB a full-scale sine wave signal to all unselected input channels and Therefore, SINAD is 49.92 dB for an 8-bit converter, 61.96 dB then determining the degree to which the signal attenuates in for a 10-bit converter, and 74 dB for a 12-bit converter. the selected channel with a 10 kHz signal. The frequency of the Total Harmonic Distortion (THD) signal in each of the unselected channels is increased from 2 kHz The ratio of the rms sum of harmonics to the fundamental. For up to 92 kHz. Figure 14 shows the worst-case across all four the AD7991/AD7995/AD7999, it is defined as channels for the AD7991. 2 2 2 2 2 Full-Power Bandwidth V2 +V3 +V4 +V5 +V6 THD (dB)= 20 log The input frequency at which the amplitude of the reconstructed V1 fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. where: Integral Nonlinearity V1 is the rms amplitude of the fundamental. The maximum deviation from a straight line passing through V2, V3, V4, V5, and V6 are the rms amplitudes of the second the endpoints of the ADC transfer function. The endpoints are through sixth harmonics. at zero scale (a point 1 LSB below the first code transition) and Peak Harmonic or Spurious Noise full scale (a point 1 LSB above the last code transition). The ratio of the rms value of the next largest component in the Differential Nonlinearity ADC output spectrum (up to f /2 and excluding dc) to the rms S The difference between the measured and the ideal 1 LSB value of the fundamental. Typically, the value of this specification change between any two adjacent codes in the ADC. is determined by the largest harmonic in the spectrum, but for Offset Error ADCs where the harmonics are buried in the noise floor, the The deviation of the first code transition (00 … 000 to largest harmonic may be a noise peak. 00 … 001) from the ideal—that is, AGND + 1 LSB. Intermodulation Distortion Offset Error Match With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion The difference in offset error between any two channels. products at sum and difference frequencies of mfa ± nfb, where Gain Error m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms The deviation of the last code transition (111 … 110 to are those for which neither m nor n equals 0. For example, 111 … 111) from the ideal (that is, VREF − 1 LSB) after second-order terms include (fa + fb) and (fa − fb), and the offset error has been adjusted out. third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and Gain Error Match (fa − 2fb). The difference in gain error between any two channels. The AD7991/AD7995/AD7999 are tested using the CCIF standard, where two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced Rev. B | Page 16 of 28 AD7991/AD7995/AD7999 THEORY OF OPERATION The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit, When the ADC starts a conversion, as shown in Figure 19, SW2 single-supply, 4-channel ADCs. Each part can be operated from opens and SW1 moves to Position B, causing the comparator to a single 2.35 V to 5.5 V supply. become unbalanced. The input is disconnected when the con- version begins. The control logic and the capacitive DAC are used The AD7991/AD7995/AD7999 provide the user with a 4-channel to add and subtract fixed amounts of charge from the sampling 2 multiplexer, an on-chip track-and-hold, an ADC, and an I C- capacitor to bring the comparator back into a balanced condition. compatible serial interface, all housed in an 8-lead SOT-23 package When the comparator is rebalanced, the conversion is complete. that offers the user considerable space-saving advantages over The control logic generates the ADC output code. Figure 20 shows alternative solutions. the ADC transfer function. The AD7991/AD7995/AD7999 normally remains in a power- CAPACITIVE down state while not converting. Therefore, when supplies are DAC first applied, the part is in a power-down state. Power-up is initiated prior to a conversion, and the device returns to the power-down A V state upon completion of the conversion. This automatic power- IN CONTROL SW1 LOGIC B down feature allows the device to save power between conversions. SW2 2 COMPARATOR This means any read or write operations across the I C interface AGND can occur while the device is in power-down. Figure 19. ADC Conversion Phase CONVERTER OPERATION ADC Transfer Function The AD7991/AD7995/AD7999 are successive approximation The output coding of the AD7991/AD7995/AD7999 is straight ADCs built around a capacitive DAC. Figure 18 and Figure 19 binary. The designed code transitions occur at successive integer show simplified schematics of the ADC during its acquisition LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for and conversion phases, respectively. Figure 18 shows the ADC /4096, V /1024, and the AD7991/AD7995/AD7999 is VREF REF during its acquisition phase: SW2 is closed, SW1 is in Position A, VREF/256, respectively. Figure 20 shows the ideal transfer the comparator is held in a balanced condition, and the sampling characteristics for the AD7991/AD7995/AD7999. capacitor acquires the signal on V . The source driving the IN analog input needs to settle the analog input signal to within one LSB in 0.6 μs, which is equivalent to the duration of the 111 ... 111 111 ... 110 power-up and acquisition time. CAPACITIVE 111 ... 000 DAC 011 ... 111 AD7991 1 LSB = REF /4096 IN A AD7995 1 LSB = REF /1024 IN 000 ... 010 V IN AD7999 1 LSB = REF /256 CONTROL IN 000 ... 001 SW1 LOGIC B 000 ... 000 SW2 AGND + 1 LSB +REF – 1 LSB IN COMPARATOR ANALOG INPUT AGND 0V TO REF IN Figure 18. ADC Acquisition Phase Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics Rev. B | Page 17 of 28 06461-020 ADC CODE 06461-022 06461-021 AD7991/AD7995/AD7999 TYPICAL CONNECTION DIAGRAM ANALOG INPUT Figure 22 shows the typical connection diagram for the Figure 21 shows an equivalent circuit of the AD7991/AD7995/ AD7991/AD7995/AD7999. AD7999 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken The reference voltage can be taken from the supply voltage, to ensure that the analog input signal does not exceed the supply V . However, the AD7991/AD7995/AD7999 can be configured DD rails by more than 300 mV. If the signal does exceed this level, to be a 3-channel device with the reference voltage applied to the diodes become forward-biased and start conducting current the V /V pin. In this case, a 1 μF decoupling capacitor on IN3 REF into the substrate. Each diode can conduct a maximum current the VIN3/VREF pin is recommended. of 10 mA without causing irreversible damage to the part. 2 SDA and SCL form the 2-wire I C compatible interface. External V DD pull-up resistors are required for both the SDA and SCL lines. The AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/ 2 D1 AD7999-1 support standard, fast, and high speed I C interface C2 2 30pF modes. Both the -0 and -1 devices have independent I C addresses, R1 V 2 IN which allows the devices to connect to the same I C bus without C1 contention issues. 4pF D2 The part requires approximately 0.6 μs to wake up from power- CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED down and to acquire the analog input. Once the acquisition phase ends, the conversion phase starts and takes approximately Figure 21. Equivalent Analog Input Circuit 1 μs to complete. The AD7991/AD7995/AD7999 enters shutdown mode after each conversion, which is useful in Capacitor C1 in Figure 21 is typically about 4 pF and can applications where power consumption is a concern. primarily be attributed to pin capacitance. Resistor R1 is a lumped component composed of the on resistance (RON) of both a track-and-hold switch and the input multiplexer. The total resistor is typically about 400 Ω. Capacitor C2, the ADC sampling capacitor, has a typical capacitance of 30 pF. 5V SUPPLY + + 10µF 0.1µF 2-WIRE SERIAL INTERFACE R R P P V IN0 V V DD IN1 SDA V IN2 MICROCONTROLLER/ SCL V /V IN3 REF MICROPROCESSOR AD7991/ AD7995/ GND AD7999 Figure 22. AD7991/AD7995/AD7999 Typical Connection Diagram Rev. B | Page 18 of 28 06461-024 06461-023 AD7991/AD7995/AD7999 0 For ac applications, removing high frequency components from V = 5V DD V = V –10 REF DD the analog input signal is recommended by use of an RC band- TEMPERATURE = T A pass filter on the relevant analog input pin. In applications f = 1.7MHz –20 SCL where harmonic distortion and signal-to-noise ratio are critical, –30 the analog input should be driven from a low impedance –40 source. Large source impedances significantly affect the ac –50 5.1kΩ performance of the ADC. This may necessitate the use of an –60 2kΩ input buffer amplifier. The choice of the op amp is a function 1.3kΩ of the particular application. –70 –80 When no amplifier is used to drive the analog input, the source 240Ω impedance should be limited to low values. The maximum –90 56Ω source impedance depends on the amount of THD that can be –100 1 10 100 tolerated. THD increases as the source impedance increases and ANALOG INPUT FREQUENCY (kHz) performance degrades. Figure 23 shows the THD vs. the analog Figure 23. THD vs. Analog Input Frequency for Various Source Impedances input signal frequency for different source impedances at a for V = 5 V, f = 1.7 MHz Without Clock Stretching DD SCL supply voltage of 5 V. Rev. B | Page 19 of 28 THD (dB) 06461-025 AD7991/AD7995/AD7999 INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register. Table 9. Configuration Register Bit Map and Default Settings at Power-Up D7 D6 D5 D4 D3 D2 D1 D0 CH3 CH2 CH1 CH0 REF_SEL FLTR Bit trial delay Sample delay 1 1 1 1 0 0 0 0 Table 10. Bit Function Descriptions Bit Mnemonic Comment D7 to D4 CH3 to CH0 These four channel address bits select the analog input channel(s) to be converted. If a channel address bit (Bit D7 to Bit D4) is set to 1, a channel is selected for conversion. If more than one channel bit is set to 1, the AD7991/AD7995/AD7999 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11 shows how these four channel address bits are decoded. Prior to the device initiating a conversion, the channel(s) must be selected in the configuration register. D3 REF_SEL This bit allows the user to select the supply voltage as the reference or choose to use an external reference. If this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. If this bit is set to 1, an external reference must be used and applied to the V /V pin, and the device acts as a 3-channel IN3 REF input part. D2 FLTR The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or bypassed. If this bit is set to 0, the filtering is enabled; if it set to 1, the filtering is bypassed. D1 Bit trial delay See the Sample Delay and Bit Trial Delay section. D0 Sample delay See the Sample Delay and Bit Trial Delay section. Table 11. Channel Selection 1 D7 D6 D5 D4 Analog Input Channel 0 0 0 0 No channel selected 0 0 0 1 Convert on V IN0 0 0 1 0 Convert on VIN1 0 0 1 1 Sequence between VIN0 and VIN1 0 1 0 0 Convert on VIN2 0 1 0 1 Sequence between V and V IN0 IN2 0 1 1 0 Sequence between V and V IN1 IN2 0 1 1 1 Sequence among V , V , and V IN0 IN1 IN2 1 0 0 0 Convert on VIN3 1 0 0 1 Sequence between VIN0 and VIN3 1 0 1 0 Sequence between VIN1 and VIN3 1 0 1 1 Sequence among V , V , and V IN0 IN1 IN3 1 1 0 0 Sequence between V and V IN2 IN3 1 1 0 1 Sequence among VIN0, VIN2, and VIN3 1 1 1 0 Sequence among VIN1, VIN2, and VIN3 1 1 1 1 Sequence among VIN0, VIN1, VIN2, and VIN3 1 The AD7991/AD7995/AD7999 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence. Rev. B | Page 20 of 28 AD7991/AD7995/AD7999 SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER 2 It is recommended that no I C bus activity occur while a The conversion result register is a 16-bit read-only register that conversion is taking place (see Figure 27 and the Placing the stores the conversion result from the ADC in straight binary AD7991/AD7995/AD7999 into High Speed Mode section). format. A 2-byte read is necessary to read data from this However, if this is not always possible, then in order to maintain register. Table 12 shows the contents of the first byte to be read the performance of the ADC, Bits D0 and D1 in the configuration from AD7991/AD7995/AD7999, and Table 13 shows the register are used to delay critical sample intervals and bit trials contents of the second byte to be read. 2 from occurring while there is activity on the I C bus. This results in Each AD7991/AD7995/AD7999 conversion result consists of a quiet period for each bit decision. However, the sample delay two leading 0s, two channel identifier bits, and the 12-/10-/8-bit protection may introduce excessive jitter, degrading the SNR for data result. For the AD7995, the two LSBs (D1 and D0) of the large signals above 300 Hz. For guaranteed ac performance, use second read contain two trailing 0s. For the AD7999, the four of clock stretching is recommended. LSBs (D3, D2, D1, and D0) of the second read contain four When Bit D0 and Bit D1 are both 0, the bit trial and sample interval trailing 0s. delay mechanism is implemented. The default setting of D0 and D1 is 0. To turn off both delay mechanisms, set D0 and D1 to 1. Table 12. Conversion Value Register (First Read) D15 D14 D13 D12 D11 D10 D9 D8 Leading 0 Leading 0 CH CH MSB B10 B9 B8 ID1 ID0 Table 13. Conversion Value Register (Second Read) D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3/0 B2/0 B1/0 B0/0 Rev. B | Page 21 of 28 AD7991/AD7995/AD7999 SERIAL INTERFACE Control of the AD7991/AD7995/AD7999 is accomplished via 4. Data is sent over the serial bus in sequences of nine clock 2 the I C-compatible serial bus. The AD7991/AD7995/AD7999 is pulses—eight bits of data followed by an acknowledge bit connected to this bus as a slave device under the control of a from the receiver of data. Transitions on the data line must master device, such as the processor. occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition SERIAL BUS ADDRESS when the clock is high may be interpreted as a stop signal. 2 Like all I C-compatible devices, the AD7991/AD7995/AD7999 has 5. When all data bytes have been read or written, stop conditions a 7-bit serial address. The devices are available in two versions, the are established. In write mode, the master pulls the data line AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/AD7999-1. th high during the 10 clock pulse to assert a stop condition. Each version has a different address (see Table 8), which allows up In read mode, the master device pulls the data line high to two AD7991/AD7995 devices to be connected to a single during the low period before the ninth clock pulse. This is serial bus. AD7999 has only one version. known as a no acknowledge. The master takes the data line The serial bus protocol operates as follows: th low during the low period before the 10 clock pulse, and th then high during the 10 clock pulse to assert a stop condition. 1. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial 6. Any number of bytes of data can be transferred over the serial data line SDA while the serial clock line, SCL, remains high. bus in one operation, but it is not possible to mix reads and This indicates that an address/data stream follows. writes in one operation because the type of operation is 2. All slave peripherals connected to the serial bus respond to determined at the beginning and cannot subsequently be the start condition and shift in the next eight bits, consisting of changed without starting a new operation. a 7-bit address (MSB first) plus an R/ bit that determines W the direction of the data transfer—that is, whether data is written to or read from the slave device. 3. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is set to 0, the master writes to the slave device. If the R/ bit is set to 1, the master reads W from the slave device. Rev. B | Page 22 of 28 AD7991/AD7995/AD7999 WRITING TO THE AD7991/AD7995/AD7999 By default, each part operates in read-only mode and all four chan- The configuration register is an 8-bit register; therefore, only nels are selected as enabled in the configuration register. To write one byte of data can be written to this register. However, writing to the AD7991/AD7995/AD7999 configuration register, the user a single byte of data to this register consists of writing the serial must first address the device. bus write address, followed by the data byte written (see Figure 24). 1 99 1 SCL 011 0 0 0 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 SDA START BY ACK BY ACK BY STOP MASTER ADC ADC FRAME 1 CONFIGURATION REGISTER BYTE SERIAL BUS ADDRESS BYTE Figure 24. Writing to the AD7991/AD7995/AD7999 Configuration Register Rev. B | Page 23 of 28 06461-026 AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 Reading data from the conversion result register is a 2-byte read operation and should not affect the read operation. The operation, as shown in Figure 25. Therefore, a read operation master reads back two bytes of data. On the ninth SCLK rising always involves two bytes. edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 After the AD7991/AD7995/AD7999 have received a read powers up and performs a second conversion. If the master sends address, any number of reads can be performed from the a NO ACK, the AD7991/AD7995/AD7999 does not power up conversion result register. on the ninth SCLK rising edge of the second byte. If a further Following a start condition, the master writes the 7-bit address conversion is required, the part converts on the next channel, as of the AD7991/AD7995/AD7999 and then sets R/ to 1. The W selected in the configuration register. See Table 11 for information AD7991/AD7995/AD7999 acknowledge this by pulling the about the channel selection. SDA line low. They then output the conversion result over the If the master sends a NO ACK on the ninth SCLK rising edge of 2 I C bus, preceded by four status bits. The status bits are two the second byte, the conversion is finished and no further leading 0s followed by the channel identifier bits. For the conversion is preformed. AD7995 there are two trailing 0s, and for the AD7999 there are To put the part into full shutdown mode, the user should issue a four trailing 0s. stop condition to the AD7991/AD7995/AD7999. If the AD7991/ After the master has addressed the AD7991/AD7995/AD7999, AD7995/AD7999 is not put into full shutdown mode, it will draw the part begins to power up on the ninth SCLK rising edge. At a few tens of microamperes from the supply. the same time, the acquisition phase begins. When approximately 0.6 μs have elapsed, the acquisition phase ends. The input is sampled and a conversion begins. This is done in parallel to the 11 9 9 SCL 0 100 1 0 A0 R/W 00 D11 D10 D9 D8 SDA ACK BY ACK BY START BY ADC MASTER CH CH ID1 ID0 MASTER FRAME 2 FRAME 1 MOST SIGNIFICANT DATA BYTE FROM ADC SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM ADC Figure 25. Reading Two Bytes of Data from the AD7991Conversion Result Register Rev. B | Page 24 of 28 06461-027 AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE High speed mode communication commences after the master All devices continue to operate in high speed mode until the addresses all devices connected to the bus with the master code, master issues a stop condition. When the stop condition is 00001XXX, to indicate that a high speed mode transfer is to issued, the devices return to fast mode. begin. No device connected to the bus is allowed to acknowledge To guarantee performance above f = 1.7 MHz, the user must SCL the high speed master code; therefore, the code is followed by a perform clock stretching—that is, the clock must be held high—for NO ACK (see Figure 26). The master must then issue a repeated 2 μs after the ninth clock rising edge (see Figure 27). Therefore, start, followed by the device address and an R/ bit. The selected W the clock must be held high for 2 μs after the device starts to power device then acknowledges its address. up (see the Reading from the AD7991/AD7995/AD7999 section). FAST MODE HIGH SPEED MODE 19 1 9 SCL 0 0 0 0 1 X X X 01 0 1 0 0 A0 SDA NO ACK Sr START BY ACK BY MASTER ADC HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE Figure 26. Placing the Part into High Speed Mode CLOCK HIGH TIME = 2µs 11 9 9 SCL 0 100 1 0 A0 R/W 00 D11 D10 D9 D8 SDA ACK BY ACK BY START BY ADC CH CH MASTER ID1 ID0 MASTER FRAME 2 FRAME 1 MOST SIGNIFICANT DATA BYTE FROM ADC SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM ADC Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991 Rev. B | Page 25 of 28 06461-028 06461-030 AD7991/AD7995/AD7999 MODE OF OPERATION The AD7991/AD7995/AD7999 powers up in shutdown mode. second byte of the conversion result. For the AD7991, this After the master addresses the AD7991/AD7995/AD7999 with second byte contains the lower eight bits of conversion data. For 2 the correct I C address, the ADC acknowledges the address. In the AD7995, this second byte contains six bits of conversion response, the AD7991/AD7995/AD7999 power up. data plus two trailing 0s. For the AD7999, this second byte contains four bits of conversion data and four trailing 0s. During this wake up time, the AD7991/AD7995/AD7999 exit shutdown mode and begin to acquire the analog input (acquisition The master then sends a NO ACK to the AD7991/AD7995/ phase). By default, all channels are selected. Which channels AD7999, as long as no further reads are required. If the master are converted depends on the status of the channel bits in the instead sends an ACK to the AD7991/AD7995/AD7999, the configuration register. ADC powers up and completes another conversion. When more than one channel bit has been set in the configuration When the read address is acknowledged, the ADC outputs two register, this conversion is performed on the second channel in bytes of conversion data. The first byte contains four status bits the selected sequence. If only one channel is selected, the ADC and the four MSBs of the conversion result. The status bits converts again on the selected channel. contain two leading 0s and two channel-identifier bits. After this first byte, the AD7991/AD7995/AD7999 outputs the 11 9 9 9 SCL SDA FIRST DATA BYTE SECOND DATA BYTE Sr 7-BIT ADDRESS RA A A Sr/P (MSB) (LSB) ACK. BY ACK. BY NO ACK. BY ADC MASTER MASTER Figure 28. Mode of Operation, Single-Channel Conversion Rev. B | Page 26 of 28 06461-029 AD7991/AD7995/AD7999 OUTLINE DIMENSIONS 3.00 2.90 2.80 8 76 5 3.00 1.70 2.80 1.60 2.60 1.50 12 34 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 0.22 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.60 0.15 MAX 8° 0.45 SEATING 0.60 0.05 MIN 4° 0.38 MAX 0.30 PLANE BSC 0° 0.22 MIN COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 29. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD7991YRJZ-1RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C56 AD7991YRJZ-1500RL7 −40°C to +125°C 8-Lead SOT-23 RJ-8 C56 AD7991YRJZ-0RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C55 AD7991YRJZ-0500RL7 −40°C to +125°C 8-Lead SOT-23 RJ-8 C55 AD7995YRJZ-1RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C58 AD7995YRJZ-1500RL7 −40°C to +125°C 8-Lead SOT-23 RJ-8 C58 AD7995YRJZ-0RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C57 AD7995YRJZ-0500RL7 −40°C to +125°C 8-Lead SOT-23 RJ-8 C57 AD7995ARJZ-0RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C6Y AD7999YRJZ-1RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C5B AD7999YRJZ-1500RL7 −40°C to +125°C 8-Lead SOT-23 RJ-8 C5B AD7999ARJZ-1RL −40°C to +125°C 8-Lead SOT-23 RJ-8 C70 EVAL-AD7991EBZ Evaluation Board EVAL-AD7995EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 27 of 28 121608-A AD7991/AD7995/AD7999 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06461-0-10/10(B) Rev. B | Page 28 of 28