ANALOG DEVICES AD7993

2 4-Channel, 10- and 12-Bit ADCs with I C- Compatible Interface in 16-Lead TSSOP AD7993/AD7994 FEATURES FUNCTIONAL BLOCK DIAGRAM 10- and 12-bit ADC with fast conversion time: 2 µs typ V AGND REF CONVST DD IN 4 single-ended analog input channels AD7993/AD7994 Specified for V of 2.7 V to 5.5 V DD 10-/12-BIT V 1 IN Low power consumption SUCCESSIVE CONTROL T/H APPROXIMATION LOGIC V 2 IN Fast throughput rate: 188 kSPS I/P ADC MUX V 3 IN Temperature range:−40°C to +125°C V 4 OSCILLATOR IN Sequencer operation Automatic cycle interval mode CONVERSION 2 I C®-compatible serial interface DATA LIMIT RESULT LOW REGISTER REGISTER CH1–CH4 2 I C interface supports standard, fast, and high speed modes CONFIGURATION ALERT/ Out-of-range indicator/alert function REGISTER BUSY DATA LIMIT HIGH Pin-selectable addressing via AS REGISTER CH1–CH4 ALERT STATUS Shutdown mode: 1 µA max REGISTER 16-lead TSSOP package HYSTERESIS CYCLE TIMER REGISTER CH1–CH4 See AD7998 and AD7992 for 8-channel and 2-channel REGISTER equivalent devices, respectively. AS SCL 2 I C INTERFACE SDA GENERAL DESCRIPTION AGND The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power, 2 successive approximation ADCs with an I C-compatible inter- Figure 1. face. The parts operate from a single 2.7 V to 5.5 V power On-chip limit registers can be programmed with high and low supply and feature a 2 µs conversion time. The parts contain a limits for the conversion result, and an open-drain, out-of- 4-channel multiplexer and track-and-hold amplifier that can range indicator output (ALERT) becomes active when the handle input frequencies up to 11 MHz. programmed high or low limits are violated by the conversion The AD7993/AD7994 provide a 2-wire serial interface that is result. This output can be used as an interrupt. 2 compatible with I C interfaces. Each part comes in two versions, PRODUCT HIGHLIGHTS AD7993-0/AD7994-0 and AD7993-1/AD7994-1, and each 2 2 1. 2 µs conversion time with low power consumption. version allows for at least two different I C addresses. The I C interface on the AD7993-0/AD7994-0 supports standard and 2 2. I C-compatible serial interface with pin-selectable 2 2 fast I C interface modes. The I C interface on the AD7993-1/ addresses. Two AD7993/AD7994 versions allow five 2 AD7994-1 supports standard, fast, and high speed I C interface AD7993/AD7994 devices to be connected to the same modes. serial bus. The AD7993/AD7994 normally remain in a shutdown state 3. The parts feature automatic shutdown while not converting while not converting, and power up only for conversions. The to maximize power efficiency. Current consumption is conversion process can be controlled using the pin, CONVST 1 µA max when in shutdown mode. 2 by a command mode where conversions occur across I C write 4. Reference can be driven up to the power supply. operations, or an automatic conversion interval mode selected through software control. 5. Out-of-range indicator that can be software disabled or enabled. The AD7993/AD7994 require an external reference that should be applied to the REF pin and can be in the range of 1.2 V to 6. One-shot and automatic conversion rates. IN V . This allows the widest dynamic input range to the ADC. DD 7. Registers can store minimum and maximum conversion results. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03472-0-001 AD7993/AD7994 TABLE OF CONTENTS Serial Interface ................................................................................ 23 AD7993 Specifications..................................................................... 3 Serial Bus Address...................................................................... 23 AD7994 Specifications..................................................................... 5 2 Writing to the AD7993/AD7994 .................................................. 24 I C Timing Specifications................................................................ 7 Writing to the Address Pointer Register for a Subsequent Absolute Maximum Ratings............................................................ 9 Read.............................................................................................. 24 ESD Caution.................................................................................. 9 Writing a Single Byte of Data to the Alert Status Register or Pin Configuration and Pin Function Descriptions.................... 10 Cycle Register.............................................................................. 24 Terminology .................................................................................... 11 Writing Two Bytes of Data to a Limit or Hysteresis Register ........................................................................................ 24 Typical Performance Characteristics ........................................... 12 Reading Data from the AD7993/AD7994................................... 26 Circuit Information........................................................................ 15 Alert/Busy Pin................................................................................. 27 Converter Operation.................................................................. 15 SMBus Alert ................................................................................ 27 Typical Connection Diagram ................................................... 16 Busy.............................................................................................. 27 Analog Input ............................................................................... 16 Placing the AD7993-1/AD7994-1 into High Speed Mode ... 27 Internal Register Structure ............................................................ 18 The Address Select (AS) Pin..................................................... 27 Address Pointer Register ........................................................... 18 Modes of Operation ....................................................................... 28 Configuration Register .............................................................. 19 Mode 1—Using the CONVST Pin ........................................... 28 Conversion Result Register ....................................................... 20 Mode 2—Command Mode....................................................... 29 Limit Registers ............................................................................ 20 Mode 3—Automatic Cycle Interval Mode.............................. 30 Alert Status Register................................................................... 21 Outline Dimensions ....................................................................... 31 Cycle Timer Register.................................................................. 22 Ordering Guide .......................................................................... 31 Sample Delay and Bit Trial Delay............................................. 22 2 Related Parts in I C-Compatible ADC Product Family........ 31 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7993/AD7994 AD7993 SPECIFICATIONS Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7993-0, all specifications apply for fSCL up to 400 kHz. For the AD7993-1, all specs apply for fSCL up to 3.4 MHz, unless otherwise noted. TA = TMIN to TMAX. Table 1. Parameter B Version Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz 2 Signal-to-Noise + Distortion (SINAD) 61 dB min 2 Total Harmonic Distortion (THD) –75 dB max 2 Peak Harmonic or Spurious Noise (SFDR) –76 dB max 2 Intermodulation Distortion (IMD) fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz Second-Order Terms –86 dB typ Third-Order Terms –86 dB typ 2 Aperture Delay 10 ns max 2 Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation -90 dB typ FIN = 108 Hz, see the Terminology section 2 Full-Power Bandwidth 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 1, 2 Integral Nonlinearity ±0.5 LSB max 1, 2 Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 2 Offset Error ±1.5 LSB max Mode 1 (CONVST Mode) ±2.5 LSB max Mode 2 (Command Mode) 2 Offset Error Match ±0.5 LSB max 2 Gain Error ±1.5 LSB max 2 Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REF V IN DC Leakage Current ±1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ±1 µA max Input Impedance 69 kΩ typ During a conversion LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) V min Input Low Voltage, VINL 0.3 (VDD) V max Input Leakage Current, I ±1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, C 10 pF max IN Input Hysteresis, VHYST 0.1(VDD) V min Rev. 0 | Page 3 of 32 AD7993/AD7994 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, V 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD Input Leakage Current, I ±1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ± 1 µA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ f = 100 kHz SCL 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ f = 400 kHz SCL 147 kSPS typ f = 3.4 MHz, 188 kSPS typ @ 5 V SCL POWER REQUIREMENTS V 2.7/5.5 V min/max DD I Digital inputs = 0 V or V DD DD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.3/0.6 mA max V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Operating, Interface Active 0.15/0.4 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 2 Mode 3 (I C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V POWER DISSIPATION Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max V = 3.3 V/5.5 V, 3.4 MHz f Mode 1 DD SCL 2.31/7.7 mW typ V = 3.3 V/5.5 V, 3.4 MHz f Mode 2 DD SCL Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V 1 2 Min/max ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I C high speed mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization. Rev. 0 | Page 4 of 32 AD7993/AD7994 AD7994 SPECIFICATIONS Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V. For the AD7994-0, all specifications apply for fSCL up to 400 kHz. For the AD7994-1, all specs apply for fSCL up to 3.4 MHz, unless otherwise noted. TA = TMIN to TMAX. Table 2. Parameter B Version Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz 2 Signal-to-Noise + Distortion (SINAD) 70.5 dB min 2 Signal-to-Noise Ratio (SNR) 71 dB min 2 Total Harmonic Distortion (THD) –78 dB max 2 Peak Harmonic or Spurious Noise (SFDR) –79 dB max 2 Intermodulation Distortion (IMD) fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for f up to 400 kHz SCL Second-Order Terms –90 dB typ Third-Order Terms –90 dB typ 2 Aperture Delay 10 ns max 2 Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation -90 dB typ FIN = 108 Hz, see the Terminology section 2 Full-Power Bandwidth 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 1, 2 Integral Nonlinearity ±1 LSB max ±0.2 LSB typ 1, 2 Differential Nonlinearity +1/–0.9 LSB max Guaranteed no missed codes to 12 bits ±0.2 LSB typ 2 Offset Error ±4 LSB max Mode 1 (CONVST Mode) ±6 LSB max Mode 2 (Command Mode) 2 Offset Error Match ±1 LSB max 2 Gain Error ±2 LSB max 2 Gain Error Match ±1 LSB max ANALOG INPUT Input Voltage Range 0 to REFINV DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ± 1 µA max Input Impedance 69 kΩ typ During a converison LOGIC INPUTS (SDA, SCL) Input High Voltage, V 0.7 (V ) V min INH DD Input Low Voltage, V 0.3 (V ) V max INL DD Input Leakage Current, I ± 1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, CIN 10 pF max Input Hysteresis, VHYST 0.1 (VDD) V min Rev. 0 | Page 5 of 32 AD7993/AD7994 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, V 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD Input Leakage Current, I ±1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ±1 µA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Serial Interface section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ f = 100 kHz SCL 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ f = 400 kHz SCL 147 kSPS typ f = 3.4 MHz , 188 kSPS typ @ 5 V SCL POWER REQUIREMENTS V 2.7/5.5 V min/max DD I Digital inputs = 0 V or V DD DD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.3/0.6 mA max V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Operating, Interface Active 0.15/0.4 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 2 Mode 3 (I C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V POWER DISSIPATION Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max V = 3.3 V/5.5 V, 3.4 MHz f Mode 1 DD SCL 2.31/7.7 mW typ V = 3.3 V/5.5 V, 3.4 MHz f Mode 2 DD SCL Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V 1 2 Min/max AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I C high speed mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization. Rev. 0 | Page 6 of 32 AD7993/AD7994 2 I C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and tf measured between 0.3 VDD and 0.7 VDD. High speed mode timing specifications apply to the AD7993-1/AD7994-1 only. Standard and fast mode timing specifications apply to both the AD7993-0/AD7994-0 and the AD7993-1/AD7994-1. See Figure 2. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; TA =TMIN to TMAX. Table 3. AD7993/AD7994 Limit at T , T MIN MAX Parameter Conditions Min Max Unit Description fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode C = 100 pF max 3.4 MHz B CB = 400 pF max 1.7 MHz t Standard mode 4 µs t , SCL high time 1 HIGH Fast mode 0.6 µs High speed mode CB = 100 pF max 60 ns CB = 400 pF max 120 ns t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs High speed mode C = 100 pF max 160 ns B C = 400 pF max 320 ns B t Standard mode 250 ns t , data setup time 3 SU;DAT Fast mode 100 ns High speed mode 10 ns 1 t Standard mode 0 3.45 µs t , data hold time 4 HD;DAT Fast mode 0 0.9 µs High speed mode 2 CB = 100 pF max 0 70 ns CB = 400 pF max 0 150 ns t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs High speed mode 160 ns t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs High speed mode 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode C = 100 pF max 10 80 ns B C = 400 pF max 20 160 ns B Rev. 0 | Page 7 of 32 AD7993/AD7994 AD7993/AD7994 Limit at T , T MIN MAX Parameter Conditions Min Max Unit Description t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode C = 100 pF max 10 80 ns B C = 400 pF max 20 160 ns B t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 20 + 0.1 C 300 ns B High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 20 + 0.1 CB 300 ns High speed mode C = 100 pF max 10 80 ns B C = 400 pF max 20 160 ns B t Standard mode 300 ns t , fall time of SCL signal 12 FCL Fast mode 20 + 0.1 C 300 ns B High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns 2 t Fast mode 0 50 ns Pulse width of suppressed spike SP High speed mode 0 10 ns t 1 typ µs Power-up time POWER-UP 1 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 2 For 3 V supplies, the maximum hold time with C = 100 pF max is 100 ns max. B t 11 t 12 t t 2 6 SCL t t 6 t t t 5 8 4 3 t 1 t 9 t 10 SDA t 7 S S P P S = START CONDITION P = STOP CONDITION Figure 2. Two-Wire Serial Interface Timing Diagram Rev. 0 | Page 8 of 32 03472-0-002 AD7993/AD7994 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to 7 V DD rating only; functional operation of the device at these or any Analog Input Voltage to GND −0.3 V to V + 0.3 V DD other conditions above those listed in the operational sections Reference Input Voltage to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to VDD + 0.3 V device reliability. 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +125°C Storage Temperature Range −65°C to +150° Junction Temperature 150°C 20-Lead TSSOP θ Thermal Impedance 150.4°C/W JA θ Thermal Impedance 27.6°C/W JC Pb/SN Temperature, Soldering Reflow (10 s to 30 s) 240(+0/-5)°C Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 32 AD7993/AD7994 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS AGND 1 16 AGND AGND SCL 2 15 AD7993/ AGND 3 14 SDA AD7994 ALERT/BUSY AGND 4 13 TOP VIEW V (Not to Scale) CONVST DD 5 12 REF 6 11 AS IN V 1 V 2 IN 7 10 IN V 4 V 3 8 9 IN IN Figure 3. 16-Lead TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Function 1, 2, 3, 4, 16 AGND Analog Ground. Ground reference point for all circuitry on the AD7993/AD7994. All analog input signals should be referred to this AGND voltage. 5 V Power Supply Input. The V range for the AD7993/AD7994 is from 2.7 V to 5.5 V. DD DD 6 REF Voltage Reference Input. The external reference for the AD7993/AD7994 should be applied to this input pin. IN The voltage range for the external reference is 1.2 V to VDD. A 0.1 µF and 1 µF capacitor should be placed between REFIN and AGND. See Figure 22. 7 VIN1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN. 8 V 3 Analog Input 3. Single-ended analog input channel. The input range is 0 V to REF . IN IN 9 V 4 Analog Input 4. Single-ended analog input channel. The input range is 0 V to REF . IN IN 10 V 2 Analog Input 2. Single-ended analog input channel. The input range is 0 V to REF . IN IN 2 11 AS Logic Input. Address select input that selects one of three I C addresses for the AD7993/AD7994, as shown in Table 6. The device address depends on the voltage applied to this pin. 12 CONVST Logic Input Signal/Convert Start Signal. This is an edge-triggered logic input. The rising edge of this signal powers up the part. The power-up time for the part is 1 µs. The falling edge of CONVST places the track/hold into hold mode and initiates a conversion. A power-up time of at least 1 µs must be allowed for the CONVST high pulse; otherwise, the conversion result is invalid (see the Modes of Operation section). 13 ALERT/BUSY Digital Output, Selectable as an ALERT or BUSY Output Function. When configured as an ALERT, this pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATA register values. See the Limit Registers section. When configured as a BUSY output, this pin LOW becomes active when a conversion is in progress. Open-drain output. 14 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 15 SCL Digital Input. Serial bus clock. External pull-up resistor required. 2 Table 6. I C Address Selection 2 Part Number AS Pin I C Address AD7993-0 GND 010 0001 AD7993-0 V 010 0010 DD AD7993-1 GND 010 0011 AD7993-1 V 010 0100 DD 1 AD7993-x Float 010 0000 AD7994-0 GND 010 0001 AD7994-0 VDD 010 0010 AD7994-1 GND 010 0011 AD7994-1 V 010 0100 DD AD7994-x1 Float 010 0000 1 If the AS pin is left floating on any of the AD7993/AD7994 parts, the device address is 010 0000. Rev. 0 | Page 10 of 32 03472-0-003 AD7993/AD7994 TERMINOLOGY Signal-to-Noise and Distortion Ratio (SINAD) Channel-to-Channel Isolation The measured ratio of signal-to-noise and distortion at the out- A measure of the level of crosstalk between channels, taken put of the A/D converter. The signal is the rms amplitude of the by applying a full-scale sine wave signal to the unselected input fundamental. Noise is the sum of all nonfundamental signals up channels, and determining how much the 108 Hz signal is to half the sampling frequency (f /2), excluding dc. The ratio is attenuated in the selected channel. The sine wave signal applied S dependent on the number of quantization levels in the digiti- to the unselected channels is then varied from 1 kHz up to zation process; the more levels, the smaller the quantization 2 MHz, each time determining how much the 108 Hz signal in noise. The theoretical signal-to-noise and distortion ratio for the selected channel is attenuated. This figure represents the an ideal N-bit converter with a sine wave input is given by worst-case level across all channels. Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Aperture Delay The measured interval between the sampling clock’s leading Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB edge and the point at which the ADC takes the sample. for a 12-bit converter. Aperture Jitter Total Harmonic Distortion (THD) The sample-to-sample variation in the effective point in time at The ratio of the rms sum of harmonics to the fundamental. For which the sample is taken. the AD7993/AD7994, it is defined as Full-Power Bandwidth 2 2 2 2 2 V2 +V3 +V4 +V5 +V6 The input frequency at which the amplitude of the reconstructed THD (dB)= 20 log V1 fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. where V1 is the rms amplitude of the fundamental and V2, V3, Power Supply Rejection Ratio (PSRR) V4, V5, and V6 are the rms amplitudes of the second through The ratio of the power in the ADC output at the full-scale sixth harmonics. frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V supply of frequency f : DD S Peak Harmonic or Spurious Noise PSRR (dB) = 10 log (Pf/Pf ) The ratio of the rms value of the next largest component in the S ADC output spectrum (up to f /2 and excluding dc) to the rms S where Pf is the power at frequency f in the ADC output; PfS is value of the fundamental. Typically, the value of this specification the power at frequency fS coupled onto the ADC VDD supply. is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a Integral Nonlinearity noise peak. The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are Intermodulation Distortion zero scale, a point 1 LSB below the first code transition, and full With inputs consisting of sine waves at two frequencies, fa scale, a point 1 LSB above the last code transition. and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, Differential Nonlinearity where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion The difference between the measured and the ideal 1 LSB terms are those for which neither m nor n equal zero. For change between any two adjacent codes in the ADC. example, second-order terms include (fa + fb) and (fa − fb), Offset Error while third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) The deviation of the first code transition (00…000) to and (fa − 2fb). (00…001) from the ideal—that is, AGND + 1 LSB. The AD7993/AD7994 is tested using the CCIF standard where Offset Error Match two input frequencies near the top end of the input bandwidth The difference in offset error between any two channels. are used. In this case, the second-order terms are usually dis- tanced in frequency from the original sine waves while the Gain Error third-order terms are usually at a frequency close to the input The deviation of the last code transition (111…110) to frequencies. As a result, the second and third-order terms are (111…111) from the ideal (that is, REF − 1 LSB) after the IN specified separately. The calculation of intermodulation distor- offset error has been adjusted out. tion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the Gain Error Match sum of the fundamentals, expressed in dB. The difference in gain error between any two channels. Rev. 0 | Page 11 of 32 AD7993/AD7994 TYPICAL PERFORMANCE CHARACTERISTICS 75 0 V = 5.5V DD FS = 121kSPS V = 5V DD FSCL = 3.4MHz 70 FIN = 10kHz –20 SNR = 71.84dB SINAD = 71.68dB V = 4.5V DD 65 THD = 86.18dB –40 SFDR = –88.70dB V = 3V DD 60 V = 3.3V DD –60 55 V = 2.7V DD –80 50 –100 45 40 –120 1 10 100 1000 06 20 400 FREQUENCY (kHz) FREQUENCY (kHz) Figure 4. AD7994 Dynamic Performance with 5 V Supply and Figure 7. AD7994 SINAD vs. Analog Input Frequency for 2.5 V Reference, 121 kSPS, Mode 1 Various Supply Voltages, 3.4 MHz fSCL, 136 kSPS 1.0 FS = 121kSPS FSCL = 3.4MHz –10 0.8 FIN = 10kHz SINAD = 61.63dB 0.6 THD = 91.82dB –30 SFDR = –94.95dB 0.4 0.2 –50 0 –0.2 –70 –0.4 –0.6 –90 –0.8 –110 –1.0 06 10 20 30 40 500 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (kHz) CODE Figure 5. AD7993 Dynamic Performance with 5 V Supply and Figure 8. AD7994 Typical INL, V = 5.5 V, Mode 1, 3.4 MHz f , 121 kSPS DD SCL 2.5 V Reference, 121 kSPS, Mode 1 100 1.0 V = 5V DD 0.8 90 V = 3V DD 0.6 80 0.4 70 0.2 60 0 –0.2 50 –0.4 40 –0.6 V = 3V/5V DD 200mV p-p SINE WAVE  30 –0.8 ON V DD 2nF CAPACITOR ON V DD 20 –1.0 10 100 1000 0 500 1000 1500 2000 2500 3000 3500 4000 SUPPLY RIPPLE FREQUENCY(kHz) CODE Figure 6. PSRR vs. Supply Ripple Frequency Figure 9. AD7994 Typical DNL, V = 5.5 V, Mode 1, 3.4 MHz f , 121 kSPS DD SCL Rev. 0 | Page 12 of 32 PSRR (dB) SINAD (dB) SINAD (dB) 03473-0-006 03473-0-005 03473-0-004 DNL ERROR (LSB) INL ERROR (LSB) SINAD (dB) 03473-0-009 03473-0-008 03473-0-007 AD7993/AD7994 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 POSITIVE DNL 0.2 0.2 0 0 –0.2 –0.2 NEGATIVE DNL –0.4 –0.4 –0.6 -0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 CODE REFERENCE VOLTAGE (V) Figure 10. Typical INL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS Figure 13. AD7994 Change in DNL vs. Reference Voltage VDD = 5 V, Mode 1, 121 kSPS 1.0 0.0007 0.8 0.0006 0.6 0.4 0.0005 –40°C 0.2 0.0004 +25°C 0 0.0003 –0.2 +85°C –0.4 0.0002 –0.6 0.0001 –0.8 –1.0 0 0 500 1000 1500 2000 2500 3000 3500 4000 2.7 3.2 3.7 4.2 4.7 5.2 CODE SUPPLY VOLTAGE (V) Figure 11. AD7994 Typical DNL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS Figure 14. AD7994 Shutdown Current vs. Supply Voltage, –40°C, +25°C, and +85°C 2.0 1.0 1.8 0.8 1.6 0.6 1.4 0.4 POSITIVE INL MODE 2 1.2 0.2 V = 5V DD 1.0 0 MODE 2 0.8 –0.2 V = 3V NEGATIVE INL DD MODE 1 –0.4 0.6 V = 5V DD 0.4 -0.6 MODE 1 0.2 –0.8 V = 3V DD –1.0 0 100 600 1100 1600 2100 2600 3100 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V) SCL FREQUENCY (kHz) 2 Figure 12. AD7994 Change in INL vs. Reference Voltage V = 5 V, DD Figure 15. AD7994 Average Supply Current vs. I C Bus Rate for Mode 1, 121 kSPS V = 3 V and 5 V DD Rev. 0 | Page 13 of 32 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 03473-0-011 03473-0-010 03473-0-012 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) DNL ERROR (LSB) 03473-0-015 03473-0-013 03472-0-014 AD7993/AD7994 2.0 12.0 74 TEMPERATURE = +85°C ENOB V = 5V DD 1.8 TEMPERATURE = +25°C 11.8 TEMPERATURE = –40°C ENOB V = 3V DD 73 1.6 TEMPERATURE = +85°C TEMPERATURE = +25°C 11.6 SINAD V = 5V DD MODE 2 - 147kSPS 1.4 TEMPERATURE = –40°C 72 11.4 1.2 1.0 11.2 71 MODE 1 - 121kSPS SINAD V = 3V DD 0.8 11.0 70 0.6 10.8 0.4 69 10.6 0.2 0 10.4 68 2.7 3.2 3.7 4.2 4.7 5.2 1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 16. AD7994 Average Supply Current vs. Supply Voltage Figure 17. AD7994 SINAD/ENOB vs. Reference Voltage, for Various Temperatures Mode 1, 121 kSPS Rev. 0 | Page 14 of 32 SUPPLY CURRENT (mA) 03473-0-016 ENOB (BITS) SINAD (dB) 03473-0-017 AD7993/AD7994 CIRCUIT INFORMATION The AD7993/AD7994 are low power, 10- and 12-bit, single- When the ADC starts a conversion, as shown in Figure 19, SW2 supply, 4-channel A/D converters, respectively. The parts can opens and SW1 moves to Position B, causing the comparator to be operated from a 2.7 V to 5.5 V supply. become unbalanced. The input is disconnected once the con- version begins. The control logic and the capacitive DAC are The AD7993/AD7994 provide the user with a 4-channel used to add and subtract fixed amounts of charge from the multiplexer, an on-chip track-and-hold, an A/D converter, an sampling capacitor to bring the comparator back into a 2 on-chip oscillator, internal data registers, and an I C-compatible balanced condition. When the comparator is rebalanced, the serial interface, all housed in a 16-lead TSSOP package that conversion is complete. The control logic generates the ADC offers the user considerable space-saving advantages over output code. Figure 20 shows the ADC transfer function. alternative solutions. The AD7993/AD7994 require an external reference in the range of 1.2 V to VDD. CAPACITIVE DAC The AD7993/AD7994 normally remain in a power-down state while not converting. When supplies are first applied, the parts A V IN CONTROL come up in a power-down state. Power-up is initiated prior to SW1 LOGIC B a conversion, and the device returns to shutdown upon com- SW2 COMPARATOR pletion of the conversion. Conversions can be initiated on the AGND AD7993/AD7994 by pulsing the signal, using an CONVST Figure 19. ADC Conversion Phase automatic cycle interval mode, or using a command mode where wake-up and a conversion occurs during a write address function (see the Modes of Operation section). When the con- ADC Transfer Function version is complete, the AD7993/AD7994 again enter shutdown The output coding of the AD7993/AD7994 is straight binary. mode. This automatic shut-down feature allows power saving The designed code transitions occur at successive integer LSB between conversions. Any read or write operations across the values—that is, 1 LSB, 2 LSB, and so on. The LSB size is 2 I C interface can occur while the devices are in shutdown. REF /1024 for the AD7993 and REF /4096 for the AD7994. IN IN Figure 20 shows the ideal transfer characteristic for the CONVERTER OPERATION AD7993/AD7994. The AD7993/AD7994 are successive approximation analog-to- digital converters based around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of an ADC during the 111...111 111...110 acquisition and conversion phase, respectively. Figure 18 shows an ADC during the acquisition phase. SW2 is closed and SW1 111...000 is in Position A. The comparator is held in a balanced condition 011...111 and the sampling capacitor acquires the signal on V x. IN AD7993 1LSB = REF /1024 IN 000...010 AD7994 1LSB = REF /4096 IN CAPACITIVE 000...001 DAC 000...000 AGND + 1LSB +REF – 1LSB IN A ANALOG INPUT V 0V TO REF IN IN CONTROL SW1 LOGIC B Figure 20. AD7993/AD7994 Transfer Characteristic SW2 COMPARATOR AGND Figure 18. ADC Acquisition Phase Rev. 0 | Page 15 of 32 03472-0-018 ADC CODE 03472-0-020 03472-0-019 AD7993/AD7994 TYPICAL CONNECTION DIAGRAM ANALOG INPUT Figure 22 shows the typical connection diagram for the AD7993/ Figure 21 shows an equivalent circuit of the AD7993/AD7994’s AD7994. In Figure 22 the address select pin (AS) is tied to VDD; analog input structure. The two diodes, D1 and D2, provide however, AS can also be tied to AGND or left floating, allowing ESD protection for the analog inputs. Care must be taken to the user to select up to five AD7993/AD7994 devices on the ensure that the analog input signal does not exceed the supply same serial bus. An external reference must be applied to the rails by more than 300 mV. This causes these diodes to become AD7993/AD7994. This reference can be in the range of 1.2 V to forward biased and start conducting current into the substrate. VDD. A precision reference like the REF 19x family, AD780, These diodes can conduct a maximum current of 10 mA ADR03, or ADR381 can be used to supply the reference voltage without causing irreversible damage to the part. to the ADC. V DD 2 SDA and SCL form the 2-wire I C/SMBus-compatible inter- face. External pull-up resisters are required for both SDA and D1 SCL lines. C2 30pF R1 2 V IN The AD7993-0/AD7994-0 support standard and fast I C C1 interface modes. The AD7993-1/AD7994-1 support standard, D2 4pF 2 fast, and high speed I C interface modes. Therefore, if operating CONVERSION PHASE—SWITCH OPEN the AD7993/AD7994 in either standard or fast mode, up to five TRACK PHASE—SWITCH CLOSED AD7993/AD7994 devices can be connected to the bus as noted: Figure 21. Equivalent Analog Input Circuit 3 × AD7993-0/AD7994-0 and 2 × AD7993-1/ AD7994-1 Capacitor C1 in Figure 21 is typically about 4 pF and primarily or can be attributed to pin capacitance. Resistor R1 is a lumped 3 × AD7993-1/AD7994-1 and 2 × AD7994-0/AD7993-0 component made up of the on resistance (R ) of a switch ON In high speed mode, up to three AD7993-1/AD7994-1 devices (track-and-hold switch), and also includes the R of the input ON can be connected to the bus. multiplexer. The total resistor is typically about 400 Ω. C2, the ADC sampling capacitor, has a typical capacitance of 30 pF. Wake-up from shutdown prior to a conversion is approximately 1 µs, and conversion time is approximately 2 µs. The AD7993/ AD7994 enter shutdown mode again after each conversion, which is useful in applications where power consumption is a concern. 5V SUPPLY 10µF 0.1µF 2-WIRE SERIAL INTERFACE R R R P P P V 1 V DD IN SDA 0V to REF IN INPUT AD7993/ SCL µC/µP V 4 AD7994 IN ALERT CONVST V GND REF 19x REF AS DD IN 0.1µF 1µF Figure 22. AD7993/AD7994 Typical Connection Diagram Rev. 0 | Page 16 of 32 03472-0-021 03472-0-022 AD7993/AD7994 –40 For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC band- –50 pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, V = 3V DD –60 the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac –70 V = 3.3V performance of the ADC. This may necessitate the use of an DD V = 2.7V DD input buffer amplifier. The choice of the op amp is a function of –80 the particular application. V = 4.5V DD V = 5.5V DD V = 5V –90 DD When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum –100 source impedance depends on the amount of total harmonic 10 100 1000 distortion (THD) that can be tolerated. THD increases as INPUT FREQUENCY(kHz) the source impedance increases, and performance degrades. Figure 23. THD vs. Analog Input Frequency for Various Figure 23 shows the THD vs. the analog input signal frequency Supply Voltages, F = 136 kSPS, Mode 1 S when using supply voltages of 3 V ± 10% and 5 V ± 10%. Figure 24 shows the THD vs. the analog input signal frequency –40 for different source impedances. V = 5V DD –50 R = 1000Ω IN –60 –70 R = 100Ω IN –80 R = 50Ω IN R = 10Ω –90 IN –100 10 100 1000 INPUT FREQUENCY(kHz) Figure 24. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V, 136 kSPS, Mode 1 Rev. 0 | Page 17 of 32 THD (dB) THD (dB) 03472-0-023 03472-0-024 AD7993/AD7994 INTERNAL REGISTER STRUCTURE The AD7993/AD7994 contain 17 internal registers (see ADDRESS POINTER REGISTER Figure 25) that are used to store conversion results, high and Because it is the register to which the first data byte of every low conversion limits, and information to configure and control write operation is written automatically, the address pointer the device. Sixteen are data registers and one is an address register does not have and does not require an address. The pointer register. address pointer register is an 8-bit register in which the 4 LSBs are used as pointer bits to store an address that points to one of Each data register has an address that the address pointer the AD7993/AD7994’s data registers. The 4 MSBs are used as register points to when communicating with it. The conversion command bits when operating in Mode 2 (see the Modes of result register is the only data register that is read only. Operation section). The first byte following each write address is the address of one of the data registers, which is stored in the CONVERSION address pointer register and selects the data register to which RESULT REGISTER subsequent data bytes are written. Only the 4 LSBs of this ALERT STATUS register are used to select a data register. On power-up, the REGISTER address pointer register contains all 0s, pointing to the CONFIGURATION conversion result register. REGISTER Table 7. Address Pointer Register CYCLE TIMER REGISTER C4 C3 C2 C1 P3 P2 P1 P0 DATA LOW 0 0 0 0 Register Select REGISTER CH1 DATA HIGH REGISTER CH1 D Table 8. AD7993/AD7994 Register Addresses HYSTERESIS A P3 P2 P1 P0 Registers REGISTER CH1 T 0 0 0 0 Conversion Result Register (Read) DATA ADDRESS LOW A POINTER REGISTER CH2 0 0 0 1 Alert Status Register (Read/Write) REGISTER DATA 0 0 1 0 Configuration Register (Read/Write) HIGH REGISTER CH2 0 0 1 1 Cycle Timer Register (Read/Write) HYSTERESIS 0 1 0 0 DATALOW Reg CH1 (Read/Write) REGISTER CH2 0 1 0 1 DATAHIGH Reg CH1 (Read/Write) DATA LOW 0 1 1 0 Hysteresis Reg CH1 (Read/Write) REGISTER CH3 0 1 1 1 DATA Reg CH2 (Read/Write) LOW DATA HIGH 1 0 0 0 DATA Reg CH2 (Read/Write) REGISTER CH3 HIGH 1 0 0 1 Hysteresis Reg CH2 (Read/Write) HYSTERESIS REGISTER CH3 1 0 1 0 DATALOW Reg CH3 (Read/Write) DATA 1 0 1 1 DATAHIGH Reg CH3 (Read/Write) LOW REGISTER CH4 1 1 0 0 Hysteresis Reg CH3 (Read/Write) DATA HIGH 1 1 0 1 DATA Reg CH4 (Read/Write) LOW REGISTER CH4 1 1 1 0 DATA Reg CH4 (Read/Write) HIGH HYSTERESIS REGISTER CH4 1 1 1 1 Hysteresis Reg CH4 (Read/Write) SDA SERIAL BUS INTERFACE SCL Figure 25. AD7993/AD7994 Register Structure Rev. 0 | Page 18 of 32 03472-0-025 AD7993/AD7994 CONFIGURATION REGISTER The configuration register is an 8-bit read/write register that is used to set the operating modes of the AD7993/AD7994. The bit functions are outlined in Table 9. A single-byte write is necessary when writing to the configuration register. Table 9. Configuration Register Bit Function Descriptions and Default Settings at Power-Up D7 D6 D5 D4 D3 D2 D1 D0 CH4 CH3 CH2 CH1 FLTR ALERT EN BUSY/ALERT ALERT/BUSY POLARITY 0 0 0 0 1 0 0 0 Table 10. Bit Function Descriptions Bit Mnemonic Comment D7 to D4 CH4 to CH1 These 4-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D7 to D4 selects a channel for conversion. If more than one channel bit is set to 1, the AD7993/AD7994 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11 shows how these 4-channel address bits are decoded. Prior to initiating a conversion, the channel(s) must be selected in the configuration register. D3 FLTR The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed. D2 ALERT EN The hardware ALERT function is enabled if this bit is set to 1 and disabled if this bit is set to 0. This bit is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin act as an ALERT or a BUSY output (see Table 12). D1 BUSY/ALERT This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/BUSY output, Pin 13, acts as an ALERT or BUSY output (see Table 12), and if Pin 13 is configured as an ALERT output pin, if it is to be reset. D0 BUSY/ALERT This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an POLARITY ALERT or BUSY output. It is active low if this bit is set to 0, and active high if it is set to 1. Table 11. Channel Selection D7 D6 D5 D4 Analog Input Channel Comments 0 0 0 0 No channel selected; see address pointer byte, Mode 2. 0 0 0 1 Convert on V 1. IN 0 0 1 0 Convert on V 2. IN 0 0 1 1 Sequence between V 1 and V 2. IN IN 0 1 0 0 Convert on VIN3. 0 1 0 1 Sequence between VIN1 and VIN3. 0 1 1 0 Sequence between VIN2 and VIN3. The AD7993/AD7994 convert on the selected channel in the sequence in ascending order, starting with the 0 1 1 1 Sequence between V 1, V 2, and V 3. IN IN IN lowest channel in the sequence. 1 0 0 0 Convert on V 4. IN 1 0 0 1 Sequence between VIN1 and VIN4. 1 0 1 0 Sequence between VIN2 and VIN4. 1 0 1 1 Sequence between VIN1, VIN2, and VIN4. 1 1 0 0 Sequence between V 3 and V 4. IN IN 1 1 0 1 Sequence between V 1, V 3, and V 4. IN IN IN 1 1 1 0 Sequence between V 2, V 3, and V 4. IN IN IN 1 1 1 1 Sequence between VIN1, VIN2, VIN3, and VIN4. Table 12. Alert/Busy Function D2 D1 ALERT/BUSY Pin Configuration 0 0 Pin does not provide any interrupt signal. 0 1 Pin configured as a busy output. 1 0 Pin configured as an alert output. 1 1 Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register (if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit, and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back. Rev. 0 | Page 19 of 32 AD7993/AD7994 DATA Register CH1/CH2/CH3/CH4 CONVERSION RESULT REGISTER HIGH The DATAHIGH registers for each channel are 16-bit read/write The conversion result register is a 16-bit read-only register that registers; only the 12 LSBs of each register are used. This stores the conversion result from the ADC in straight binary register stores the upper limit that activates the alert output format. A 2-byte read is necessary to read data from this and/or the Alert_Flag bit in the conversion result register. If the register. Table 13 shows the contents of the first byte to be read value in the conversion result register for a channel is greater from the AD7993/AD7994 and Table 14 shows the contents of than the value in the DATA register for that channel, an the second byte to be read. HIGH alert occurs. When the conversion result returns to a value at Table 13. Conversion Value Register (First Read) least N LSB below the DATA register value, the ALERT HIGH D15 D14 D13 D12 D11 D10 D9 D8 output pin and Alert_Flag bit are reset. The value of N is taken Alert_Flag Zero CH CH MSB B10 B9 B8 ID1 ID0 from the hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bits D2 and D1 in the Table 14. Conversion Value Register (Second Read) configuration register. For the AD7993, D1 and D0 of the D7 D6 D5 D4 D3 D2 D1 D0 DATA register should contain 0s. HIGH B7 B6 B5 B4 B3 B2 B1/0 B0/0 Table 16. DATA Register (First Read/Write) HIGH D15 D14 D13 D12 D11 D10 D9 D8 The conversion result of the AD7993/AD7994 consists of an 0 0 0 0 B11 B10 B9 B8 Alert_Flag bit, a zero bit, two channel identifier bits, and the 10- and 12-bit data result. For the AD7993, the 2 LSB (D1 and Table 17. DATAHIGH Register (Second Read/Write) D0) of the second read contain two trailing 0s. D7 D6 D5 D4 D3 D2 D1 D0 The Alert_Flag bit indicates whether the conversion result B7 B6 B5 B4 B3 B2 B1 B0 being read or any other channel result has violated the limit registers associated with it. If an alert occurs, the master may DATA Register CH1/CH2/CH3/CH4 LOW wish to read the alert status register to obtain more information on where the alert occurred if the Alert_Flag bit is set. The DATA register for each channel is a 16-bit read/write LOW register; only the 12 LSBs of each register are used. The register The Alert_Flag bit is followed by a zero bit and two channel stores the lower limit that activates the ALERT output and/or identifier bits that indicate which channel the conversion result the Alert_Flag bit in the conversion result register. If the value corresponds to. These, in turn, are followed by the 10- bit and in the conversion result register for a channel is less than the 12-bit conversion result, MSB first. value in the DATA register for that channel, an ALERT LOW occurs. When the conversion result returns to a value at least N Table 15. Channel Identifier Bits LSB above the DATA register value, the ALERT output pin Alert_Flag Zero CH CH Channel No. Result LOW ID1 ID0 and Alert_Flag bit are reset. The value of N is taken from the 0/1 0 0 0 Channel 1 (V 1) IN hysteresis register associated with that channel. The ALERT 0/1 0 0 1 Channel 2 (V 2) IN output pin can also be reset by writing to Bits D2 and D1 in the 0/1 0 1 0 Channel 3 (V 3) IN configuration register. For the AD7993, D1 to D0 of the 0/1 0 1 1 Channel 4 (VIN4) DATA register should contain 0s. LOW LIMIT REGISTERS Table 18. DATA Register (First Read/Write) LOW The AD7993/AD7994 have four pairs of limit registers. Each D15 D14 D13 D12 D11 D10 D9 D8 pair stores high and low conversion limits for each analog 0 0 0 0 B11 B10 B9 B8 input channel. Each pair of limit registers has one associated hysteresis register. All 12 registers are 16 bits wide; only the Table 19. DATALOW Register (Second Read/Write) 12 LSBs of the registers are used for the AD7993/AD7994. For D7 D6 D5 D4 D3 D2 D1 D0 the AD7993, the 2 LSBs, D1 and D0, should contain 0s. On B7 B6 B5 B4 B3 B2 B1 B0 power-up, the contents of the DATAHIGH register for each channel is full scale, while the contents of the DATALOW registers is zero scale by default. The AD7993/AD7994 signal an alert (in either hardware, software, or both, depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers. Rev. 0 | Page 20 of 32 AD7993/AD7994 ALERT STATUS REGISTER Hysteresis Register (CH1/CH2/CH3/CH4) Each hysteresis register is a 16-bit read/write register, of which The alert status register is an 8-bit read/write register that provides information on an alert event. If a conversion results in only the 12 LSBs of the register are used. The hysteresis register activating the ALERT pin or the Alert_Flag bit in the stores the hysteresis value, N, when using the limit registers. conversion result register, as described in the Limit Registers Each pair of limit registers has a dedicated hysteresis register. section, the alert status register may be read to gain further The hysteresis value determines the reset point for the ALERT information. It contains two status bits per channel, one pin/Alert_Flag if a violation of the limits has occurred. For example, if a hysteresis value of 8 LSB is required on the upper corresponding to the DATAHIGH limit and the other to the and lower limits of Channel 1, the 12-bit word, 0000 0000 0000 DATALOW limit. The bit with a status of 1 shows where the violation occurred—that is, on which channel—and whether 1000, should be written to the hysteresis register of CH1, the the violation occurred on the upper or lower limit. If a second address of which is shown in Table 8. On power-up, the alert event occurs on the other channel between receiving the hysteresis registers contain a value of 8 LSB for the AD7994 and first alert and interrogating the alert status register, the 2 LSB for the AD7993. If a different hysteresis value is required, corresponding bit for that alert event is also set. that value must be written to the hysteresis register for the channel in question. For the AD7993, D1 and D0 of the The entire contents of the alert status register may be cleared by hysteresis register should contain 0s. writing 1, 1 to Bits D2 and D1 in the configuration register, as shown in Table 12. This may also be achieved by writing all 1s Table 20. Hysteresis Register (First Read/Write) to the alert status register itself. Therefore, if the alert status D15 D14 D13 D12 D11 D10 D9 D8 register is addressed for a write operation, which is all 1s, the 0 0 0 0 B11 B10 B9 B8 contents of the alert status register are cleared or reset to all 0s. Table 22. Alert Status Register Table 21. Hysteresis Register (Second Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CH4HI CH4LO CH3HI CH3LO CH2HI CH2LO CH1HI CH1LO B7 B6 B5 B4 B3 B2 B1 B0 Using the Limit Registers to Store Min/Max Conversion Results for CH1 to CH4 Table 23. Alert Status Register Bit Function Descriptions Bit Mnemonic Comment If full scale, that is, all 1s, is written to the hysteresis register for D0 CH1 Violation of DATA limit on Channel 1 if a particular channel, the DATA and DATA registers for LO LOW HIGH LOW this bit set to 1, no violation if bit is set to 0. that channel no longer act as limit registers as previously D1 CH1 HI Violation of DATAHIGH limit on Channel 1 if described, but instead act as storage registers for the maximum this bit set to 1, no violation if if bit is set to 0. and minimum conversion results returned from conversions on D2 CH2LO Violation of DATALOW limit on Channel 2 if a channel over any given period of time. This function is useful this bit set to 1, no violation if if bit is set to 0. in applications where the widest span of actual conversion D3 CH2 Violation of DATA limit on Channel 2 if HI HIGH results is required rather than using the alert to signal that an this bit set to 1, no violation if if bit is set to 0. intervention is necessary. This function could be useful for D4 CH3LO Violation of DATALOW limit on Channel 3 if monitoring temperature extremes during refrigerated goods this bit set to 1, no violation if if bit is set to 0. transportation. D5 CH3HI Violation of DATAHIGH limit on Channel 3 if this bit set to 1, no violation if if bit is set to 0. It must be noted that on power-up, the contents of the D6 CH4 Violation of DATA limit on Channel 4 if LO LOW DATAHIGH register for each channel are full scale, while the this bit set to 1, no violation if if bit is set to 0. contents of the DATALOW registers are zero scale by default. D7 CH4HI Violation of DATAHIGH limit on Channel 4 if Therefore, minimum and maximum conversion values being this bit set to 1, no violation if if bit is set to 0. stored in this way are lost if power is removed or cycled. Rev. 0 | Page 21 of 32 AD7993/AD7994 CYCLE TIMER REGISTER SAMPLE DELAY AND BIT TRIAL DELAY 2 The cycle timer register is an 8-bit read/write register that stores It is recommended that no I C bus activity occur when a the conversion interval value for the automatic cycle interval conversion is taking place. However, if this is not possible, for mode of the AD7993/AD7994 (see the Modes of Operation example when operating in Mode 2 or Mode 3, then in order to section). D5 to D3 of the cycle timer register are unused and maintain the performance of the ADC, Bits D7 and D6 in the should contain 0s at all times. On power-up, the cycle timer cycle timer register are used to delay critical sample intervals 2 register contains all 0s, thus disabling automatic cycle operation and bit trials from occurring while there is activity on the I C of the AD7993/AD7994. To enable automatic cycle mode, the bus. This results in a quiet period for each bit decision. In user must write to the cycle timer register, selecting the required certain cases where there is excessive activity on the interface conversion interval. Table 24 shows the structure of the cycle lines, this may have the effect of increasing the overall timer register while Table 25 shows how the bits in this register conversion time. However, if bit trial delays extend longer than are decoded to provide various automatic sampling intervals. 1 µs, the conversion terminates. Table 24. Cycle Timer Register and Default Power-Up Settings When Bits D7 and D6 are both 0, the bit trial and sample D7 D6 D5 D4 D3 D2 D1 D0 interval delaying mechanism is implemented. The default Sample Bit Trial Cyc Cyc Cyc setting of D7 and D6 is 0. To turn off both delay mechanisms, 0 0 0 Delay Delay Bit2 Bit1 Bit0 set D7 and D6 to 1. 0 0 0 0 0 0 0 0 Table 26. Cycle Timer Register and Defaults at Power-Up D7 D6 D5 D4 D3 D2 D1 D0 Table 25. Cycle Timer Intervals Sample Bit Trial 0 0 0 Cyc Cyc Cyc Typical Conversion Interval Delay Delay Bit 2 Bit 1 Bit 0 D2 D1 D0 (TCONVERT = conversion time of the ADC) 0 0 0 0 0 0 0 0 0 0 0 Mode not selected 0 0 1 TCONVERT × 32 0 1 0 TCONVERT × 64 0 1 1 TCONVERT × 128 1 0 0 TCONVERT × 256 1 0 1 T × 512 CONVERT 1 1 0 T × 1024 CONVERT 1 1 1 TCONVERT × 2048 Rev. 0 | Page 22 of 32 AD7993/AD7994 SERIAL INTERFACE 2 Control of the AD7993/AD7994 is carried out via the I C- Data is sent over the serial bus in sequences of nine clock compatible serial bus. The AD7993/AD7994 is connected to pulses, eight bits of data followed by an acknowledge bit from this bus as a slave device under the control of a master device, the receiver of data. Transitions on the data line must occur for example, the processor. during the low period of the clock signal and remain stable during the high period because a low-to-high transition when SERIAL BUS ADDRESS the clock is high may be interpreted as a stop signal. 2 Like all I C-compatible devices, the AD7993/AD7994 have a When all data bytes have been read or written, stop conditions 7-bit serial address. The 3 MSB of this address for the AD7993/ are established. In write mode, the master pulls the data line AD7994 are set to 010. The AD7993/AD7994 come in two high during the 10th clock pulse to assert a stop condition. In versions, the AD7993-0/AD7994-0 and AD7993-1AD7994-1. 2 read mode, the master device pulls the data line high during the The two versions have three different I C addresses available, low period before the ninth clock pulse. This is known as No which are selected by either tying the address select pin, AS, to Acknowledge. The master then takes the data line low during AGND or V , or by letting the pin float (see Table 6). By giving DD the low period before the 10th clock pulse, then high during the different addresses for the two versions, up to five AD7993/ 10th clock pulse to assert a stop condition. AD7994 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the Any number of bytes of data may be transferred over the serial bus. See Table 6. bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at The serial bus protocol operates as follows: the beginning and cannot subsequently be changed without The master initiates data transfer by establishing a start starting a new operation. condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/ bit is a 0, the master writes to the slave device. If the W R/W bit is a 1, the master reads from the slave device. Rev. 0 | Page 23 of 32 AD7993/AD7994 WRITING TO THE AD7993/AD7994 Depending on the register being written to, there are three WRITING TWO BYTES OF DATA TO A LIMIT OR different writes for the AD7993/AD7994. HYSTERESIS REGISTER Each of the four limit registers are 16-bit registers, so two bytes WRITING TO THE ADDRESS POINTER REGISTER of data are required to write a value to any one of them. Writing FOR A SUBSEQUENT READ two bytes of data to one of these registers consists of the serial In order to read from a particular register, the address pointer bus write address, the chosen limit register address written to register must first contain the address of that register. If it does the address pointer register, followed by two data bytes written not, the correct address must be written to the address pointer to the selected data register. See Figure 28. register by performing a single-byte write operation, as shown in Figure 26. The write operation consists of the serial bus If the master is write addressing the AD7993/AD7994, it can address followed by the address pointer byte. No data is write to more than one register. After the first write operation written to any of the data registers. A read operation may be has completed for the first data register in the next byte, the subsequently performed to read the register of interest. master writes to the address pointer byte to select the next data register for a write operation. This eliminates the need to WRITING A SINGLE BYTE OF DATA TO THE ALERT readdress the device in order to write to another data register. STATUS REGISTER OR CYCLE REGISTER The alert status register, configuration register and the cycle register are 8-bit registers, so only one byte of data can be written to each. Writing a single byte of data to one of these registers consists of the serial bus write address, the chosen data register address written to the address pointer register, followed by the data byte written to the selected data register. See Figure 27. 191 9 SCL P3 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P2 P1 P0 SDA START BY ACK. BY ACK. BY STOP BY MASTER AD7993/AD7994 AD7993/AD7994 MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER BYTE Figure 26. Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation 11 9 9 SCL 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P3 P2 P1 P0 SDA START BY ACK. BY ACK. BY MASTER AD7993/AD7994 AD7993/AD7994 FRAME 2 FRAME 1 ADDRESS POINTER REGISTER BYTE SERIAL BUS ADDRESS BYTE 91 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D3 D2 D1 D0 D4 ACK. BY STOP BY AD7993/AD7994 MASTER FRAME 3 DATA BYTE Figure 27. Single-Byte Write Sequence Rev. 0 | Page 24 of 32 03472-0-027 03472-0-026 AD7993/AD7994 11 9 9 SCL P3 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P2 P1 P0 SDA START BY ACK. BY ACK. BY MASTER AD7993/AD7994 AD7993/AD7994 FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER 91 99 1 SCL (CONTINUED) SDA (CONTINUED) 0 00 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1/0 D0/0 ACK. BY ACK. BY STOP BY AD7993/AD7994 AD7993/AD7994 MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE Figure 28. Two-Byte Write Sequence Rev. 0 | Page 25 of 32 03472-0-028 AD7993/AD7994 READING DATA FROM THE AD7993/AD7994 Reading data from the AD7993/AD7994 is a 1-byte or 2-byte Reading data from the configuration register, conversion result operation. Reading back the contents of the alert status register register, DATAHIGH registers, DATALOW registers, or hysteresis or the cycle timer register is a single-byte read operation, as registers is a 2-byte operation, as shown in Figure 30. The same shown in Figure 29. This assumes the particular register address rules apply for a 2-byte read as a 1-byte read. has previously been set up by a single-byte write operation to When reading data back from a register on the AD7993 or the the address pointer register, as shown in Figure 26. Once the AD7994, for example the conversion result register, if more than register address has been set up, any number of reads can be two read bytes are supplied, the same or new data is read from performed from that particular register without having to write the AD7993/AD7994 without the need to readdress the device. to the address pointer register again. If a read from a different This allows the master to continuously read from a data register register is required, the relevant register address has to be without having to readdress the AD7993/AD7994. written to the address pointer register, and again, any number of reads from this register may then be performed. 1199 SCL 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 R/W SDA START BY ACK. BY NO ACK. BY STOP BY MASTER AD7993/AD7994 MASTER MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE SINGLE DATA BYTE FROM AD7993/AD7994 Figure 29. Reading a Single Byte of Data from a Selected Register 11 9 9 SCL 0 1 0 A3 A2 A1 A0 R/W D11 D10 D9 D8 SDA ACK. BY ACK. BY START BY ALERT CH CH ZERO ID1 ID0 AD7993/AD7994 MASTER MASTER FLAG FRAME 2 FRAME 1 MOST SIGNIFICANT DATA BYTE FROM SERIAL BUS ADDRESS BYTE AD7993/AD7994 1 9 SCL (CONTINUED) SDA (CONTINUED) D3 D1/0 D0/0 D7 D6 D5 D4 D2 NO ACK. BY STOP BY MASTER MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD7993/AD7994 Figure 30. Reading Two Bytes of Data from the Conversion Result Register Rev. 0 | Page 26 of 32 03472-0-030 03472-0-029 AD7993/AD7994 ALERT/BUSY PIN The ALERT/BUSY pin may be configured as an alert output or BUSY busy output, as shown in Table 12. When the ALERT/BUSY pin is configured as a BUSY output, the pin is used to indicate when a conversion is taking place. SMBus ALERT The polarity of the BUSY pin is programmed through bit D0 in The AD7993/AD7994 alert output is an SMBus interrupt line the configuration register. for devices that want to trade their ability to master for an extra pin. The AD7993/AD7994 is a slave-only device and uses the PLACING THE AD7993-1/AD7994-1 INTO HIGH SMBus alert to signal the host device that it wants to talk. The SPEED MODE SMBus alert on the AD7993/AD7994 is used as an out-of- High speed mode communication commences after the master conversion range indicator (a limit violation indicator). addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to The ALERT pin has an open-drain configuration that allows begin. No device connected to the bus is allowed to acknowl- the alert outputs of several AD7993/AD7994s to be wired- edge the high speed master code; therefore, the code is followed AND’ed together when the ALERT pin is active low. D0 of the by a not acknowledge (see Figure 31). The master must then configuration register is used to set the active polarity of the issue a repeated start followed by the device address with a R/W ALERT output. The power-up default is active low. The ALERT bit. The selected device then acknowledges its address. function can be enabled or disabled by setting D2 of the configuration register to 1 or 0, respectively. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is The host device can process the ALERT interrupt and issued, the devices all return to fast mode. simultaneously access all SMBus ALERT devices through the alert response address. Only the device that pulled the ALERT THE ADDRESS SELECT (AS) PIN low acknowledges the ARA (alert response address). If more The address select pin on the AD7993/AD7994 is used to set than one device pulls the ALERT pin low, the highest priority 2 the I C address for the AD7993/AD7994 device. The AS pin (lowest address) device wins communication rights via standard 2 can be tied to VDD, to AGND, or left floating. The selection I C arbitration during the slave address transfer. should be made as close as possible to the AS pin; avoid having The ALERT output becomes active when the value in the long tracks introducing extra capacitance on the pin. This is conversion result register exceeds the value in the DATA HIGH important for the float selection, because the AS pin has to register or falls below the value in the DATA register. It is LOW charge to a midpoint after the start bit during the first address reset when a write operation to the configuration register sets byte. Extra capacitance on the AS pin increases the time taken D1 and D0 to a 1, or when the conversion result returns N LSB to charge to the midpoint and may cause an incorrect decision below or above the value stored in the DATAHIGH register or on the device address. When the AS pin is left floating, the DATALOW register, respectively. N is the value in the hysteresis AD7993/AD7994 can work with a capacitive load up to 40 pF. register (see the Limit Registers section). The ALERT output requires an external pull-up resistor that can be connected to a voltage different from V provided the DD maximum voltage rating of the ALERT output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be as large as possible to avoid excessive sink currents at the ALERT output. FAST MODE HIGH SPEED MODE 19 1 9 SCL A3 0 0 0 0 1 X X X 0 1 0 A2 A1 A0 SDA NACK Sr ACK. BY START BY AD7993/AD7994 MASTER HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE Figure 31. Placing the Part into High Speed Mode Rev. 0 | Page 27 of 32 03472-0-031 AD7993/AD7994 MODES OF OPERATION When supplies are first applied to the AD7993/AD7994, the If the CONVST pulse does not remain high for more than 1 µs, ADC powers up in shutdown mode and normally remains in the falling edge of CONVST still initiates a conversion but the this shutdown state while not converting. There are three result is invalid because the AD7993/AD7994 are not fully different methods of initiating a conversion on the devices. powered up when the conversion takes place. To maintain the performance of the AD7993/AD7994 in this mode it is MODE 1—USING THE PIN CONVST 2 recommended that the I C bus is quiet when a conversion is A conversion can be initiated on the AD7993/AD7994 by taking place. pulsing the CONVST signal. The conversion clock for the part The cycle timer register and Bits C4 to C1 in the address pointer is internally generated so no external clock is required, except register should contain all 0s when operating the AD7994/ 2 when reading from or writing to the I C interface. On the rising AD7993 in this mode. The pin should be tied low for CONVST edge of , the AD7993/AD7994 begin to power up CONVST all other modes of operation. To select an analog input channel (see Point A in Figure 32). The power-up time from shutdown for conversion in this mode, the user must write to the mode for the AD7993/AD7994 is approximately 1 µs; the configuration register and select the corresponding channel for signal must remain high for 1 µs for the part to power CONVST conversion. To set up a sequence of channels to be converted up fully. CONVST can be brought low after this time. The with each pulse, set the corresponding channel bits in CONVST falling edge of the signal places the track-and-hold CONVST the configuration register (see Table 11). into hold mode; a conversion is also initiated at this point (Point B in Figure 32). When the conversion is complete, Once the conversion is complete, the master can address the approximately 2 µs later, the parts return to shutdown (Point C AD7993/AD7994 to read the conversion result. If further in Figure 32) and remain there until the next rising edge of conversions are required, the SCL line can be taken high while . The master can then read the ADC to obtain the CONVST the signal is pulsed again; then an additional 18 SCL CONVST conversion result. The address pointer register must be pointing pulses are required to read the conversion result. to the conversion result register in order to read back the When operating the AD7993-1/AD7994-1 in Mode 1 and conversion result. reading after the conversion with a 3.4 MHz SCL, the ADCs can achieve a throughput rate of up to 121 kSPS. A B C t POWER-UP CONVST t CONVERT 11 9 9 9 SCA SDA S 7-BIT ADDRESS RA A A P FIRST DATA BYTE (MSBs) SECOND DATA BYTE (LSBs) Figure 32. Mode 1 Operation Rev. 0 | Page 28 of 32 03472-0-032 AD7993/AD7994 MODE 2—COMMAND MODE This mode allows a conversion to be automatically initiated any Table 27 shows the channel selection in this mode via time a write operation occurs. In order to use this mode, Command Bits C4 to C1 in the address pointer register. The Command Bits C4 to C1 in the address pointer byte, shown in wake-up and conversion times combined should take Table 7, must be programmed. approximately 3 µs. Following this, the AD7993/AD7994 must be addressed again to indicate that a read operation is required. To select a single analog input for conversion in this mode, The read then takes place from the conversion result register. the user must set bits C4 to C1of the address pointer byte to This read accesses the conversion result from the channel indicate which channel to convert (see Table 27). When all four selected via the command bits. If the Command Bits C2 and C1 command bits are 0, this mode is not in use. were set to 1, 1, then a four byte read would be necessary. The first read accesses the data from the conversion on VIN1. While A sequence can also be set up for this mode. If more than one this read takes place, a conversion occurs on V 2. The second IN command bit is set in the address pointer byte, the ADC starts read accesses this data from V 2. Figure 34 illustrates how this IN converting on the lowest channel in the sequence and then the mode operates. next lowest until all the channels in the sequence have been converted. The ADC stops converting the sequence when it When operating the AD7994-1/AD7993-1 in Mode 2 with a receives a STOP bit. high speed mode, 3.4 MHz SCL, the conversion may not be complete before the master tries to read the conversion result. Figure 29 illustrates a 2-byte read operation from the conver- If this is the case, the AD7994-1/AD7993-1 hold the SCL line sion result register. This operation is normally preceded by a low during the ACK clock after the read address until the con- write to the address pointer register so that the following read version is complete. When the conversion is complete, the accesses the desired register, in this case the conversion result AD7994-1/AD7993-1 release the SCL line and the master can register (Figure 26). If Command Bits C4 to C1 are set when the then read the conversion result. contents of the address pointer register are being loaded, the AD7993/AD7994 begin to power up and convert the selected After the conversion is initiated by setting the command bits in channel(s). Power-up begins on the fifth SCL falling edge of the the address pointer byte, if the AD7993/AD7994 receive a stop address point byte (see Point A in Figure 33). or NACK from the master, the devices stop converting. Table 27. Address Pointer Byte C4 C3 C2 C1 P3 P2 P1 P0 Mode 2, Convert On Comments 0 0 0 0 0 0 0 0 Not selected 0 0 0 1 0 0 0 0 VIN1 0 0 1 0 0 0 0 0 VIN2 0 0 1 1 0 0 0 0 Sequence between VIN1 and VIN2 0 1 0 0 0 0 0 0 V 3 IN 0 1 0 1 0 0 0 0 Sequence between V 1 and V 3 IN IN 0 1 1 0 0 0 0 0 Sequence between VIN2 and VIN3 With the pointer bits set to all 0s, the next 0 1 1 1 0 0 0 0 Sequence between VIN1, VIN2, and VIN3 read accesses the results of the conversion 1 0 0 0 0 0 0 0 VIN4 result register. 1 0 0 1 0 0 0 0 Sequence between V 1 and V 4 IN IN 1 0 1 0 0 0 0 0 Sequence between V 2 and V 4 IN IN 1 0 1 1 0 0 0 0 Sequence between V 1, V 2, and V 4 IN IN IN 1 1 0 0 0 0 0 0 Sequence between VIN3 and VIN4 1 1 0 1 0 0 0 0 Sequence between VIN1, VIN3, and VIN4 1 1 1 0 0 0 0 0 Sequence between VIN2, VIN3, and VIN4 1 1 1 1 0 0 0 0 Sequence between V 1, V 2, V 3, and V 4 IN IN IN IN Rev. 0 | Page 29 of 32 AD7993/AD7994 11 8 9 A 9 SCL SDA COMMAND/ADDRESS 7-BIT ADDRESS WA A S POINT BYTE ACK BY ACK BY AD7993/AD7994 AD7993/AD7994 11 9 9 9 SCL SDA FIRST DATA BYTE SECOND DATA BYTE Sr 7-BIT ADDRESS RA A Sr/P A (MSBs) (LSBs) ACK BY ACK BY NACK BY AD7993/AD7994 MASTER MASTER Figure 33. Mode 2 Operation 11 8 9 9 SCL SDA COMMAND/ADDRESS 7-BIT ADDRESS A S WA POINT BYTE ACK BY ACK BY AD7993/AD7994 AD7993/AD7994 9 9 9 1 9 1 9 SCL SDA FIRST DATA BYTE SECOND DATA BYTE FIRST DATA BYTE SECOND DATA BYTE A A A Sr 7-BIT ADDRESS RA A/A (MSBs) (LSBs) (MSBs) (LSBs) ACK BY ACK BY ACK BY ACK BY AD7993/AD7994 MASTER MASTER MASTER RESULT FROM CH1 RESULT FROM CH2 Figure 34. Mode 2 Sequence Operation MODE 3—AUTOMATIC CYCLE INTERVAL MODE An automatic conversion cycle can be selected and enabled by operation, the user must program the 3 LSB of the cycle timer writing a value to the cycle timer register. A conversion cycle register to contain all 0s. To select a channel(s) for operation in interval can be set up on the AD7993/AD7994 by programming the cycle mode, set the corresponding channel bit(s), D7 to D4, the relevant bits in the 8-bit cycle timer register, as decoded in of the configuration register. If more than one channel bit is set Table 25. Only the 3 LSB are used; the 5 MSB should contain 0s. in the configuration register, the ADC automatically cycles When the 3 LSB of the register are programmed with any through the channel sequence starting with the lowest channel configuration other than all 0s, a conversion takes place every and working its way up through the sequence. Once the X ms; the cycle interval, X, depends on the configuration of sequence is complete, the ADC starts converting on the lowest these three bits in the cycle timer register. There are seven channel again, continuing to loop through the sequence until different cycle time intervals to choose from, as shown in the cycle timer register’s contents are set to all 0s. This mode Table 25. Once the conversion takes place, the part powers is useful for monitoring signals such as battery voltage, and down again until the next conversion. To exit this mode of temperature, alerting only when the limits are violated. Rev. 0 | Page 30 of 32 03472-0-033 03472-0-034 AD7993/AD7994 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0° 0.65 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1 2 Model Temperature Range Linearity Error (Max) Package Option Package Description AD7993BRU-0 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-0REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package 3 AD7993BRUZ-0 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package 3 AD7993BRUZ-0REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-1 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-1REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package 3 AD7993BRUZ-1 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package 3 AD7993BRUZ-1REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-0 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-0REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package 3 AD7994BRUZ-0 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package 3 AD7994BRUZ-0REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-1 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-1REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package 3 AD7994BRUZ-1 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package 3 AD7994BRUZ-1REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package EVAL-AD7993CB Standalone Evaluation Board EVAL-AD7994CB Standalone Evaluation Board 1 2 2 The AD7993-0/AD7994-0 supports standard and fast I C interface modes. The AD7993-1/AD7994-1 support standard, fast, and high speed I C interface modes. 2 Linearity error here refers to integral nonlinearity. 3 Z = Pb-free part. 2 RELATED PARTS IN I C-COMPATIBLE ADC PRODUCT FAMILY Part Number Resolution Number of Input Channels Package AD7998 12 8 20-lead TSSOP AD7997 10 8 20-lead TSSOP AD7992 12 2 10-lead MSOP Rev. 0 | Page 31 of 32 AD7993/AD7994 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03472–0–10/04(0) Rev. 0 | Page 32 of 32