ANALOG DEVICES AD7986

18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) AD7986 FEATURES APPLICATION DIAGRAM 1.8V 18-bit resolution with no missing codes TO V+ 5V 2.5V 2.7V Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low) 15Ω Low power dissipation 0V VIO BVDD AVDD, TO 15 mW at 2 MSPS, with external reference 2.7nF DVDD V VIO REF IN+ TURBO 26 mW at 2 MSPS with internal reference V– SDI 3- OR 4-WIRE AD7986 INTERFACE: INL: ±1 LSB typical, ±2.5 LSB maximum SCK V+ SPI, CS IN– SDO SNR DAISY CHAIN 1 CNV REF GND (TURBO = LOW) 15Ω 95.5 dB, with on-chip reference V REF 97.0 dB, with external reference TO 2.7nF 10µF 0V 4.096 V internal reference: typical drift of 10 ppm/°C V– True differential analog input voltage range: ±V REF NOTES 0 V to V with V up to 5.0 V REF REF 1. GND REFERS TO REFGND, AGND, AND DGND. Allows use of any input range Figure 1. No pipeline delay GENERAL DESCRIPTION Logic interface: 1.8 V/2.5 V/2.7 V The AD7986 is an 18-bit, 2 MSPS successive approximation, Serial interface: SPI/QSPI™/MICROWIRE™/DSP compatible analog-to-digital converter (ADC). It contains a low power, Ability to daisy-chain multiple ADCs with busy indicator high speed, 18-bit sampling ADC, an internal conversion clock, 20-lead 4 mm × 4 mm LFCSP (QFN) an internal reference (and buffer), error correction circuits, and APPLICATIONS a versatile serial interface port. On the rising edge of CNV, the Battery-powered equipment AD7986 samples the voltage difference between the IN+ and Data acquisition systems IN− pins. The voltages on these pins usually swing in opposite Medical instruments phases between 0 V and V . It features a very high sampling REF Seismic data acquisition systems rate turbo mode (TURBO = high) and a reduced power normal mode (TURBO = low) for low power applications where the power is scaled with the throughput. In normal mode (TURBO = low), the SPI-compatible serial interface also features the ability, using the SDI input, to daisy- chain several ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V using the separate VIO supply. The AD7986 is available in a 20-lead LFCSP (QFN) with operation specified from −40°C to +85°C. Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 1 1 14-Bit AD7940 AD7942 AD7946 1 1 1 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4941-1 1 1 1 AD7683 AD7687 AD7688 AD7983 ADA4841-x 1 AD7684 AD7694 AD7693 1 1 1 18-Bit ADA4941-1 AD7691 AD7690 AD7982 1 ADA4841-x AD7984 AD7986 AD8021 1 Pin-for-pin compatible. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07956-001 AD7986 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Application Diagram ........................................................................ 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply ............................................................................... 16 Revision History ............................................................................... 2 Digital Interface .............................................................................. 17 Specifications ..................................................................................... 3 Data Reading Options ............................................................... 18 Timing Specifications .................................................................. 5 CS Mode, 3-Wire Without Busy Indicator ............................. 19 Absolute Maximum Ratings ............................................................ 6 CS Mode, 3-Wire with Busy Indicator .................................... 20 ESD Caution .................................................................................. 6 CS Mode, 4-Wire Without Busy Indicator ............................. 21 Pin Configuration and Function Descriptions ............................. 7 CS Mode, 4-Wire with Busy Indicator .................................... 22 Typical Performance Characteristics ............................................. 9 Chain Mode Without Busy Indicator ...................................... 23 Terminology .................................................................................... 12 Chain Mode with Busy Indicator ............................................. 24 Theory of Operation ...................................................................... 13 Application Hints ........................................................................... 25 Circuit Information .................................................................... 13 Layout .......................................................................................... 25 Converter Operation .................................................................. 13 Evaluating the AD7986 Performance ...................................... 25 Conversion Modes of Operation .............................................. 13 Outline Dimensions ....................................................................... 27 Typical Connection Diagram.................................................... 14 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/11—Rev. A to Rev. B Added Common-Mode Input Range Parameter, Table 2 ........... 3 8/10—Rev. 0 to Rev. A Changes to Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) Parameter, Table 4 ....... 5 Changes to Figure 32 ...................................................................... 22 4/09—Revision 0: Initial Version Rev. B | Page 2 of 28 AD7986 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V = 4.096 V, T = −40°C to +85°C, unless otherwise noted. REF A Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range (IN+) − (IN−) −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V × 0.475 V × 0.5 V × 0.525 V REF REF REF 1 Analog Input CMRR f = 500 kHz 100 dB IN Leakage Current at 25°C Acquisition phase 250 nA Input Impedance See the Analog Inputs section ACCURACY No Missing Codes 18 Bits 2 Differential Linearity Error −0.95 ±0.60 +1.50 LSB 2 Integral Linearity Error −2.50 ±1.00 +2.50 LSB 2 Transition Noise 2.0 LSB 3 2 Gain Error, T to T −20 ±2.4 +20 LSB MIN MAX Gain Error Temperature Drift ±0.5 ppm/°C 3 Zero Error, T to T −0.8 +0.8 mV MIN MAX Zero Temperature Drift ±0.3 ppm/°C 2 Power Supply Sensitivity AVDD = 2.5 V ± 5% ±4 LSB THROUGHPUT Conversion Rate 0 2.00 MSPS Transient Response Full-scale step 100 ns AC ACCURACY 1 Dynamic Range V = 4.096 V, internal reference 95.5 96.5 dB REF V = 5.0 V, external reference 97 98 REF 1 Signal-to-Noise Ratio, SNR f = 20 kHz, V = 4.096 V, internal 94.5 95.5 dB IN REF reference 1 f = 20 kHz, V = 5.0 V, external 96.5 97.0 dB IN REF reference 1 Spurious-Free Dynamic Range, SFDR f = 20 kHz −115 dB IN 4 1 Total Harmonic Distortion , THD f = 20 kHz, V = 4.096 V, internal −113 dB IN REF reference 1 f = 20 kHz, V = 5.0 V, external −114 dB IN REF reference 1 Signal-to-(Noise + Distortion), SINAD f = 20 kHz, V = 4.096 V 94.5 95.5 dB IN REF SAMPLING DYNAMICS −3 dB Input Bandwidth 19 MHz Aperture Delay 0.7 ns 1 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2 LSB means least significant bit. With the ±4.096 V input range, one LSB is 31.25 µV. 3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 Tested fully in production at f = 1 kHz. IN Rev. B | Page 3 of 28 AD7986 AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V = 4.096 V, T = −40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter Conditions Min Typ Max Unit INTERNAL REFERENCE PDREF = low Output Voltage T = 25°C 4.081 4.096 4.111 V A Temperature Drift −40°C to +85°C ±10 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±50 ppm/V Turn-On Settling Time C = 10 μF, C = 0.1 μF 220 ms REF REFBUFIN REFIN Output Voltage REFIN @ 25°C 1.2 V REFIN Output Resistance 7.5 kΩ EXTERNAL REFERENCE PDREF = high, REFIN = low Voltage Range 2.4 5.1 V Current Drain 2 MSPS, V = 5.0 V 500 µA REF REFERENCE BUFFER REFIN Input Voltage Range 1.2 V REFIN Input Current 160 µA DIGITAL INPUTS Logic Levels V −0.3 +0.1 × VIO V IL V +0.9 × VIO VIO + 0.3 V IH I −1 +1 µA IL I −1 +1 µA IH DIGITAL OUTPUTS Data Format Serial, 18 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion V I = +500 µA 0.4 V OL SINK V I = −500 µA VIO − 0.3 V OH SOURCE POWER SUPPLIES AVDD, DVDD 2.375 2.5 2.625 V BVDD 4.75 5.0 5.25 VIO Specified performance 1.8 2.5 2.7 V VIO Range V 1, 2 Standby Current AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V 2.25 µA Power Dissipation With Internal Reference 2 MSPS throughput 29 34 mW Without Internal Reference 2 MSPS throughput 15 16.5 mW With Internal Reference 1.5 MSPS throughput 26 30 mW Without Internal Reference 1.5 MSPS throughput 11.5 13 mW 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. B | Page 4 of 28 AD7986 TIMING SPECIFICATIONS 1 AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V = 4.096 V, T = −40°C to +85°C, unless otherwise noted. REF A Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) t 400/500 ns CONV Acquisition Time t 100 ns ACQ Time Between Conversions (Turbo Mode/Normal Mode) t 500/660 ns CYC CNV Pulse Width (CS Mode) t 10 ns CNVH Data Read During Conversion (Turbo Mode/Normal Mode) t 200/300 ns DATA Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge t 20 ns QUIET SCK Period (CS Mode) t 9 ns SCK SCK Period (Chain Mode) t 11 ns SCK SCK Low Time t 3.5 ns SCKL SCK High Time t 3.5 ns SCKH SCK Falling Edge to Data Remains Valid t 2 ns HSDO SCK Falling Edge to Data Valid Delay t 6 ns DSDO CNV or SDI Low to SDO D17 MSB Valid (CS Mode) t 10 ns EN CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 8 ns DIS SDI Valid Setup Time from CNV Rising Edge t 4 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) t 0 ns HSDICNV SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t 0 ns HSDICNV SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t 5 ns SSCKCNV SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 5 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 2 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 3 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t 5 ns DSDOSDI 1 See Figure 2 and Figure 3 for load conditions. 10% VIO 500µA I OL 90% VIO t t DELAY DELAY 1 1 V V IH IH TO SDO 1.4V 1 1 V V C IL IL L 20pF 1 MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3. 500µA I OH Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 28 07956-002 07956-003 AD7986 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs other conditions above those indicated in the operational 1 IN+, IN− to GND −0.3 V to V + 0.3 V REF section of this specification is not implied. Exposure to absolute or ±130 mA maximum rating conditions for extended periods may affect Supply Voltage device reliability. REF, BVDD to GND, REFGND −0.3 V to +6.0 V AVDD, DVDD, VIO to GND −0.3 V to +2.7 V AVDD and DVDD to VIO +3 V to −6 V ESD CAUTION Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 20-Lead LFCSP (QFN) 30.4°C/W Lead Temperatures Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section for an explanation of IN+ and IN −. Rev. B | Page 6 of 28 AD7986 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR REF 1 15 TURBO REF 2 14 SDI AD7986 13 CNV REFGND 3 TOP VIEW REFGND 4 12 SCK (Not to Scale) IN– 5 11 DVDD NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 2 REF AI Reference Output/Input Voltage. When PDREF = low, the internal reference and buffer are enabled, producing 4.096 V on this pin. When PDREF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V. Decoupling is required with or without the internal reference and buffer. This pin is referred to the REFGND pins and should be decoupled closely to the REFGND pins with a 10 µF capacitor. 3, 4 REFGND AI Reference Input Analog Ground. 5 IN− AI Differential Negative Analog Input. 6 IN+ AI Differential Positive Analog Input. 7 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must be used. 8 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, or 2.7 V). 9 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 10 DGND P Digital Power Ground. 11 DVDD P Digital Power. Nominally at 2.5 V. 12 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 13 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 14 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 15 TURBO DI Conversion Mode Selection. When TURBO = high, the maximum throughput (2 MSPS) is achieved. The ADC does not power down between conversions. When TURBO = low, the maximum throughput is lower (1.5 MSPS). The ADC powers down between conversions. Rev. B | Page 7 of 28 07956-004 IN+ 6 20 REFIN PDREF 7 19 BVDD VIO 8 18 AGND 17 AGND SDO 9 DGND 10 16 AVDD AD7986 1 Pin No. Mnemonic Type Description 16 AVDD P Input Analog Power. Nominally at 2.5 V. 17,18 AGND P Analog Power Ground. 19 BVDD P Reference buffer power. Nominally 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. 20 REFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF = low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF = high, use an external reference to provide a 1.2 V (typical) to this pin. When PDREF = high, and REFIN = low, the on-chip reference buffer and band gap are powered down. An external reference must be connected to REF and BVDD. 21 (EPAD) Exposed Pad EP The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = bidirectional analog; DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 28 AD7986 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, V = 5.0 V, external reference (PDREF = high, REFIN = low), unless otherwise noted. REF 2.5 2.0 POSITIVE INL = +1.57LSB POSITIVE DNL = +0.54LSB 2.0 NEGATIVE INL = –1.25LSB 1.5 NEGATIVE DNL = –0.60LSB 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.5 –2.0 0 65,536 131,072 196,608 262,144 0 65,536 131,072 196,608 262,144 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 45,000 45,000 41,811 41,434 38,665 40,000 40,000 35,204 34,894 35,000 35,000 30,897 30,000 30,000 25,000 25,000 20,000 20,000 15,000 15,000 10,211 10,000 10,000 8250 7662 6399 5000 5000 2283 1661 1418 1002 101 68 142 34 0 3 0 0 4 1 0 0 0 3FF6 3FF8 3FFA 3FFC 3FFE 0 3FF5 3FF7 3FF9 3FFB 3FFD 3FFF 1 CODE IN HEX CODE IN HEX Figure 6. Histogram of DC Input at Code Center (External Reference) Figure 9. Histogram of DC Input at Code Transition (External Reference) 45,000 40,000 37,385 36,210 39,395 40,000 35,000 35,000 30,000 31,020 29,138 30,000 25,000 22,077 25,000 18,953 20,000 20,000 15,000 15,000 12,773 11,107 10,000 10,000 6879 6513 5000 5000 3662 2932 1438 547 1282 407 150 0 1 55 35 0 165 0 1 3 16 0 0 0 3FFEC 3FFEE 3FF0 3FF2 3FF4 3FF6 3FF8 3FFEB 3FFED 3FFEF 3FF1 3FF3 3FF5 3FF7 3FF9 CODE IN HEX CODE IN HEX Figure 7. Histogram of DC Input at Code Center (Internal Reference) Figure 10. Histogram of DC Input at Code Transition (Internal Reference) Rev. B | Page 9 of 28 COUNTS COUNTS INL (LSB) 07956-005 07956-007 07956-006 COUNTS COUNTS DNL (LSB) 07956-008 07956-010 07956-009 AD7986 0 0 f = 2MSPS f = 2MSPS –20 S –20 S f = 20kHz f = 20kHz IN IN –40 SNR = 97.0dB SNR = 95.5dB –40 THD = –114.0dB THD = –113.0dB SINAD = 95.5dB SINAD = 97.0dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –200 –180 0 200k 400k 600k 800k 1M 0 200k 400k 600k 800k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. FFT Plot (External Reference) Figure 14. FFT Plot (Internal Reference) 100 18 –95 125 SNR –100 120 95 17 SINAD –105 115 SFDR ENOB 16 90 –110 110 THD –115 105 85 15 –120 100 80 14 –125 95 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCEVOLTAGE(V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD and SFDR vs. Reference Voltage 100 –80 –85 –90 95 –95 –100 90 –105 –110 85 –115 –120 80 –125 1k 10k 100k 1M 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. SINAD vs. Frequency Figure 16. THD vs. Frequency Rev. B | Page 10 of 28 SNR, SINAD (dB) AMPLITUDE (dB) SINAD (dB) ENOB (Bits) 07956-013 07956-111 07956-212 THD (dB) THD (dB) AMPLITUDE (dB) 07956-114 07956-216 SFDR (dB) 07956-015 AD7986 100 3.0 99 I REF 2.5 98 97 2.0 I AVDD 96 95 1.5 94 1.0 93 92 0.5 I BVDD 91 90 0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 –55 –35 –15 5 25 45 65 85 105 125 INPUT LEVEL (dB) TEMPERATURE (C) Figure 17. SNR vs. Input Level Figure 19. Operating Currents vs. Temperature 3.0 14 I REF 2.5 12 10 2.0 I AVDD 8 1.5 I DVDD 6 1.0 4 I + I + I AVDD DVDD VIO I BVDD 0.5 2 I VIO 0 0 2.375 2.425 2.475 2.525 2.575 2.625 125 –55 –35 –15 5 25 45 65 85 105 AVDD AND DVDD VOLTAGE (V) TEMPERATURE (°C) Figure 18. Operating Currents vs. Supply Voltage Figure 20. Power-Down Currents vs. Temperature Rev. B | Page 11 of 28 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) SNR (dB REFERRED TO FULL SCALE) 07956-032 07956-033 SUPPLY CURRENT (µA) 07956-035 07956-034 AD7986 TERMINOLOGY Noise-Free Code Resolution Integral Nonlinearity Error (INL) Noise-free code resolution is the number of bits beyond which it is INL refers to the deviation of each individual code from a line impossible to distinctly resolve individual codes. It is calculated as drawn from negative full scale through positive full scale. The N point used as negative full scale occurs ½ LSB before the first Noise-Free Code Resolution = log (2 /Peak-to-Peak Noise) 2 code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from Effective Resolution the middle of each code to the true straight line (see Figure 22). Effective resolution is calculated as Differential Nonlinearity Error (DNL) N Effective Resolution = log (2 /RMS Input Noise) 2 In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in and is expressed in bits. terms of resolution for which no missing codes are guaranteed. Total Harmonic Distortion (THD) Zero Error THD is the ratio of the rms sum of the first five harmonic Zero error is the difference between the ideal midscale voltage, components to the rms value of a full-scale input signal and is that is, 0 V, from the actual voltage producing the midscale expressed in decibels. output code, that is, 0 LSB. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to Gain Error The first transition (from 100 ... 00 to 100 ... 01) should occur at the total rms noise measured with the inputs shorted together. a level ½ LSB above nominal negative full scale (−4.095984 V The value for dynamic range is expressed in decibels. It is for the ±4.096 V range). The last transition (from 011 … 10 to measured with a signal at −60 dBF so that it includes all noise 011 … 11) should occur for an analog voltage 1½ LSB below sources and DNL artifacts. the nominal full scale (+4.095953 V for the ±5 V range). The Signal-to-Noise Ratio (SNR) gain error is the deviation of the difference between the actual SNR is the ratio of the rms value of the actual input signal to level of the last transition and the actual level of the first the rms sum of all other spectral components below the Nyquist transition from the difference between the ideal levels. frequency, excluding harmonics and dc. The value for SNR is Spurious-Free Dynamic Range (SFDR) expressed in decibels. SFDR is the difference, in decibels (dB), between the rms Signal-to-(Noise + Distortion) (SINAD) amplitude of the input signal and the peak spurious signal. SINAD is the ratio of the rms value of the actual input signal to Effective Number of Bits (ENOB) the rms sum of all other spectral components that are less than ENOB is a measurement of the resolution with a sine wave the Nyquist frequency, including harmonics but excluding dc. input. It is related to SINAD as follows: The value of SINAD is expressed in decibels. ENOB = (SINAD Aperture Delay − 1.76)/6.02 dB Aperture delay is the measure of the acquisition performance and is expressed in bits. and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 12 of 28 AD7986 THEORY OF OPERATION IN+ SWITCHES CONTROL SW+ MSB LSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND 131,072C 65,536C 4C 2C C C OUTPUT CODE MSB LSB SW– CNV IN– Figure 21. ADC Simplified Schematic two capacitor arrays are then disconnected from the analog CIRCUIT INFORMATION inputs and connected to the REFGND input. Therefore, the The AD7986 is a fast, low power, single-supply, precise, 18-bit differential voltage between Input IN+ and Input IN− captured ADC using a successive approximation architecture. The AD7986 at the end of the acquisition phase is applied to the comparator features different modes to optimize performance according to inputs, causing the comparator to become unbalanced. By the application. In turbo mode, the AD7986 is capable of convert- switching each element of the capacitor array between ing 2,000,000 samples per second (2 MSPS). REFGND and REF, the comparator input varies by binary- The AD7986 provides the user with an on-chip track-and-hold weighted voltage steps (V /2, V /4 … V /262,144). The REF REF REF and does not exhibit any pipeline delay or latency, making it ideal control logic toggles these switches, starting with the MSB, to for multiple multiplexed channel applications. bring the comparator back into a balanced condition. After the The AD7986 can be interfaced to any 1.8 V to 2.7 V digital logic completion of this process, the part returns to the acquisition family. It is available in a 20-lead LFCSP (QFN) that allows space phase, and the control logic generates the ADC output code and savings and flexible configurations. a busy signal indicator. Because the AD7986 has an on-board conversion clock, the CONVERTER OPERATION serial clock, SCK, is not required for the conversion process. The AD7986 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified CONVERSION MODES OF OPERATION schematic of the ADC. The capacitive DAC consists of two The AD7986 features two conversion modes of operation: turbo identical arrays of 18 binary-weighted capacitors that are and normal. Turbo conversion mode (TURBO = high) allows connected to the two comparator inputs. the fastest conversion rate of up to 2 MSPS, and does not power down between conversions. The first conversion in turbo mode During the acquisition phase, terminals of the array tied to the input of the comparator are connected to AGND via SW+ and should be ignored because it contains meaningless data. For SW−. All independent switches are connected to the analog applications that require lower power and slightly slower inputs. Therefore, the capacitor arrays are used as sampling sampling rates, the normal mode (TURBO = low) allows a capacitors and acquire the analog signal on the IN+ and IN− maximum conversion rate of 1.5 MSPS, and powers down inputs. When the acquisition phase is complete and the CNV between conversion. The first conversion in normal mode does contain meaningful data. input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The Rev. B | Page 13 of 28 07956-011 AD7986 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Analog Input Digital Output The ideal transfer characteristic for the AD7986 is shown in Description V = 5 V Code (Hex) REF Figure 22 and Table 7. 1 FSR − 1 LSB +4.095969 V 0x1FFFF Midscale + 1 LSB +31.25 µV 0x00001 011 ... 111 Midscale 0 V 0x00000 011 ... 110 Midscale − 1 LSB −31.25 µV 0x3FFFF 011 ... 101 −FSR + 1 LSB −4.095969 V 0x20001 2 −FSR −4.096 V 0x20000 1 This is also the code for an overranged analog input (V − V above V − IN+ IN− REF REFGND). 2 This is also the code for an underranged analog input (V − V below REFGND). IN+ IN− 100 ... 010 TYPICAL CONNECTION DIAGRAM 100 ... 001 100 ... 000 Figure 23 shows an example of the recommended connection –FSR –FSR + 1 LSB +FSR – 1 LSB diagram for the AD7986 when multiple supplies are available. –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function 5V 2.5V 1.8V TO 2.7V V+ 15Ω BVDD AVDD, DD VIO DVDD 0V TO V REF 2.7nF TURBO VIO IN+ SDI V– 3- OR 4-WIRE SCLK INTERFACE: AD7986 V+ SPI, CS SDO IN– DAISY CHAIN (TURBO = LOW) CNV 15Ω 1 REF GND V TO 0V REF 2.7nF 10µF V– NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. Figure 23. Typical Application Diagram with Multiple Supplies Rev. B | Page 14 of 28 ADC CODE (TWOS COMPLEMENT) 07956-012 07956-016 AD7986 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the input structure of Although the AD7986 is easy to drive, the driver amplifier must the AD7986. meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the • The noise generated by the driver amplifier must be kept as analog inputs, IN+ and IN−. Care must be taken to ensure that low as possible to preserve the SNR and transition noise the analog input signal does not exceed the reference input performance of the AD7986. The noise from the driver is voltage (REF) by more than 0.3 V. If the analog input signal filtered by the AD7986 analog input circuit’s one-pole, low- exceeds this level, the diodes become forward-biased and start pass filter, made by R and C or by the external filter, if IN IN conducting current. These diodes can handle a forward-biased one is used. Because the typical noise of the AD7986 is current of 130 mA maximum. However, if the supplies of the 62.5 µV rms, the SNR degradation due to the amplifier is input buffer (for example, the V+ and V− supplies of the buffer   amplifier in Figure 23) are different from those of REF, the   62.5   analog input signal may eventually exceed the supply rails by SNR = 20 log LOSS   π 2 2 more than 0.3 V. In such a case (for example, an input buffer  34.4 + f (Ne )  −3dB N 2   with a short circuit), the current limitation can be used to protect the part. where: REF f is the input bandwidth, in megahertz, of the AD7986 –3dB (20 MHz) or the cutoff frequency of the input filter, if D1 C IN R IN one is used. IN+ OR IN– N is the noise gain of the amplifier (for example, 1 in buffer C D2 PIN GND configuration). e is the equivalent input noise voltage of the op amp, in N Figure 24. Equivalent Analog Input Circuit nV/√Hz. The analog input structure allows the sampling of the true • For ac applications, the driver should have a THD perfor- differential signal between IN+ and IN−. By using these mance commensurate with the AD7986. differential inputs, signals common to both inputs are rejected. • For multichannel multiplexed applications, the driver amplifier and the AD7986 analog input circuit must settle During the acquisition phase, the impedance of the analog for a full-scale step onto the capacitor array at an 18-bit level inputs (IN+ or IN−) can be modeled as a parallel combination (0.0004%, 4 ppm). In the data sheet of the driver amplifier, of Capacitor C and the network formed by the series connection PIN settling at 0.1% to 0.01% is more commonly specified. This of R and C . C is primarily the pin capacitance. R is typically IN IN PIN IN may differ significantly from the settling time at an 18-bit 400 Ω and is a lumped component composed of serial resistors level and should be verified prior to driver selection. and the on resistance of the switches. C is typically 30 pF and IN is mainly the ADC sampling capacitor. Table 8. Recommended Driver Amplifiers During the sampling phase, where the switches are closed, the Amplifier Typical Application input impedance is limited to C . R and C make a one-pole, PIN IN IN AD8021 Very low noise and high frequency low-pass filter that reduces undesirable aliasing effects and AD8022 Low noise and high frequency limits noise. ADA4899-1 Ultralow noise and high frequency When the source impedance of the driving circuit is low, the AD8014 Low power and high frequency AD7986 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. B | Page 15 of 28 07956-014 AD7986 The advantages of directly using the external voltage reference are: VOLTAGE REFERENCE INPUT • The SNR and dynamic range improvement (about 1.7 dB) The AD7986 allows the choice of a very low temperature drift resulting from the use of a larger reference voltage (5 V) internal voltage reference, an external reference, or an external instead of a typical 4.096 V reference when the internal buffered reference. reference is used. This is calculated by The internal reference of the AD7986 provides excellent performance and can be used in almost all applications. 4.096   SNR= 20 log    5.0  Internal Reference, REF = 4.096V (PDREF = Low) To use the internal reference, the PDREF input must be low. • The power savings when the internal reference is powered This enables the on-chip band gap reference and buffer, result- down (PDREF high). ing in a 4.096 V reference on the REF pin (1.2 V on REFIN). Reference Decoupling The internal reference is temperature compensated to 4.096 V ± The AD7986 voltage reference input, REF, has a dynamic input 15 mV. The reference is trimmed to provide a typical drift of impedance that requires careful decoupling between the REF 10 ppm/°C. and REFGND pins. The Layout section describes how this can The output resistance of REFIN is 6 kΩ when the internal be done. reference is enabled. It is necessary to decouple this pin with a When using an external reference, a very low impedance source ceramic capacitor of at least 100 nF. The output resistance of (for example, a reference buffer using the AD8031 or the REFIN and the decoupling capacitor form an RC filter, which AD8605), and a 10 µF (X5R, 0805 size) ceramic chip capacitor helps to reduce noise. are appropriate for optimum performance. Because the output impedance of REFIN is typically 6 kΩ, relative If an unbuffered reference voltage is used, the decoupling value humidity (among other industrial contaminants) can directly depends on the reference used. For instance, a 22 µF (X5R, affect the drift characteristics of the reference. A guard ring is 1206 size) ceramic chip capacitor is appropriate for optimum typically used to reduce the effects of drift under such circum- performance using a low temperature drift ADR43x reference. stances. However, the fine pitch of the AD7986 makes this If desired, a reference decoupling capacitor with values as small difficult to implement. One solution, in these industrial and as 2.2 µF can be used with minimal impact on performance, other types of applications, is to use a conformal coating, such as especially DNL. Dow Corning® 1-2577 or HumiSeal® 1B73. Regardless, there is no need for an additional lower value ceramic External 1.2 V Reference and Internal Buffer (PDREF = High) decoupling capacitor (for example, 100 nF) between the REF To use an external reference along with the internal buffer, PDREF and REFGND pins. should be high. This powers down the internal reference and POWER SUPPLY allows the 1.2 V reference to be applied to REFIN, producing 4.096 V (typically) on the REF pin. The AD7986 uses four power supply pins: an analog supply (AVDD), a buffer supply (BVDD), a digital supply (DVDD), External Reference (PDREF = High, REFIN = Low) and a digital input/output interface supply (VIO). VIO allows To apply an external reference voltage directly to the REF pin, direct interface with any logic between 1.8 V and 2.7 V. To reduce PDREF should be tied high, and REFIN should be tied low. the number of supplies needed, VIO, DVDD, and AVDD can BVDD should also be driven to the same potential as REF. For be tied together. The AD7986 is independent of power supply example, if REF = 2.5 V, BVDD should be tied to 2.5 V. sequencing among all of its supplies. Additionally, it is very insensitive to power supply variations over a wide frequency range. Rev. B | Page 16 of 28 AD7986 DIGITAL INTERFACE Although the AD7986 has a reduced number of pins, it offers The busy indicator feature is enabled in CS mode if CNV or flexibility in its serial interface modes. SDI is low when the ADC conversion ends (see Figure 28 and Figure 32), and TURBO must be kept low for both digital When in CS mode, the AD7986 is compatible with SPI, interfaces. MICROWIRE™, QSPI™, and digital hosts. In this mode, the AD7986 can use either a 3-wire or a 4-wire interface. A 3-wire When CNV is low, reading can occur during conversion and interface using the CNV, SCK, and SDO signals minimizes acquisition, and when split across acquisition and conversion, wiring connections, which is useful, for instance, in isolated as detailed in the following sections. applications. A 4-wire interface using the SDI, CNV, SCK, and A discontinuous SCK is recommended because the part is SDO signals allows CNV, which initiates conversions, to be selected with CNV low, and SCK activity begins to clock independent of the readback timing (SDI). This is useful in low out data. jitter sampling or simultaneous sampling applications. Note that in the following sections, the timing diagrams When in chain mode, the AD7986 provides a daisy-chain feature indicate digital activity (SCK, CNV, SDI, and SDO) during using the SDI input for cascading multiple ADCs on a single the conversion. However, due to the possibility of performance data line similar to a shift register. Chain mode is only available degradation, digital activity should occur only prior to the safe in normal mode (TURBO = low). data reading time, t , because the AD7986 provides error DATA The mode in which the part operates depends on the SDI level correction circuitry that can correct for an incorrect bit decision when the CNV rising edge occurs. The CS mode is selected if during this time. From t to t , there is no error correction, DATA CONV and conversion results may be corrupted. Similarly, t , the SDI is high, and the chain mode is selected if SDI is low. The QUIET time from the last falling edge of SCK to the rising edge of CNV, SDI hold time is such that when SDI and CNV are connected must remain free of digital activity. The user should configure together, the chain mode is always selected. the AD7986 and initiate the busy indicator (if desired in normal In normal mode operation, the AD7986 offers the option of mode) prior to t . It is also possible to corrupt the sample by DATA forcing a start bit in front of the data bits. This start bit can be having SCK near the sampling instant. Therefore, it is recom- used as a busy signal indicator to interrupt the digital host and mended to keep the digital pins quiet for approximately 20 ns trigger the data reading. Otherwise, without a busy indicator, before and 10 ns after the rising edge of CNV, using a the user must time out the maximum conversion time prior to discontinuous SCK whenever possible to avoid any potential readback. performance degradation. Rev. B | Page 17 of 28 AD7986 To determine how to split the read for a particular SCK frequency, DATA READING OPTIONS follow these examples to read data from conversion (n − 1). There are three different data reading options for the AD7986. For turbo mode (2 MSPS), There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 27 and Figure 28), f = 65 MHz; t = 200 ns SCK DATA and in normal mode, to read during acquisition. The desired Number_SCK_Edges = 65 MHz × 200 ns = 13 SCK frequency largely determines which reading option to pursue. Thirteen bits are read during conversion (n), and five bits are read during acquisition (n). Reading During Conversion, Fast Hosts (Turbo or Normal Mode) For normal mode (1.5 MSPS), When reading during conversion (n), conversion results are for f = 50 MHz; t = 300 ns SCK DATA the previous (n − 1) conversion. Reading should only occur up Number_SCK_Edges = 50 MHz × 300 ns = 15 to t and, because this time is limited, the host must use a DATA Fifteen bits are read during conversion (n), and three bits are fast SCK. read during acquisition (n). The required SCK frequency is calculated by For slow throughputs, the time restriction is dictated by the Number _ SCK _ Edges user’s required throughput, and the host is free to run at any f ≥ SCK t DATA speed. Similar to the reading during acquisition, for slow hosts, the data access must take place during the acquisition phase To determine the SCK frequency, follow these examples to read with additional time into the conversion. data from conversion (n − 1). Note that data access spanning conversion requires the CNV to Turbo mode (2 MSPS): be driven high to initiate a new conversion, and data access is Number_SCK_Edges = 18; t = 200 ns DATA not allowed when CNV is high. Thus, the host must perform f = 18/200 ns = 90 MHz two bursts of data access when using this method. SCK Normal mode (1.5 MSPS): Reading During Acquisition, Any Speed Hosts (Turbo or Normal Mode) Number_SCK_Edges = 18; t = 300 ns DATA When reading during acquisition (n), conversion results are f = 18/300 ns = 60 MHz SCK for the previous (n − 1) conversion. Maximum throughput is The time between t and t is an I/O quiet time where DATA CONV achievable in normal mode (1.5 MSPS); however, in turbo digital activity should not occur, or sensitive bit decisions may mode, 2 MSPS throughput is not achievable. be corrupt. For the maximum throughput, the only time restriction is that Split-Reading, Any Speed Host (Turbo or Normal Mode) the reading takes place during the t (minimum) time. For ACQ To allow for slower SCK, there is the option of a split read where slow throughputs, the time restriction is dictated by throughput data access starts at the current acquisition (n) and spans into the required by the user, and the host is free to run at any speed. conversion (n). Conversion results are for the previous (n − 1) Thus for slow hosts, data access must take place during the conversion. acquisition phase. Similar to reading during conversion, split-reading should only occur up to t . For the maximum throughput, the only time DATA restriction is that split-reading take place during the t ACQ (minimum) + t − t time. The time between the falling DATA QUIET edge of SCK and CNV rising is an acquisition quiet time, t . QUIET Rev. B | Page 18 of 28 AD7986 conversion time elapses and then held high for the maximum CS MODE, 3-WIRE WITHOUT BUSY INDICATOR possible conversion time to avoid the generation of the busy This mode is usually used when a single AD7986 is connected signal indicator. When the conversion is complete, the AD7986 to an SPI-compatible digital host. The connection diagram is enters the acquisition phase and powers down. When CNV shown in Figure 25, and the corresponding timing is given in goes low, the MSB is output onto SDO. The remaining data bits Figure 26. are clocked by subsequent SCK falling edges. The data is valid on With SDI tied to VIO, a rising edge on CNV initiates a conversion, both SCK edges. Although the rising edge can be used to selects the CS mode, and forces SDO to high impedance. Once capture the data, a digital host using the SCK falling edge allows a conversion is initiated, it continues until completion irrespective a faster reading rate, provided that it has an acceptable hold th of the state of CNV. This can be useful, for instance, to bring time. After the 18 SCK falling edge or when CNV goes high CNV low to select other SPI devices, such as analog multiplexers; (whichever occurs first), SDO returns to high impedance. however, CNV must be returned high before the minimum CONVERT DIGITAL HOST CNV VIO SDI SDO DATA IN AD7986 SCK CLK Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) t CYC > t CONV t t CONV CONV t t DATA DATA t SDI = 1 CNVH CNV t ACQ ACQUISITION (I/O QUIET (QUIET (I/O QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n - 1) TIME) TIME) TIME) (n + 1) t QUIET SCK 16 17 18 1 2 16 17 18 t SCK t HSDO t EN t t DSDO EN SDO 2 1 0 17 16 15 2 1 0 t END DATA (n – 2) t t END DATA (n – 1) t DIS DIS BEGIN DATA (n – 1) DIS DIS Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 19 of 28 07956-018 07956-116 AD7986 When the conversion is complete, SDO goes from high imped- CS MODE, 3-WIRE WITH BUSY INDICATOR ance to low impedance. With a pull-up on the SDO line, this This mode is usually used when a single AD7986 is connected transition can be used as an interrupt signal to initiate the data to an SPI-compatible digital host having an interrupt input. reading controlled by the digital host. The AD7986 then enters It is only available in normal conversion mode (TURBO = low). the acquisition phase and powers down. The data bits are then The connection diagram is shown in Figure 27, and the clocked out, MSB first, by subsequent SCK falling edges. The corresponding timing is given in Figure 28. data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling With SDI tied to VIO, a rising edge on CNV initiates a conversion, edge allows a faster reading rate, provided that it has an acceptable selects the CS mode, and forces SDO to high impedance. SDO th hold time. After the optional 19 SCK falling edge, SDO returns is maintained in high impedance until the completion of the to high impedance. conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, If multiple AD7986 devices are selected at the same time, the such as analog multiplexers, but CNV must be returned low SDO output pin handles this contention without damage or before the minimum conversion time elapses and then held low induced latch-up. Meanwhile, it is recommended to keep this for the maximum possible conversion time to guarantee the contention as short as possible to limit extra power dissipation. generation of the busy signal indicator. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI AD7986 SDO DATA IN IRQ SCK TURBO CLK CS Figure 27. Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) TURBO = 0 SDI = 1 t CYC t CNVH CNV t t CONV ACQ (QUIET ACQUISITION CONVERSION ACQUISITION TIME) t SCK t t QUIET SCKL SCK 1 2 3 17 18 19 t t HSDO SCKH t t DSDO DIS SDO D17 D16 D1 D0 Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 20 of 28 07956-020 07956-021 AD7986 but SDI must be returned high before the minimum conversion CS MODE, 4-WIRE WITHOUT BUSY INDICATOR time elapses and then held high for the maximum possible This mode is usually used when multiple AD7986 devices are conversion time to avoid the generation of the busy signal connected to an SPI-compatible digital host. indicator. When the conversion is complete, the AD7986 enters A connection diagram example using two AD7986 devices is the acquisition phase and powers down. Each ADC result can shown in Figure 29, and the corresponding timing is given in be read by bringing its SDI input low, which consequently Figure 30. outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on With SDI high, a rising edge on CNV initiates a conversion, selects both SCK edges. Although the rising edge can be used to capture the CS mode, and forces SDO to high impedance. In this mode, the data, a digital host using the SCK falling edge allows a faster CNV must be held high during the conversion phase and the reading rate, provided that it has an acceptable hold time. After subsequent data readback. (If SDI and CNV are low, SDO is th the 18 SCK falling edge, SDO returns to high impedance and driven low.) Prior to the minimum conversion time, SDI can be another AD7986 can be read. used to select other SPI devices, such as analog multiplexers, CS2 CS1 CONVERT CNV CNV DIGITAL HOST SDI SDO AD7986 SDI AD7986 SDO SCK SCK DATA IN CLK Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram t CYC t t CONV CONV t t DATA DATA CNV t ACQ ACQUISITION (I/O QUIET (QUIET (I/O QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n + 1) (n – 1) TIME) TIME) TIME) t HSDICNV SDI t SSDICNV t QUIET SCK 16 17 18 1 2 16 17 18 t SCK t HSDO t EN t t EN DSDO 2 1 0 17 16 15 2 1 0 SDO END DATA (n – 2) t t t HSDO BEGIN DATA (n – 1) END DATA (n – 1) DIS DIS Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. B | Page 21 of 28 07956-022 07956-120 AD7986 used to select other SPI devices, such as analog multiplexers, CS MODE, 4-WIRE WITH BUSY INDICATOR but SDI must be returned low before the minimum conversion This mode is usually used when a single AD7986 is connected time elapses and then held low for the maximum possible to an SPI-compatible digital host with an interrupt input and conversion time to guarantee the generation of the busy signal when it is desired to keep CNV, which is used to sample the indicator. When the conversion is complete, SDO goes from analog input, independent of the signal used to select the data high impedance to low impedance. With a pull-up on the SDO reading. This independence is particularly important in line, this transition can be used as an interrupt signal to initiate applications where low jitter on CNV is desired. This mode is the data readback controlled by the digital host. The AD7986 only available in normal conversion mode (TURBO = low). then enters the acquisition phase and powers down. The data The connection diagram is shown in Figure 31, and the bits are then clocked out, MSB first, by subsequent SCK falling corresponding timing is given in Figure 32. edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the With SDI high, a rising edge on CNV initiates a conversion, SCK falling edge allows a faster reading rate, provided that it CS selects the mode, and forces SDO to high impedance. In this th has an acceptable hold time. After the optional 19 SCK falling mode, CNV must be held high during the conversion phase and edge or SDI going high (whichever occurs first), SDO returns to the subsequent data readback. (If SDI and CNV are low, SDO is high impedance. driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ SDI SDO DATA IN AD7986 IRQ TURBO SCK CLK CS Figure 31. Mode, 4-Wire with Busy Indicator Connection Diagram TURBO = 0 t CYC CNV t t CONV ACQ (I/O QUIET ACQUISITION CONVERSION ACQUISITION TIME) t SSDICNV SDI t SCK t HSDICNV t t SCKL QUIET SCK 1 2 3 17 18 19 t t HSDO SCKH t t DSDO DIS t EN SDO D17 D16 D1 D0 Figure 32. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. B | Page 22 of 28 07956-024 07956-025 AD7986 held high during the conversion phase and the subsequent data CHAIN MODE WITHOUT BUSY INDICATOR readback. When the conversion is complete, the MSB is output This mode can be used to daisy-chain multiple AD7986 devices onto SDO, and the AD7986 enters the acquisition phase and on a 3-wire serial interface. It is only available in normal conver- powers down. The remaining data bits stored in the internal sion mode (TURBO = low). This feature is useful for reducing shift register are clocked by subsequent SCK falling edges. For component count and wiring connections, for example, in each ADC, SDI feeds the input of the internal shift register and isolated multiconverter applications or for systems with a is clocked by the SCK falling edge. Each ADC in the chain limited interfacing capacity. Data readback is analogous to outputs its data MSB first, and 18 × N clocks are required to clocking a shift register. read back the N ADCs. The data is valid on both SCK edges. A connection diagram example using two AD7986 devices is Although the rising edge can be used to capture the data, a shown in Figure 33, and the corresponding timing is given in digital host using the SCK falling edge allows a faster reading Figure 34. rate and consequently more AD7986 devices in the chain, When SDI and CNV are low, SDO is driven low. With SCK low, provided that the digital host has an acceptable hold time. The a rising edge on CNV initiates a conversion, selects the chain maximum conversion rate may be reduced due to the total mode, and disables the busy indicator. In this mode, CNV is readback time. CONVERT CNV CNV DIGITAL HOST SDI AD7986 SDO SDI AD7986 SDO DATA IN A B TURBO TURBO SCK SCK CLK Figure 33. Chain Mode Without Busy Indicator Connection Diagram TURBO= 0 t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t t SSCKCNV SCKH SCK 1 2 3 4 17 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t t SCKL t DSDOSDI t HSDISCK EN SDO = SDI D 17 D 16 D 15 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 17 D 16 D 15 D 1 D 0 D 17 D 16 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 17 D 16 D 15 D 1 D 0 D 17 D 16 D 1 D 0 D 17 D 16 D 1 D 0 C C C C C B B B B A A A A Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 23 of 28 07956-026 07956-027 AD7986 subsequent data readback. When all ADCs in the chain have CHAIN MODE WITH BUSY INDICATOR completed their conversions, the SDO pin of the ADC closest to This mode can also be used to daisy-chain multiple AD7986 the digital host (see the AD7986 ADC labeled C in Figure 35) is devices on a 3-wire serial interface while providing a busy driven high. This transition on SDO can be used as a busy indicator indicator. This feature is useful for reducing component count to trigger the data readback controlled by the digital host. The and wiring connections, for example, in isolated multiconverter AD7986 then enters the acquisition phase and powers down. applications or for systems with a limited interfacing capacity. The data bits stored in the internal shift register are clocked out, Data readback is analogous to clocking a shift register. A MSB first, by subsequent SCK falling edges. For each ADC, SDI connection diagram example using three AD7986 devices is feeds the input of the internal shift register and is clocked by the shown in Figure 35, and the corresponding timing is given in SCK falling edge. Each ADC in the chain outputs its data MSB Figure 36. first, and 18 × N + 1 clocks are required to read back the N ADCs. When SDI and CNV are low, SDO is driven low. With SCK Although the rising edge can be used to capture the data, a digital high, a rising edge on CNV initiates a conversion, selects the host using the SCK falling edge allows a faster reading rate and chain mode, and enables the busy indicator feature. In this consequently more AD7986 devices in the chain, provided that mode, CNV is held high during the conversion phase and the the digital host has an acceptable hold time. CONVERT CNV CNV CNV DIGITAL HOST SDI AD7986 SDO SDI AD7986 SDO SDI SDO AD7986 DATA IN A B C IRQ SCK SCK SCK TURBO TURBO TURBO CLK Figure 35. Chain Mode with Busy Indicator Connection Diagram TURBO = 0 t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t t QUIET SCKH SCK 1 2 3 4 17 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t HSDISCK EN SDO = SDI D 17 D 16 D 15 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 17 D 16 D 15 D 1 D 0 D 17 D 16 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 17 D 16 D 15 D 1 D 0 D 17 D 16 D 1 D 0 D 17 D 16 D 1 D 0 C C C C C B B B B A A A A Figure 36. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 24 of 28 07956-028 07956-029 AD7986 APPLICATION HINTS The AD7986 voltage reference input, REF, has a dynamic input LAYOUT impedance and should be decoupled with minimal parasitic induc- The printed circuit board (PCB) that houses the AD7986 should tances. This is done by placing the reference decoupling ceramic be designed so that the analog and digital sections are separated capacitor close to, ideally right up against, the REF and REFGND and confined to certain areas of the board. The pinout of the pins and connecting them with wide, low impedance traces. AD7986, with its analog signals on the left side and its digital Finally, the power supplies, VDD and VIO of the AD7986, signals on the right side, eases this task. should be decoupled with ceramic capacitors, typically 100 nF, Avoid running digital lines under the device because these couple placed close to the AD7986 and connected using short, wide noise onto the die, unless a ground plane under the AD7986 is traces to provide low impedance paths and to reduce the effect used as a shield. Fast switching signals, such as CNV or clocks, of glitches on the power supply lines. should not run near analog signal paths. Crossover of digital and analog signals should be avoided. EVALUATING THE AD7986 PERFORMANCE At least one ground plane should be used. It can be common or The evaluation board package for the AD7986 (EVAL-AD7986EB) split between the digital and analog sections. In the latter case, includes a fully assembled and tested evaluation board and soft- the planes should be joined underneath the AD7986 devices. ware for controlling the board from a PC via the converter evaluation and development board, EVAL-CED1Z. Rev. B | Page 25 of 28 AD7986 BVDD AVDD REF REF REF PADDLE 1 2 GND GND 3 GND GND 4 DVDD 5 6 GND GND GND VIO Figure 37. Example Layout of the AD7986 (Top Layer) 5V EXTERNAL BVDD AVDD CAVDD REFERENCE CBVDD (ADR435 OR ADR445) REF REF REF GND CREF GND GND CDVDD GND GND DVDD GND GND GND VIO CVIO VIO Figure 38. Example Layout of the AD7986 (Bottom Layer) Rev. B | Page 26 of 28 07956-031 07956-030 AD7986 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 16 20 1 PIN 1 0.50 2.65 3.75 EXPOSED INDICATOR BSC BSC SQ PAD 2.50 SQ (BOTTOM VIEW) 2.35 5 10 6 11 0.50 0.25 MIN TOP VIEW 0.40 0.30 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Package Ordering 1, 2, 3 Model Temperature Range Package Description Option Quantity AD7986BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray CP-20-4 490 AD7986BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-20-4 1,500 EVAL-AD7986EBZ Evaluation Board EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD7986EBZ can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. 3 The EVAL-CED1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the EB designator. Rev. B | Page 27 of 28 PIN 1 INDICATOR 090408-B AD7986 NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07956-0-3/11(B) Rev. B | Page 28 of 28