ANALOG DEVICES AD7985

16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP AD7985 FEATURES APPLICATION DIAGRAM 1.8V 16-bit resolution with no missing codes TO 5V 2.5V 2.7V Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low) Low power dissipation VIO BVDD AVDD, 15.5 mW at 2.5 MSPS, with external reference DVDD 0V TURBO VIO TO 28 mW at 2.5 MSPS, with internal reference IN+ SDI 3- OR 4-WIRE V REF AD7985 INTERFACE: INL: ±0.7 LSB typical, ±1.5 LSB maximum SCK IN– SPI, CS, SDO SNR DAISY CHAIN CNV (TURBO = LOW) GND REF 88.5 dB, with on-chip reference 90 dB, with external reference 10µF 4.096 V internal reference: typical drift of ±10 ppm/°C Pseudo differential analog input voltage range NOTES 0 V to V with V up to 5.0 V REF REF 1. GND REFERS TO REFGND, AGND, AND DGND. Allows use of any input range Figure 1. No pipeline delay GENERAL DESCRIPTION Logic interface: 1.8 V/2.5 V/2.7 V The AD7985 is a 16-bit, 2.5 MSPS successive approximation Serial interface: SPI-/QSPI™-/MICROWIRE™-/DSP-compatible analog-to-digital converter (SAR ADC). It contains a low power, Ability to daisy-chain multiple ADCs with busy indicator high speed, 16-bit sampling ADC, an internal conversion clock, 20-lead, 4 mm × 4 mm LFCSP (QFN) an internal reference (and buffer), error correction circuits, and APPLICATIONS a versatile serial interface port. On the rising edge of CNV, the Battery-powered equipment AD7985 samples an analog input, IN+, between 0 V and REF Communications with respect to a ground sense, IN−. The AD7985 features a ATE very high sampling rate turbo mode (TURBO is high) and a Data acquisition systems reduced power normal mode (TURBO is low) for low power Medical instruments applications where the power is scaled with the throughput. In normal mode (TURBO is low), the SPI-compatible serial inter- face also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V supplies using the separate VIO supply. The AD7985 is available in a 20-lead LFCSP with operation specified from −40°C to +85°C. 1 Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR® ADCs Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 2 2 14-Bit AD7940 AD7942 AD7946 2 2 2 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4941-1 2 2 2 AD7683 AD7687 AD7688 AD7983 ADA4841-x 2 3 AD7684 AD7694 AD7693 AD7985 AD8021 2 2 2 18-Bit AD7691 AD7690 AD7982 ADA4941-1 2 AD7984 ADA4841-x 3 AD7986 AD8021 1 See www.analog.com for the latest selection of PulSAR ADCs and ADC drivers. 2 Pin-for-pin compatible with all other parts marked with this endnote. 3 The AD7985 and AD7986 are pin-for-pin compatible. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved. 07947-001 AD7985 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Application Diagram ........................................................................ 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply ............................................................................... 16 Revision History ............................................................................... 2 Digital Interface .............................................................................. 17 Specifications ..................................................................................... 3 Data Reading Options ............................................................... 18 Timing Specifications .................................................................. 5 CS Mode, 3-Wire Without Busy Indicator ............................. 19 Absolute Maximum Ratings ............................................................ 6 CS Mode, 3-Wire with Busy Indicator .................................... 20 ESD Caution .................................................................................. 6 CS Mode, 4-Wire Without Busy Indicator ............................. 21 Pin Configuration and Function Descriptions ............................. 7 CS Mode, 4-Wire with Busy Indicator .................................... 22 Typical Performance Characteristics ............................................. 9 Chain Mode Without Busy Indicator ...................................... 23 Terminology .................................................................................... 12 Chain Mode with Busy Indicator ............................................. 24 Theory of Operation ...................................................................... 13 Applications Information .............................................................. 25 Circuit Information .................................................................... 13 Layout .......................................................................................... 25 Converter Operation .................................................................. 13 Evaluating AD7985 Performance ............................................. 25 Conversion Modes of Operation .............................................. 13 Outline Dimensions ....................................................................... 27 Typical Connection Diagram.................................................... 14 Ordering Guide .......................................................................... 27 REVISION HISTORY 8/10—Rev. 0 to Rev. A Change to Table 4, Conversion Time: CNV Rising Edge to Data Available ............................................................................... 5 9/09—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7985 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range (IN+) − (IN−) 0 V V REF Absolute Input Voltage IN+ −0.1 V + 0.1 V REF IN− −0.1 +0.1 V Leakage Current at 25°C Acquisition phase 250 nA Input Impedance See the Analog Inputs section ACCURACY No Missing Codes 16 Bits 1 Differential Nonlinearity Error, DNL −0.99 ±0.50 +0.99 LSB 1 Integral Nonlinearity Error, INL −1.50 ±0.7 +1.50 LSB 1 Transition Noise 0.8 LSB 2 1 Gain Error, T to T −15 ±2 +15 LSB MIN MAX Gain Error Temperature Drift ±0.8 ppm/°C 2 Zero Error, TMIN to TMAX −0.99 ±0.08 +0.99 mV Zero Temperature Drift 0.55 ppm/°C 3 Power Supply Sensitivity AVDD = 2.5 V ± 5% 90 dB THROUGHPUT Conversion Rate 0 2.5 MSPS Transient Response Full-scale step 100 ns AC ACCURACY 3 Dynamic Range V = 4.096 V, internal reference 87.5 89 dB REF 3 V = 5.0 V, external reference 89.0 90 dB REF 3 Signal-to-Noise Ratio, SNR f = 20 kHz, V = 4.096 V, internal 87.0 88.5 dB IN REF reference 3 fIN = 20 kHz, VREF = 5.0 V, external 89.0 90.0 dB reference 3 Spurious-Free Dynamic Range, SFDR f = 20 kHz 103 dB IN 4 3 Total Harmonic Distortion , THD f = 20 kHz, V = 4.096 V, internal −100 dB IN REF reference 3 Signal-to-Noise-and-Distortion Ratio, fIN = 20 kHz, VREF = 4.096 V 90.5 dB SINAD SAMPLING DYNAMICS −3 dB Input Bandwidth 19 MHz Aperture Delay 0.7 ns 1 LSB means least significant bit. With the ±4.096 V input range, one LSB is 62.5 µV. 2 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 3 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Tested fully in production at f = 1 kHz. IN Rev. A | Page 3 of 28 AD7985 Table 3. Parameter Test Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE PDREF is low Output Voltage TA = 25°C 4.081 4.096 4.111 V Temperature Drift −40°C to +85°C ±10 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±50 ppm/V Turn-On Settling Time C = 10 μF, C = 0.1 μF 40 ms REF REFIN REFIN Output Voltage REFIN at 25°C 1.2 V REFIN Output Resistance 6 kΩ EXTERNAL REFERENCE PDREF is high, REFIN is low Voltage Range 2.4 5.1 V Current Drain 500 µA REFERENCE BUFFER REFIN Input Voltage Range 1.2 V REFIN Input Current 160 µA DIGITAL INPUTS Logic Levels VIL −0.3 0.1 × VIO V V 0.9 × VIO VIO + 0.3 V IH I −1 +1 µA IL IIH −1 +1 µA DIGITAL OUTPUTS Data Format Serial 16 bits, straight binary Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = +500 µA 0.4 V V I = −500 µA VIO − 0.3 V OH SOURCE POWER SUPPLIES AVDD, DVDD 2.375 2.5 2.625 V BVDD 4.75 5.0 5.25 V VIO Specified performance 1.8 2.5 2.7 V 1, 2 Standby Current AVDD = DVDD = VIO = 2.5 V 1.0 µA Power Dissipation With Internal Reference 2.5 MSPS throughput 28 33 mW 2.0 MSPS throughput 25 30 mW With External Reference 2.5 MSPS throughput 15.5 17 mW 2.0 MSPS throughput 12 13 mW 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. A | Page 4 of 28 AD7985 TIMING SPECIFICATIONS 1 AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Conversion Time: CNV Rising Edge t Turbo mode/normal mode 320/420 ns CONV to Data Available Acquisition Time tACQ 80 ns Time Between Conversions t Turbo mode/normal mode 400/500 ns CYC CNV Pulse Width t CS mode 10 ns CNVH Data Read During Conversion t Turbo mode/normal mode 190/290 ns DATA Quiet Time During Acquisition from Last SCK tQUIET 20 ns Falling Edge to CNV Rising Edge SCK Period tSCK CS mode 9 ns t Chain mode 11 ns SCK SCK Low Time t 3.5 ns SCKL SCK High Time t 3.5 ns SCKH SCK Falling Edge to Data Remains Valid tHSDO 2 ns SCK Falling Edge to Data Valid Delay tDSDO 4 ns CNV or SDI Low to SDO D15 MSB Valid tEN 5 ns CNV or SDI High or Last SCK Falling Edge t CS mode 8 ns DIS to SDO High Impedance SDI Valid Setup Time from CNV Rising Edge tSSDICNV 4 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV CS mode 0 ns tHSDICNV Chain mode 0 ns SCK Valid Setup Time from CNV Rising Edge t Chain mode 5 ns SSCKCNV SCK Valid Hold Time from CNV Rising Edge t Chain mode 5 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge t Chain mode 2 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge tHSDISCK Chain mode 3 ns SDI High to SDO High tDSDOSDI Chain mode with busy indicator 15 ns 1 See Figure 2 and Figure 3 for load conditions. 10% VIO 500µA I OL 90% VIO t t DELAY DELAY 1 1 V V IH 1.4V IH TO SDO 1 1 V V IL IL C L 20pF 1 MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3. 500µA I OH Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. A | Page 5 of 28 07947-002 07947-003 AD7985 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs other conditions above those indicated in the operational 1 IN+, IN− to GND −0.3 V to V + 0.3 V REF section of this specification is not implied. Exposure to absolute or ±130 mA maximum rating conditions for extended periods may affect Supply Voltage device reliability. REF, BVDD to GND, REFGND −0.3 V to +6.0 V AVDD, DVDD, VIO to GND −0.3 V to +2.7 V AVDD, DVDD to VIO −6 V to +3 V ESD CAUTION Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 20-Lead LFCSP (QFN) 30.4°C/W Lead Temperatures Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section for an explanation of IN+ and IN −. Rev. A | Page 6 of 28 AD7985 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR REF 1 15 TURBO REF 2 14 SDI AD7985 REFGND 3 13 CNV TOP VIEW REFGND 4 12 SCK (Not to Scale) IN– 5 11 DVDD NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 2 REF AI Reference Output/Input Voltage. When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin. When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V. Decoupling is required with or without the internal reference and buffer. This pin is referred to the REFGND pins and should be decoupled closely to the REFGND pins with a 10 µF capacitor. 3, 4 REFGND AI Reference Input Analog Ground. 5 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense. 6 IN+ AI Analog Input. This pin is referred to IN −. The voltage range, that is, the difference between IN+ and IN− , is 0 V to VREF. 7 PDREF DI Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When this pin is high, the internal reference is powered down and an external reference must be used. 8 VIO P Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface (1.8 V, 2.5 V, or 2.7 V). 9 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 10 DGND P Digital Power Ground. 11 DVDD P Digital Power. Nominally at 2.5 V. 12 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 13 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 14 SDI DI Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 15 TURBO DI Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved, and the ADC does not power down between conversions. When TURBO is low, the maximum throughput is lower (2.0 MSPS), and the ADC powers down between conversions. 16 AVDD P Input Analog Power. Nominally at 2.5 V. 17, 18 AGND P Analog Power Ground. Rev. A | Page 7 of 28 07947-004 IN+ 6 20 REFIN 19 BVDD PDREF 7 VIO 8 18 AGND SDO 9 17 AGND DGND 10 16 AVDD AD7985 1 Pin No. Mnemonic Type Description 19 BVDD P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. 20 REFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin. When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD. 21 Exposed Pad EP The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power. Rev. A | Page 8 of 28 AD7985 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF is high, REFIN is low), unless otherwise noted. 1.25 1.00 POSITIVE INL = +0.38LSB POSITIVE DNL = +0.19LSB NEGATIVE INL = –0.46LSB NEGATIVE DNL = –0.20LSB 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.25 –1.00 0 16,384 32,768 49,152 65,536 0 16,384 32,768 49,152 65,536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 60,000 60,000 57,138 53,522 48,730 50,000 50,000 38,843 40,000 40,000 30,000 30,000 26,249 20,000 20,000 15,645 11,888 10,000 10,000 6150 2537 800 479 0 122 33 0 0 2 6 0 0 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX CODE IN HEX Figure 6. Histogram of DC Input at Code Center (External Reference) Figure 9. Histogram of DC Input at Code Transition (External Reference) 60,000 50,000 46,649 43,622 45,000 49,585 50,000 40,000 35,000 40,000 30,000 33,064 31,957 30,000 25,000 20,474 20,000 15,598 20,000 15,000 10,000 8455 10,000 7024 5000 2947 1662 565 403 0 11 8 0 0 90 30 0 0 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 CODE IN HEX CODE IN HEX Figure 7. Histogram of DC Input at Code Center (Internal Reference) Figure 10. Histogram of DC Input at Code Transition (Internal Reference) Rev. A | Page 9 of 28 INL (LSB) COUNTS COUNTS 07947-107 07947-106 07947-105 DNL (LSB) COUNTS COUNTS 07947-110 07947-109 07947-108 AD7985 0 0 f = 2.5MSPS f = 2.5MSPS S S f = 20kHz f = 20kHz IN IN –20 –20 SNR = 89.87dB SNR = 88.45dB THD = –102.76dB THD = –103.42dB –40 –40 SINAD = 89.66dB SINAD = 88.32dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. FFT Plot (External Reference) Figure 14. FFT Plot (Internal Reference) 100 –90 16 100 95 15 –95 95 SFDR ENOB SNR 90 14 –100 90 SINAD 85 13 –105 85 THD 80 12 –110 80 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD and SFDR vs. Reference Voltage 95 –85 90 –90 85 –95 80 –100 75 –105 70 65 –110 1 10 100 1000 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 13. SINAD vs. Frequency Figure 16. THD vs. Frequency Rev. A | Page 10 of 28 SNR, SINAD (dB) AMPLITUDE (dB) SINAD (dB) ENOB (Bits) 07947-113 07947-111 07947-112 THD (dB) THD (dB) AMPLITUDE (dB) SFDR (dB) 07947-114 07947-116 07947-115 AD7985 95 2.0 94 1.8 I AVDD 93 1.6 92 1.4 91 1.2 90 1.0 89 0.8 I BVDD 88 0.6 I REF 87 0.4 86 0.2 85 0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 –55 –35 –15 5 25 45 65 85 105 125 INPUT LEVEL (dBFS) TEMPERATURE (°C) Figure 17. SNR vs. Input Level Figure 19. Operating Current vs. Temperature 2.0 14 1.8 I AVDD 12 1.6 I DVDD 10 1.4 I VIO 1.2 8 1.0 6 0.8 I BVDD 0.6 4 I REF I + I + I AVDD DVDD VIO 0.4 2 0.2 0 0 2.375 2.425 2.475 2.525 2.575 2.625 –55 –35 –15 5 25 45 65 85 105 125 AVDD AND DVDD VOLTAGE (V) TEMPERATURE (°C) Figure 18. Operating Current vs. Supply Voltage Figure 20. Power-Down Current vs. Temperature Rev. A | Page 11 of 28 OPERATING CURRENT (mA) SNR (dB) 07947-117 07947-118 OPERATING CURRENT (mA) SUPPLY CURRENT (µA) 07947-120 07947-119 AD7985 TERMINOLOGY Aperture Delay Noise-Free Code Resolution Aperture delay is the measure of the acquisition performance Noise-free code resolution is the number of bits beyond which it and is the time between the rising edge of the CNV input and is impossible to distinctly resolve individual codes. It is expressed when the input signal is held for a conversion. in bits and is calculated as follows: N Differential Nonlinearity Error (DNL) Noise-Free Code Resolution = log (2 /Peak-to-Peak Noise) 2 In an ideal ADC, code transitions are 1 LSB apart. DNL is the Signal-to-Noise Ratio (SNR) maximum deviation from this ideal value. It is often specified in SNR is the ratio of the rms value of the actual input signal to terms of resolution for which no missing codes are guaranteed. the rms sum of all other spectral components below the Nyquist Dynamic Range frequency, excluding harmonics and dc. The value for SNR is Dynamic range is the ratio of the rms value of the full scale to expressed in decibels. the total rms noise measured with the inputs shorted together. Signal-to-Noise-and-Distortion Ratio (SINAD) The value for dynamic range is expressed in decibels. It is mea- SINAD is the ratio of the rms value of the actual input signal to sured with a signal at −60 dBFS so that it includes all noise the rms sum of all other spectral components below the Nyquist sources and DNL artifacts. frequency, including harmonics but excluding dc. The value for Effective Number of Bits (ENOB) SINAD is expressed in decibels. ENOB is a measurement of the resolution with a sine wave Spurious-Free Dynamic Range (SFDR) input. It is expressed in bits and is related to SINAD as follows: SFDR is the difference, in decibels (dB), between the rms ENOB = (SINADdB − 1.76)/6.02 amplitude of the input signal and the peak spurious signal. Effective Resolution Total Harmonic Distortion (THD) Effective resolution is expressed in bits and is calculated as follows: THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is N Effective Resolution = log (2 /RMS Input Noise) 2 expressed in decibels. Gain Error Transient Response The last transition (from 111 … 10 to 111 … 11) should occur Transient response is the time required for the ADC to accurately for an analog voltage 1½ LSB below the nominal full scale acquire its input after a full-scale step function is applied. (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the difference between the actual level of the last Zero Error transition and the actual level of the first transition from the Zero error is the difference between the ideal midscale voltage, difference between the ideal levels. that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Rev. A | Page 12 of 28 AD7985 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 32,768C 16,384C 4C 2C C C LSB SW– MSB CNV IN– Figure 21. ADC Simplified Schematic When the conversion phase begins, SW+ and SW− are opened CIRCUIT INFORMATION first. The two capacitor arrays are then disconnected from the The AD7985 is a fast, low power, single-supply, precise, 16-bit analog inputs and connected to the REFGND input. Therefore, ADC using a successive approximation architecture. The AD7985 the differential voltage between the IN+ and IN − inputs captured features different modes to optimize performance according to the at the end of the acquisition phase is applied to the comparator application. In turbo mode, the AD7985 is capable of converting inputs, causing the comparator to become unbalanced. By switch- 2,500,000 samples per second (2.5 MSPS). ing each element of the capacitor array between REFGND and The AD7985 provides the user with an on-chip track-and-hold REF, the comparator input varies by binary-weighted voltage and does not exhibit any pipeline delay or latency, making it steps (V /2, V /4, … V /65,536). The control logic toggles REF REF REF ideal for multiple multiplexed channel applications. these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this The AD7985 can be interfaced to any 1.8 V to 2.7 V digital logic process, the part returns to the acquisition phase, and the control family. It is available in a space-saving 20-lead LFCSP that allows flexible configurations. It is pin-for-pin compatible with the logic generates the ADC output code and a busy signal indicator. 18-bit AD7986. Because the AD7985 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. CONVERTER OPERATION The AD7985 is a successive approximation ADC based on a CONVERSION MODES OF OPERATION charge redistribution DAC. Figure 21 shows the simplified The AD7985 features two conversion modes of operation: turbo schematic of the ADC. The capacitive DAC consists of two and normal. Turbo conversion mode (TURBO is high) allows identical arrays of 16 binary-weighted capacitors that are the fastest conversion rate of up to 2.5 MSPS and does not connected to the two comparator inputs. power down between conversions. The first conversion in turbo During the acquisition phase, the terminals of the array tied to mode should be ignored because it contains meaningless data. For applications that require lower power and slightly slower the input of the comparator are connected to AGND via SW+ sampling rates, the normal mode (TURBO is low) allows a and SW−. All independent switches are connected to the analog maximum conversion rate of 2.0 MSPS and powers down inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− between conversions. The first conversion in normal mode inputs. When the acquisition phase is completed and the CNV contains meaningful data. input goes high, a conversion phase is initiated. Rev. A | Page 13 of 28 07947-005 AD7985 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Analog Input, Digital Output The ideal transfer characteristic for the AD7985 is shown in Description V = 4.096 V Code (Hex) REF Figure 22 and Table 7. 1 FSR – 1 LSB 4.095938 V 0xFFFF Midscale + 1 LSB 2.048063 V 0x8001 111 ... 111 Midscale 2.048 V 0x8000 111 ... 110 Midscale – 1 LSB 2.047938 V 0x7FFF 111 ... 101 –FSR + 1 LSB 62.5 µV 0x0001 2 –FSR 0 V 0x0000 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − REFGND). 2 This is also the code for an underranged analog input (VIN+ − VIN− below REFGND). 000 ... 010 TYPICAL CONNECTION DIAGRAM 000 ... 001 000 ... 000 Figure 23 shows an example of the recommended connection –FSR –FSR + 1 LSB +FSR – 1 LSB diagram for the AD7985 when multiple supplies are available. –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function 1.8V TO 5V 2.5V 2.7V V+ VIO BVDD AVDD, DVDD VIO 15Ω TURBO IN+ SDI 3- OR 4-WIRE 0V TO V REF 2.7nF AD7985 INTERFACE: SCK IN– SPI, CS, V– SDO DAISY CHAIN CNV (TURBO = LOW) REF GND 10µF NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. Figure 23. Typical Application Diagram with Multiple Supplies Rev. A | Page 14 of 28 ADC CODE (STRAIGHT BINARY) 07947-006 07947-007 AD7985 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the input structure of Although the AD7985 is easy to drive, the driver amplifier must the AD7985. meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the • The noise generated by the driver amplifier must be kept as analog inputs, IN+ and IN−. Care must be taken to ensure that low as possible to preserve the SNR and transition noise the analog input signal does not exceed the reference input performance of the AD7985. The noise from the driver is voltage (REF) by more than 0.3 V. If the analog input signal filtered by the AD7985 analog input circuit’s one-pole, low- exceeds this level, the diodes become forward-biased and start pass filter, made by R and C , or by the external filter, if IN IN conducting current. These diodes can handle a forward-biased one is used. Because the typical noise of the AD7985 is current of 130 mA maximum. However, if the supplies of the 50 µV rms, the SNR degradation due to the amplifier is input buffer (for example, the V+ and V− supplies of the buffer   amplifier in Figure 23) are different from those of REF, the   50   analog input signal may eventually exceed the supply rails by SNR = 20 log LOSS   π 2 2 more than 0.3 V. In such a case (for example, an input buffer 50 + f (Ne )   −3dB N 2   with a short circuit), the current limitation can be used to protect the part. where: REF f–3dB is the input bandwidth, in megahertz, of the AD7985 (20 MHz) or the cutoff frequency of the input filter, if D1 C IN R IN one is used. IN+ OR IN– N is the noise gain of the amplifier (for example, 1 in buffer C D2 PIN REFGND configuration). e is the equivalent input noise voltage of the op amp, in N Figure 24. Equivalent Analog Input Circuit nV/√Hz. The analog input structure allows the sampling of the true • For ac applications, the driver should have a THD perfor- differential signal between IN+ and IN−. By using these mance commensurate with that of the AD7985. differential inputs, signals common to both inputs are rejected. • For multichannel multiplexed applications, the driver amplifier and the AD7985 analog input circuit must settle During the acquisition phase, the impedance of the analog inputs for a full-scale step onto the capacitor array at a 16-bit level (IN+ and IN−) can be modeled as a parallel combination of (0.0015%, 15 ppm). In the data sheet of the driver amplifier, Capacitor CPIN and the network formed by the series connection settling at 0.1% to 0.01% is more commonly specified. This of R and C . C is primarily the pin capacitance. R is typically IN IN PIN IN value may differ significantly from the settling time at a 400 Ω and is a lumped component composed of serial resistors 16-bit level and should be verified prior to driver selection. and the on resistance of the switches. C is typically 30 pF and IN is mainly the ADC sampling capacitor. Table 8. Recommended Driver Amplifiers During the sampling phase, where the switches are closed, the Amplifier Typical Application input impedance is limited to CPIN. RIN and CIN make a one-pole, AD8021 Very low noise and high frequency low-pass filter that reduces undesirable aliasing effects and AD8022 Low noise and high frequency limits noise. ADA4899-1 Ultralow noise and high frequency When the source impedance of the driving circuit is low, the AD8014 Low power and high frequency AD7985 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. A | Page 15 of 28 07947-008 AD7985 Reference Decoupling VOLTAGE REFERENCE INPUT The AD7985 voltage reference input, REF, has a dynamic input The AD7985 allows the choice of a very low temperature drift impedance that requires careful decoupling between the REF internal voltage reference, an external reference, or an external and REFGND pins. The Layout section describes how this can buffered reference. be done. The internal reference of the AD7985 provides excellent When using an external reference, a very low impedance source performance and can be used in almost all applications. (for example, a reference buffer using the AD8031 or the AD8605) Internal Reference, REF = 4.096 V (PDREF Low) and a 10 µF (X5R, 0805 size) ceramic chip capacitor are appro- To use the internal reference, the PDREF input must be low. priate for optimum performance. This enables the on-chip band gap reference and buffer, result- If an unbuffered reference voltage is used, the decoupling value ing in a 4.096 V reference on the REF pin (1.2 V on REFIN). depends on the reference used. For example, a 22 µF (X5R, The internal reference is temperature compensated to 1206 size) ceramic chip capacitor is appropriate for optimum 4.096 V ± 15 mV. The reference is trimmed to provide performance using a low temperature drift ADR43x reference. a typical drift of 10 ppm/°C. If desired, a reference decoupling capacitor with a value as small The output resistance of REFIN is 6 kΩ when the internal as 2.2 µF can be used with minimal impact on performance, reference is enabled. It is necessary to decouple this pin with a especially DNL. ceramic capacitor of at least 100 nF. The output resistance of In any case, there is no need for an additional lower value ceramic REFIN and the decoupling capacitor form an RC filter, which decoupling capacitor (for example, 100 nF) between the REF helps to reduce noise. and REFGND pins. Because the output impedance of REFIN is typically 6 kΩ, POWER SUPPLY relative humidity (among other industrial contaminants) can directly affect the drift characteristics of the reference. A guard The AD7985 has four power supply pins: an analog supply ring is typically used to reduce the effects of drift under such (AVDD), a buffer supply (BVDD), a digital supply (DVDD), circumstances. However, the fine pitch of the AD7985 makes and a digital input/output interface supply (VIO). VIO allows this difficult to implement. One solution, in these industrial direct interface with any logic from 1.8 V to 2.7 V. To reduce the and other types of applications, is to use a conformal coating, number of supplies needed, VIO, DVDD, and AVDD can be tied such as Dow Corning® 1-2577 or HumiSeal® 1B73. together. The power supplies do not need to be started in a par- ticular sequence. In addition, the AD7985 is very insensitive to External 1.2 V Reference and Internal Buffer (PDREF High) power supply variations over a wide frequency range. To use an external reference along with the internal buffer, PDREF In normal mode, the AD7985 powers down automatically at must be high. This powers down the internal reference and allows the end of each conversion phase and, therefore, the power the 1.2 V reference to be applied to REFIN, producing 4.096 V scales linearly with the sampling rate. This makes the part ideal (typically) on the REF pin. for low sampling rates (even a few SPS) and battery-powered External Reference (PDREF High, REFIN Low) applications. To apply an external reference voltage directly to the REF pin, 10 PDREF should be tied high and REFIN should be tied low. BVDD should also be driven to the same potential as REF. For example, if REF = 2.5 V, BVDD should be tied to 2.5 V. 1 The advantages of directly using an external voltage reference are as follows: • SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a larger reference voltage (5 V) 0.1 I BVDD instead of a typical 4.096 V reference when the internal I AVDD reference is used. This is calculated by I DVDD I VIO 4.096 I   VREF SNR = 20 log   0.01  5.0  0.1 1 SAMPLING RATE (MSPS) • Power savings when the internal reference is powered Figure 25. Operating Current vs. Sampling Rate in Normal Mode down (PDREF high). Rev. A | Page 16 of 28 OPERATING CURRENT (mA) 07947-121 AD7985 DIGITAL INTERFACE Although the AD7985 has a reduced number of pins, it offers The busy indicator feature is enabled in CS mode if CNV or flexibility in its serial interface modes. SDI is low when the ADC conversion ends (see Figure 29 and Figure 33). TURBO must be kept low for both digital interfaces. In CS mode, the AD7985 is compatible with SPI, MICROWIRE, CS When CNV is low, readback can occur during conversion or QSPI, and digital hosts. In mode, the AD7985 can use either acquisition, or it can be split across acquisition and conversion, a 3-wire or a 4-wire interface. A 3-wire interface that uses the as described in the following sections. CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for example, in isolated applications. A 4-wire A discontinuous SCK is recommended because the part is selected interface that uses the SDI, CNV, SCK, and SDO signals allows with CNV low, and SCK activity begins to clock out data. CNV, which initiates conversions, to be independent of the Note that in the following sections, the timing diagrams indicate readback timing (SDI). This is useful in low jitter sampling digital activity (SCK, CNV, SDI, and SDO) during the conversion. or simultaneous sampling applications. However, due to the possibility of performance degradation, digi- In chain mode, the AD7985 provides a daisy-chain feature that tal activity should occur only prior to the safe data reading time, uses the SDI input for cascading multiple ADCs on a single data t , because the AD7985 provides error correction circuitry DATA line similar to a shift register. Chain mode is available only in that can correct for an incorrect bit decision during this time. normal mode (TURBO is low). From t to t , there is no error correction, and conversion DATA CONV results may be corrupted. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI Similarly, tQUIET, the time from the last falling edge of SCK to is high, and chain mode is selected if SDI is low. The SDI hold the rising edge of CNV, must remain free of digital activity. time is such that when SDI and CNV are connected together, The user should configure the AD7985 and initiate the busy chain mode is always selected. indicator (if desired in normal mode) prior to t . DATA In normal mode operation, the AD7985 offers the option of It is also possible to corrupt the sample by having SCK near the forcing a start bit in front of the data bits. This start bit can be sampling instant. Therefore, it is recommended that the digital used as a busy signal indicator to interrupt the digital host and pins be kept quiet for approximately 20 ns before and 10 ns after trigger the data reading. Otherwise, without a busy indicator, the rising edge of CNV, using a discontinuous SCK whenever the user must time out the maximum conversion time prior to possible to avoid any potential performance degradation. readback. Rev. A | Page 17 of 28 AD7985 To determine how to split the read for a particular SCK frequency, DATA READING OPTIONS follow these examples to read data from conversion (n − 1). There are three different data reading options for the AD7985. For turbo mode (2.5 MSPS): There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 28 and Figure 29), fSCK = 70 MHz; tDATA = 190 ns and, in normal mode, to read during acquisition. The desired Number_SCK_Edges = 70 MHz × 190 ns = 13.3 SCK frequency largely determines which reading option to use. Thirteen bits are read during conversion (n), and three bits are Reading During Conversion, Fast Host (Turbo or read during acquisition (n). Normal Mode) For normal mode (2.0 MSPS): When reading during conversion (n), conversion results are for the previous (n − 1) conversion. Reading should occur only up f = 45 MHz; t = 290 ns SCK DATA to tDATA and, because this time is limited, the host must use a Number_SCK_Edges = 45 MHz × 290 ns = 13.05 fast SCK. Thirteen bits are read during conversion (n), and three bits are The required SCK frequency is calculated by read during acquisition (n). Number _ SCK _ Edges For slow throughputs, the time restriction is dictated by the f ≥ SCK t DATA throughput required by the user; the host is free to run at any speed. Similar to reading during acquisition, data access for To determine the minimum SCK frequency, follow these slow hosts must take place during the acquisition phase with examples to read data from conversion (n − 1). additional time into the conversion. For turbo mode (2.5 MSPS): Note that data access spanning conversion requires the CNV Number_SCK_Edges = 16; t = 190 ns DATA pin to be driven high to initiate a new conversion, and data f = 16/190 ns = 84.2 MHz SCK access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method. For normal mode (2.0 MSPS): Reading During Acquisition, Any Speed Host (Turbo or Number_SCK_Edges = 16; t = 290 ns DATA Normal Mode) fSCK = 16/290 ns = 55.2 MHz When reading during acquisition (n), conversion results are The time between tDATA and tCONV is an I/O quiet time during for the previous (n − 1) conversion. Maximum throughput is which digital activity should not occur, or sensitive bit decisions achievable in normal mode (2.0 MSPS); however, in turbo may be corrupted. mode, 2.5 MSPS throughput is not achievable. Split-Reading, Any Speed Host (Turbo or Normal Mode) For the maximum throughput, the only time restriction is that reading take place during the t (minimum) time. For slow To allow for a slower SCK, there is the option of a split read, ACQ where data access starts at the current acquisition (n) and spans throughputs, the time restriction is dictated by the throughput into the conversion (n). Conversion results are for the previous required by the user; the host is free to run at any speed. Thus, (n − 1) conversion. for slow hosts, data access must take place during the acquisi- tion phase. Similar to reading during conversion, split-reading should occur only up to t . For the maximum throughput, the DATA only time restriction is that split-reading take place during the t (minimum) + (t − t ) time. The time between the ACQ DATA QUIET falling edge of SCK and CNV rising is an acquisition quiet time, tQUIET. Rev. A | Page 18 of 28 AD7985 minimum conversion time elapses and then held high for the CS MODE, 3-WIRE WITHOUT BUSY INDICATOR maximum possible conversion time to avoid the generation of This mode is usually used when a single AD7985 is connected the busy signal indicator. to an SPI-compatible digital host. The connection diagram is When the conversion is complete, the AD7985 enters the shown in Figure 26, and the corresponding timing is given in acquisition phase and powers down. When CNV goes low, the Figure 27. MSB is output onto SDO. The remaining data bits are clocked With SDI tied to VIO, a rising edge on CNV initiates a con- by subsequent SCK falling edges. The data is valid on both SCK version, selects CS mode, and forces SDO to high impedance. edges. Although the rising edge can be used to capture the data, When a conversion is initiated, it continues until completion, a digital host using the SCK falling edge allows a faster reading irrespective of the state of CNV. This can be useful, for example, th rate, provided that it has an acceptable hold time. After the 16 to bring CNV low to select other SPI devices, such as analog SCK falling edge or when CNV goes high (whichever occurs multiplexers; however, CNV must be returned high before the first), SDO returns to high impedance. CONVERT DIGITAL HOST CNV VIO SDI AD7985 SDO DATA IN SCK CLK Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) t CYC >t CONV t t CONV CONV t t DATA DATA t SDI = 1 CNVH CNV t ACQ ACQUISITION (I/O QUIET (I/O QUIET (I/O QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n – 1) TIME) TIME) TIME) (n + 1) t QUIET SCK 1 14 15 16 2 14 15 16 t SCK t HSDO t EN t t DSDO EN SDO 2 1 0 15 14 13 2 1 0 t END DATA (n – 2) t t t BEGIN DATA (n – 1) END DATA (n – 1) DIS DIS DIS DIS Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 19 of 28 07947-009 07947-010 AD7985 When the conversion is complete, SDO goes from high imped- CS MODE, 3-WIRE WITH BUSY INDICATOR ance to low impedance. With a pull-up on the SDO line, this This mode is usually used when a single AD7985 is connected transition can be used as an interrupt signal to initiate the data to an SPI-compatible digital host that has an interrupt input. It readback controlled by the digital host. The AD7985 then enters is available only in normal conversion mode (TURBO is low). the acquisition phase and powers down. The data bits are then The connection diagram is shown in Figure 28, and the corre- clocked out, MSB first, by subsequent SCK falling edges. The sponding timing is given in Figure 29. data is valid on both SCK edges. Although the rising edge can With SDI tied to VIO, a rising edge on CNV initiates a con- be used to capture the data, a digital host using the SCK falling version, selects CS mode, and forces SDO to high impedance. edge allows a faster reading rate, provided that it has an acceptable th SDO is maintained in high impedance until the completion of hold time. After the optional 17 SCK falling edge, SDO returns the conversion, irrespective of the state of CNV. Prior to the to high impedance. minimum conversion time, CNV can be used to select other SPI If multiple AD7985 devices are selected at the same time, the devices, such as analog multiplexers, but CNV must be returned SDO output pin handles this contention without damage or low before the minimum conversion time elapses and then held induced latch-up. Meanwhile, it is recommended that this low for the maximum possible conversion time to guarantee the contention be kept as short as possible to limit extra power generation of the busy signal indicator. dissipation. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI AD7985 SDO DATA IN IRQ SCK TURBO CLK Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) TURBO = 0 SDI = 1 t CYC t CNVH CNV t t CONV ACQ (I/O QUIET ACQUISITION CONVERSION ACQUISITION TIME) t SCK t t QUIET SCKL SCK 1 2 3 15 16 17 t t HSDO SCKH t t DSDO DIS SDO D15 D14 D1 D0 Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 20 of 28 07947-011 07947-012 AD7985 conversion time elapses and then held high for the maximum CS MODE, 4-WIRE WITHOUT BUSY INDICATOR possible conversion time to avoid the generation of the busy This mode is usually used when multiple AD7985 devices are signal indicator. connected to an SPI-compatible digital host. A connection dia- When the conversion is complete, the AD7985 enters the gram example using two AD7985 devices is shown in Figure 30, acquisition phase and powers down. Each ADC result can be and the corresponding timing is given in Figure 31. read by bringing its SDI input low, which consequently outputs With SDI high, a rising edge on CNV initiates a conversion, the MSB onto SDO. The remaining data bits are then clocked by selects CS mode, and forces SDO to high impedance. In this subsequent SCK falling edges. The data is valid on both SCK mode, CNV must be held high during the conversion phase edges. Although the rising edge can be used to capture the data, and the subsequent data readback. (If SDI and CNV are low, a digital host using the SCK falling edge allows a faster reading SDO is driven low.) Prior to the minimum conversion time, th rate, provided that it has an acceptable hold time. After the 16 SDI can be used to select other SPI devices, such as analog multi- SCK falling edge, SDO returns to high impedance and another plexers, but SDI must be returned high before the minimum AD7985 can be read. CS2 CS1 CONVERT CNV CNV DIGITAL HOST SDI AD7985 SDO SDI SDO AD7985 SCK SCK DATA IN CLK Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram t CYC t t CONV CONV t t DATA DATA CNV t ACQ ACQUISITION (I/O QUIET ACQUISITION (I/O QUIET (I/O QUIET ACQUISITION (n) CONVERSION (n – 1) CONVERSION (n) (n – 1) TIME) (n + 1) TIME) TIME) t HSDICNV SDI t SSDICNV t QUIET SCK 1 14 15 16 2 14 15 16 t SCK t HSDO t EN t t DSDO EN SDO 2 1 0 15 14 13 2 1 0 t t t END DATA (n – 2) BEGIN DATA (n – 1) END DATA (n – 1) HSDO DIS DIS Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. A | Page 21 of 28 07947-013 07947-014 AD7985 used to select other SPI devices, such as analog multiplexers, but CS MODE, 4-WIRE WITH BUSY INDICATOR SDI must be returned low before the minimum conversion time This mode is usually used when a single AD7985 is connected elapses and then held low for the maximum possible conversion to an SPI-compatible digital host with an interrupt input and time to guarantee the generation of the busy signal indicator. when it is desired to keep CNV, which is used to sample the When the conversion is complete, SDO goes from high imped- analog input, independent of the signal used to select the data ance to low impedance. With a pull-up on the SDO line, this reading. This independence is particularly important in applica- transition can be used as an interrupt signal to initiate the data tions where low jitter on CNV is desired. This mode is available readback controlled by the digital host. The AD7985 then enters only in normal conversion mode (TURBO is low). The connection the acquisition phase and powers down. The data bits are then diagram is shown in Figure 32, and the corresponding timing is clocked out, MSB first, by subsequent SCK falling edges. The given in Figure 33. data is valid on both SCK edges. Although the rising edge can With SDI high, a rising edge on CNV initiates a conversion, be used to capture the data, a digital host using the SCK falling CS selects mode, and forces SDO to high impedance. In this edge allows a faster reading rate, provided that it has an accept- mode, CNV must be held high during the conversion phase and th able hold time. After the optional 17 SCK falling edge or when the subsequent data readback. (If SDI and CNV are low, SDO is SDI goes high (whichever occurs first), SDO returns to high driven low.) Prior to the minimum conversion time, SDI can be impedance. CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ SDI SDO DATA IN AD7985 IRQ TURBO SCK CLK CS Figure 32. Mode, 4-Wire with Busy Indicator Connection Diagram TURBO = 0 t CYC CNV t t CONV ACQ (I/O QUIET ACQUISITION CONVERSION ACQUISITION TIME) t SSDICNV SDI t SCK t HSDICNV t t SCKL QUIET SCK 1 2 3 15 16 17 t t HSDO SCKH t t DSDO DIS t EN SDO D15 D14 D1 D0 Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. A | Page 22 of 28 07947-015 07947-016 AD7985 When the conversion is complete, the MSB is output onto SDO, CHAIN MODE WITHOUT BUSY INDICATOR and the AD7985 enters the acquisition phase and powers down. This mode can be used to daisy-chain multiple AD7985 devices on The remaining data bits stored in the internal shift register are a 3-wire serial interface. It is available only in normal conversion clocked by subsequent SCK falling edges. For each ADC, SDI mode (TURBO is low). This feature is useful for reducing com- feeds the input of the internal shift register and is clocked by the ponent count and wiring connections, for example, in isolated SCK falling edge. Each ADC in the chain outputs its data MSB multiconverter applications or for systems with a limited inter- first, and 16 × N clocks are required to read back the N ADCs. facing capacity. Data readback is analogous to clocking a shift The data is valid on both SCK edges. Although the rising edge register. A connection diagram example using two AD7985 can be used to capture the data, a digital host using the SCK devices is shown in Figure 34, and the corresponding timing is falling edge allows a faster reading rate and consequently more given in Figure 35. AD7985 devices in the chain, provided that the digital host has When SDI and CNV are low, SDO is driven low. With SCK low, an acceptable hold time. The maximum conversion rate may be a rising edge on CNV initiates a conversion, selects chain mode, reduced due to the total readback time. and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. CONVERT CNV CNV DIGITAL HOST SDI AD7985 SDO SDI SDO DATA IN AD7985 A B TURBO TURBO SCK SCK CLK Figure 34. Chain Mode Without Busy Indicator Connection Diagram TURBO = 0 SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t QUIET SCK 1 2 3 14 15 16 17 18 30 31 32 t t t HSCKCNV SSDISCK SCKH t t EN HSDISCK D 15 D 14 D 13 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 15 D 14 D 13 D 1 D 0 D 15 D 14 D 1 D 0 SDO B B B B B A A A A B Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing Rev. A | Page 23 of 28 07947-017 07947-018 AD7985 When all ADCs in the chain have completed their conversions, the CHAIN MODE WITH BUSY INDICATOR SDO pin of the ADC closest to the digital host (see the AD7985 This mode can be used to daisy-chain multiple AD7985 devices ADC labeled C in Figure 36) is driven high. This transition on on a 3-wire serial interface while providing a busy indicator. It SDO can be used as a busy indicator to trigger the data read- is available only in normal conversion mode (TURBO is low). back controlled by the digital host. The AD7985 then enters the This feature is useful for reducing component count and wiring acquisition phase and powers down. The data bits stored in the connections, for example, in isolated multiconverter applications internal shift register are clocked out, MSB first, by subsequent SCK or for systems with a limited interfacing capacity. Data readback falling edges. For each ADC, SDI feeds the input of the internal is analogous to clocking a shift register. A connection diagram shift register and is clocked by the SCK falling edge. Each ADC example using three AD7985 devices is shown in Figure 36, and in the chain outputs its data MSB first, and 16 × N + 1 clocks the corresponding timing is given in Figure 37. are required to read back the N ADCs. Although the rising edge When SDI and CNV are low, SDO is driven low. With SCK high, can be used to capture the data, a digital host using the SCK a rising edge on CNV initiates a conversion, selects chain mode, falling edge allows a faster reading rate and consequently more and enables the busy indicator feature. In this mode, CNV is AD7985 devices in the chain, provided that the digital host has held high during the conversion phase and the subsequent data an acceptable hold time. readback. CONVERT CNV CNV CNV DIGITAL HOST SDI SDO SDI SDO AD7985 AD7985 SDI AD7985 SDO DATA IN A B C IRQ SCK TURBO SCK TURBO SCK TURBO CLK Figure 36. Chain Mode with Busy Indicator Connection Diagram TURBO = 0 t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 1 2 3 4 15 16 17 18 19 31 32 33 34 35 47 48 49 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t HSDISCK EN SDO = SDI A B D 15 D 14 D 13 D 1 D 0 A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI B C D 15 D 14 D 13 D 1 D 0 D 15 D 14 D 1 D 0 B B B B B A A A A t t DSDOSDI DSDOSDI SDO D 15 D 14 D 13 D 1 D 0 D 15 D 14 D 1 D 0 D 15 D 14 D 1 D 0 C C C C C C B B B B A A A A Figure 37. Chain Mode with Busy Indicator Serial Interface Timing Rev. A | Page 24 of 28 07947-019 07947-020 AD7985 APPLICATIONS INFORMATION Finally, the power supplies, VDD and VIO of the AD7985, LAYOUT should be decoupled with ceramic capacitors, typically 100 nF, The printed circuit board (PCB) that houses the AD7985 placed close to the AD7985 and connected using short, wide should be designed so that the analog and digital sections traces to provide low impedance paths and to reduce the effect are separated and confined to certain areas of the board. of glitches on the power supply lines. The pinout of the AD7985, with its analog signals on the left side and its digital signals on the right side, eases this task. EVALUATING AD7985 PERFORMANCE Avoid running digital lines under the device because they Other recommended layouts for the AD7985 are outlined couple noise onto the die, unless a ground plane under the in the documentation for the AD7985 evaluation board AD7985 is used as a shield. Fast switching signals, such as (EVAL-AD7985EBZ). The evaluation board package includes CNV or clocks, should not run near analog signal paths. a fully assembled and tested evaluation board, documentation, Crossover of digital and analog signals should be avoided. and software for controlling the board from a PC via the EVAL-CED1Z board. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7985 devices. The AD7985 voltage reference inputs (REF) have a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and REFGND pins and connecting them with wide, low impedance traces. Rev. A | Page 25 of 28 AD7985 BVDD AVDD REF REF REF PADDLE 1 2 GND GND 3 GND GND 4 5 DVDD 6 GND GND GND VIO Figure 38. Example Layout of the AD7985 (Top Layer) 5V EXTERNAL BVDD AVDD C C AVDD BVDD REFERENCE (ADR435 OR ADR445) REF REF REF GND C REF GND GND C DVDD GND GND DVDD GND GND GND VIO C VIO VIO Figure 39. Example Layout of the AD7985 (Bottom Layer) Rev. A | Page 26 of 28 07947-031 07947-030 AD7985 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 16 20 1 PIN 1 0.50 2.65 3.75 EXPOSED INDICATOR BSC BSC SQ PAD 2.50 SQ (BOTTOM VIEW) 2.35 5 10 6 11 0.50 0.25 MIN TOP VIEW 0.40 0.30 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Package Ordering 1, 2, 3 Model Temperature Range Package Description Option Quantity AD7985BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray CP-20-4 490 AD7985BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape CP-20-4 1,500 and Reel EVAL-AD7985EBZ Evaluation Board EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD7985EBZ can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. 3 The EVAL-CED1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the EB designator. Rev. A | Page 27 of 28 PIN 1 INDICATOR 090408-B AD7985 NOTES ©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07947-0-8/10(A) Rev. A | Page 28 of 28