ANALOG DEVICES AD7984

18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN AD7984 FEATURES APPLICATION DIAGRAM 2.9V TO 5V 2.5V 18-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW at 1.33 MSPS INL: ±2.25 LSB maximum VIO 1.8V TO 5V REF VDD IN+ SDI Dynamic range: 99.7 dB typical 3- OR 4-WIRE SCK AD7984 INTERFACE True differential analog input range: ±V REF ±10V, ±5V, .. SDO (SPI, CS IN– 0 V to V with V between 2.9 V to 5.0 V DAISY CHAIN) REF REF GND CNV ADA4941 Allows use of any input range Easy to drive with the ADA4941 Figure 1. No pipeline delay GENERAL DESCRIPTION Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface The AD7984 is an 18-bit, successive approximation, analog-to- Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible digital converter (ADC) that operates from a single power Ability to daisy-chain multiple ADCs and busy indicator supply, VDD. It contains a low power, high speed, 18-bit 10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN sampling ADC and a versatile serial interface port. On the CNV (LFCSP), SOT-23 size rising edge, the AD7984 samples the voltage difference between the IN+ and IN− pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, APPLICATIONS REF, is applied externally and can be set independent of the Battery-powered equipment supply voltage, VDD. Data acquisition systems Medical instruments The SPI-compatible serial interface also features the ability, Seismic data acquisition systems using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD7984 is available in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 1 1 14-Bit AD7940 AD7942 AD7946 1 1 1 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4941-x 1 1 1 AD7683 AD7687 AD7688 AD7983 ADA4841-x 1 AD7684 AD7694 AD7693 1 1 1 18-Bit AD7691 AD7690 AD7982 ADA4941-x 1 AD7984 ADA4841-x 1 Pin-for-pin compatible. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06973-001 AD7984 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications ....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram ........................................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply ............................................................................... 15 Revision History ............................................................................... 2 Digital Interface .......................................................................... 16 Specif ica t ions ..................................................................................... 3 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Timing Specifications .................................................................. 5 CS Mode, 3-Wire with Busy Indicator .................................... 18 Absolute Maximum Ratings ............................................................ 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 ESD Caution .................................................................................. 6 CS Mode, 4-Wire with Busy Indicator .................................... 20 Pin Configurations and Function Descriptions ........................... 7 Chain Mode Without Busy Indicator ...................................... 21 Typical Performance Characteristics ............................................. 8 Chain Mode with Busy Indicator ............................................. 22 Terminology .................................................................................... 11 Application Hints ........................................................................... 23 Theory of Operation ...................................................................... 12 Layout .......................................................................................... 23 Circuit Information .................................................................... 12 Evaluating the AD7984 Performance ...................................... 23 Converter Operation .................................................................. 12 Outline Dimensions ....................................................................... 24 Typical Connection Diagram ................................................... 13 Ordering Guide .......................................................................... 24 Analog Inputs .............................................................................. 14 REVISION HISTORY 8/10—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 11/07—Revision 0: Initial Version Rev. A | Page 2 of 24 AD7984 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range IN+ − IN− −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V × 0.475 V × 0.5 V × 0.525 V REF REF REF 1 Analog Input CMRR fIN = 450 kHz 67 dB Leakage Current at 25°C Acquisition phase 200 nA Input Impedance See the Analog Inputs section ACCURACY No Missing Codes 18 Bits 2 Differential Linearity Error −1 +1.5 LSB 2 Integral Linearity Error −2.25 +2.25 LSB 2 Transition Noise 0.95 LSB 3 Gain Error, TMIN to TMAX −0.075 ±0.022 +0.075 % of FS Gain Error Temperature Drift −0.6 ppm/°C 3 Zero Error, TMIN to TMAX −700 ±100 +700 μV Zero Temperature Drift 0.3 ppm/°C 1 Power Supply Sensitivity 90 dB VDD = 2.5 V ± 5% THROUGHPUT Conversion Rate 0 1.33 MSPS Transient Response Full-scale step 290 ns AC ACCURACY 1 Dynamic Range V = 5 V 99.7 dB REF 1 Signal-to-Noise, SNR f = 1 kHz, V = 5 V, T = 25°C 96.5 98.5 dB IN REF A 1 Spurious-Free Dynamic Range, SFDR fIN = 10 kHz 112.5 dB 4 1 Total Harmonic Distortion , THD fIN = 10 kHz −110.5 dB 1 Signal-to-(Noise + Distortion), SINAD fIN = 10 kHz, VREF = 5 V, TA = 25°C 98 dB 1 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2 LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 μV. 3 See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 Tested fully in production at f = 1 kHz. IN Rev. A | Page 3 of 24 AD7984 VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, T = −40°C to +85°C, unless otherwise noted. A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 2.9 5.1 V Load Current 1.33 MSPS 520 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 10 MHz Aperture Delay 2 ns DIGITAL INPUTS Logic Levels V VIO > 3 V –0.3 +0.3 × VIO V IL V VIO > 3 V 0.7 × VIO VIO + 0.3 V IH VIL VIO ≤ 3 V –0.3 +0.1 × VIO V VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V IIL −1 +1 μA I −1 +1 μA IH DIGITAL OUTPUTS Data Format Serial 18 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = +500 μA 0.4 V VOH ISOURCE = −500 μA VIO − 0.3 V POWER SUPPLIES VDD 2.375 2.5 2.625 V VIO Specified performance 2.3 5.5 V VIO Range 1.8 5.5 V 1, 2 Standby Current VDD and VIO = 2.5 V 1.1 mA Power Dissipation 1.33 MSPS throughput 10.5 14 mW Energy per Conversion 7.9 nJ/sample 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. A | Page 4 of 24 AD7984 TIMING SPECIFICATIONS 1 TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 300 500 ns CONV Acquisition Time tACQ 250 ns Time Between Conversions tCYC 750 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) t SCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) t SCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time t 4.5 ns SCKH SCK Falling Edge to Data Remains Valid t 3 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) t EN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge t 5 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) t 2 ns HSDICNV SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t 0 ns HSDICNV SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 3 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t 15 ns DSDOSDI 1 See Figure 2 and Figure 3 for load conditions. 1 Y% VIO 500µA I OL 1 X% VIO t t DELAY DELAY 2 2 V V IH TO SDO 1.4V IH 2 2 V V C IL IL L 20pF 1 FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2 MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS 500µA I IH IL OH SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. A | Page 5 of 24 06973-002 06973-003 AD7984 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs other conditions above those indicated in the operational 1 IN+, IN− to GND −0.3 V to V + 0.3 V REF section of this specification is not implied. Exposure to absolute or ±130 mA maximum rating conditions for extended periods may affect Supply Voltage device reliability. REF, VIO to GND −0.3 V to +6.0 V VDD to GND −0.3 V to +3.0 V VDD to VIO +3 V to −6 V Digital Inputs to GND −0.3 V to VIO + 0.3 V ESD CAUTION Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 10-Lead MSOP 200°C/W 10-Lead QFN (LFCSP) 48.7°C/W θJC Thermal Impedance 10-Lead MSOP 44°C/W 10-Lead QFN (LFCSP) 2.96°C/W Lead Temperatures Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section for an explanation of IN+ and IN−. Rev. A | Page 6 of 24 AD7984 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI AD7984 SCK IN+ 3 8 (EXPOSED REF 1 10 VIO PAD)* IN– 4 SDO 7 VDD 2 9 SDI AD7984 GND CNV IN+ 3 8 SCK 5 6 TOP VIEW (Not to Scale) IN– 4 7 SDO *EXPOSED PADDLE CAN BE CONNECTED GND 5 6 CNV TO GROUND. Figure 4. 10-Lead MSOP Pin Configuration Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is 2.9 V to 5.1 V. This pin is referred to the GND pin and should be decoupled closely to the GND pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 24 06973-004 06973-005 AD7984 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V. 2.0 2.0 POSITIVE INL: +1.07LSB POSITIVE DNL: +0.63LSB NEGATIVE INL: –0.73LSB NEGATIVE DNL: –0.34LSB 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 60k 60k 55354 48273 48266 50k 50k 40k 40k 32350 31003 30k 30k 20k 20k 16593 14653 10k 10k 5992 5708 1801 1378 00 7 326 326 60 0 00 2 69 37 00 0 0 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 CODE IN HEX CODE IN HEX Figure 7. Histogram of a DC Input at the Code Center Figure 10. Histogram of a DC Input at the Code Transition 0 100 f = 1.33MSPS S f = 10kHz 99 IN –20 SNR = 98.2dB THD = –110.6dB 98 –40 SFDR = 112.5dB SINAD = 98.0dB 97 –60 96 –80 95 –100 94 –120 93 –140 92 –160 91 –180 90 0 100 200 300 400 500 600 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 FREQUENCY (kHz) INPUT LEVEL (dB of Full Scale) Figure 8. FFT Plot Figure 11. SNR vs. Input Level Rev. A | Page 8 of 24 INL (LSB) AMPLITUDE (dB of Full Scale) COUNTS 06973-032 06973-033 06973-041 DNL (LSB) SNR (dB) COUNTS 06973-038 06973-039 06973-042 AD7984 100 18 –100 SNR 95 17 –105 SINAD 90 16 –110 ENOB 85 15 –115 80 14 –120 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD vs. Reference Voltage 100 –100 98 –105 96 –110 94 –115 92 90 –120 –55 –35 –15 5 25 45 65 85 105 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature 100 –80 –85 95 –90 –95 90 –100 –105 85 –110 80 –115 110 100 1000 110 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. SINAD vs. Frequency Figure 17. THD vs. Frequency Rev. A | Page 9 of 24 SNR, SINAD (dB) SINAD (dB) SNR (dB) 06973-034 06973-044 06973-043 ENOB (Bits) THD (dB) THD (dB) THD (dB) 06973-045 06973-040 06973-046 AD7984 2.5 2.5 I VDD I VDD 2.0 2.0 1.5 1.5 1.0 1.0 I REF I REF 0.5 0.5 I I VIO VIO 0 0 2.375 2.425 2.475 2.525 2.575 2.625 –55 –35 –15 5 25456585 105 125 V VOLTAGE (V) TEMPERATURE (°C) DD Figure 20. Operating Currents vs. Temperature Figure 18. Operating Currents vs. Supply 1.5 1.4 1.3 1.2 I + I VDD VIO 1.1 1.0 0.9 0.8 0.7 0.6 0.5 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) Figure 19. Standby Currents vs. Temperature Rev. A | Page 10 of 24 STANDBY CURRENTS (mA) OPERATING CURRENTS (mA) 06973-036 06973-035 OPERATING CURRENTS (mA) 06973-037 AD7984 TERMINOLOGY Integral Nonlinearity Error (INL) Noise-Free Code Resolution INL refers to the deviation of each individual code from a line Noise-free code resolution is the number of bits beyond which it is drawn from negative full scale through positive full scale. The impossible to distinctly resolve individual codes. It is calculated as point used as negative full scale occurs ½ LSB before the first N Noise-Free Code Resolution = log2(2 /Peak-to-Peak Noise) code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Effective Resolution Effective resolution is calculated as Differential Nonlinearity Error (DNL) N Effective Resolution = log (2 /RMS Input Noise) In an ideal ADC, code transitions are 1 LSB apart. DNL is the 2 maximum deviation from this ideal value. It is often specified in and is expressed in bits. terms of resolution for which no missing codes are guaranteed. Total Harmonic Distortion (THD) Zero Error THD is the ratio of the rms sum of the first five harmonic Zero error is the difference between the ideal midscale voltage, components to the rms value of a full-scale input signal and is that is, 0 V, from the actual voltage producing the midscale expressed in decibels. output code, that is, 0 LSB. Dynamic Range Gain Error Dynamic range is the ratio of the rms value of the full scale to The first transition (from 100 ... 00 to 100 ... 01) should occur at the total rms noise measured with the inputs shorted together. a level ½ LSB above nominal negative full scale (−4.999981 V The value for dynamic range is expressed in decibels. It is for the ±5 V range). The last transition (from 011 … 10 to measured with a signal at −60 dBF so that it includes all noise 011 … 11) should occur for an analog voltage 1½ LSB below sources and DNL artifacts. the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual Signal-to-Noise Ratio (SNR) level of the last transition and the actual level of the first SNR is the ratio of the rms value of the actual input signal to transition from the difference between the ideal levels. the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is Spurious-Free Dynamic Range (SFDR) expressed in decibels. SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to Effective Number of Bits (ENOB) the rms sum of all other spectral components that are less than ENOB is a measurement of the resolution with a sine wave the Nyquist frequency, including harmonics but excluding dc. input. It is related to SINAD as follows: The value of SINAD is expressed in decibels. ENOB = (SINAD − 1.76)/6.02 dB Aperture Delay and is expressed in bits. Aperture delay is the measurement of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. A | Page 11 of 24 AD7984 THEORY OF OPERATION IN+ SWITCHES CONTROL SW+ MSB LSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND 131,072C 65,536C 4C 2C C C OUTPUT CODE MSB LSB SW– CNV IN– Figure 21. ADC Simplified Schematic During the acquisition phase, terminals of the array tied to the CIRCUIT INFORMATION input of the comparator are connected to GND via SW+ and The AD7984 is a fast, low power, single-supply, precise, 18-bit SW−. All independent switches are connected to the analog ADC using a successive approximation architecture and is inputs. Therefore, the capacitor arrays are used as sampling capable of converting 1,330,000 samples per second (1.33 MSPS). capacitors and acquire the analog signal on the IN+ and IN− The AD7984 provides the user with an on-chip track-and-hold inputs. When the acquisition phase is complete and the CNV and does not exhibit any pipeline delay or latency, making it input goes high, a conversion phase is initiated. When the ideal for multiple multiplexed channel applications. conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and The AD7984 can be interfaced to any 1.8 V to 5 V digital logic connected to the GND input. Therefore, the differential voltage family. It is available in a 10-lead MSOP or a tiny 10-lead QFN between the inputs IN+ and IN− captured at the end of the (LFCSP) that allows space savings and flexible configurations. acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each It is pin-for-pin-compatible with the 18-bit AD7982. element of the capacitor array between GND and REF, the CONVERTER OPERATION comparator input varies by binary-weighted voltage steps (V /2, V /4 ... V /262,144). The control logic toggles these REF REF REF The AD7984 is a successive approximation ADC based on a switches, starting with the MSB, to bring the comparator back charge redistribution DAC. Figure 21 shows the simplified into a balanced condition. After the completion of this process, schematic of the ADC. The capacitive DAC consists of two the part returns to the acquisition phase, and the control logic identical arrays of 18 binary-weighted capacitors, which are generates the ADC output code and a busy signal indicator. connected to the two comparator inputs. Because the AD7984 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. A | Page 12 of 24 06973-011 AD7984 Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7984 is shown in Analog Input Digital Output Figure 22 and Table 7. Description V = 5 V Code (Hex) REF 1 FSR − 1 LSB +4.999962 V 0x1FFFF Midscale + 1 LSB +38.15 μV 0x00001 011 ... 111 Midscale 0 V 0x00000 011 ... 110 Midscale − 1 LSB −38.15 μV 0x3FFFF 011 ... 101 −FSR + 1 LSB −4.999962 V 0x20001 2 −FSR −5 V 0x20000 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND 100 ... 010 TYPICAL CONNECTION DIAGRAM 100 ... 001 100 ... 000 Figure 23 shows an example of the recommended connection –FSR –FSR + 1 LSB +FSR – 1 LSB diagram for the AD7984 when multiple supplies are available. –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function 1 REF 2.5V V+ 2 10µF 100nF V+ 1.8V TO 5V 15Ω 100nF 0 TO VREF REF VDD VIO 2.7nF SDI IN+ V– SCK 4 AD7984 V+ SDO 3-WIRE INTERFACE IN– CNV 15Ω GND VREF TO 0 2.7nF 2, 3 ADA4841 V– 4 NOTES 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF SEE RECOMMENDED LAYOUT IN FIGURE 40 AND FIGURE 41. 3 SEE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE ANALOG INPUTS SECTION. Figure 23. Typical Application Diagram with Multiple Supplies Rev. A | Page 13 of 24 ADC CODE (TWOS COMPLEMENT) 06973-012 06973-013 AD7984 When the source impedance of the driving circuit is low, the ANALOG INPUTS AD7984 can be driven directly. Large source impedances Figure 24 shows an equivalent circuit of the input structure of significantly affect the ac performance, especially THD. The the AD7984. dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD The two diodes, D1 and D2, provide ESD protection for the that can be tolerated. The THD degrades as a function of the analog inputs, IN+ and IN−. Care must be taken to ensure that source impedance and the maximum input frequency. the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal DRIVER AMPLIFIER CHOICE exceeds this level, the diodes become forward-biased and start Although the AD7984 is easy to drive, the driver amplifier must conducting current. These diodes can handle a forward-biased meet the following requirements: current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841 in • The noise generated by the driver amplifier must be kept as Figure 23) are different from those of REF, the analog input low as possible to preserve the SNR and transition noise signal may eventually exceed the supply rails by more than performance of the AD7984. The noise from the driver is 0.3 V. In such a case (for example, an input buffer with a short- filtered by the AD7984 analog input circuit’s 1-pole, low- circuit), the current limitation can be used to protect the part. pass filter made by R and C or by the external filter, if IN IN REF one is used. Because the typical noise of the AD7984 is 36.24 μV rms, the SNR degradation due to the amplifier is D1 C IN R IN IN+ OR IN– ⎛ ⎞ C D2 ⎜ ⎟ PIN 36.24 ⎜ ⎟ GND SNR = 20 log LOSS ⎜ ⎟ π 2 2 ⎜ 36.24 + f (Ne ) ⎟ −3dB N 2 Figure 24. Equivalent Analog Input Circuit ⎝ ⎠ where: The analog input structure allows the sampling of the true f is the input bandwidth, in megahertz, of the AD7984 differential signal between IN+ and IN−. By using these –3dB (10 MHz) or the cutoff frequency of the input filter, if differential inputs, signals common to both inputs are rejected. one is used. 90 N is the noise gain of the amplifier (for example, 1 in buffer configuration). 85 e is the equivalent input noise voltage of the op amp, in N nV/√Hz. 80 • For ac applications, the driver should have a THD perfor- 75 mance commensurate with the AD7984. • For multichannel multiplexed applications, the driver 70 amplifier and the AD7984 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level 65 (0.0004%, 4 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This 60 1 10 100 1000 10000 may differ significantly from the settling time at an 18-bit FREQUENCY (kHz) level and should be verified prior to driver selection. Figure 25. Analog Input CMRR vs. Frequency Table 8. Recommended Driver Amplifiers During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination Amplifier Typical Application of capacitor, C , and the network formed by the series connection PIN ADA4941-x Very low noise, low power single-to-differential of R and C . C is primarily the pin capacitance. R is typically IN IN PIN IN ADA4841-x Very low noise, small, and low power 400 Ω and is a lumped component composed of serial resistors AD8021 Very low noise and high frequency and the on resistance of the switches. CIN is typically 30 pF and AD8022 Low noise and high frequency is mainly the ADC sampling capacitor. OP184 Low power, low noise, and low frequency AD8655 5 V single supply, low noise During the sampling phase, where the switches are closed, the AD8605, AD8615 5 V single supply, low power input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. Rev. A | Page 14 of 24 CMRR (dB) 06973-014 06973-015 AD7984 SINGLE-TO-DIFFERENTIAL DRIVER If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, For applications using a single-ended analog signal, either 1206 size) ceramic chip capacitor is appropriate for optimum bipolar or unipolar, the ADA4941-x single-ended-to- performance using a low temperature drift ADR43x reference. differential driver allows for a differential input into the part. The schematic is shown in Figure 26. If desired, a reference-decoupling capacitor with values as small as 2.2 μF can be used with a minimal impact on performance, R1 and R2 set the attenuation ratio between the input range and especially DNL. the ADC range (V ). R1, R2, and C are chosen depending on REF F the desired input resistance, signal bandwidth, antialiasing, and Regardless, there is no need for an additional lower value noise contribution. For example, for the ±10 V range with a 4 kΩ ceramic decoupling capacitor (for example, 100 nF) between the impedance, R2 = 1 kΩ and R1 = 4 kΩ. REF and GND pins. R3 and R4 set the common mode on the IN− input, and R5 and R6 POWER SUPPLY set the common mode on the IN+ input of the ADC. The common The AD7984 uses two power supply pins: a core supply (VDD) and mode should be close to V /2. For example, for the ±10 V range REF a digital input/output interface supply (VIO). VIO allows direct with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, interface with any logic between 1.8 V and 5.5 V. To reduce the and R6 = 9.76 kΩ. number of supplies needed, VIO and VDD can be tied together. R5 R6 The AD7984 is independent of power supply sequencing between R3 R4 VIO and VDD. Additionally, it is very insensitive to power supply +5V REF 10µF +5.2V variations over a wide frequency range, as shown in Figure 27. +2.5V 100nF REF 95 15Ω OUTN REF VDD IN+ 2.7nF 90 AD7984 OUTP 2.7nF IN– 100nF 15Ω IN 85 GND FB 80 ADA4941 –0.2V R1 ±10V, 75 ±5V, .. R2 70 C F Figure 26. Single-Ended-to-Differential Driver Circuit 65 VOLTAGE REFERENCE INPUT 60 1 10 100 1000 The AD7984 voltage reference input, REF, has a dynamic input FREQUENCY (kHz) Figure 27. PSRR vs. Frequency impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND To ensure optimum performance, VDD should be roughly half pins, as explained in the Layout section. of REF, the voltage reference input. For example, if REF is 5.0 V, When REF is driven by a very low impedance source (for VDD should be set to 2.5 V (±5%). example, a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. Rev. A | Page 15 of 24 06973-016 PSRR (dB) 06973-017 AD7984 DIGITAL INTERFACE The mode in which the part operates depends on the SDI level CS when the CNV rising edge occurs. The mode is selected if Although the AD7984 has a reduced number of pins, it offers SDI is high, and the chain mode is selected if SDI is low. The flexibility in its serial interface modes. SDI hold time is such that when SDI and CNV are connected, CS When in mode, the AD7984 is compatible with SPI, QSPI, the chain mode is always selected. digital hosts, and DSPs. In this mode, the AD7984 can use In either mode, the AD7984 offers the option of forcing a start either a 3-wire or 4-wire interface. A 3-wire interface using the bit in front of the data bits. This start bit can be used as a busy CNV, SCK, and SDO signals minimizes wiring connections signal indicator to interrupt the digital host and trigger the data useful, for instance, in isolated applications. A 4-wire interface reading. Otherwise, without a busy indicator, the user must timeout using the SDI, CNV, SCK, and SDO signals allows CNV, which the maximum conversion time prior to readback. initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or The busy indicator feature is enabled simultaneous sampling applications. • In CS mode if CNV or SDI is low when the ADC When in chain mode, the AD7984 provides a daisy-chain feature conversion ends (see Figure 31 and Figure 35). using the SDI input for cascading multiple ADCs on a single • In chain mode if SCK is high during the CNV rising edge data line similar to a shift register. (see Figure 39). Rev. A | Page 16 of 24 AD7984 high for the maximum possible conversion time to avoid the CS MODE, 3-WIRE WITHOUT BUSY INDICATOR generation of the busy signal indicator. When the conversion is This mode is usually used when a single AD7984 is connected complete, the AD7984 enters the acquisition phase and goes to an SPI-compatible digital host. The connection diagram is into standby mode. When CNV goes low, the MSB is output shown in Figure 28, and the corresponding timing is given in onto SDO. The remaining data bits are clocked by subsequent Figure 29. SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host With SDI tied to VIO, a rising edge on CNV initiates a using the SCK falling edge allows a faster reading rate, provided CS conversion, selects the mode, and forces SDO to high th it has an acceptable hold time. After the 18 SCK falling edge or impedance. When a conversion is initiated, it continues until when CNV goes high (whichever occurs first), SDO returns to completion irrespective of the state of CNV. This can be useful, high impedance. for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held CONVERT DIGITAL HOST CNV VIO SDI AD7984 SDO DATA IN SCK CLK Figure 28. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 16 17 18 t t HSDO SCKH t t t DSDO EN DIS SDO D17 D16 D15 D1 D0 Figure 29. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 17 of 24 06973-018 06973-019 AD7984 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, This mode is usually used when a single AD7984 is connected this transition can be used as an interrupt signal to initiate the to an SPI-compatible digital host having an interrupt input. data reading controlled by the digital host. The AD7984 then The connection diagram is shown in Figure 30, and the enters the acquisition phase and goes into standby mode. The corresponding timing is given in Figure 31. data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the With SDI tied to VIO, a rising edge on CNV initiates a rising edge can be used to capture the data, a digital host using CS conversion, selects the mode, and forces SDO to high the SCK falling edge allows a faster reading rate, provided it has th impedance. SDO is maintained in high impedance until the an acceptable hold time. After the optional 19 SCK falling edge completion of the conversion irrespective of the state of CNV. or when CNV goes high (whichever occurs first), SDO returns Prior to the minimum conversion time, CNV can be used to to high impedance. select other SPI devices, such as analog multiplexers, but CNV If multiple AD7984s are selected at the same time, the SDO must be returned low before the minimum conversion time output pin handles this contention without damage or induced elapses and then held low for the maximum possible conversion latch-up. Meanwhile, it is recommended to keep this contention time to guarantee the generation of the busy signal indicator. as short as possible to limit extra power dissipation. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI AD7984 SDO DATA IN IRQ SCK CLK Figure 30. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 17 18 19 t t HSDO SCKH t t DSDO DIS SDO D17 D16 D1 D0 Figure 31. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 18 of 24 06973-020 06973-021 AD7984 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible This mode is usually used when multiple AD7984s are connected conversion time to avoid the generation of the busy signal to an SPI-compatible digital host. indicator. When the conversion is complete, the AD7984 A connection diagram example using two AD7984s is shown in enters the acquisition phase and goes into standby mode. Each Figure 32, and the corresponding timing is given in Figure 33. ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data With SDI high, a rising edge on CNV initiates a conversion, bits are then clocked by subsequent SCK falling edges. The data CS selects the mode, and forces SDO to high impedance. In this is valid on both SCK edges. Although the rising edge can be mode, CNV must be held high during the conversion phase and used to capture the data, a digital host using the SCK falling the subsequent data readback (if SDI and CNV are low, SDO is edge allows a faster reading rate, provided it has an acceptable th driven low). Prior to the minimum conversion time, SDI can be hold time. After the 18 SCK falling edge or when SDI goes used to select other SPI devices, such as analog multiplexers, high (whichever occurs first), SDO returns to high impedance and another AD7984 can be read. CS2 CS1 CONVERT CNV CNV DIGITAL HOST SDI SDO AD7984 SDI AD7984 SDO SCK SCK DATA IN CLK CS Figure 32. Mode, 4-Wire Without Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 16 17 18 19 20 34 35 36 t t HSDO SCKH t t t EN DSDO DIS SDO D17 D16 D15 D1 D0 D17 D16 D1 D0 Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. A | Page 19 of 24 06973-022 06973-023 AD7984 used to select other SPI devices, such as analog multiplexers, CS MODE, 4-WIRE WITH BUSY INDICATOR but SDI must be returned low before the minimum conversion This mode is usually used when a single AD7984 is connected time elapses and then held low for the maximum possible to an SPI-compatible digital host with an interrupt input and conversion time to guarantee the generation of the busy signal when it is desired to keep CNV, which is used to sample the indicator. When the conversion is complete, SDO goes from analog input, independent of the signal used to select the data high impedance to low impedance. With a pull-up on the SDO reading. This independence is particularly important in line, this transition can be used as an interrupt signal to initiate applications where low jitter on CNV is desired. the data readback controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The connection diagram is shown in Figure 34, and the The data bits are then clocked out, MSB first, by subsequent corresponding timing is given in Figure 35. SCK falling edges. The data is valid on both SCK edges. Although With SDI high, a rising edge on CNV initiates a conversion, the rising edge can be used to capture the data, a digital host selects the CS mode, and forces SDO to high impedance. In this using the SCK falling edge allows a faster reading rate, provided th it has an acceptable hold time. After the optional 19 SCK mode, CNV must be held high during the conversion phase and falling edge or SDI going high (whichever occurs first), SDO the subsequent data readback. (If SDI and CNV are low, SDO is returns to high impedance. driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ SDI SDO DATA IN AD7984 IRQ SCK CLK CS Figure 34. Mode, 4-Wire with Busy Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 171819 t t HSDO SCKH t t DSDO DIS t EN SDO D17 D16 D1 D0 CS Figure 35. Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. A | Page 20 of 24 06973-024 06973-025 AD7984 readback. When the conversion is complete, the MSB is output CHAIN MODE WITHOUT BUSY INDICATOR onto SDO and the AD7984 enters the acquisition phase and This mode can be used to daisy-chain multiple AD7984s on goes into standby mode. The remaining data bits stored in the a 3-wire serial interface. This feature is useful for reducing internal shift register are clocked by subsequent SCK falling component count and wiring connections, for example, in edges. For each ADC, SDI feeds the input of the internal shift isolated multiconverter applications or for systems with a register and is clocked by the SCK falling edge. Each ADC in limited interfacing capacity. Data readback is analogous to the chain outputs its data MSB first, and 18 × N clocks are clocking a shift register. required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the A connection diagram example using two AD7984s is shown in data, a digital host using the SCK falling edge will allow a faster Figure 36, and the corresponding timing is given in Figure 37. reading rate and consequently more AD7984s in the chain, When SDI and CNV are low, SDO is driven low. With SCK low, provided the digital host has an acceptable hold time. The a rising edge on CNV initiates a conversion, selects the chain maximum conversion rate may be reduced due to the total mode, and disables the busy indicator. In this mode, CNV is readback time. held high during the conversion phase and the subsequent data CONVERT CNV CNV DIGITAL HOST SDI AD7984 SDO SDI SDO DATA IN AD7984 A B SCK SCK CLK Figure 36. Chain Mode Without Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 12 3 16 17 18 19 20 34 35 36 t t t HSCKCNV SSDISCK SCKH t t EN HSDISCK D 17 D 16 D 15 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 SDO B B B B B A A A A B Figure 37. Chain Mode Without Busy Indicator Serial Interface Timing Rev. A | Page 21 of 24 06973-026 06973-027 AD7984 subsequent data readback. When all ADCs in the chain have CHAIN MODE WITH BUSY INDICATOR completed their conversions, the SDO pin of the ADC closest to This mode can also be used to daisy-chain multiple AD7984s the digital host (see the AD7984 ADC labeled C in Figure 38) is on a 3-wire serial interface while providing a busy indicator. driven high. This transition on SDO can be used as a busy indicator This feature is useful for reducing component count and wiring to trigger the data readback controlled by the digital host. The connections, for example, in isolated multiconverter applications or AD7984 then enters the acquisition phase and goes into standby for systems with a limited interfacing capacity. Data readback is mode. The data bits stored in the internal shift register are clocked analogous to clocking a shift register. out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked A connection diagram example using three AD7984s is shown by the SCK falling edge. Each ADC in the chain outputs its data in Figure 38, and the corresponding timing is given in Figure 39. MSB first, and 18 × N + 1 clocks are required to read back the N When SDI and CNV are low, SDO is driven low. With SCK ADCs. Although the rising edge can be used to capture the data, a high, a rising edge on CNV initiates a conversion, selects the digital host using the SCK falling edge allows a faster reading chain mode, and enables the busy indicator feature. In this rate and, consequently, more AD7984s in the chain, provided mode, CNV is held high during the conversion phase and the the digital host has an acceptable hold time. CONVERT CNV CNV CNV DIGITAL HOST SDI SDO AD7984 SDI AD7984 SDO SDI AD7984 SDO DATA IN A B C IRQ SCK SCK SCK CLK Figure 38. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 417 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t HSDISCK EN SDO = SDI D 17 D 16 D 15 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 17 D 16 D 15 D1D0D D 17 D 16 D1D0D 17 16 D1D 0 C C C C C B B B B A A A A Figure 39. Chain Mode with Busy Indicator Serial Interface Timing Rev. A | Page 22 of 24 06973-028 06973-029 AD7984 APPLICATION HINTS LAYOUT AD7984 The printed circuit board (PCB) that houses the AD7984 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7984, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7984 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, Figure 40. Example Layout of the AD7984 (Top Layer) the planes should be joined underneath the AD7984. The AD7984 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7984 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7984 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 40 and Figure 41. EVALUATING THE AD7984 PERFORMANCE Figure 41. Example Layout of the AD7984 (Bottom Layer) Other recommended layouts for the AD7984 are outlined in the documentation of the evaluation board for the AD7984 (EVAL-AD7984CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3Z. Rev. A | Page 23 of 24 06973-031 06973-030 AD7984 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 43. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE 1, 2, 3 Model Temperature Range Package Description Package Option Ordering Quantity Branding AD7984BRMZ −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C60 AD7984BRMZ-RL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C60 AD7984BCPZ-RL7 −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 1,500 C60 AD7984BCPZ-RL −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 5,000 C60 EVAL-AD7984CBZ Evaluation Board EVAL-CONTROL BRD3Z Evaluation Board 1 Z = RoHS compliant part. 2 The EVAL-AD7984CBZ board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3Z for evaluation/demonstration purposes. 3 The EVAL-CONTROL BRD3Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06973-0-8/10(A) Rev. A | Page 24 of 24 PIN 1 INDICATOR (R 0.15) 091709-A 121009-A