ANALOG DEVICES AD7982

18-Bit, 1 MSPS PulSAR 7.0 mW ADC in MSOP/QFN AD7982 FEATURES APPLICATION DIAGRAM EXAMPLE 2.5V TO 5V 2.5V 18-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 7.0 mW at 1 MSPS VIO 1.8V TO 5V REF VDD IN+ SDI 70 μW at 10 kSPS 3- OR 4-WIRE SCK AD7982 INTERFACE INL: ±1 LSB typical, ±2 LSB maximum ±10V, ±5V, .. (SPI, CS SDO IN– DAISY CHAIN) Dynamic range: 99 dB GND CNV ADA4941 True differential analog input range: ±V REF 0 V to V with V between 2.5 V to 5.0 V REF REF Figure 1. Allows use of any input range GENERAL DESCRIPTION Easy to drive with the ADA4941 No pipeline delay The AD7982 is an 18-bit, successive approximation, analog-to- Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic digital converter (ADC) that operates from a single power supply, interface VDD. It contains a low power, high speed, 18-bit sampling ADC Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible and a versatile serial interface port. On the CNV rising edge, Ability to daisy-chain multiple ADCs and busy indicator the AD7982 samples the voltage difference between the IN+ 10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN and IN− pins. The voltages on these pins usually swing in (LFCSP), SOT-23 size opposite phases between 0 V and V . The reference voltage, REF REF, is applied externally and can be set independent of the APPLICATIONS supply voltage, VDD. Its power scales linearly with throughput. Battery-powered equipment Data acquisition systems The SPI-compatible serial interface also features the ability, Medical instruments using the SDI input, to daisy-chain several ADCs on a single Seismic data acquisition systems 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD7982 is available in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADCs Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 18-Bit True Differential AD7691 AD7690 AD7982 ADA4941 AD7984 ADA4841 16-Bit True Differential AD7684 AD7687 AD7688 ADA4941 AD7693 ADA4841 16-Bit Pseudo Differential AD7680 AD7685 AD7686 AD7980 ADA4841 AD7683 AD7694 14-Bit Pseudo Differential AD7940 AD7942 AD7946 ADA4841 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06513-001 AD7982 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram Example........................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply............................................................................... 15 Revision History ............................................................................... 2 Digital Interface.......................................................................... 16 Specifications..................................................................................... 3 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Timing Specifications .................................................................. 5 CS Mode, 3-Wire with Busy Indicator .................................... 18 Absolute Maximum Ratings............................................................ 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 ESD Caution.................................................................................. 6 CS Mode, 4-Wire with Busy Indicator .................................... 20 Pin Configurations and Function Descriptions ........................... 7 Chain Mode Without Busy Indicator ...................................... 21 Terminology ...................................................................................... 8 Chain Mode with Busy Indicator............................................. 22 Typical Performance Characteristics ............................................. 9 Application Hints ........................................................................... 23 Theory of Operation ...................................................................... 12 Layout .......................................................................................... 23 Circuit Information.................................................................... 12 Evaluating AD7982 Performance............................................. 23 Converter Operation.................................................................. 12 Outline Dimensions ....................................................................... 24 Typical Connection Diagram ................................................... 13 Ordering Guide .......................................................................... 24 Analog Inputs.............................................................................. 14 REVISION HISTORY 10/07—Rev. 0 to Rev. A Changes to Table 1 and Layout ....................................................... 1 Changes to Table 2............................................................................ 3 Changes to Layout ............................................................................ 5 Changes to Layout ............................................................................ 6 Changes to Figure 5.......................................................................... 7 Changes to Figure 18 and Figure 20............................................. 11 Changes to Figure 23...................................................................... 13 Changers to Figure 26 .................................................................... 15 Changes to Digital Interface Section............................................ 16 Changes to Figure 38...................................................................... 21 Changes to Figure 40...................................................................... 22 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/07—Revision 0: Initial Version Rev. A | Page 2 of 24 AD7982 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range IN+ − IN− −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V × 0.475 V × 0.5 V × 0.525 V REF REF REF Analog Input CMRR fIN = 450 kHz 67 dB Leakage Current at 25°C Acquisition phase 200 nA Input Impedance See the Analog Inputs section ACCURACY No Missing Codes 18 Bits 1 Differential Linearity Error −0.85 ±0.5 +1.5 LSB 1 Integral Linearity Error −2 ±1 +2 LSB 1 Transition Noise REF = 5 V 1.05 LSB 2 Gain Error, TMIN to TMAX −0.023 +0.004 +0.023 % of FS Gain Error Temperature Drift ±1 ppm/°C 2 Zero Error, TMIN to TMAX ±100 +700 μV Zero Temperature Drift 0.5 ppm/°C Power Supply Rejection Ratio VDD = 2.5 V ± 5% 90 dB THROUGHPUT Conversion Rate 0 1 MSPS Transient Response Full-scale step 290 ns AC ACCURACY 3 Dynamic Range V = 5 V 97 99 dB REF 3 V = 2.5 V 93 dB REF 4 3 Oversampled Dynamic Range FO = 1 kSPS 129 dB 3 Signal-to-Noise fIN = 1 kHz, VREF = 5 V, TA = 25°C 95.5 98 dB 3 fIN = 1 kHz, VREF = 2.5 V, TA = 25°C 92.5 dB 3 Spurious-Free Dynamic Range f = 10 kHz −115 dB IN 5 3 Total Harmonic Distortion f = 10 kHz −120 dB IN 3 Signal-to-(Noise + Distortion) f = 1 kHz, V = 5 V, T = 25°C 97 dB IN REF A 1 LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 μV. 2 See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 3 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Dynamic range is obtained by oversampling the ADC running at a throughput Fs of 1 MSPS followed by postdigital filtering with an output word rate of FO. 5 Tested fully in production at f = 1 kHz. IN Rev. A | Page 3 of 24 AD7982 VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, T = −40°C to +85°C, unless otherwise noted. A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 2.4 5.1 V Load Current 1 MSPS, REF = 5 V 350 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 10 MHz Aperture Delay VDD = 2.5 V 2 ns DIGITAL INPUTS Logic Levels V VIO > 3 V –0.3 +0.3 × VIO V IL V VIO > 3 V 0.7 × VIO VIO + 0.3 V IH VIL VIO ≤ 3 V –0.3 +0.1 × VIO V VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V IIL −1 +1 μA I −1 +1 μA IH DIGITAL OUTPUTS Data Format Serial 18 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = +500 μA 0.4 V VOH ISOURCE = −500 μA VIO − 0.3 V POWER SUPPLIES VDD 2.375 2.5 2.625 V VIO Specified performance 2.3 5.5 V VIO Range 1.8 5.5 V 1, 2 Standby Current VDD and VIO = 2.5 V, 25°C 0.35 μA Power Dissipation 10 kSPS throughput 70 86 μW 1 MSPS throughput 7.0 8.6 mW Energy per Conversion 7.0 nJ/sample 3 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact an Analog Devices, Inc. sales representative for the extended temperature range. Rev. A | Page 4 of 24 AD7982 TIMING SPECIFICATIONS 1 TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 500 710 ns CONV Acquisition Time tACQ 290 ns Time Between Conversions tCYC 1000 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) t SCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) t SCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time t 4.5 ns SCKH SCK Falling Edge to Data Remains Valid t 3 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) t EN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge t 5 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) t 2 ns HSDICNV SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t 0 ns HSDICNV SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 3 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t 15 ns DSDOSDI 1 See Figure 2 and Figure 3 for load conditions. 1 Y% VIO 500µA I OL 1 X% VIO t t DELAY DELAY 2 2 V V IH IH 1.4V TO SDO 2 2 V V IL IL C L 20pF 1 FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2 MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS 500µA I IH IL OH SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. A | Page 5 of 24 06513-002 06513-003 AD7982 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs other conditions above those indicated in the operational 1 IN+, IN− to GND −0.3 V to V + 0.3 V REF section of this specification is not implied. Exposure to absolute or ±130 mA maximum rating conditions for extended periods may affect Supply Voltage device reliability. REF, VIO to GND −0.3 V to +6.0 V VDD to GND −0.3 V to +3.0 V VDD to VIO +3 V to −6 V Digital Inputs to GND −0.3 V to VIO + 0.3 V ESD CAUTION Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 10-Lead MSOP 200°C/W 10-Lead QFN (LFCSP_WD) 48.7°C/W θJC Thermal Impedance 10-Lead MSOP 44°C/W 10-Lead QFN (LFCSP_WD) 2.96°C/W Lead Temperatures Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section for an explanation of IN+ and IN−. Rev. A | Page 6 of 24 AD7982 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO REF 1 10 VIO VDD 2 9SDI VDD 2 9 SDI AD7982 AD7982 IN+ 3 8SCK IN+ 3 8 SCK TOP VIEW TOP VIEW IN– 4 7SDO (Not to Scale) IN– 4 7 SDO GND 5 6 CNV GND 5 6 CNV Figure 4. 10-Lead MSOP Pin Configuration Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions Pin 1 No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and should be decoupled closely to the GND pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 24 06513-004 06513-005 AD7982 TERMINOLOGY Integral Nonlinearity Error (INL) Effective Resolution INL refers to the deviation of each individual code from a line Effective resolution is calculated as drawn from negative full scale through positive full scale. The N Effective Resolution = log2(2 /RMS Input Noise) point used as negative full scale occurs ½ LSB before the first and is expressed in bits. code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from Total Harmonic Distortion (THD) the middle of each code to the true straight line (see Figure 22). THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is Differential Nonlinearity Error (DNL) expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in Dynamic Range terms of resolution for which no missing codes are guaranteed. Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. Zero Error The value for dynamic range is expressed in decibels. It is Zero error is the difference between the ideal midscale voltage, measured with a signal at −60 dBF so that it includes all noise that is, 0 V, from the actual voltage producing the midscale sources and DNL artifacts. output code, that is, 0 LSB. Signal-to-Noise Ratio (SNR) Gain Error SNR is the ratio of the rms value of the actual input signal to the The first transition (from 100 ... 00 to 100 ... 01) should occur at rms sum of all other spectral components below the Nyquist a level ½ LSB above nominal negative full scale (−4.999981 V frequency, excluding harmonics and dc. The value for SNR is for the ±5 V range). The last transition (from 011 … 10 to expressed in decibels. 011 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The Signal-to-(Noise + Distortion) Ratio (SINAD) gain error is the deviation of the difference between the actual SINAD is the ratio of the rms value of the actual input signal to level of the last transition and the actual level of the first transition the rms sum of all other spectral components that are less than from the difference between the ideal levels. the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms Aperture Delay amplitude of the input signal and the peak spurious signal. Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and Effective Number of Bits (ENOB) when the input signal is held for a conversion. ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows Transient Response ENOB = (SINAD − 1.76)/6.02 Transient response is the time required for the ADC to accurately dB acquire its input after a full-scale step function is applied. and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as N Noise-Free Code Resolution = log (2 /Peak-to-Peak Noise) 2 and is expressed in bits. Rev. A | Page 8 of 24 AD7982 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V. 2.0 2.0 POSITIVE INL: +0.79 LSB POSITIVE INL: +0.46 LSB NEGATIVE INL: –0.68 LSB NEGATIVE INL: –0.49 LSB 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 50000 60000 44806 45000 43239 50975 50000 40000 35000 40000 30000 32476 29064 30000 25000 20013 20000 16682 20000 15000 10000 9064 10000 7795 3158 5000 2793 745 881 145 222 43 00 29 0 0 00 7 70 0 0 0 0 1 2 3 4 5 6789A B C D 3FFF0 3FFF2 3FFF4 3FFF6 3FFF8 3FFFA 3FFFC CODE IN HEX CODE IN HEX Figure 7. Histogram of a DC Input at the Code Center Figure 10. Histogram of a DC Input at the Code Transition 0 100 f = 1MSPS S 99 –20 f = 2kHz IN SNR = 97.3dB 98 –40 THD = –121.8dB SFDR = 120.2dB 97 SINAD = 97.3dB –60 96 –80 95 –100 94 –120 93 –140 92 –160 91 –180 90 0 100 200 300 400 500 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 8. FFT Plot Figure 11. SNR vs. Input Level Rev. A | Page 9 of 24 INL (LSB) AMPLITUDE (dB OF FULL SCALE) COUNTS 06513-008 06513-007 06513-006 DNL (LSB) COUNTS SNR (dB REFERRED TO FULL SCALE) 06513-032 06513-010 06513-009 AD7982 100 18 –100 130 125 –105 SNR, SINAD 95 17 –110 120 SFDR 90 16 115 –115 ENOB –120 110 THD 85 15 –125 105 –130 100 80 14 2.25 2.75 3.25 3.75 4.25 4.75 5.25 2.25 2.75 3.25 3.75 4.25 4.75 5.25 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD, SFDR vs. Reference Voltage 100 –115 98 –117 96 –119 94 –121 92 –123 90 –125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature 100 –80 –85 –90 95 –95 –100 90 –105 –110 85 –115 –120 –125 80 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. SINAD vs. Frequency Figure 17. THD vs. Frequency Rev. A | Page 10 of 24 SNR, SINAD (dB) SINAD (dB) SNR (dB) 06513-042 06513-031 06513-034 ENOB (Bits) THD (dB) THD (dB) THD (dB) 06513-041 06513-030 SFDR (dB) 06513-033 AD7982 1.4 1.4 I I VDD VDD 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 I REF I REF 0.4 0.4 I I VIO VIO 0.2 0.2 0 0 2.375 2.425 2.475 2.525 2.575 2.625 –55 –35 –15 5 25 45 65 85 105 125 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 18. Operating Currents vs. Supply Voltage Figure 20. Operating Currents vs. Temperature 8 7 6 5 4 3 I + I VDD VIO 2 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 19. Power-Down Currents vs. Temperature Rev. A | Page 11 of 24 OPERATING CURRENTS (mA) POWER-DOWN CURRENTS (µA) 06513-038 06513-036 OPERATING CURRENTS (mA) 06513-035 AD7982 THEORY OF OPERATION IN+ SWITCHES CONTROL SW+ MSB LSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND 131,072C 65,536C 4C 2C C C OUTPUT CODE SW– MSB LSB CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and The AD7982 is a fast, low power, single-supply, precise, 18-bit SW−. All independent switches are connected to the analog ADC using a successive approximation architecture. inputs. Therefore, the capacitor arrays are used as sampling The AD7982 is capable of converting 1,000,000 samples per capacitors and acquire the analog signal on the IN+ and IN− second (1 MSPS) and powers down between conversions. When inputs. When the acquisition phase is complete and the CNV operating at 10 kSPS, for example, it typically consumes 70 μW, input goes high, a conversion phase is initiated. When the making it ideal for battery-powered applications. conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and The AD7982 provides the user with an on-chip track-and-hold connected to the GND input. Therefore, the differential voltage and does not exhibit any pipeline delay or latency, making it between the inputs IN+ and IN− captured at the end of the ideal for multiple multiplexed channel applications. acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each The AD7982 can be interfaced to any 1.8 V to 5 V digital logic element of the capacitor array between GND and REF, the family. It is available in a 10-lead MSOP or a tiny 10-lead QFN comparator input varies by binary-weighted voltage steps (LFCSP) that allows space savings and flexible configurations. (VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these It is pin-for-pin-compatible with the 16-bit AD7980. switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, CONVERTER OPERATION the part returns to the acquisition phase, and the control logic The AD7982 is a successive approximation ADC based on a generates the ADC output code and a busy signal indicator. charge redistribution DAC. Figure 21 shows the simplified Because the AD7982 has an on-board conversion clock, the schematic of the ADC. The capacitive DAC consists of two serial clock, SCK, is not required for the conversion process. identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs. Rev. A | Page 12 of 24 06513-011 AD7982 Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7982 is shown in Analog Input Digital Output Figure 22 and Table 7. Description V = 5 V Code (Hex) REF 1 FSR – 1 LSB +4.999962 V 0x1FFFF Midscale + 1 LSB +38.15 μV 0x00001 011...111 Midscale 0 V 0x00000 011...110 Midscale – 1 LSB −38.15 μV 0x3FFFF 011...101 –FSR + 1 LSB −4.999962 V 0x20001 2 –FSR −5 V 0x20000 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND 100...010 TYPICAL CONNECTION DIAGRAM 100...001 100...000 Figure 23 shows an example of the recommended connection –FSR –FSR + 1 LSB +FSR – 1 LSB diagram for the AD7982 when multiple supplies are available. –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function 1 REF 2.5V V+ 2 10µF 100nF V+ 1.8V TO 5V 20Ω 100nF 0 TO VREF REF VDD VIO 2.7nF SDI IN+ V– SCK 4 AD7982 V+ SDO 3-WIRE INTERFACE IN– CNV 20Ω GND VREF TO 0 2.7nF 2, 3 ADA4841 V– 4 NOTES 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF SEE RECOMMENDED LAYOUT FIGURE 41 AND FIGURE 42. 3 SEE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 23. Typical Application Diagram with Multiple Supplies Rev. A | Page 13 of 24 ADC CODE (TWOS COMPLEMENT) 06513-012 06513-013 AD7982 When the source impedance of the driving circuit is low, the ANALOG INPUTS AD7982 can be driven directly. Large source impedances Figure 24 shows an equivalent circuit of the input structure of significantly affect the ac performance, especially THD. The the AD7982. dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD The two diodes, D1 and D2, provide ESD protection for the that can be tolerated. The THD degrades as a function of the analog inputs, IN+ and IN−. Care must be taken to ensure that source impedance and the maximum input frequency. the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal DRIVER AMPLIFIER CHOICE exceeds this level, the diodes become forward biased and start Although the AD7982 is easy to drive, the driver amplifier must conducting current. These diodes can handle a forward-biased meet the following requirements: current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841 in • The noise generated by the driver amplifier must be kept Figure 23) are different from those of the REF, the analog input as low as possible to preserve the SNR and transition noise signal may eventually exceed the supply rails by more than performance of the AD7982. The noise from the driver is 0.3 V. In such a case (for example, an input buffer with a short- filtered by the AD7982 analog input circuit’s 1-pole, low- circuit), the current limitation can be used to protect the part. pass filter made by R and C or by the external filter, if IN IN REF one is used. Because the typical noise of the AD7982 is 40 μV rms, the SNR degradation due to the amplifier is D1 C IN R IN IN+ OR IN– ⎛ ⎞ ⎜ ⎟ C D2 PIN 40 ⎜ ⎟ GND SNR = 20 log LOSS ⎜ ⎟ π 2 2 40 + f (Ne ) ⎜ ⎟ N −3dB 2 ⎝ ⎠ Figure 24. Equivalent Analog Input Circuit where: The analog input structure allows the sampling of the true is the input bandwidth, in megahertz, of the AD7982 f–3dB differential signal between IN+ and IN−. By using these (10 MHz) or the cutoff frequency of the input filter, if differential inputs, signals common to both inputs are rejected. one is used. 90 N is the noise gain of the amplifier (for example, 1 in buffer configuration). 85 e is the equivalent input noise voltage of the op amp, in N nV/√Hz. 80 • For ac applications, the driver should have a THD perfor- 75 mance commensurate with the AD7982. • For multichannel multiplexed applications, the driver 70 amplifier and the AD7982 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level 65 (0.0004%, 4 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This 60 may differ significantly from the settling time at an 18-bit 1 10 100 1000 10000 FREQUENCY (kHz) level and should be verified prior to driver selection. Figure 25. Analog Input CMRR vs. Frequency Table 8. Recommended Driver Amplifiers During the acquisition phase, the impedance of the analog Amplifier Typical Application inputs (IN+ or IN−) can be modeled as a parallel combination ADA4941 Very low noise, low power, single to differential of Capacitor CPIN and the network formed by the series connection ADA4841 Very low noise, small, and low power of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically AD8021 Very low noise and high frequency 400 Ω and is a lumped component composed of serial resistors AD8022 Low noise and high frequency and the on resistance of the switches. C is typically 30 pF and IN OP184 Low power, low noise, and low frequency is mainly the ADC sampling capacitor. AD8655 5 V single supply, low noise During the sampling phase, where the switches are closed, the AD8605, AD8615 5 V single supply, low power input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. Rev. A | Page 14 of 24 CMRR (dB) 06513-014 06513-040 AD7982 POWER SUPPLY SINGLE-TO-DIFFERENTIAL DRIVER The AD7982 uses two power supply pins: a core supply (VDD) and For applications using a single-ended analog signal, either a digital input/output interface supply (VIO). VIO allows direct bipolar or unipolar, the ADA4941 single-ended-to-differential interface with any logic between 1.8 V and 5.5 V. To reduce the driver allows for a differential input to the part. The schematic number of supplies needed, VIO and VDD can be tied together. is shown in Figure 26. The AD7982 is independent of power supply sequencing between R1 and R2 set the attenuation ratio between the input range and VIO and VDD. Additionally, it is very insensitive to power supply the ADC range (V ). R1, R2, and C are chosen depending on REF F variations over a wide frequency range, as shown in Figure 27. the desired input resistance, signal bandwidth, antialiasing, and 95 noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. 90 R3 and R4 set the common mode on the IN− input, and R5 and R6 85 set the common mode on the IN+ input of the ADC. The common 80 mode should be close to V /2. For example, for the ±10 V range REF with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, 75 and R6 = 9.76 kΩ. 70 R5 R6 R3 R4 +5V REF 65 10µF +5.2V +2.5V 60 100nF REF 1 10 100 1000 OUTN 20Ω REF VDD FREQUENCY (kHz) IN+ 2.7nF Figure 27. PSRR vs. Frequency AD7982 OUTP 2.7nF IN– 100nF IN 20Ω To ensure optimum performance, VDD should be roughly half GND of REF, the voltage reference input. For example, if REF is 5.0 V, FB ADA4941 VDD should be set to 2.5 V (±5%). –0.2V R1 ±10V, The AD7982 powers down automatically at the end of each ±5V, .. R2 conversion phase; therefore, the power scales linearly with the C sampling rate. This makes the part ideal for low sampling rates F (even of a few hertz) and low battery-powered applications. Figure 26. Single-Ended-to-Differential Driver Circuit 10.000 VOLTAGE REFERENCE INPUT The AD7982 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance 1.000 source with efficient decoupling between the REF and GND I VDD pins, as explained in the Layout section. I 0.100 REF When REF is driven by a very low impedance source (for I VIO example, a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate 0.010 for optimum performance. If an unbuffered reference voltage is used, the decoupling value 0.001 depends on the reference used. For instance, a 22 μF (X5R, 10000 100000 1000000 SAMPLING RATE (SPS) 1206 size) ceramic chip capacitor is appropriate for optimum Figure 28. Operating Currents vs. Sampling Rate performance using a low temperature drift ADR43x reference. If desired, a reference decoupling capacitor with values as small as 2.2 μF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. Rev. A | Page 15 of 24 06513-015 OPERATING CURRENTS (mA) PSRR (dB) 06513-039 06513-037 AD7982 DIGITAL INTERFACE The mode in which the part operates depends on the SDI level CS when the CNV rising edge occurs. The mode is selected if Although the AD7982 has a reduced number of pins, it offers SDI is high, and the chain mode is selected if SDI is low. The flexibility in its serial interface modes. SDI hold time is such that when SDI and CNV are connected CS When in mode, the AD7982 is compatible with SPI, QSPI, together, the chain mode is always selected. digital hosts, and DSPs. In this mode, the AD7982 can use In either mode, the AD7982 offers the option of forcing a start either a 3-wire or 4-wire interface. A 3-wire interface using the bit in front of the data bits. This start bit can be used as a busy CNV, SCK, and SDO signals minimizes wiring connections signal indicator to interrupt the digital host and trigger the data useful, for instance, in isolated applications. A 4-wire interface reading. Otherwise, without a busy indicator, the user must timeout using the SDI, CNV, SCK, and SDO signals allows CNV, which the maximum conversion time prior to readback. initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or The busy indicator feature is enabled simultaneous sampling applications. • In the CS mode if CNV or SDI is low when the ADC When in chain mode, the AD7982 provides a daisy-chain feature conversion ends (see Figure 32 and Figure 36). using the SDI input for cascading multiple ADCs on a single • In the chain mode if SCK is high during the CNV rising data line similar to a shift register. edge (see Figure 40). Rev. A | Page 16 of 24 AD7982 high for the maximum possible conversion time to avoid the CS MODE, 3-WIRE WITHOUT BUSY INDICATOR generation of the busy signal indicator. When the conversion is This mode is usually used when a single AD7982 is connected complete, the AD7982 enters the acquisition phase and powers to an SPI-compatible digital host. The connection diagram is down. When CNV goes low, the MSB is output onto SDO. The shown in Figure 29, and the corresponding timing is given in remaining data bits are clocked by subsequent SCK falling edges. Figure 30. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK With SDI tied to VIO, a rising edge on CNV initiates a falling edge allows a faster reading rate, provided it has an CS conversion, selects the mode, and forces SDO to high th acceptable hold time. After the 18 SCK falling edge or when impedance. Once a conversion is initiated, it continues until CNV goes high (whichever occurs first), SDO returns to high completion irrespective of the state of CNV. This can be useful, impedance. for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held CONVERT DIGITAL HOST CNV VIO SDI AD7982 SDO DATA IN SCK CLK Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 16 17 18 t t HSDO SCKH t t t EN DSDO DIS SDO D17 D16 D15 D1 D0 CS Figure 30. Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 17 of 24 06513-016 06513-017 AD7982 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, This mode is usually used when a single AD7982 is connected this transition can be used as an interrupt signal to initiate the to an SPI-compatible digital host having an interrupt input. data reading controlled by the digital host. The AD7982 then The connection diagram is shown in Figure 31, and the enters the acquisition phase and powers down. The data bits are corresponding timing is given in Figure 32. then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge With SDI tied to VIO, a rising edge on CNV initiates a can be used to capture the data, a digital host using the SCK CS conversion, selects the mode, and forces SDO to high falling edge allows a faster reading rate, provided it has an th impedance. SDO is maintained in high impedance until the acceptable hold time. After the optional 19 SCK falling edge completion of the conversion irrespective of the state of CNV. or when CNV goes high (whichever occurs first), SDO returns Prior to the minimum conversion time, CNV can be used to to high impedance. select other SPI devices, such as analog multiplexers, but CNV If multiple AD7982s are selected at the same time, the SDO must be returned low before the minimum conversion time output pin handles this contention without damage or induced elapses and then held low for the maximum possible conversion latch-up. Meanwhile, it is recommended to keep this contention time to guarantee the generation of the busy signal indicator. as short as possible to limit extra power dissipation. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI AD7982 SDO DATA IN IRQ SCK CLK Figure 31. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 17 18 19 t t HSDO SCKH t t DSDO DIS SDO D17 D16 D1 D0 CS Figure 32. Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 18 of 24 06513-018 06513-019 AD7982 time elapses and then held high for the maximum possible CS MODE, 4-WIRE WITHOUT BUSY INDICATOR conversion time to avoid the generation of the busy signal This mode is usually used when multiple AD7982s are indicator. When the conversion is complete, the AD7982 enters connected to an SPI-compatible digital host. the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently A connection diagram example using two AD7982s is shown in outputs the MSB onto SDO. The remaining data bits are then Figure 33, and the corresponding timing is given in Figure 34. clocked by subsequent SCK falling edges. The data is valid on With SDI high, a rising edge on CNV initiates a conversion, both SCK edges. Although the rising edge can be used to CS capture the data, a digital host using the SCK falling edge allows selects the mode, and forces SDO to high impedance. In this a faster reading rate, provided it has an acceptable hold time. mode, CNV must be held high during the conversion phase and th After the 18 SCK falling edge or when SDI goes high (whichever the subsequent data readback. (If SDI and CNV are low, SDO is occurs first), SDO returns to high impedance and another driven low.) Prior to the minimum conversion time, SDI can be AD7982 can be read. used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV CNV DIGITAL HOST SDI AD7982 SDO SDI SDO AD7982 SCK SCK DATA IN CLK CS Figure 33. Mode, 4-Wire Without Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 16 17 18 19 20 34 35 36 t t HSDO SCKH t t t EN DSDO DIS D17 D16 D15 D1 D0 D17 D16 D1 D0 SDO CS Figure 34. Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. A | Page 19 of 24 06513-020 06513-021 AD7982 used to select other SPI devices, such as analog multiplexers, CS MODE, 4-WIRE WITH BUSY INDICATOR but SDI must be returned low before the minimum conversion This mode is usually used when a single AD7982 is connected time elapses and then held low for the maximum possible to an SPI-compatible digital host with an interrupt input and conversion time to guarantee the generation of the busy signal when it is desired to keep CNV, which is used to sample the indicator. When the conversion is complete, SDO goes from analog input, independent of the signal used to select the data high impedance to low impedance. With a pull-up on the SDO reading. This independence is particularly important in line, this transition can be used as an interrupt signal to initiate applications where low jitter on CNV is desired. the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data Figure 35, and the The connection diagram is shown in bits are then clocked out, MSB first, by subsequent SCK falling corresponding timing is given in Figure 36. edges. The data is valid on both SCK edges. Although the rising With SDI high, a rising edge on CNV initiates a conversion, edge can be used to capture the data, a digital host using the CS mode, and forces SDO to high impedance. In this SCK falling edge allows a faster reading rate, provided it has an selects the th acceptable hold time. After the optional 19 SCK falling edge or mode, CNV must be held high during the conversion phase and SDI going high (whichever occurs first), SDO returns to high the subsequent data readback. (If SDI and CNV are low, SDO is impedance. driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ SDI AD7982 SDO DATA IN IRQ SCK CLK CS Figure 35. Mode, 4-Wire with Busy Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 171819 t t HSDO SCKH t t DSDO DIS t EN SDO D17 D16 D1 D0 Figure 36. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. A | Page 20 of 24 06513-022 06513-023 AD7982 held high during the conversion phase and the subsequent data CHAIN MODE WITHOUT BUSY INDICATOR readback. When the conversion is complete, the MSB is output This mode can be used to daisy-chain multiple AD7982s on onto SDO and the AD7982 enters the acquisition phase and a 3-wire serial interface. This feature is useful for reducing powers down. The remaining data bits stored in the internal component count and wiring connections, for example, in shift register are clocked by subsequent SCK falling edges. For isolated multiconverter applications or for systems with a each ADC, SDI feeds the input of the internal shift register and limited interfacing capacity. Data readback is analogous to is clocked by the SCK falling edge. Each ADC in the chain clocking a shift register. outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. A connection diagram example using two AD7982s is shown in Although the rising edge can be used to capture the data, a Figure 37, and the corresponding timing is given in Figure 38. digital host using the SCK falling edge allows a faster reading When SDI and CNV are low, SDO is driven low. With SCK low, rate and consequently more AD7982s in the chain, provided the a rising edge on CNV initiates a conversion, selects the chain digital host has an acceptable hold time. The maximum conversion mode, and disables the busy indicator. In this mode, CNV is rate may be reduced due to the total readback time. CONVERT CNV CNV DIGITAL HOST SDI AD7982 SDO SDI SDO AD7982 DATA IN A B SCK SCK CLK Figure 37. Chain Mode Without Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 16 17 18 19 20 343536 t t t HSCKCNV SSDISCK SCKH t t EN HSDISCK D 17 D 16 D 15 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 SDO B B B B B A A A A B Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing Rev. A | Page 21 of 24 06513-024 06513-025 AD7982 subsequent data readback. When all ADCs in the chain have CHAIN MODE WITH BUSY INDICATOR completed their conversions, the SDO pin of the ADC closest to This mode can also be used to daisy-chain multiple AD7982s the digital host (see the AD7982 ADC labeled C in Figure 39) is on a 3-wire serial interface while providing a busy indicator. driven high. This transition on SDO can be used as a busy indicator This feature is useful for reducing component count and wiring to trigger the data readback controlled by the digital host. The connections, for example, in isolated multiconverter applications or AD7982 then enters the acquisition phase and powers down. for systems with a limited interfacing capacity. Data readback is The data bits stored in the internal shift register are clocked out, analogous to clocking a shift register. MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the A connection diagram example using three AD7982s is shown SCK falling edge. Each ADC in the chain outputs its data MSB in Figure 39, and the corresponding timing is given in Figure 40. first, and 18 × N + 1 clocks are required to read back the N ADCs. When SDI and CNV are low, SDO is driven low. With SCK Although the rising edge can be used to capture the data, a digital high, a rising edge on CNV initiates a conversion, selects the host using the SCK falling edge allows a faster reading rate and chain mode, and enables the busy indicator feature. In this consequently more AD7982s in the chain, provided the digital mode, CNV is held high during the conversion phase and the host has an acceptable hold time. CONVERT CNV CNV CNV DIGITAL HOST SDI AD7982 SDO SDI SDO SDI SDO AD7982 AD7982 DATA IN A B C IRQ SCK SCK SCK CLK Figure 39. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 123 417 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t SCKL t DSDOSDI t t HSDISCK EN SDO = SDI A B D 17 D 16 D 15 D 1 D 0 A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI B C D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 B B B B B A A A A t t DSDOSDI DSDOSDI SDO D 17 D 16 D 15 D1D0D D 17 D 16 D1D0D 17 16 D1D 0 C C C C C C B B B B A A A A Figure 40. Chain Mode with Busy Indicator Serial Interface Timing Rev. A | Page 22 of 24 06513-026 06513-027 AD7982 APPLICATION HINTS LAYOUT AD7982 The printed circuit board that houses the AD7982 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7982, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7982 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7982s. Figure 41. Example Layout of the AD7982 (Top Layer) The AD7982 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7982 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7982 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 41 and Figure 42. EVALUATING AD7982 PERFORMANCE Figure 42. Example Layout of the AD7982 (Bottom Layer) Other recommended layouts for the AD7982 are outlined in the documentation of the evaluation board for the AD7982 (EVAL-AD7982CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. A | Page 23 of 24 06513-029 06513-028 AD7982 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.40 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 43. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.30 3.00 0.23 0.50 BSC BSC SQ 0.18 5 8 PIN 1 INDEX 1.74 EXPOSED AREA PAD 1.64 (BOTTOM VIEW) 1.49 0.50 0.40 4 1 0.30 TOP VIEW 2.48 2.38 0.80 MAX 2.23 0.80 0.55 NOM 0.05 MAX 0.75 0.02 NOM 0.70 SEATING PLANE 0.20 REF Figure 44. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding 1 AD7982BRMZ −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C5F 1 AD7982BRMZRL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1000 C5F 1 AD7982BCPZ −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Tube, 75 C5F 1 AD7982BCPZ-RL7 −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 1000 C5F 1 AD7982BCPZ-RL −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 5000 C5F 1, 2 EVAL-AD7982CBZ Evaluation Board 3 EVAL-CONTROL BRD3Z Controller Board 1 Z = RoHS compliant part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06513–0–10/07(A) Rev. A | Page 24 of 24 PIN 1 INDICATOR (R 0.19) 062507-B