ANALOG DEVICES AD7952

14-Bit, 1 MSPS, Differential, ® Programmable Input PulSAR ADC AD7952 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND Multiple pins/software-programmable input ranges OVDD +5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), AGND AD7952 REF OGND ±10 V (40 V p-p) AVDD AMP SERIAL DATA REF Pins or serial SPI®-compatible input ranges/mode selection PDREF PORT SERIAL PDBUF Throughput CONFIGURATION 14 PORT IN+ 1 MSPS (warp mode) SWITCHED D[13:0] CAP DAC IN– 800 kSPS (normal mode) SER/PAR BYTESWAP 670 kSPS (impulse mode) PARALLEL OB/2C 14-bit resolution with no missing codes CLOCK INTERFACE CNVST BUSY INL: ±0.3 LSB typical, ±1 LSB maximum (±61 ppm of FSR) PD CONTROL LOGIC AND RD CALIBRATION CIRCUITRY SNR: 85 dB @ 2 kHz RESET CS iCMOS® process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output WARP IMPULSE BIPOLAR TEN No pipeline delay (SAR architecture) Figure 1. Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Table 1. 48-Lead PulSAR Selection Power dissipation 100 to 500 to 570 to Res 250 570 1000 >1000 235 mW @ 1 MSPS Input Type (Bits) (kSPS) (kSPS) (kSPS) kSPS 10 mW @ 1 kSPS Bipolar 14 AD7951 48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm) Differential 14 AD7952 Bipolar APPLICATIONS Process controls Unipolar 16 AD7651 AD7653 Medical instruments AD7660 AD7650 AD7667 High speed data acquisition AD7661 AD7652 Digital signal processing AD7664 Instrumentation AD7666 Spectrum analysis Bipolar 16 AD7610 AD7665 AD7612 ATE AD7663 AD7671 Differential 16 AD7675 AD7676 AD7677 AD7621 GENERAL DESCRIPTION Unipolar AD7622 The AD7952 is a 14-bit, charge redistribution, successive AD7623 approximation register (SAR) architecture analog-to-digital Simultaneous/ 16 AD7654 converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS Multichannel AD7655 high voltage process. The device is configured through hardware or Unipolar via a dedicated write-only serial configuration port for input Differential 18 AD7678 AD7679 AD7674 AD7641 range and operating mode. The AD7952 contains a high speed Unipolar AD7643 14-bit sampling ADC, an internal conversion clock, an internal 18 AD7631 AD7634 Differential reference (and buffer), error correction circuits, and both serial Bipolar and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN−. The AD7952 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. Operation is specified from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06589-001 AD7952 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 21 Applications....................................................................................... 1 Voltage Reference Input/Output .............................................. 22 General Description ......................................................................... 1 Power Supplies............................................................................ 22 Functional Block Diagram .............................................................. 1 Conversion Control ................................................................... 23 Revision History ............................................................................... 2 Interfaces.......................................................................................... 24 Specifications..................................................................................... 3 Digital Interface.......................................................................... 24 Timing Specifications .................................................................. 5 Parallel Interface......................................................................... 24 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 25 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 25 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 27 Typical Performance Characteristics ........................................... 12 Hardware Configuration ........................................................... 29 Terminology .................................................................................... 16 Software Configuration ............................................................. 29 Theory of Operation ...................................................................... 17 Microprocessor Interfacing....................................................... 30 Overview...................................................................................... 17 Application Information................................................................ 31 Converter Operation.................................................................. 17 Layout Guidelines....................................................................... 31 Modes of Operation ................................................................... 18 Evaluating Performance ............................................................ 31 Transfer Functions...................................................................... 18 Outline Dimensions ....................................................................... 32 Typical Connection Diagram ................................................... 18 Ordering Guide .......................................................................... 32 Analog Inputs.............................................................................. 20 REVISION HISTORY 2/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7952 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V = 5 V; all specifications T to T , unless otherwise noted. REF MIN MAX Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUTS Differential Voltage Range, VIN (VIN+) − (VIN−) 0 V to 5 V VIN = 10 V p-p −VREF +VREF V 0 V to 10 V VIN = 20 V p-p −2 VREF +2 VREF V ±5 V V = 20 V p-p −2 V +2 V V IN REF REF ±10 V V = 40 V p-p −4 V +4 V V IN REF REF Operating Voltage Range V , V to AGND IN+ IN− 0 V to 5 V −0.1 +5.1 V 0 V to 10 V −0.1 +10.1 V ±5 V −5.1 +5.1 V ±10 V −10.1 +10.1 V Common-Mode Voltage Range V , V IN+ IN− 5 V V /2 − 0.1 V/2 V /2 + 0.1 V REF REF REF 10 V VREF − 0.2 VREF VREF + 0.2 V Bipolar Ranges −0.1 0 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB 1 Input Current VIN = ±5 V, ±10 V @ 670 kSPS 220 μA Input Impedance See Analog Inputs section THROUGHPUT SPEED Complete Cycle In warp mode 1 μs Throughput Rate In warp mode 1 1 MSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.25 μs Throughput Rate In normal mode 0 800 kSPS Complete Cycle In impulse mode 1.49 μs Throughput Rate In impulse mode 0 670 kSPS DC ACCURACY 2 3 Integral Linearity Error −1 ±0.3 +1 LSB 2 No Missing Codes 14 Bits 2 Differential Linearity Error −1 +1 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −15 +15 LSB Zero-Error Temperature Drift ±1 ppm/°C Full-Scale Error (Unipolar or Bipolar) −20 +20 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB AC ACCURACY 4 Dynamic Range f = 2 kHz, −60 dB 84.5 85.5 dB IN Signal-to-Noise Ratio, SNR f = 2 kHz 84.5 85.5 dB IN f = 20 kHz 85.5 dB IN Signal-to-(Noise + Distortion), SINAD f = 2 kHz 83 85.4 dB IN Total Harmonic Distortion f = 2 kHz −105 dB IN Spurious-Free Dynamic Range f = 2 kHz 102 dB IN −3 dB Input Bandwidth V = 0 V to 5 V 45 MHz IN Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns Rev. 0 | Page 3 of 32 AD7952 Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 22 μF 10 ms REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 1 MSPS throughput 200 μA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL V 2.1 OVDD + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Parallel or serial 14-bit 5 Pipeline Delay V I = 500 μA 0.4 V OL SINK V I = −500 μA OVDD − 0.6 V OH SOURCE POWER SUPPLIES Specified Performance 6 AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V 7 , 8 Operating Current @ 1 MSPS throughput AVDD With Internal Reference 20 mA With Internal Reference Disabled 18.5 mA DVDD 7 mA OVDD 0.5 mA VCC VCC = 15 V, with internal reference buffer 4 mA VCC = 15 V 3 mA VEE VEE = −15 V 2 mA Power Dissipation @ 1 MSPS throughput With Internal Reference PDREF = PDBUF = low 235 260 mW With Internal Reference Disabled PDREF = PDBUF = high 215 240 mW 9 In Power-Down Mode PD = high 10 μW 10 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With VIN = unipolar 5 V or unipolar 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or V − 0.1 V, whichever is larger. REF 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. Rev. 0 | Page 4 of 32 AD7952 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 34 and Figure 35) Convert Pulse Width t1 10 ns Time Between Conversions t2 1 Warp Mode/Normal Mode/Impulse Mode 1/1.25/1.49 μs CNVST Low to BUSY High Delay t 35 ns 3 BUSY High All Modes (Except Master Serial Read After Convert) t 4 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t 7 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Acquisition Time t 8 Warp Mode/Normal Mode/Impulse Mode 200 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 36 and Figure 38) CNVST Low to DATA Valid Delay t10 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns DATA Valid to BUSY Low Delay t 20 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 2 15 ns 13 2 MASTER SERIAL INTERFACE MODES (See Figure 40 and Figure 41) CS Low to SYNC Valid Delay t 10 ns 14 2 t 10 ns CS Low to Internal SDCLK Valid Delay 15 CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns SYNC Asserted to SDCLK First Edge Delay t 3 ns 18 3 Internal SDCLK Period t 30 45 ns 19 3 Internal SDCLK High t20 15 ns 3 Internal SDCLK Low t21 10 ns 3 SDOUT Valid Setup Time t22 4 ns 3 SDOUT Valid Hold Time t 5 ns 23 3 SDCLK Last Edge to SYNC Delay t 5 ns 24 t 10 ns CS High to SYNC High-Z 25 CS High to Internal SDCLK High-Z t26 10 ns CS High to SDOUT High-Z t27 10 ns 3 BUSY High in Master Serial Read After Convert t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert t 29 Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns SYNC Deasserted to BUSY Low Delay t 25 ns 30 Rev. 0 | Page 5 of 32 AD7952 Parameter Symbol Min Typ Max Unit 2 SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES (See Figure 43, Figure 44, and Figure 46) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t 2 18 ns 32 SDIN/SCIN Setup Time t 5 ns 33 SDIN/SCIN Hold Time t 5 ns 34 External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t 12 30 60 120 ns 20 Internal SDCLK Low Minimum t 10 25 55 115 ns 21 SDOUT Valid Setup Time Minimum t 4 20 20 20 ns 22 SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 Warp Mode 1.60 2.35 3.75 6.75 μs Normal Mode 1.85 2.60 4.00 7.00 μs Impulse Mode 2.10 2.85 4.25 7.25 μs 1.6mA I OL TO OUTPUT 1.4V PIN 2V C L 60pF 0.8V t t DELAY DELAY 500µA I OH 2V 2V NOTES 0.8V 0.8V 1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SDCLK Outputs, C = 10 pF L Rev. 0 | Page 6 of 32 06589-002 06589-003 AD7952 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 1 IN+ , IN− to AGND VEE − 0.3 V to VCC + 0.3 V other conditions above those indicated in the operational REF, REFBUFIN, TEMP, AVDD + 0.3 V to section of this specification is not implied. Exposure to absolute REFGND to AGND AGND − 0.3 V maximum rating conditions for extended periods may affect Ground Voltage Differences device reliability. AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V ESD CAUTION DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD + 0.3 V PDREF, PDBUF ±20 mA 2 Internal Power Dissipation 700 mW 3 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, JA θJC = 30°C/W. 3 Specification is for the device in free air: 48-Lead LFCSP; θ = 26°C/W. JA Rev. 0 | Page 7 of 32 AD7952 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 36 AGND BIPOLAR PIN 1 2 AVDD 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7952 6 31 WARP RD TOP VIEW 7 30 IMPULSE TEN (Not to Scale) 8 29 SER/PAR BUSY 9 28 NC D13/SCCS 10 27 D12/SCCLK NC 11 26 D11/SCIN D0/DIVSCLK[0] 12 25 D1/DIVSCLK[1] D10/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8 Bit/14 Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 2 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 2 6 WARP DI Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following. Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 2 7 IMPULSE DI Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port, and the remaining data bits are high impedance outputs. 9, 10 NC DO No Connect. Do not connect. 11, 12 D[0:1] or DI/O In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus. DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 32 D2/EXT/INT PDBUF D3/INVSYNC PDREF D4/INVSCLK REFBUFIN TEMP D5/RDC/SDIN AVDD OGND OVDD IN+ AGND DVDD VEE DGND VCC D6/SDOUT D7/SDCLK IN– D8/SYNC REFGND D9/RDERROR REF 06589-004 AD7952 1 Pin No. Mnemonic Type Description 13 D2 or DI/O In parallel mode, this output is used as Bit 2 of the parallel port data output bus. EXT/INT Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7952 output data. When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output. When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. 14 D3 or DI/O In parallel mode, this output is used as Bit 3 of the parallel port data output bus. INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low), RDC is used to select the read mode. Refer to the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN Serial Data In. In serial slave mode (SER/PAR = high, EXT/INT = high), SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D6 or DO In parallel mode, this output is used as Bit 6 of the parallel port data output bus. SDOUT Serial Data Output. In all serial modes, this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7952 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode): When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. 22 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. Rev. 0 | Page 9 of 32 AD7952 1 Pin No. Mnemonic Type Description 24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is completed, the current data is lost and RDERROR is pulsed high. 25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7952 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7952 is configured through software using the serial configuration register. When HW/SW = high, the AD7952 is configured through dedicated hardware input pins. 26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus. SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. 27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started and remains high until the conversion is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low), the busy time changes according to Table 4. 2 30 TEN DI Input Range Select. Used in conjunction with BIPOLAR per the following. Input Range (V) BIPOLAR TEN 0 to 5 Low Low 0 to 10 Low High ±5 High Low ±10 High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 DI CS Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial configurable port). 33 RESET DI Reset Input. When high, reset the AD7952. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 2 34 PD DI Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power-down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 2 36 BIPOLAR DI Input Range Select. See description for Pin 30. 37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF capacitor is required with or without the internal reference and buffer. See the Reference Decoupling section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. Rev. 0 | Page 10 of 32 AD7952 1 Pin No. Mnemonic Type Description 39 IN− AI Analog Input. Referenced to IN+. In the 0 V to 5 V input range, IN− is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V range, IN− is between 0 V and 2 VREF V centered about VREF. In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 V V (±5 V range) or ±4 V V (±10 V range) REF REF and centered about 0 V. In all ranges, IN− must be driven 180° out of phase with IN+. 40 VCC P High Voltage Positive Supply. Normally 7 V to 15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI Analog Input. Referenced to IN−. In the 0 V to 5 V input range, IN+ is between 0 V and V V centered about V /2. In the 0 V to REF REF 10 V range, IN+ is between 0 V and 2 V V centered about V . REF REF In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range) and centered about 0 V. In all ranges, IN+ must be driven 180° out of phase with IN−. 45 TEMP AO Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low), this pin outputs a voltage proportional to the temperature of the AD7952. See the Temperature Sensor section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Single-to-Differential Driver section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 PAR SW In serial configuration mode (SER/ = high, HW/ = low), this input is programmed with the serial configuration register, and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. Rev. 0 | Page 11 of 32 AD7952 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 1.0 1.0 POSITIVE INL = +0.15 POSITIVE DNL = +0.27 NEGATIVE INL = –0.15 NEGATIVE DNL = –0.27 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 250 200 NEGATIVE INL NEGATIVE DNL POSITIVE INL POSITIVE DNL 180 200 160 140 150 120 100 100 80 60 50 40 20 0 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INL DISTRIBUTION (LSB) DNL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution (239 Devices) Figure 9. Differential Nonlinearity Distribution (239 Devices) 300000 140000 132052 129068 261120 120000 250000 100000 200000 80000 150000 60000 100000 40000 50000 20000 00 00 00 0 0 0 0 1FFF 2000 2001 2002 2003 8192 8193 8194 8195 8196 8197 CODE IN HEX CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center at the Code Transition Rev. 0 | Page 12 of 32 COUNTS INL (LSB) NUMBER OF UNITS 06589-006 06589-005 06589-007 COUNTS DNL (LSB) NUMBER OF UNITS 06589-009 06589-010 06589-008 AD7952 0 86.5 f = 1000kSPS S f = 19.94kHz IN –20 SNR = 85.4dB THD = –107dB SFDR = 116dB –40 SINAD = 85.4dB 86.0 SNR –60 –80 SINAD –100 85.5 –120 –140 –160 85.0 0 100 200 300 400 500 –60 –50 –40 –30 –20 –10 0 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 11. FFT 20 kHz Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) 88 14.5 –70 120 –80 110 86 14.3 SFDR SNR –90 100 SINAD 84 14.1 –100 90 THD ENOB 13.9 82 THIRD HARMONIC –110 80 SECOND HARMONIC 13.7 80 –120 70 78 13.5 –130 60 1 10 100 110 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. SNR, SINAD, and ENOB vs. Frequency Figure 15. THD, Harmonics, and SFDR vs. Frequency 86.0 86.0 0V TO 5V 0V TO 5V 0V TO 10V 0V TO 10V ±5V ±5V ±10V ±10V 85.5 85.5 85.0 85.0 84.5 84.5 84.0 84.0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. SINAD vs. Temperature Rev. 0 | Page 13 of 32 SNR, SINAD (dB) SNR (dB) AMPLITUDE (dB OF FULL SCALE) ENOB (Bits) 06589-013 06589-011 06589-012 THD, HARMONICS (dB) SINAD (dB) SNR, SINAD REFERRED TO FULL SCALE (dB) 06589-014 06589-016 SFDR (dB) 06589-015 AD7952 –96 124 0V TO 5V 0V TO 5V 0V TO 10V 0V TO 10V 122 ±5V ±5V ±10V ±10V –100 120 –104 118 116 –108 114 –112 112 110 –116 108 –120 106 –55 –35 –15 5 25456585 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. THD vs. Temperature Figure 20. SFDR vs. Temperature (Excludes Harmonics) 1.5 5.008 NEGATIVE FULL-SCALE ERROR 1.0 5.006 0.5 5.004 POSITIVE FULL-SCALE ERROR 0 5.002 –0.5 5.000 ZERO ERROR –1.0 4.998 –1.5 4.996 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Zero Error, Positive and Negative Full-Scale Error vs. Temperature Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 60 100000 AVDD, WARP/NORMAL 10000 50 DVDD, ALL MODES 1000 40 100 AVDD, IMPULSE 30 10 VCC +15V 1 VEE –15V 20 ALL MODES 0.1 OVDD, ALL MODES 10 0.01 PDREF = PDBUF = HIGH 0 0.001 08 1234567 10 100 1000 10000 100000 1000000 SAMPLING RATE (SPS) REFERENCE DRIFT (ppm/°C) Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. 0 | Page 14 of 32 ZERO ERROR, FULL-SCALE ERROR (LSB) THD (dB) NUMBER OF UNITS 06589-019 06589-018 06589-017 OPERATING CURRENTS (µA) VREF (V) SFDR (dB) 06589-021 06589-020 06589-022 AD7952 50 700 PD = PDBUF = PDREF = HIGH OVDD = 2.7V @ 85°C 45 VEE = –15V 600 VCC = +15V OVDD = 2.7V @ 25°C DVDD 40 OVDD AVDD 500 35 30 400 25 OVDD = 5V @ 85°C 300 20 OVDD = 5V @ 25°C 15 200 10 100 5 0 0 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) C (pF) L Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance C L Rev. 0 | Page 15 of 32 POWER–DOWN OPERATING CURRENTS (nA) 06589-023 t DELAY (ns) 12 06589-024 AD7952 TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that THD is the ratio of the rms sum of the first five harmonic can be represented by a converter. For a fully differential input components to the rms value of a full-scale input signal and is ADC with N bits of resolution, the LSB expressed in volts is expressed in decibels. V Signal-to-(Noise + Distortion) Ratio (SINAD) INp-p LSB (V) = N 2 SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist Integral Nonlinearity Error (INL) frequency, including harmonics but excluding dc. The value for Linearity error refers to the deviation of each individual code SINAD is expressed in decibels. from a line drawn from negative full scale through positive full Spurious-Free Dynamic Range (SFDR) scale. The point used as negative full scale occurs a ½ LSB before the first code transition. Positive full scale is defined as a The difference, in decibels (dB), between the rms amplitude of level 1½ LSBs beyond the last code transition. The deviation is the input signal and the peak spurious signal. measured from the middle of each code to the true straight line. Effective Number of Bits (ENOB) Differential Nonlinearity Error (DNL) ENOB is a measurement of the resolution with a sine wave In an ideal ADC, code transitions are 1 LSB apart. Differential input. It is related to SINAD and is expressed in bits by nonlinearity is the maximum deviation from this ideal value. It ENOB = [(SINADdB − 1.76)/6.02] is often specified in terms of resolution for which no missing Aperture Delay codes are guaranteed. Aperture delay is a measure of the acquisition performance Bipolar Zero Error measured from the falling edge of the CNVST input to when The difference between the ideal midscale input voltage (0 V) the input signal is held for a conversion. and the actual voltage producing the midscale output code. Transient Response Unipolar Offset Error The time required for the AD7952 to achieve its rated accuracy The first transition should occur at a level ½ LSB above analog after a full-scale step function is applied to its input. ground. The unipolar offset error is the deviation of the actual transition from that point. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the Full-Scale Error typical shift of the output voltage at 25°C on a sample of parts at The last transition (from 111…10 to 111…11) should occur for the maximum and minimum reference output voltage (VREF) an analog voltage 1½ LSB below the nominal full scale. The full- measured at T , T (25°C), and T . It is expressed in ppm/°C as MIN MAX scale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and V (Max) –V (Min) REF REF 6 TCV (ppm/°C) = × 10 REF includes the effect of the offset error. Closely related is the gain V (25°C) × (T –T ) REF MIN MAX error (also in LSB or % of full-scale range), which does not where: include the effects of the offset error. V (Max) = maximum V at T , T (25°C), or T . REF REF MIN MAX Dynamic Range VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX. Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The VREF (25°C) = VREF at 25°C. value for dynamic range is expressed in decibels. TMAX = +85°C. Signal-to-Noise Ratio (SNR) TMIN = –40°C. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. 0 | Page 16 of 32 AD7952 THEORY OF OPERATION IN+ AGND SWITCHES CONTROL LSB SW+ MSB 8192C 4096C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 8192C 4C 2C C C 4096C SW– MSB LSB CNVST AGND IN– Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7952 is a very fast, low power, precise, 14-bit ADC using The AD7952 is a successive approximation ADC based on a successive approximation, capacitive digital-to-analog (CDAC) charge redistribution DAC. Figure 25 shows the simplified converter architecture. schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected The AD7952 can be configured at any time for one of four input to the two comparator inputs. ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write-only, SPI-compatible During the acquisition phase, terminals of the array tied to the interface via a configuration register in serial software mode. comparator’s input are connected to AGND via SW+ and SW−. The AD7952 uses Analog Devices’ patented iCMOS high All independent switches are connected to the analog inputs. voltage process to accommodate 0 V to +5 V, 0 V to +10 V, Therefore, the capacitor arrays are used as sampling capacitors ±5 V, and ±10 V input ranges without the use of conventional and acquire the analog signal on IN+ and IN− inputs. A thin films. Only one acquisition cycle, t , is required for the inputs conversion phase is initiated once the acquisition phase is 8 to latch to the correct configuration. Resetting or power cycling CNVST completed and the input goes low. When the is not required for reconfiguring the ADC. conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and The AD7952 features different modes to optimize performance connected to the REFGND input. Therefore, the differential according to the applications. It is capable of converting voltage between the inputs (IN+ and IN−) captured at the end 1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS of the acquisition phase is applied to the comparator inputs, in normal mode, and 670 kSPS in impulse mode. causing the comparator to become unbalanced. By switching The AD7952 provides the user with an on-chip, track-and-hold, each element of the capacitor array between REFGND and REF, successive approximation ADC that does not exhibit any the comparator input varies by binary weighted voltage steps pipeline or latency, making it ideal for multiple, multiplexed (V /2, V /4 through V /16,384). The control logic toggles REF REF REF channel applications. these switches, starting with the MSB first, to bring the For unipolar input ranges, the AD7952 typically requires three comparator back into a balanced condition. supplies: VCC, AVDD (which can supply DVDD), and OVDD After the completion of this process, the control logic generates (which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital the ADC output code and brings the BUSY output low. logic). For bipolar input ranges, the AD7952 requires the use of the additional VEE supply. The device is housed in Pb-free, 48-lead LQFP or tiny, 48-lead LFCSP (7 mm × 7 mm) that combines space savings with flexibility. In addition, the AD7952 can be configured as either a parallel or a serial SPI-compatible interface. Rev. 0 | Page 17 of 32 06589-025 AD7952 MODES OF OPERATION TRANSFER FUNCTIONS The AD7952 features three modes of operation: warp, normal, Using the OB/2C digital input or via the configuration register, and impulse. Each of these modes is more suitable to specific the AD7952 offers two output codings: straight binary and twos applications. The mode is configured with the input pins, WARP complement. See Figure 26 and Table 7 for the ideal transfer and IMPULSE, or via the configuration register. See Table 6 for characteristic and digital output codes for the different analog the pin details and the Hardware Configuration section and input ranges, V . Note that when using the configuration IN Software Configuration section for programming the mode 2C register, the OB/ input is a don’t care and should be tied to selection with either pins or configuration register. Note that either high or low. when using the configuration register, the WARP and IMPULSE inputs are don’t cares and should be tied to either high or low. 111...111 111...110 Warp Mode 111...101 Setting WARP = high and IMPULSE = low allows the fastest conversion rate up to 1 MSPS. However, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power-up), the first conversion result should be ignored because in warp mode, 000...010 the ADC performs a background calibration during the SAR 000...001 000...000 conversion process. This calibration can drift if the time between –FSR + 1 LSB +FSR –1LSB –FSR conversions exceeds 1 ms, thus causing the first conversion to –FSR + 0.5 LSB +FSR – 1.5 LSB appear offset. This mode makes the AD7952 ideal for applications ANALOG INPUT Figure 26. ADC Ideal Transfer Function where both high accuracy and fast sample rate are required. Normal Mode TYPICAL CONNECTION DIAGRAM Setting WARP = IMPULSE = low or WARP = IMPULSE = high Figure 27 shows a typical connection diagram for the AD7952 allows the fastest mode (800 kSPS) without any limitation on using the internal reference, serial data, and serial configuration time between conversions. This mode makes the AD7952 ideal interfaces. Different circuitry from that shown in Figure 27 is for asynchronous applications, such as data acquisition systems, optional and is discussed in the following sections. where both high accuracy and fast sample rate are required. Impulse Mode Setting WARP = low and IMPULSE = high uses the lowest power dissipation mode and allows power saving between conversions. The maximum throughput in this mode is 670 kSPS, and in this mode, the ADC powers down circuits after conversion, making the AD7952 ideal for battery-powered applications. Table 7. Output Codes and Ideal Input Voltages V = 5 V Digital Output Code REF VIN = 0 V to 5 V VIN = 0 V to 10 V VIN = ±5 V VIN = ±10 V Description (10 V p-p) (20 V p-p) (20 V p-p) (40 V p-p) Straight Binary Twos Complement 1 1 FSR − 1 LSB 4.999695 V 9.999389 V +4.999389 V +9.998779 V 0x3FFF 0x1FFF FSR − 2 LSB 4.999390 V 9.998779 V +4.998779 V +9.997558 V 0x3FFE 0x1FFE Midscale + 1 LSB 2.500610 V 5.000610 V +1.228 mV +2.442 mV 0x2001 0x0001 Midscale 2.5 V 5.000000 V 0 V 0 V 0x2000 0x0000 Midscale − 1 LSB 2.499390 V 4.999389 V −1.228 mV −2.442 mV 0x1FFF 0x3FFF −FSR + 1 LSB 610.4 μV 1.228 mV −4.999389 V −9.998779 V 0x0001 0x2001 2 2 −FSR 0 V 0 V −5 V −10 V 0x0000 0x2000 1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). 2 This is also the code for overrange analog input (V − V below V − V ). IN+ IN− REF REFGND Rev. 0 | Page 18 of 32 ADC CODE (Straight Binary) 06589-026 AD7952 DIGITAL SUPPLY (5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (5V) (2.5V, 3.3V, OR 5V) 10µF 100nF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND ® MicroConverter / +7V TO +15.75V MICROPROCESSOR/ SUPPLY VCC BUSY DSP 100nF 10µF SDCLK SERIAL PORT 1 SDOUT 10µF 100nF SCCLK –7V TO –15.75V SERIAL VEE SUPPLY PORT 2 SCIN NOTE 6 REF NOTE 3 SCCS C REF REFBUFIN NOTE 7 22µF NOTE 4 33Ω 100nF D CNVST REFGND AD7952 OB/2C NOTE 2 ANALOG SER/PAR OVDD INPUT+ 15Ω IN+ U1 HW/SW BIPOLAR C 2.7nF C TEN CLOCK WARP IMPULSE IN– NOTE 3 NOTE 2 ANALOG PDREF PDBUF INPUT– 15Ω PD RD CS RESET U1 C 2.7nF C AGND DGND NOTE 1 NOTE 8 NOTES 1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 5. OPTIONAL, SEE POWER SUPPLIES SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC. SEE LAYOUT GUIDELINES SECTION. Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. 0 | Page 19 of 32 06589-027 AD7952 For instance, by using IN− to sense a remote signal ground, ANALOG INPUTS ground potential differences between the sensor and the local Input Range Selection ADC ground are eliminated. In parallel mode and serial hardware mode, the input range is 100 selected by using the BIPOLAR (bipolar) and TEN (10 V range) 90 inputs. See Table 6 for pin details and the Hardware 80 Configuration section and Software Configuration section for programming the mode selection with either pins or the 70 configuration register. Note that when using the configuration 60 register, the BIPOLAR and TEN inputs are don’t cares and 50 should be tied high or low. 40 Input Structure 30 Figure 28 shows an equivalent circuit for the input structure of 20 the AD7952. 10 0V TO 5V RANGE ONLY 0 1 10 100 1000 10000 AVDD VCC FREQUENCY (kHz) D1 D3 C R Figure 29. Analog Input CMRR vs. Frequency IN IN IN+ OR IN– During the acquisition phase for ac signals, the impedance of C D2 D4 PIN the analog inputs, IN+ and IN−, can be modeled as a parallel VEE combination of Capacitor CPIN and the network formed by AGND the series connection of RIN and CIN. CPIN is primarily the pin Figure 28. Simplified Analog Input capacitance. RIN is typically 70 Ω and is a lumped component The four diodes, D1 to D4, provide ESD protection for the analog comprised of serial resistors and the on resistance of the inputs, IN+ and IN−. Care must be taken to ensure that the analog switches. C is primarily the ADC sampling capacitor and IN input signal never exceeds the supply rails by more than 0.3 V depending on the input range selected is typically 48 pF in the because this causes the diodes to become forward-biased and to 0 V to +5 V range, typically 24 pF in the 0 V to +10 V and ±5 V start conducting current. These diodes can handle a forward- ranges, and typically 12 pF in the ±10 V range. During the biased current of 120 mA maximum. For instance, these conditions conversion phase, when the switches are opened, the input could eventually occur when the input buffer’s U1 supplies are impedance is limited to CPIN. different from AVDD, VCC, and VEE. In such a case, an input Because the input impedance of the AD7952 is very high, it buffer with a short-circuit current limitation can be used to protect can be directly driven by a low impedance source without gain the part although most op amps’ short-circuit current is <100 mA. error. To further improve the noise filtering achieved by the Note that D3 and D4 are only used in the 0 V to 5 V range to AD7952 analog input circuit, an external, 1-pole RC filter allow for additional protection in applications that are switching between the amplifier’s outputs and the ADC analog inputs from the higher voltage ranges. can be used, as shown in Figure 27. However, large source This analog input structure allows the sampling of the differential impedances significantly affect the ac performance, especially signal between IN+ and IN−. By using this differential input, THD. The maximum source impedance depends on the small signals common to both inputs are rejected as shown in amount of THD that can be tolerated. The THD degrades as Figure 29, which represents the typical CMRR over frequency. a function of the source impedance and the maximum input frequency. Rev. 0 | Page 20 of 32 06589-028 CMRR (dB) 06589-029 AD7952 applications where high frequency performance (above 100 kHz) DRIVER AMPLIFIER CHOICE is not required. In applications with a gain of 1, an 82 pF Although the AD7952 is easy to drive, the driver amplifier must compensation capacitor is required. The AD8610 is an option meet the following requirements: when low bias current is needed in low frequency applications. • For multichannel, multiplexed applications, the driver Because the AD7952 uses a large geometry, high voltage input amplifier and the AD7952 analog input circuit must be switch, the best linearity performance is obtained when using able to settle for a full-scale step of the capacitor array at a the amplifier at its maximum full power bandwidth. Gaining 14-bit level (0.006%). For the amplifier, settling at 0.1% to the amplifier to make use of the more dynamic range of the 0.01% is more commonly specified. This differs significantly ADC results in increased linearity errors. For applications from the settling time at a 14-bit level and should be requiring more resolution, the use of an additional amplifier verified prior to driver selection. The AD8021 op amp com- with gain should precede a unity follower driving the AD7952. bines ultralow noise and high gain bandwidth and meets See Table 8 for a list of recommended op amps. this settling time requirement even when used with gains of up to 13. Table 8. Recommended Driver Amplifiers • The noise generated by the driver amplifier needs to be Amplifier Typical Application kept as low as possible to preserve the SNR and transition AD829 ±15 V supplies, very low noise, low frequency noise performance of the AD7952. The noise coming from AD8021 ±12 V supplies, very low noise, high frequency the driver is filtered by the external 1-pole, low-pass filter, AD8022 ±12 V supplies, very low noise, high as shown in Figure 27. The SNR degradation due to the frequency, dual amplifier is ADA4922-1 ±12 V supplies, low noise, high frequency, single-ended-to-differential driver ⎛ ⎞ ⎜ ⎟ AD8610/ ±13 V supplies, low bias current, low V ⎜ NADC ⎟ AD8620 frequency, single/dual SNR = 20log LOSS ⎜ ⎟ π π 2 2 2 V + f (Ne ) + f (Ne ) ⎜ ⎟ NADC −3dB N+ −3dB N − 2 2 ⎝ ⎠ Single-to-Differential Driver For single-ended sources, a single-to-differential driver, such where: as the ADA4922-1, can be used because the AD7952 needs to VNADC is the noise of the ADC, which is: be driven differentially. The 1-pole filter using R = 15 Ω and C = 2.7 nF provides a corner frequency of 3.9 MHz. V INp-p 15Ω OUT+ VCC 2 2 IN+ V = 2.7nF NADC R R SNR G F AD7952 ANALOG IN 20 10 INPUT 15Ω OUT– U2 IN– ADA4922-1 REF f–3dB is the cutoff frequency of the input filter (3.9 MHz). VEE 2.7nF N is the noise factor of the amplifier (1 in the buffer REF R1 10µF configuration). R2 100nF e and e are the equivalent input voltage noise densities N+ N− Figure 30. Single-to-Differential Driver Using the ADA4922-1 of the op amps connected to IN+ and IN−, in nV/√Hz. For unipolar 5 V and 10 V input ranges, the internal (or When the resistances used around the amplifiers are small, external) reference source can be used to level shift U2 for this approximation can be used. If larger resistances are the correct input span. If using an external reference, the used, their noise contributions should also be root-sum values for R1/R2 can be lowered to reduce resistive Johnson squared. noise (1.29E − 10 × √R). For the bipolar ±5 V and ±10 V input • The driver needs to have a THD performance suitable to ranges, the reference connection is not required because the that of the AD7952. Figure 15 shows the THD vs. frequency common-mode voltage is 0 V. See Table 9 for R1/R2 for the that the driver should exceed. different input ranges. The AD8021 meets these requirements and is appropriate for Table 9. R1/R2 Configuration almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an Input Range (V) R1 (Ω) R2 (Ω) Common-Mode Voltage (V) NPO ceramic or mica type. Moreover, the use of a noninverting 5 2.5 k 2.5 k 2.5 +1 gain arrangement is recommended and helps to obtain the 10 2.5 k Open 5 best SNR. ±5, ±10 100 0 The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in Rev. 0 | Page 21 of 32 06589-047 AD7952 This circuit can also be made discretely, and thus more flexible, For applications that use multiple AD7952s or other PulSAR using any of the recommended low noise amplifiers in Table 8. devices, it is more effective to use the internal reference buffer Again, to preserve the SNR of the converter, the resistors, R to buffer the external 2.5 V reference voltage. F and R , should be kept low. G The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy VOLTAGE REFERENCE INPUT/OUTPUT matters, care must be taken with the TC. For instance, a The AD7952 allows the choice of either a very low temperature ±60 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. drift internal voltage reference, an external reference, or an Temperature Sensor external buffered reference. When the internal reference is enabled (PDREF = PDBUF = The internal reference of the AD7952 provides excellent perform- low), the on-chip temperature sensor output (TEMP) is enabled ance and can be used in almost all applications. However, the and can be use to measure the temperature of the AD7952. To linearity performance is guaranteed only with an external reference. improve the calibration accuracy over the temperature range, the Internal Reference (REF = 5 V, PDREF = Low, output of the TEMP pin is applied to one of the inputs of the PDBUF = Low) analog switch (such as ADG779), and the ADC itself is used to To use the internal reference, the PDREF and PDBUF inputs measure its own temperature. This configuration is shown must be low. This enables the on-chip, band gap reference, buffer, in Figure 31. and TEMP sensor, resulting in a 5.00 V reference on the REF pin. TEMP ADG779 The internal reference is temperature-compensated to 5.000 V ± 35 mV. The reference is trimmed to provide a typical drift of TEMPERATURE IN+ ANALOG INPUT SENSOR 3 ppm/°C. This typical drift characteristic is shown in Figure 19. AD7952 C C External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) Figure 31. Use of the Temperature Sensor To use an external reference with the internal buffer, PDREF POWER SUPPLIES should be high and PDBUF should be low. This powers down The AD7952 uses five sets of power supply pins: the internal reference and allows the 2.5 V reference to be applied • AVDD: analog 5 V core supply to REFBUFIN, producing 5 V on the REF pin. The internal reference buffer is useful in multiconverter applications because • VCC: analog high voltage, positive supply a buffer is typically required in these applications. • VEE: high voltage, negative supply External 5 V Reference (PDREF = High, PDBUF = High) • DVDD: digital 5 V core supply To use an external reference directly on the REF pin, PDREF • OVDD: digital input/output interface supply and PDBUF should both be high. PDREF and PDBUF power Core Supplies down the internal reference and the internal reference buffer, The AVDD and DVDD supply the AD7952 analog and digital respectively. For improved drift performance, an external cores, respectively. Sufficient decoupling of these supplies is reference, such as the ADR445 or the ADR435, is recommended. required, consisting of at least a 10 μF capacitor and a 100 nF Reference Decoupling capacitor on each supply. The 100 nF capacitors should be Whether using an internal or external reference, the AD7952 placed as close as possible to the AD7952. To reduce the number voltage reference input (REF) has a dynamic input impedance; of supplies needed, the DVDD can be supplied through a simple therefore, it should be driven by a low impedance source with RC filter from the analog supply, as shown in Figure 27. efficient decoupling between the REF and REFGND inputs. This High Voltage Supplies decoupling depends on the choice of the voltage reference but The high voltage bipolar supplies, VCC and VEE, are required usually consists of a low ESR capacitor connected to REF and and must be at least 2 V larger than the maximum input, V . IN REFGND with minimum parasitic inductance. A 22 μF (X5R, For example, if using the bipolar 10 V range, the supplies should 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) be ±12 V minimum. Sufficient decoupling of these supplies is is appropriate when using either the internal reference or the also required, consisting of at least a 10 μF capacitor and a ADR445/ADR435 external reference. 100 nF capacitor on each supply. For unipolar operation, the The placement of the reference decoupling is also important to VEE supply can be grounded with some slight THD the performance of the AD7952. The decoupling capacitor should performance degradation. be mounted on the same side as the ADC, right at the REF pin Digital Output Supply with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance The OVDD supplies the digital outputs and allows direct interface with any logic working between 2.3 V and 5.25 V. and to the analog ground plane with several vias. Rev. 0 | Page 22 of 32 06589-030 AD7952 OVDD should be set to the same level as the system interface. Power Down Sufficient decoupling is required, consisting of at least a 10 μF Setting PD = high powers down the AD7952, thus reducing capacitor and a 100 nF capacitor with the 100 nF capacitors supply currents to their minimums, as shown in Figure 23. When placed as close as possible to the AD7952. the ADC is in power-down, the current conversion (if any) is completed and the digital bus remains active. To further reduce Power Sequencing the digital supply currents, drive the inputs to OVDD or OGND. The AD7952 is independent of power supply sequencing and is very insensitive to power supply variations on AVDD over a wide Power-down can also be programmed with the configuration frequency range, as shown in Figure 32. register. See the Software Configuration section for details. Note that when using the configuration register, the PD input is a 80 EXT REF don’t care and should be tied to either high or low. 75 INT REF 70 CONVERSION CONTROL 65 CNVST The AD7952 is controlled by the input. A falling edge 60 CNVST on is all that is necessary to initiate a conversion. A detailed timing diagram of the conversion process is shown in 55 Figure 34. Once initiated, it cannot be restarted or aborted, 50 even by the power-down input, PD, until the conversion is 45 CNVST CS completed. The signal operates independently of the 40 RD and signals. 35 t 2 30 t 1 1 10000 10 100 1000 CNVST FREQUENCY (kHz) Figure 32. AVDD PSRR vs. Frequency Power Dissipation vs. Throughput BUSY t 4 In impulse mode, the AD7952 automatically reduces its power t 3 t 6 consumption at the end of each conversion phase. During the t 5 acquisition phase, the operating currents are very low, which allows MODE ACQUIRE CONVERT ACQUIRE CONVERT a significant power savings when the conversion rate is reduced t t 7 8 (see Figure 33). This feature makes the AD7952 ideal for very Figure 34. Basic Conversion Timing low power, battery-operated applications. Although CNVST is a digital signal, it should be designed with It should be noted that the digital interface remains active even special care with fast, clean edges, and levels with minimum during the acquisition phase. To reduce the operating digital supply overshoot, undershoot, or ringing. currents even further, drive the digital inputs close to the power CNVST The trace should be shielded with ground, and a low value rails (that is, OVDD and OGND). (such as 50 Ω) serial resistor termination should be added close 1000 to the output of the component that drives this line. CNVST For applications where SNR is critical, the signal should have very low jitter. This can be achieved by using a dedicated WARP MODE POWER 100 oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 27. IMPULSE MODE POWER 10 PDREF = PDBUF = HIGH 1 10 100 1000 10000 100000 1000000 Figure 33. Power Dissipation vs. Sample Rate Rev. 0 | Page 23 of 32 POWER DISSIPATION (mW) PSRR (dB) 06589-031 06589-032 06589-033 AD7952 INTERFACES CS = RD = 0 DIGITAL INTERFACE t 1 The AD7952 has a versatile digital interface that can be set up CNVST as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7952 BUSY digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In t 4 t most applications, the OVDD supply pin is connected to the host 3 t 11 system interface 2.5 V to 5.25 V digital supply. Finally, by using DATA 2C input pin, both twos complement or straight binary PREVIOUS CONVERSION DATA NEW DATA the OB/ BUS coding can be used. Figure 36. Master Parallel Data Timing for Reading (Continuous Read) CS RD Two signals, and , control the interface. When at least Slave Parallel Interface one of these signals is high, the interface outputs are in high In slave parallel reading mode, the data can be read either after CS impedance. Usually, allows the selection of each AD7952 in each conversion, which is during the next acquisition phase, or multicircuit applications and is held low in a single AD7952 during the following conversion, as shown in Figure 37 and design. RD is generally used to enable the conversion result on Figure 38, respectively. When the data is read during the conver- the data bus. sion, it is recommended that it is read-only during the first half RESET of the conversion phase. This avoids any potential feedthrough The RESET input is used to reset the AD7952. A rising edge on between voltage transients on the digital interface and the most RESET aborts the current conversion (if any) and tristates the critical analog conversion circuitry. data bus. The falling edge of RESET resets the AD7952 and CS clears the data bus and configuration register. See Figure 35 for the RESET timing details. t 9 RD RESET BUSY BUSY DATA BUS t 8 DATA CURRENT BUS CONVERSION CNVST t t 12 13 Figure 35. RESET Timing Figure 37. Slave Parallel Data Timing for Reading (Read After Convert) PARALLEL INTERFACE CS = 0 The AD7952 is configured to use the parallel interface when CNVST, t 1 RD SER/PAR is held low. Master Parallel Interface CS RD Data can be continuously read by tying and low, thus BUSY t 4 requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in t 3 shared bus applications (unless the device is held in RESET). Figure 36 details the timing for this mode. DATA PREVIOUS BUS CONVERSION t t 12 13 Figure 38. Slave Parallel Data Timing for Reading (Read During Convert) Rev. 0 | Page 24 of 32 06589-034 06589-036 06589-037 06589-035 AD7952 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. The pins multiplexed on D[8:0] and used for master serial As shown in Figure 39, when BYTESWAP is low, the LSB byte is interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC, output on D[7:0] and the MSB is output on D[13:8]. When INVSCLK, RDC, SDOUT, SDCLK, and SYNC. BYTESWAP is high, the LSB and MSB bytes are swapped; the PAR INT Internal Clock (SER/ = High, EXT/ = Low) LSB is output on D[13:8] and the MSB is output on D[7:0]. By The AD7952 is configured to generate and provide the serial connecting BYTESWAP to an address line, the 14-bit data can data clock, SDCLK, when the EXT/INT pin is held low. The be read in two bytes on either D[13:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. AD7952 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK and the SYNC signals can be inverted, if desired, using the INVSCLK and INVSYNC CS inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conversion. RD Figure 40 and Figure 41 show detailed timing diagrams of these two modes. BYTESWAP Read During Convert (RDC = High) HI-Z HI-Z Setting RDC = high allows the master read (previous PINS D[13:8] HIGH BYTE LOW BYTE conversion result) during conversion mode. Usually, because t t t 12 12 13 the AD7952 is used with a fast throughput, this mode is the HI-Z HI-Z LOW BYTE HIGH BYTE PINS D[7:0] most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instances, minimizing potential Figure 39. 8-Bit and 14-Bit Parallel Interface feedthrough between digital activity and critical conversion SERIAL INTERFACE decisions. In this mode, the SDCLK period changes because the The AD7952 has a serial interface (SPI-compatible) multiplexed LSBs require more time to settle and the SDCLK is derived on the data pins D[13:0]. The AD7952 is configured to use the from the SAR conversion cycle. In this mode, the AD7952 PAR serial interface when SER/ is held high. generates a discontinuous SDCLK of two different periods and the host should use an SPI interface. Data Interface Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) The AD7952 outputs 14 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 14 clock pulses provided Setting RDC = low allows the read after conversion mode. on the SDCLK pin. The output data is valid on both the rising Unlike the other serial modes, the BUSY signal returns low and falling edge of the data clock. after the 14 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width (refer to Serial Configuration Interface Table 4 for BUSY timing specifications). The DIVSCLK[1:0] The AD7952 can be configured through the serial configuration inputs control the SDCLK period and SDOUT data rate. As a register only in serial mode, because the serial configuration result, the maximum throughput cannot be achieved in this pins are also multiplexed on the data pins D[13:10]. See the mode. In this mode, the AD7952 also generates a discontinuous Hardware Configuration section and Software Configuration SDCLK; however, a fixed period and hosts supporting both SPI section for more information. and serial ports can also be used. Rev. 0 | Page 25 of 32 06589-038 AD7952 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 12 13 14 SDCLK t 15 t 27 SDOUT D13 D12 D2 D1 D0 X t t 16 23 t 22 Figure 40. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 19 14 t t 20 21 t 24 t 26 t 15 SDCLK 12 3 12 13 14 t 18 t 27 SDOUT X D13 D12 D2 D1 D0 t t 16 23 t 22 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 26 of 32 06589-040 06589-039 AD7952 CNVST SLAVE SERIAL INTERFACE Simultaneous sampling is possible by using a common signal. Note that the SDIN input is latched on the opposite edge The pins multiplexed on D[19:2] used for slave serial of SDCLK used to shift out the data on SDOUT (SDCLK interface are: EXT/INT, INVSCLK, SDIN, SDOUT, falling edge when INVSCLK = low). Therefore, the MSB SDCLK, and RDERROR. of the upstream converter follows the LSB of the downstream PAR INT External Clock (SER/ = High, EXT/ = High) converter on the next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot be used because the SDIN-to-SDCLK setup Setting the EXT/INT = high allows the AD7952 to accept an time, t , is less than the minimum time specified. (SDCLK- 33 externally supplied serial data clock on the SDCLK pin. In this to-SDOUT delay, t , is the same for all converters when 32 mode, several methods can be used to read the data. The simultaneously sampled). For proper operation, the SDCLK external serial clock is gated by CS. When CS and RD are both edge for latching SDIN (or ½ period of SDCLK) needs to be low, the data can be read after each conversion or during the following conversion. A clock can be either normally high or t = t + t 1/2SDCLK 32 33 normally low when inactive. For detailed timing diagrams, or the maximum SDCLK frequency needs to be see Figure 43 and Figure 44. 1 f = While the AD7952 is performing a bit decision, it is important SDCLK 2(t + t ) 32 33 that voltage transients be avoided on digital input/output pins If not using the daisy-chain feature, the SDIN input should or degradation of the conversion result may occur. This is always be tied either high or low. particularly important during the last 450 ns of the conversion phase because the AD7952 provides error correction circuitry BUSY OUT that can correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recom- BUSY BUSY mended that any external clock provided is a discontinuous AD7952 AD7952 #2 #1 clock that transitions only when BUSY is low or, more importantly, (UPSTREAM) (DOWNSTREAM) that it does not transition during the last 450 ns of BUSY high. DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT External Discontinuous Clock Data Read After CNVST CNVST Conversion CS CS Though the maximum throughput cannot be achieved using SDCLK SDCLK this mode, it is the most recommended of the serial slave modes. Figure 43 shows the detailed timing diagrams for this method. SDCLK IN CS IN After a conversion is complete, indicated by BUSY returning low, CNVST IN CS RD the conversion result can be read while both and are low. Figure 42. Two AD7952 Devices in a Daisy-Chain Configuration Data is shifted out MSB first with 14 clock pulses and, depending External Clock Data Read During Previous Conversion on the SDCLK frequency, can be valid on the falling and rising edges of the clock. Figure 44 shows the detailed timing diagrams for this method. CS RD During a conversion, while both and are low, the result One advantage of this method is that conversion performance is of the previous conversion can be read. The data is shifted out, not degraded because there are no voltage transients on the digital MSB first, with 14 clock pulses, and depending on the SDCLK interface during the conversion process. Another advantage is frequency, can be valid on both the falling and rising edges the ability to read the data at any speed up to 40 MHz, which of the clock. The 14 bits have to be read before the current accommodates both the slow digital host interface and the fastest conversion is completed; otherwise, RDERROR is pulsed high serial reading. and can be used to interrupt the host interface to prevent Daisy-Chain Feature incomplete data reading. Also in the read after convert mode, the AD7952 provides a To reduce performance degradation due to digital activity, daisy-chain feature for cascading multiple converters together a fast discontinuous clock of at least 40 MHz is recommended to using the serial data input pin, SDIN. This feature is useful for ensure that all the bits are read during the first half of the SAR reducing component count and wiring connections when conversion phase. desired, for instance, in isolated multiconverter applications. Figure 43 for the timing details. The daisy-chain feature should not be used in this mode because See digital activity occurs during the second half of the SAR An example of the concatenation of two devices is shown in conversion phase, likely resulting in performance degradation. Figure 42. Rev. 0 | Page 27 of 32 06589-041 AD7952 External Clock Data Read After/During Conversion It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode, and 13 MHz in impulse mode can be used. SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t t t t 31 35 36 31 SDCLK X* 1 2 3 4 12 13 14 15 16 17 t 32 t 37 SDOUT D13 D12 X13 X12 D11 D2 D1 D0 t 16 SDIN X13 X12 X11 X2 X1 X0 Y13 Y12 t t 33 34 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 43. Slave Serial Data Timing for Reading (Read After Convert) SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t t t t 31 35 36 31 SDCLK X* X* X* X* X* X* 12 3 13 14 t 32 t 37 SDOUT D13 D12 D1 D0 DATA = SDIN t t 16 27 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 28 of 32 06589-043 06589-042 AD7952 it is not recommended to write to the SCP during the last 450 ns HARDWARE CONFIGURATION of conversion (BUSY = high), or performance degradation can The AD7952 can be configured at any time with the dedicated result. In addition, the SCP can be accessed in both serial master hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and and serial slave read during and read after convert modes. PAR PD for parallel mode (SER/ = low) or serial hardware mode Note that at power-up, the configuration register is undefined. PAR SW (SER/ = high, HW/ = high). Programming the AD7952 The RESET input clears the configuration register (sets all bits for mode selection and input range configuration can be done to 0), thus placing the configuration to 0 V to 5 V input, normal before or during conversion. Like the RESET input, the ADC mode, and twos complemented output. requires at least one acquisition time to settle, as shown in Figure 45. See Table 6 for pin descriptions. Note that these Table 10. Configuration Register Description inputs are high impedance when using the software Bit Name Description configuration mode. 8 START START bit. With the SCP enabled (SCCS = low), when START is high, the first rising edge of SCCLK SOFTWARE CONFIGURATION (INVSCLK = low) begins to load the register with the The pins multiplexed on D[13:10] used for software configura- new configuration. tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7952 is 7 BIPOLAR Input Range Select. Used in conjunction with Bit 6, TEN, per the following. programmed using the dedicated write-only serial configurable Input Range (V) BIPOLAR TEN port (SCP) for conversion mode, input range selection, output 0 to 5 Low Low coding, and power-down using the serial configuration register. 0 to 10 Low High See Table 10 for details of each bit in the configuration register. ±5 High Low The SCP can only be used in serial software mode selected with ±10 High High SER/PAR = high and HW/SW = low because the port is 6 TEN Input Range Select. See Bit 7, BIPOLAR. multiplexed on the parallel interface. 5 PD Power Down. PD = low, normal operation. The SCP is accessed by asserting the port’s chip select, SCCS, PD = high, power down the ADC. The SCP is and then writing SCIN synchronized with SCCLK, which (like accessible while in power-down. To power-up SDCLK) is edge sensitive depending on the state of INVSCLK. the ADC, write PD = low on the next configuration See Figure 46 for timing details. SCIN is clocked into the con- setting. figuration register MSB first. The configuration register is an 4 IMPULSE Mode Select. Used in conjunction with Bit 3, WARP, per the following. internal shift register that begins with Bit 8, the START bit. The th Mode WARP IMPULSE 9 SPPCLK edge updates the register and allows the new settings to Normal Low Low be used. As indicated in the timing diagram, at least one acquisition Impulse Low High th time is required from the 9 SCCLK edge. Bits [1:0] are reserved Warp High Low bits and are not written to while the SCP is being updated. Normal High High The SCP can be written to at any time, up to 40 MHz, and it is 3 WARP Mode Select. See Bit 4, IMPULSE. recommended to write to while the AD7952 is not busy 2 OB/2C Output Coding. 2C converting, as detailed in Figure 46. In this mode, the full OB/ = low, use twos complement output. OB/2C = high, use straight binary output. 1 MSPS is not attainable because the time required for SCP access 1 RSV Reserved. is (t31 + 9 × 1/SCCLK + t8) minimum. If the full throughput is 0 RSV Reserved. required, the SCP can be written to during conversion; however, HW/SW = 0 PD = 0 SER/PAR = 0, 1 t t 8 8 CNVST BUSY BIPOLAR, TEN WARP, IMPULSE Figure 45. Hardware Configuration Timing Rev. 0 | Page 29 of 32 06589-044 AD7952 WARP = 0 OR 1 BIPOLAR = 0 OR 1 SER/PAR = 1 INVSCLK = 0 t IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 PD = 0 8 CNVST BUSY t 31 SCCS t t t 31 35 36 SCCLK 123 4 5 67 89 t 37 SCIN X BIPOLAR TEN PD IMPULSE WARP OB/2C START X t 33 t 34 Figure 46. Serial Configuration Port Timing The reading process can be initiated in response to the end-of- MICROPROCESSOR INTERFACING conversion signal (BUSY going low) using an interrupt line of The AD7952 is ideally suited for traditional dc measurement the DSP. The serial peripheral interface (SPI) on the ADSP-219x applications supporting a microprocessor and ac signal is configured for master mode (MSTR) = 1, clock polarity bit processing applications interfacing to a digital signal processor. (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable The AD7952 is designed to interface with a parallel 8-bit or (TIMOD) = 0 by writing to the SPI control register (SPICLTx). 14-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC be used with the AD7952 to prevent digital noise from coupling result in less than 1 μs. When a higher sampling rate is desired, into the ADC. use one of the parallel interface modes. SPI Interface DVDD The AD7952 is compatible with SPI and QSPI digital hosts and AD7952* ADSP-219x* DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x. SER/PAR Figure 47 shows an interface diagram between the AD7952 and BUSY PFx EXT/INT CS SPIxSEL (PFx) the SPI-equipped ADSP-219x. To accommodate the slower SDOUT MISOx speed of the DSP, the AD7952 acts as a slave device, and data must RD SDCLK SCKx be read after conversion. This mode also allows the daisy-chain INVSCLK CNVST PFx OR TFSx feature. The convert command could be initiated in response to an internal timer interrupt. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 47. Interfacing the AD7952 to SPI Interface Rev. 0 | Page 30 of 32 06589-045 06589-046 AD7952 APPLICATION INFORMATION The DVDD supply of the AD7952 can either be a separate supply LAYOUT GUIDELINES or come from the analog supply, AVDD, or from the digital While the AD7952 has very good immunity to noise on the interface supply, OVDD. When the system digital supply is noisy, power supplies, exercise care with the grounding layout. To or fast switching digital signals are present, and no separate supply facilitate the use of ground planes that can be easily separated, is available, it is recommended to connect the DVDD digital supply design the printed circuit board that houses the AD7952 so that to the analog supply AVDD through an RC filter, and to connect the analog and digital sections are separated and confined to the system supply to the interface digital supply OVDD and the certain areas of the board. Digital and analog ground planes remaining digital circuitry. See Figure 27 for an example of this should be joined in only one place, preferably underneath the configuration. When DVDD is powered from the system supply, AD7952, or as close as possible to the AD7952. If the AD7952 is it is useful to insert a bead to further reduce high frequency spikes. in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at The AD7952 has four different ground pins: REFGND, AGND, DGND, and OGND. one point only, a star ground point, established as close as possible to the AD7952. • REFGND senses the reference voltage and, because it carries To prevent coupling noise onto the die, to avoid radiating noise, pulsed currents, should be a low impedance return to the and to reduce feedthrough: reference. • Do not run digital lines under the device. • AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least • Do run the analog ground plane under the AD7952. resistance to the analog ground plane. CNVST • Shield fast switching signals, like or clocks, with • DGND must be tied to the analog or digital ground plane digital ground to avoid radiating noise to other sections of depending on the configuration. the board, and never run them near analog signal paths. • OGND is connected to the digital system ground. • Avoid crossover of digital and analog signals. The layout of the decoupling of the reference voltage is important. • Run traces on different but close layers of the board, at right To minimize parasitic inductances, place the decoupling capacitor angles to each other, to reduce the effect of feedthrough through close to the ADC and connect it with short, thick traces. the board. EVALUATING PERFORMANCE The power supply lines to the AD7952 should use as large a trace as A recommended layout for the AD7952 is outlined in the possible to provide low impedance paths and reduce the effect of EVAL-AD7952CBZ evaluation board documentation. The glitches on the power supply lines. Good decoupling is also evaluation board package includes a fully assembled and tested important to lower the impedance of the supplies presented to evaluation board, documentation, and software for controlling the AD7952, and to reduce the magnitude of the supply spikes. the board from a PC via the EVAL-CONTROL BRD3. Decoupled ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 31 of 32 PAD AD7952 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 48. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO VEE. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP REQUIRED TO MEET THE 0.85 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 49. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7952BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7952BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7952BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7952BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1, 2 EVAL-AD7952CBZ Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06589-0-2/07(0) TTTT Rev. 0 | Page 32 of 32 051706-A