ANALOG DEVICES AD7949

14-Bit, 8-Channel, 250 kSPS PulSAR ADC Data Sheet AD7949 FEATURES FUNCTIONAL BLOCK DIAGRAM 2.3V TO 5.5V 0.5V TO VDD – 0.5V 0.5V TO VDD 14-bit resolution with no missing codes 0.1µF 10µF 8-channel multiplexer with choice of inputs REFIN REF VDD Unipolar single-ended Differential (GND sense) 1.8V BAND GAP VIO TO Pseudobipolar REF AD7949 VDD Throughput: 250 kSPS TEMP SENSOR INL/DNL: ±0.5/±0.25 LSB typical CNV IN0 SINAD: 85 dB @ 20 kHz IN1 SCK IN2 SPI SERIAL 14-BIT SAR THD: −100 dB @ 20 kHz MUX IN3 INTERFACE ADC SDO Analog input range: 0 V to V with V up to VDD IN4 REF REF ONE-POLE DIN IN5 Multiple reference types LPF IN6 SEQUENCER IN7 Internal selectable 2.5 V or 4.096 V COM External buffered (up to 4.096 V) GND External (up to VDD) Internal temperature sensor (TEMP) Figure 1. Channel sequencer, selectable 1-pole filter, busy indicator Table 1. Multichannel 14-/16-Bit PulSAR® ADCs No pipeline delay, SAR architecture Type Channels 250 kSPS 500 kSPS ADC Driver Single-supply 2.3 V to 5.5 V operation with 14-Bit 8 AD7949 ADA4841-x 1.8 V to 5.5 V logic interface 16-Bit 4 AD7682 ADA4841-x Serial interface compatible with SPI, MICROWIRE, 16-Bit 8 AD7689 AD7699 ADA4841-x QSPI, and DSP Power dissipation 2.9 mW @ 2.5 V/200 kSPS GENERAL DESCRIPTION 10.8 mW @ 5 V/250 kSPS The AD7949 is an 8-channel, 14-bit, charge redistribution Standby current: 50 nA successive approximation register (SAR) analog-to-digital 20-lead 4 mm × 4 mm LFCSP package converter (ADC) that operates from a single power supply, VDD. APPLICATIONS The AD7949 contains all components for use in a multichannel, low power data acquisition system, including a true 14-bit SAR Multichannel system monitoring ADC with no missing codes; an 8-channel, low crosstalk Battery-powered equipment multiplexer that is useful for configuring the inputs as single- Medical instruments: ECG/EKG Mobile communications: GPS ended (with or without ground sense), differential, or bipolar; Power line monitoring an internal low drift reference (selectable 2.5 V or 4.096 V) and Data acquisition buffer; a temperature sensor; a selectable one-pole filter; and a Seismic data acquisition systems sequencer that is useful when channels are continuously Instrumentation scanned in order. Process control The AD7949 uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7949 is housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07351-001 AD7949 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference Output/Input .............................................. 19 Applications ....................................................................................... 1 Power Supply ............................................................................... 21 Functional Block Diagram .............................................................. 1 Supplying the ADC from the Reference .................................. 21 General Description ......................................................................... 1 Digital Interface .............................................................................. 22 Revision History ............................................................................... 3 Reading/Writing During Conversion, Fast Hosts .................. 22 Specifications ..................................................................................... 4 Reading/Writing After Conversion, Any Speed Hosts .......... 22 Timing Specifications .................................................................. 6 Reading/Writing Spanning Conversion, Any Speed Host .... 23 Absolute Maximum Ratings ............................................................ 8 Configuration Register, CFG .................................................... 23 ESD Caution .................................................................................. 8 General Timing Without a Busy Indicator ............................. 25 Pin Configuration and Function Descriptions ............................. 9 General Timing with a Busy Indicator .................................... 26 Typical Performance Characteristics ........................................... 10 Channel Sequencer .................................................................... 27 Terminology .................................................................................... 13 Read/Write Spanning Conversion Without a Busy Indicator ...................................................................................... 28 Theory of Operation ...................................................................... 14 Read/Write Spanning Conversion with a Busy Indicator ..... 30 Overview ...................................................................................... 14 Application Hints ........................................................................... 31 Converter Operation .................................................................. 14 Layout .......................................................................................... 31 Transfer Functions...................................................................... 15 Evaluating AD7949 Performance ............................................. 31 Typical Connection Diagrams .................................................. 16 Outline Dimensions ....................................................................... 32 Analog Inputs .............................................................................. 17 Ordering Guide .......................................................................... 32 Driver Amplifier Choice ............................................................ 19 Rev. D | Page 2 of 32 Data Sheet AD7949 REVISION HISTORY 3/12—Rev. C to Rev. D Added Figure 30; Renumbered Sequentially ............................... 18 Changes to External Reference and Internal Buffer Section, Changes to Figure 26 ...................................................................... 16 External Reference Section, and Reference Decoupling Changes to Internal Reference/Temperature Sensor Section .... 19 Section .............................................................................................. 19 Changes to External Reference and Internal Buffer Section ..... 20 Added Figure 31 and Figure 32 ..................................................... 19 Changes to Bits[5:3] Function, Table 9 ......................................... 24 Changes to Power Supply Section ................................................. 20 Updated Outline Dimensions ........................................................ 32 Changed Reading/Writing During Conversion, Fast Hosts 8/11—Rev. B to Rev. C Section to Reading/Writing After Conversion, Changes to Internal Reference Section ........................................ 18 Any Speed Hosts ............................................................................. 21 Changes to External Reference and Internal Buffer Section and Changes to Configuration Register, CFG Section and External Reference Section ............................................................ 19 Table 9 ............................................................................................... 22 Changes to Bits[5:3] Function, Table 9 ......................................... 22 Added General Timing Without a Busy Indicator Section and Figure 36 ........................................................................................... 23 5/09—Rev. A to Rev. B Added General Timing with a Busy Indicator Section and Changes to Features Section, Applications Section, and Figure 37 ........................................................................................... 24 Figure 1 ............................................................................................... 1 Added Channel Sequencer Section, Examples Section, and Changes to Specifications Section ................................................... 3 Figure 38 ........................................................................................... 25 Changes to Timing Specifications Section ..................................... 5 Changes to Read/Write Spanning Conversion Without a Busy Changes to Table 5 ............................................................................ 7 Indicator Section and Figure 40 .................................................... 26 Changes to Figure 4 and Table 6 ..................................................... 8 Changes to Read/Write Spanning Conversion with a Busy Changes to Figure 20 ...................................................................... 11 Indicator Section and Figure 42 .................................................... 27 Changes to Converter Operation Section .................................... 13 Changes to Evaluating AD7949 Performance Section ............... 28 Changes to Table 7 .......................................................................... 14 Added Exposed Pad Notation to Outline Dimensions .............. 29 Changes to Figure 25 and Figure 26 ............................................. 15 Changes to Ordering Guide ........................................................... 29 Changes to Bipolar Single Supply Section, Input Structure 5/08—Rev. 0 to Rev. A Section, and Selectable Low-Pass Filter Section ......................... 16 Changes to Input Configurations Section, Sequencer Section, Changes to Ordering Guide ........................................................... 26 and Source Resistance Section....................................................... 17 5/08—Revision 0: Initial Version Changes to Internal Reference/Temperature Sensor Section .... 18 Rev. D | Page 3 of 32 AD7949 Data Sheet SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUT Voltage Range Unipolar mode 0 +V V REF Bipolar mode −V /2 +V /2 REF REF Absolute Input Voltage Positive input, unipolar and bipolar modes −0.1 V + 0.1 V REF Negative or COM input, unipolar mode −0.1 +0.1 Negative or COM input, bipolar mode VREF/2 − 0.1 VREF/2 VREF/2 + 0.1 Analog Input CMRR f = 250 kHz 68 dB IN Leakage Current at 25°C Acquisition phase 1 nA 1 Input Impedance THROUGHPUT Conversion Rate 2 Full Bandwidth VDD = 4.5 V to 5.5 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 kSPS 2 ¼ Bandwidth VDD = 4.5 V to 5.5 V 0 62.5 kSPS VDD = 2.3 V to 4.5 V 0 50 kSPS Transient Response Full-scale step, full bandwidth 1.8 μs Full-scale step, ¼ bandwidth 14.5 μs ACCURACY No Missing Codes 14 Bits 3 Integral Linearity Error −1 ±0.5 +1 LSB Differential Linearity Error −1 ±0.25 +1 LSB Transition Noise REF = VDD = 5 V 0.1 LSB 4 Gain Error −5 ±0.5 +5 LSB Gain Error Match −1 ±0.2 +1 LSB Gain Error Temperature Drift ±1 ppm/°C 4 Offset Error ±0.5 LSB Offset Error Match −1 ±0.2 +1 LSB Offset Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity ±0.2 LSB VDD = 5 V ± 5% 5 AC ACCURACY 6 Dynamic Range 85.6 dB Signal-to-Noise f = 20 kHz, V = 5 V 84.5 85.5 dB IN REF f = 20 kHz, V = 4.096 V internal REF 85 dB IN REF fIN = 20 kHz, VREF = 2.5 V internal REF 84 dB SINAD fIN = 20 kHz, VREF = 5 V 84 85 dB fIN = 20 kHz, VREF = 5 V, −60 dB input 33.5 dB fIN = 20 kHz, VREF = 4.096 V internal REF 85 dB f = 20 kHz, V = 2.5 V internal REF 84 dB IN REF Total Harmonic Distortion f = 20 kHz −100 dB IN Spurious-Free Dynamic Range fIN = 20 kHz 108 dB Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s) −125 dB SAMPLING DYNAMICS −3 dB Input Bandwidth Full bandwidth 1.7 MHz ¼ bandwidth 0.425 MHz Aperture Delay VDD = 5 V 2.5 ns Rev. D | Page 4 of 32 Data Sheet AD7949 Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE REF Output Voltage 2.5 V, @ 25°C 2.490 2.500 2.510 V 4.096 V, @ 25°C 4.086 4.096 4.106 V 7 REFIN Output Voltage 2.5 V, @ 25°C 1.2 V 4.096 V, @ 25°C 2.3 V REF Output Current ±300 µA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 10 µF 5 ms EXTERNAL REFERENCE Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.5 V Current Drain 250 kSPS, REF = 5 V 50 µA TEMPERATURE SENSOR 8 Output Voltage @ 25°C 283 mV Temperature Sensitivity 1 mV/°C DIGITAL INPUTS Logic Levels VIL −0.3 +0.3 × VIO V VIH 0.7 × VIO VIO + 0.3 V IIL −1 +1 µA I −1 +1 µA IH DIGITAL OUTPUTS 9 Data Format 10 Pipeline Delay V I = +500 µA 0.4 V OL SINK V I = −500 µA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V Operating range 1.8 VDD + 0.3 V 11, 12 Standby Current VDD and VIO = 5 V, @ 25°C 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.5 µW VDD = 2.5 V, 100 kSPS throughput 1.45 2.0 mW VDD = 2.5 V, 200 kSPS throughput 2.9 4.0 mW VDD = 5 V, 250 kSPS throughput 10.8 12.5 mW VDD = 5 V, 250 kSPS throughput with internal 13.5 15.5 mW reference Energy per Conversion 50 nJ 13 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 See the Analog Inputs section. 2 The bandwidth is set in the configuration register. 3 LSB means least significant bit. With the 5 V input range, one LSB = 305 µV. 4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 7 This is the output from the internal band gap. 8 The output voltage is internal and present on a dedicated multiplexer input. 9 Unipolar mode: serial 14-bit straight binary. Bipolar mode: serial 14-bit twos complement. 10 Conversion results available immediately after completed conversion. 11 With all digital inputs forced to VIO or GND as required. 12 During acquisition phase. 13 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. D | Page 5 of 32 AD7949 Data Sheet TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 2.2 µs CONV Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 4.0 µs Data Write/Read During Conversion t 1.0 µs DATA CNV Pulse Width t 10 ns CNVH SCK Period t t + 2 ns SCK DSDO SCK Low Time tSCKL 11 ns SCK High Time tSCKH 11 ns SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay t DSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 32 ns CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge t 5 ns HDIN 1 See Figure 2 and Figure 3 for load conditions. Rev. D | Page 6 of 32 Data Sheet AD7949 VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T to T , unless otherwise noted. MIN MAX Table 4. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 µs Acquisition Time t 1.8 µs ACQ Time Between Conversions t 5 µs CYC Data Write/Read During Conversion t 1.2 µs DATA CNV Pulse Width tCNVH 10 ns SCK Period tSCK tDSDO + 2 ns SCK Low Time tSCKL 12 ns SCK High Time t 12 ns SCKH SCK Falling Edge to Data Remains Valid t 5 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV Low to SDO D15 MSB Valid t EN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns CNV High or Last SCK Falling Edge to SDO High Impedance t 50 ns DIS CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. I 500µA OL 1.4V TO SDO C L 50pF 500µA I OH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V 2 2 0.8V OR 0.5V 0.8V OR 0.5V 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. D | Page 7 of 32 07351-002 07351-003 AD7949 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational INx, COM GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA section of this specification is not implied. Exposure to absolute REF, REFIN GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V ESD CAUTION VIO to VDD −0.3 V to VDD + 0.3 V DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance (LFCSP) 47.6°C/W JA θ Thermal Impedance (LFCSP) 4.4°C/W JC 1 See the Analog Inputs section. Rev. D | Page 8 of 32 Data Sheet AD7949 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR VDD 1 15 VIO REF 2 14 SDO AD7949 13 SCK REFIN 3 GND 4 12 DIN TOP VIEW GND 5 11 CNV (Not to Scale) NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 20 VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for 2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.5 V. 2 REF AI/O Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. 3 REFIN AI/O Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above. 4, 5 GND P Power Supply Ground. 6 to 9 IN4 to IN7 AI Channel 4 through Channel 7 Analog Inputs. 10 COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V. 11 CNV DI Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. 12 DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. 14 SDO DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 16 to 19 IN0 to IN3 AI Channel 0 through Channel 3 Analog Inputs. 21 Exposed Pad NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is (EPAD) (EPAD) recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. D | Page 9 of 32 07351-004 IN4 6 20 VDD IN5 7 19 IN3 IN6 8 18 IN2 17 IN1 IN7 9 COM 10 16 IN0 AD7949 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted. 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 4,096 8,192 0 4,096 8,192 12,288 16,384 12,288 16,384 CODES CODES Figure 5. Integral Nonlinearity vs. Code, VREF = VDD = 5 V Figure 8. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 300k 300k V = VDD = 5V 261,120 REF 259,473 V = VDD = 2.5V REF 250k 250k 200k 200k 150k 150k 100k 100k 50k 50k 955 693 00 0 1 0 00 0 00 0 00 0 0 0 1FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 1FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 2004 CODE IN HEX CODE IN HEX Figure 6. Histogram of a DC Input at Code Center Figure 9. Histogram of a DC Input at Code Center 0 0 V = VDD = 5V V = VDD = 2.5V REF REF f = 250kSPS –20 f = 200kSPS –20 S s f = 19.9kHz f = 19.9kHz IN IN SNR = 85.3dB SNR = 84.2dB –40 –40 SINAD = 85.2dB SINAD = 82.4dB THD = –100dB THD = –84dB –60 SFDR = 103dB SFDR = 85dB –60 SECOND HARMONIC = –110dB SECOND HARMONIC = –100dB –80 THIRD HARMONIC = –103dB THIRD HARMONIC = –85dB –80 –100 –100 –120 –120 –140 –140 –160 –180 –160 05 250 75 100 125 05 250 75 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 7. 20 kHz FFT, V = VDD = 5 V Figure 10. 20 kHz FFT, V = VDD = 2.5 V REF REF Rev. D | Page 10 of 32 AMPLITUDE (dB of Full-Scale) COUNTS INL (LSB) 07351-006 07351-005 07351-007 AMPLITUDE (dB of Full-Scale) DNL (LSB) COUNTS 07351-009 07351-008 07351-010 Data Sheet AD7949 90 90 85 85 80 80 75 75 70 70 VDD = V = 5V, –0.5dB VDD = V = 5V, –0.5dB REF REF VDD = V = 5V, –10dB VDD = V = 5V, –10dB REF REF VDD = V = 2.5V, –0.5dB VDD = V = 2.5V, –0.5dB 65 65 REF REF VDD = V = 2.5V, –10dB VDD = V = 2.5V, –10dB REF REF 60 60 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. SNR vs. Frequency Figure 14. SINAD vs. Frequency 88 15.5 130 –60 SNR 125 –65 SINAD ENOB 120 –70 86 15.0 115 –75 110 –80 SFDR 84 14.5 105 –85 100 –90 95 –95 82 14.0 THD 90 –100 85 –105 80 13.5 80 –110 75 –115 78 13.0 70 –120 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. SFDR and THD vs. Reference Voltage 90 –90 f = 20kHz f = 20kHz IN IN VDD = V = 5V REF 85 –95 VDD = V = 2.5V REF VDD = V = 5V REF 80 VDD = V = 2.5V REF –100 75 70 –105 65 60 –110 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature Rev. D | Page 11 of 32 SNR, SINAD (dB) SNR (dB) SNR (dB) ENOB (Bits) 07351-013 07351-011 07351-012 SFDR (dB) THD (dB) SINAD (dB) THD (dB) 07351-014 07351-016 07351-015 AD7949 Data Sheet –60 2750 100 2.5V INTERNAL REF f = 200kSPS S 4.096V INTERNAL REF 2500 90 –70 INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF 2250 80 EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF –80 VIO 2000 70 –90 1750 60 1500 50 –100 1250 40 VDD = V = 5V, –0.5dB REF VDD = V = 2.5V, –0.5dB –110 REF VDD = V = 2.5V, –10dB REF 1000 30 VDD = V = 5V, –10dB REF –120 750 20 0 50 100 150 200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) VDD SUPPLY (V) Figure 17. THD vs. Frequency Figure 20. Operating Currents vs. Supply 90 3000 180 f = 20kHz IN f = 200kSPS 89 S 2750 160 88 87 2500 140 VDD = V = 5V 86 VDD = 5V, INTERNAL 4.096V REF REF 2250 120 85 84 2000 100 VDD = V = 2.5V REF VDD = 5V, EXTERNAL REF 83 1750 80 82 81 1500 VIO 60 VDD = 2.5, EXTERNAL REF 80 1250 40 79 1000 20 78 –10 –8 –6 –4 –2 0 –55 –35 –15 5 25 45 65 85 105 125 INPUT LEVEL (dB) TEMPERATURE (°C) Figure 18. SNR vs. Input Level Figure 21. Operating Currents vs. Temperature 25 2 20 VDD = 2.5V, 85°C 1 15 VDD = 2.5V, 25°C 0 10 VDD = 5V, 85°C –1 UNIPOLAR ZERO VDD = 5V, 25°C 5 UNIPOLAR GAIN VDD = 3.3V, 85°C BIPOLAR ZERO BIPOLAR GAIN VDD = 3.3V, 25°C –2 0 –55 –35 –15 5 25 45 65 85 105 125 0 2040 6080 100 120 TEMPERATURE (°C) SDO CAPACITIVE LOAD (pF) Figure 19. Offset and Gain Errors vs. Temperature Figure 22. t Delay vs. SDO Capacitance Load and Supply DSDO Rev. D | Page 12 of 32 THD (dB) SNR (dB) OFFSET ERROR AND GAIN ERROR (LSB) 07351-019 07351-018 07351-017 VDD CURRENT (µA) VDD CURRENT (µA) t DELAY (ns) DSDO VIO CURRENT (µA) 07351-022 07351-021 VIO CURRENT (µA) 07351-020 Data Sheet AD7949 TERMINOLOGY Signal-to-Noise Ratio (SNR) Least Significant Bit (LSB) SNR is the ratio of the rms value of the actual input signal to the The LSB is the smallest increment that can be represented by a rms sum of all other spectral components below the Nyquist converter. For an analog-to-digital converter with N bits of frequency, excluding harmonics and dc. The value for SNR is resolution, the LSB expressed in volts is expressed in decibels. V REF LSB (V)= Signal-to-(Noise + Distortion) Ratio (SINAD) N 2 SINAD is the ratio of the rms value of the actual input signal to Integral Nonlinearity Error (INL) the rms sum of all other spectral components below the Nyquist INL refers to the deviation of each individual code from a line frequency, including harmonics but excluding dc. The value for drawn from negative full scale through positive full scale. The SINAD is expressed in decibels. point used as negative full scale occurs ½ LSB before the first Total Harmonic Distortion (THD) code transition. Positive full scale is defined as a level 1½ LSB THD is the ratio of the rms sum of the first five harmonic beyond the last code transition. The deviation is measured from components to the rms value of a full-scale input signal and is the middle of each code to the true straight line (see Figure 24). expressed in decibels. Differential Nonlinearity Error (DNL) Spurious-Free Dynamic Range (SFDR) In an ideal ADC, code transitions are 1 LSB apart. DNL is the SFDR is the difference, in decibels, between the rms amplitude maximum deviation from this ideal value. It is often specified in of the input signal and the peak spurious signal. terms of resolution for which no missing codes are guaranteed. Effective Number of Bits (ENOB) Offset Error ENOB is a measurement of the resolution with a sine wave The first transition should occur at a level ½ LSB above analog input. It is related to SINAD by the formula ground. The offset error is the deviation of the actual transition ENOB = (SINAD − 1.76)/6.02 from that point. dB and is expressed in bits. Gain Error The last transition (from 111 … 10 to 111 … 11) should occur Channel-to-Channel Crosstalk for an analog voltage 1½ LSB below the nominal full scale. The Channel-to-channel crosstalk is a measure of the level of crosstalk gain error is the deviation in LSB (or percentage of full-scale between any two adjacent channels. It is measured by applying a range) of the actual level of the last transition from the ideal dc to the channel under test and applying a full-scale, 100 kHz level after the offset error is adjusted out. Closely related is the sine wave signal to the adjacent channel(s). The crosstalk is the full-scale error (also in LSB or percentage of full-scale range), amount of signal that leaks into the test channel and is expressed which includes the effects of the offset error. in decibels. Aperture Delay Reference Voltage Temperature Coefficient Aperture delay is the measure of the acquisition performance. It Reference voltage temperature coefficient is derived from the is the time between the rising edge of the CNV input and the typical shift of output voltage at 25°C on a sample of parts at the point at which the input signal is held for a conversion. maximum and minimum reference output voltage (VREF) measured Transient Response at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as Transient response is the time required for the ADC to accurately V (Max) –V (Min) REF REF 6 TCV (ppm/°C)= ×10 acquire its input after a full-scale step function is applied. REF V (25°C)× (T –T ) REF MAX MIN Dynamic Range where: Dynamic range is the ratio of the rms value of the full scale to V (Max) = maximum V at T , T (25°C), or T . REF REF MIN MAX the total rms noise measured with the inputs shorted together. V (Min) = minimum V at T , T (25°C), or T . REF REF MIN MAX The value for dynamic range is expressed in decibels. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C. Rev. D | Page 13 of 32 AD7949 Data Sheet THEORY OF OPERATION INx+ SWITCHES CONTROL MSB LSB SW+ 8,192C 4,096C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 8,192C 4,096C 4C 2C C C MSB LSB SW– CNV INx– OR COM Figure 23. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7949 is an 8-channel, 14-bit, charge redistribution The AD7949 is a successive approximation ADC based on a successive approximation register (SAR) analog-to-digital charge redistribution DAC. Figure 23 shows the simplified converter (ADC). The AD7949 is capable of converting 250,000 schematic of the ADC. The capacitive DAC consists of two samples per second (250 kSPS) and powers down between identical arrays of 14 binary-weighted capacitors, which are conversions. For example, when operating with an external connected to the two comparator inputs. reference at 1 kSPS, it consumes 15 µW typically, ideal for During the acquisition phase, terminals of the array tied to the battery-powered applications. comparator input are connected to GND via SW+ and SW−. The AD7949 contains all of the components for use in a All independent switches are connected to the analog inputs. multichannel, low power data acquisition system, including Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) • 14-bit SAR ADC with no missing codes inputs. When the acquisition phase is complete and the CNV • 8-channel, low crosstalk multiplexer input goes high, a conversion phase is initiated. When the • Internal low drift reference and buffer conversion phase begins, SW+ and SW− are opened first. The • Temperature sensor two capacitor arrays are then disconnected from the inputs and • Selectable one-pole filter connected to the GND input. Therefore, the differential voltage • Channel sequencer between the INx+ and INx− (or COM) inputs captured at the These components are configured through an SPI-compatible, end of the acquisition phase is applied to the comparator inputs, 14-bit register. Conversion results, also SPI compatible, can be causing the comparator to become unbalanced. By switching read after or during conversions with the option for reading each element of the capacitor array between GND and REF, the back the configuration associated with the conversion. comparator input varies by binary-weighted voltage steps (V /2, V /4, ... V /8,192). The control logic toggles these REF REF REF The AD7949 provides the user with an on-chip track-and-hold switches, starting with the MSB, to bring the comparator back and does not exhibit pipeline delay or latency. into a balanced condition. After the completion of this process, The AD7949 is specified from 2.3 V to 5.5 V and can be the part returns to the acquisition phase, and the control logic interfaced to any 1.8 V to 5 V digital logic family. The part is generates the ADC output code and a busy signal indicator. housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space Because the AD7949 has an on-board conversion clock, the savings and allows flexible configurations. It is pin-for-pin serial clock, SCK, is not required for the conversion process. compatible with the 16-bit AD7682, AD7689, and AD7699. Rev. D | Page 14 of 32 07351-023 Data Sheet AD7949 TRANSFER FUNCTIONS TWOS STRAIGHT COMPLEMENT BINARY With the inputs configured for unipolar range (single-ended, 011...111 111...111 COM with ground sense, or paired differentially with INx− as 011...110 111...110 ground sense), the data output is straight binary. 011...101 111...101 With the inputs configured for bipolar range (COM = V /2 or REF paired differentially with INx− = V /2), the data outputs are REF twos complement. The ideal transfer characteristic for the AD7949 is shown in Figure 24 and for both unipolar and bipolar ranges with the 100...010 000...010 internal 4.096 V reference. 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT Figure 24. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages 1 2 Unipolar Analog Input Digital Output Code Bipolar Analog Input Digital Output Code Description V = 4.096 V (Straight Binary Hex) V = 4.096 V (Twos Complement Hex) REF REF 3 3 FSR − 1 LSB 4.095750 V 0x3FFF 2.047750 V 0x1FFF Midscale + 1 LSB 2.048250 V 0x2001 250 μV 0x0001 Midscale 2.048000 V 0x2000 0 V 0x0000 Midscale − 1 LSB 2.047750 V 0x1FFF −250 μV 0x3FFF −FSR + 1 LSB 250 μV 0x0001 −2.047750 V 0x2001 4 4 −FSR 0 V 0x0000 −2.048 V 0x2000 1 With COM or INx− = 0 V or all INx referenced to GND. 2 With COM or INx− = V /2. REF 3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − GND). 4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND). Rev. D | Page 15 of 32 ADC CODE 07351-024 AD7949 Data Sheet TYPICAL CONNECTION DIAGRAMS 5V 1.8V TO VDD 100nF 2 100nF 100nF 10µF V+ REFIN VDD REF VIO 0V TO V REF 3 ADA4841-x IN0 V– V+ DIN MOSI IN[7:1] SCK SCK AD7949 SDO MISO 0V TO V REF SS CNV 3 ADA4841-x V– 0V OR COM V /2 REF GND NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 25. Typical Application Diagram with Multiple Supplies +5V 1.8V TO VDD 100nF 2 10µF 100nF 100nF V+ REF REFIN VDD VIO 3 ADA4841-x V– IN0 DIN MOSI IN[7:1] SCK SCK V+ AD7949 MISO SDO 3 ADA4841-x V– SS CNV V p-p REF COM GND V /2 REF NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 26. Typical Application Diagram Using Bipolar Input Rev. D | Page 16 of 32 07351-025 07351-026 Data Sheet AD7949 70 Unipolar or Bipolar 65 Figure 25 shows an example of the recommended connection diagram for the AD7949 when multiple supplies are available. 60 Bipolar Single Supply 55 Figure 26 shows an example of a system with a bipolar input 50 using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the 45 amplifier/signal conditioning circuit is remotely located with 40 some common mode present. Note that for any input config- uration, the INx inputs are unipolar and are always referenced 35 to GND (no negative voltages even in bipolar range). 30 10 1k 10k 1 100 For this circuit, a rail-to-rail input/output amplifier can be used; FREQUENCY (kHz) however, the offset voltage vs. input common-mode range should Figure 28. Analog Input CMRR vs. Frequency be noted and taken into consideration (1 LSB = 250 μV with During the acquisition phase, the impedance of the analog inputs VREF = 4.096 V). Note that the conversion results are in twos can be modeled as a parallel combination of the capacitor, CPIN, complement format when using the bipolar input configuration. and the network formed by the series connection of RIN and CIN. Refer to the AN-581 Application Note, Biasing and Decoupling C is primarily the pin capacitance. R is typically 2.4 kΩ and PIN IN Op Amps in Single Supply Applications, at www.analog.com for is a lumped component composed of serial resistors and the on additional details about using single-supply amplifiers. resistance of the switches. C is typically 27 pF and is mainly IN ANALOG INPUTS the ADC sampling capacitor. Input Structure Selectable Low-Pass Filter Figure 27 shows an equivalent circuit of the input structure of During the conversion phase, where the switches are opened, the AD7949. The two diodes, D1 and D2, provide ESD protec- the input impedance is limited to C . While the AD7949 is PIN tion for the analog inputs, IN[7:0] and COM. Care must be acquiring, R and C make a one-pole, low-pass filter that IN IN taken to ensure that the analog input signal does not exceed the reduces undesirable aliasing effects and limits the noise from supply rails by more than 0.3 V because this causes the diodes the driving circuitry. The low-pass filter can be programmed for to become forward biased and to start conducting current. the full bandwidth or ¼ of the bandwidth with CFG[6], as These diodes can handle a forward-biased current of 130 mA shown in Table 9. This setting changes RIN to 19 kΩ. Note that the maximum. For instance, these conditions may eventually occur converter throughput must also be reduced by ¼ when using the when the input buffer supplies are different from VDD. In such filter. If the maximum throughput is used with the bandwidth a case, for example, an input buffer with a short circuit, the (BW) set to ¼, the converter acquisition time, t , is violated, ACQ current limitation can be used to protect the part. resulting in increased THD. VDD D1 INx+ C IN R IN OR INx– OR COM C PIN D2 GND Figure 27. Equivalent Analog Input Circuit This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or V ± 0.1 V). By using these REF differential inputs, signals common to both inputs are rejected, as shown in Figure 28. Rev. D | Page 17 of 32 07351-027 CMRR (dB) 07351-028 AD7949 Data Sheet Input Configurations CH0+ IN0 CH0+ IN0 Figure 29 shows the different methods for configuring the analog CH1+ IN1 CH1+ IN1 inputs with the configuration register, CFG[12:10]. Refer to the CH2+ IN2 CH2+ IN2 Configuration Register, CFG, section for more details. CH3+ IN3 CH3+ IN3 CH4+ IN4 CH4+ IN4 The analog inputs can be configured as CH5+ CH5+ IN5 IN5 • Figure 29A, single-ended referenced to system ground; CH6+ CH6+ IN6 IN6 CFG[12:10] = 111 . 2 CH7+ CH7+ IN7 IN7 In this configuration, all inputs (IN[7:0]) have a range of COM– COM COM GND to V . REF GND GND • Figure 29B, bipolar differential with a common reference B—8 CHANNELS, A—8 CHANNELS, point; COM = V /2; CFG[12:10] = 010 . REF 2 SINGLE ENDED COMMON REFERNCE Unipolar differential with COM connected to a ground sense; CFG[12:10] = 1102. CH0+ (–) IN0 CH0+ (–) IN0 In these configurations, all inputs IN[7:0] have a range of CH0– (+) IN1 CH0– (+) IN1 GND to VREF. CH1+ (–) CH1+ (–) IN2 IN2 • Figure 29C, bipolar differential pairs with the negative CH1– (+) CH1– (+) IN3 IN3 input channel referenced to V /2; CFG[12:10] = 00X . REF 2 CH2+ (–) IN4 CH2+ IN4 Unipolar differential pairs with the negative input channel CH2– (+) IN5 CH3+ IN5 referenced to a ground sense; CFG[12:10] = 10X . 2 CH3+ (–) IN6 CH4+ IN6 In these configurations, the positive input channels have CH3– (+) IN7 CH5+ IN7 the range of GND to VREF. The negative input channels are COM COM– COM senses referred to VREF/2 for bipolar pairs, or GND for GND GND unipolar pairs. The positive channel is configured with CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 C—4 CHANNELS, D—COMBINATION DIFFERENTIAL are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 Figure 29. Multiplexed Analog Input Configurations are used (channels with parentheses). For example, for IN0/IN1 pairs with the positive channel on IN0, CFG[9:7] Sequencer = 000 . For IN4/IN5 pairs with the positive channel on 2 The AD7949 includes a channel sequencer useful for scanning IN5, CFG[9:7] = 1012. channels in a repeated fashion. Refer to the Channel Sequencer Note that for the sequencer, detailed in the Channel section for further details of the sequencer operation. Sequencer section, the positive channels are always IN0, Source Resistance IN2, IN4, and IN6. When the source impedance of the driving circuit is low, the • Figure 29D, inputs configured in any of the preceding AD7949 can be driven directly. Large source impedances combinations (showing that the AD7949 can be configured significantly affect the ac performance, especially THD. The dc dynamically). performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. D | Page 18 of 32 07351-029 Data Sheet AD7949 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE OUTPUT/INPUT Although the AD7949 is easy to drive, the driver amplifier must The AD7949 allows the choice of a very low temperature drift meet the following requirements: internal voltage reference, an external reference, or an external buffered reference.  The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise The internal reference of the AD7949 provides excellent performance of the AD7949. Note that the AD7949 has a performance and can be used in almost all applications. There noise much lower than most of the other 14-bit ADCs and, are six possible choices of voltage reference schemes briefly therefore, can be driven by a noisier amplifier to meet a described in Table 9, with more details in each of the following given system noise specification. The noise from the sections. amplifier is filtered by the AD7949 analog input circuit Internal Reference/Temperature Sensor low-pass filter made by RIN and CIN or by an external filter, The precision internal reference, suitable for most applications, if one is used. can be set for either a 2.5 V or a 4.096 V output, as detailed in  For ac applications, the driver should have a THD perfor- Table 9. With the internal reference enabled, the band gap mance commensurate with the AD7949. Figure 17 shows voltage is also present on the REFIN pin, which requires an THD vs. frequency for the AD7949. external 0.1 μF capacitor. Because the current output of REFIN  For multichannel, multiplexed applications on each input is limited, it can be used as a source if followed by a suitable or input pair, the driver amplifier and the AD7949 analog buffer, such as the AD8605. Note that the voltage of REFIN input circuit must settle a full-scale step onto the capacitor changes depending on the 2.5 V or 4.096 V internal reference. array at a 14-bit level (0.0015%). In amplifier data sheets, Enabling the reference also enables the internal temperature settling at 0.1% to 0.01% is more commonly specified. This sensor, which measures the internal temperature of the AD7949 may differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. and is thus useful for performing a system calibration. For applications requiring the use of the temperature sensor, the Table 8. Recommended Driver Amplifiers internal reference must be active (internal buffer can be Amplifier Typical Application disabled in this case). Note that, when using the temperature ADA4841-x Very low noise, small, and low power sensor, the output is straight binary referenced from the AD8655 5 V single supply, low noise AD7949 GND pin. AD8021 Very low noise and high frequency The internal reference is temperature-compensated to within AD8022 Low noise and high frequency 10 mV. The reference is trimmed to provide a typical drift of OP184 Low power, low noise, and low frequency ±10 ppm/°C. AD8605, AD8615 5 V single supply, low power Connect the AD7949 as shown in Figure 30 for either a 2.5 V or 4.096 V internal reference. 10µF 100nF REF REFIN AD7949 TEMP GND Figure 30. 2.5 V or 4.096 V Internal Reference Connection Rev. D | Page 19 of 32 07351-030 AD7949 Data Sheet External Reference and Internal Buffer Reference Decoupling For improved drift performance, an external reference can be Whether using an internal or external reference, the AD7949 used with the internal buffer, as shown in Figure 31. The voltage reference output/input, REF, has a dynamic input external source is connected to REFIN, the input to the on-chip impedance and should therefore be driven by a low impedance unity gain buffer, and the output is produced on the REF pin. source with efficient decoupling between the REF and GND An external reference can be used with the internal buffer with pins. This decoupling depends on the choice of the voltage or without the temperature sensor enabled. Refer to Table 9 for reference but usually consists of a low ESR capacitor connected register details. With the buffer enabled, the gain is unity and is to REF and GND with minimum parasitic inductance. A 10 μF limited to an input/output of VDD = −0.2 V; however, the (X5R, 1206 size) ceramic chip capacitor is appropriate when maximum voltage allowable must be ≤(VDD − 0.5 V). using the internal reference, the ADR43x/ADR44x external reference, or a low impedance buffer such as the AD8031 or The internal reference buffer is useful in multiconverter appli- the AD8605. cations because a buffer is typically required in these applications. In addition, a low power reference can be used because the The placement of the reference decoupling capacitor is also impor- internal buffer provides the necessary performance to drive the tant to the performance of the AD7949, as explained in the SAR architecture of the AD7949. Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND REF SOURCE ≤ (VDD – 0.5V) should also be connected to the reference decoupling capacitor 10µF 100nF with the shortest distance and to the analog ground plane with several vias. REF REFIN If desired, smaller reference decoupling capacitor values down AD7949 to 2.2 μF can be used with minimal impact on performance, TEMP especially on DNL. GND Regardless, there is no need for an additional lower value ceramic Figure 31. External Reference Using Internal Buffer decoupling capacitor (for example, 100 nF) between the REF External Reference and GND pins. In any of the six voltage reference schemes, an external reference For applications that use multiple AD7949 devices or other can be connected directly on the REF pin as shown in Figure 32 PulSAR devices, it is more effective to use the internal reference because the output impedance of REF is >5 kΩ. To reduce power buffer to buffer the external reference voltage, thus reducing consumption, the reference and buffer should be powered down. SAR conversion crosstalk. When using only the external reference (and optional reference The voltage reference temperature coefficient (TC) directly buffer as shown in Figure 35), the internal buffer is disabled. impacts full scale; therefore, in applications where full-scale Refer to Table 9 for register details. For improved drift perfor- accuracy matters, care must be taken with the TC. For instance, mance, an external reference such as the ADR43x or ADR44x is a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. recommended. REF SOURCE 0.5V < REF < (VDD + 0.3V) 10µF NO CONNECTION REQUIRED REF REFIN AD7949 TEMP GND Figure 32. External Reference Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows: 4.096 SNR  20 log LOSS 5 Rev. D | Page 20 of 32 07351-031 07351-032 Data Sheet AD7949 POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7949 uses two power supply pins: an analog and digital For simplified applications, the AD7949, with its low operating core supply (VDD) and a digital input/output interface supply current, can be supplied directly using an external reference (VIO). VIO allows direct interface with any logic between 1.8 V circuit like the one shown in Figure 35. The reference line can and VDD. To reduce the supplies needed, the VIO and VDD be driven by: pins can be tied together. The AD7949 is independent of power  The system power supply directly supply sequencing between VIO and VDD. Additionally, it is  A reference voltage with enough current output capability, very insensitive to power supply variations over a wide such as the ADR43x or ADR44x frequency range, as shown in Figure 33.  A reference buffer, such as the AD8605, which can also 75 filter the system power supply, as shown in Figure 35 70 65 5V 5V 60 10Ω 5V 10kΩ 55 1µF 0.1µF 10µF 0.1µF AD8605 1µF 50 1 45 REF VDD VIO 40 AD7949 35 30 1 OPTIONAL REFERENCE BUFFER AND FILTER. 1 10 100 1k 10k FREQUENCY (kHz) Figure 35. Example of an Application Circuit Figure 33. PSRR vs. Frequency The AD7949 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low battery- powered applications. 10,000 1000 VDD = 5V, INTERNAL REF 100 VDD = 5V, EXTERNAL REF 10 VDD = 2.5V, EXTERNAL REF 1 VIO 0.1 0.010 0.001 10 100 1k 10k 100k 1M SAMPLING RATE (SPS) Figure 34. Operating Currents vs. Sampling Rate Rev. D | Page 21 of 32 OPERATING CURRENT (µA) PSSR (dB) 07351-033 07351-034 07351-035 AD7949 Data Sheet DIGITAL INTERFACE The AD7949 uses a simple 4-wire interface and is compatible READING/WRITING DURING CONVERSION, FAST with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for HOSTS example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and When reading/writing during conversion (n), conversion ADSP-218x. results are for the previous (n − 1) conversion, and writing the The interface uses the CNV, DIN, SCK, and SDO signals and CFG register is for the next (n + 1) acquisition and conversion. allows CNV, which initiates the conversion, to be independent After the CNV is brought high to initiate conversion, it must be of the readback timing. This is useful in low jitter sampling or brought low again to allow reading/writing during conversion. simultaneous sampling applications. Reading/writing should only occur up to t and, because this DATA A 14-bit register, CFG[13:0], is used to configure the ADC for time is limited, the host must use a fast SCK. the channel to be converted, the reference selection, and other The SCK frequency required is calculated by components, which are detailed in the Configuration Register, Number _ SCK _ Edges CFG, section. f ≥ SCK t DATA When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conver- The time between tDATA and tCONV is a safe time when digital sion), as detailed in the following sections. The CFG word is activity should not occur, or sensitive bit decisions may be updated on the first 14 SCK rising edges, and conversion results corrupted. are output on the first 13 (or 14 if busy mode is selected) SCK READING/WRITING AFTER CONVERSION, ANY falling edges. If the CFG readback is enabled, an additional SPEED HOSTS 14 SCK falling edges are required to output the CFG word When reading/writing after conversion, or during acquisition associated with the conversion results with the CFG MSB (n), conversion results are for the previous (n − 1) conversion, following the LSB of the conversion result. and writing is for the (n + 1) acquisition. A discontinuous SCK is recommended because the part is For the maximum throughput, the only time restriction is that selected with CNV low, and SCK activity begins to write a new the reading/writing take place during the tACQ (minimum) time. configuration word and clock out data. For slow throughputs, the time restriction is dictated by the Note that in the following sections, the timing diagrams indicate throughput required by the user, and the host is free to run at digital activity (SCK, CNV, DIN, SDO) during the conversion. any speed. Thus for slow hosts, data access must take place However, due to the possibility of performance degradation, during the acquisition phase. digital activity should occur only prior to the safe data reading/ writing time, t , because the AD7949 provides error correc- DATA tion circuitry that can correct for an incorrect bit during this time. From t to t , there is no error correction and conver- DATA CONV sion results may be corrupted. The user should configure the AD7949 and initiate the busy indicator (if desired) prior to tDATA. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation. Rev. D | Page 22 of 32 Data Sheet AD7949 Note that data access spanning conversion requires the CNV to READING/WRITING SPANNING CONVERSION, ANY be driven high to initiate a new conversion, and data access is SPEED HOST not allowed when CNV is high. Thus, the host must perform When reading/writing spanning conversion, the data access starts two bursts of data access when using this method. at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and CONFIGURATION REGISTER, CFG writing the CFG register is for the next (n + 1) acquisition and The AD7949 uses a 14-bit configuration register (CFG[13:0]), conversion. as detailed in Table 9, to configure the inputs, the channel to be Similar to reading/writing during conversion, reading/writing converted, the one-pole filter bandwidth, the reference, and the should only occur up to t . For the maximum throughput, channel sequencer. The CFG register is latched (MSB first) on DATA the only time restriction is that reading/writing take place DIN with 14 SCK rising edges. The CFG update is edge depen- dent, allowing for asynchronous or synchronous hosts. during the tACQ + tDATA time. For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion. Rev. D | Page 23 of 32 AD7949 Data Sheet The register can be written to during conversion, during acquisi- • IN[7:0] unipolar referenced to GND, sequenced in order tion, or spanning acquisition/conversion, and is updated at the end • Full bandwidth for a one-pole filter of conversion, t (maximum). There is always a one deep CONV • Internal reference/temperature sensor disabled, buffer delay when writing the CFG register. Note that, at power-up, the enabled CFG register is undefined and two dummy conversions are • Enables the internal sequencer required to update the register. To preload the CFG register with a • No readback of the CFG register factory setting, hold DIN high for two conversions. Thus Table 9 summarizes the configuration register bit details. See CFG[13:0] = 0x3FFF. This sets the AD7949 for the following: the Theory of Operation section for more details. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG INCC INCC INCC INx INx INx BW REF REF REF SEQ SEQ RB Table 9. Configuration Register Description Bit(s) Name Description [13] CFG Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register. [12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function 1 0 0 X Bipolar differential pairs; INx− referenced to V /2 ± 0.1 V. REF 0 1 0 Bipolar; INx referenced to COM = V /2 ± 0.1 V. REF 0 1 1 Temperature sensor. 1 1 0 X Unipolar differential pairs; INx− referenced to GND ± 0.1 V. 1 1 0 Unipolar, INx referenced to COM = GND ± 0.1 V. 1 1 1 Unipolar, INx referenced to GND. [9:7] INx Input channel selection in binary fashion. Bit 9 Bit 8 Bit 7 Channel 0 0 0 IN0 0 0 1 IN1 … … … 1 1 1 IN7 [6] BW Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼. 1 = full BW. [5:3] REF Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section. Bit 5 Bit 4 Bit 3 Function 0 0 0 Internal reference, REF = 2.5 V output, temperature enabled. 0 0 1 Internal reference, REF = 4.096 V output, temperature enabled. 0 1 0 External reference, temperature enabled. 0 1 1 External reference, internal buffer, temperature enabled. 1 1 0 External reference, temperature disabled. 1 1 1 External reference, internal buffer, temperature disabled. [2:1] SEQ Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section. Bit 2 Bit 1 Function 0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature. 1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]). [0] RB Read back the CFG register. 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. 1 X = don’t care. Rev. D | Page 24 of 32 Data Sheet AD7949 When CNV is brought low after EOC, SDO is driven from high GENERAL TIMING WITHOUT A BUSY INDICATOR impedance to the MSB. Falling SCK edges clock out bits starting Figure 36 details the timing for all three modes: read/write with MSB − 1. during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating The SCK can idle high or low depending on the clock polarity item for both CFG and data readback is at the end of conversion (CPOL) and clock phase (CPHA) settings if SPI is used. A simple (EOC). At EOC, if CNV is high, the busy indicator is disabled. solution is to use CPOL = CPHA = 0 as shown in Figure 36 with SCK idling low. As detailed previously in the Digital Interface section, the data From power-up, in any read/write mode, the first three conver- access should occur up to safe data reading/writing time, tDATA. sion results are undefined because a valid CFG does not take If the full CFG word was not written to prior to EOC, it is dis- nd place until the 2 EOC; thus two dummy conversions are carded and the current configuration remains. If the conversion required. Also, if the state machine writes the CFG during the result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For power-up state (RDC shown), the CFG register needs to be detailed timing, refer to Figure 39 and Figure 40, which depict rewritten again at the next phase. Note that the first valid data reading/writing spanning conversion with all timing details, occurs in Phase (n + 1) when the CFG register is written during including setup, hold, and SCK. Phase (n − 1). SOC t CYC EOC EOC EOC EOC POWER t t CONV DATA UP CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n – 1) UNDEFINED (n) (n) (n + 1) (n + 1) (n + 2) NOTE 1 CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) RDC MSB MSB DATA (n – 3) DATA (n – 2) MSB DATA (n – 1) DATA (n) SDO (n) XXX XXX XXX XXX XXX 1 1 1 1 SCK 14 14 14 14 NOTE 2 NOTE 1 CNV CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) DIN RAC DATA (n – 2) DATA (n – 1) SDO DATA (n) DATA (n + 1) XXX XXX 1 14 1 14 1 14 1 SCK NOTE 2 NOTE 1 CNV CFG (n + 3) CFG (n) CFG (n) CFG (n + 1) CFG (n + 1) CFG (n + 2) CFG (n + 2) DIN RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) DATA (n + 1) SDO XXX XXX XXX XXX 1 1 1n n + 1 nnn n + 1 n + 1 14 1 14 14 SCK NOTE 2 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. 3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED. Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator Rev. D | Page 25 of 32 07351-036 AD7949 Data Sheet generation requires either a high impedance or a remaining bit GENERAL TIMING WITH A BUSY INDICATOR high-to-low transition. Because most SPI hosts are usually Figure 37 details the timing for all three modes: read/write limited to 8-bit or 16-bit bursts, this should not be an issue. during conversion (RDC), read/write after conversion (RAC), Additional clocks are not a concern because SDO remains high and read/write spanning conversion (RSC). Note that the gating th impedance after the 15 falling edge. item for both CFG and data readback is at the end of conversion (EOC). As detailed previously, the data access should occur up The SCK can idle high or low depending on the CPOL and to safe data reading/writing time, t . If the full CFG word is CPHA settings if SPI is used. A simple solution is to use CPOL DATA = CPHA = 1 (not shown) with SCK idling high. not written to prior to EOC, it is discarded and the current configuration remains. From power-up, in any read/write mode, the first three conver- sion results are undefined because a valid CFG does not take At the EOC, if CNV is low, the busy indicator is enabled. In nd place until the 2 EOC; thus, two dummy conversions are addition, to generate the busy indicator properly, the host must assert a minimum of 15 SCK falling edges to return SDO to required. Also, if the state machine writes the CFG during the high impedance because the last bit on SDO remains active. power-up state (RDC shown), the CFG register needs to be Unlike the case detailed in the General Timing Without a Busy rewritten again at the next phase. Note that the first valid data Indicator section, if the conversion result is not read out fully occurs in Phase (n + 1) when the CFG register is written during Phase (n − 1). prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy START OF CONVERSION (SOC) t CYC EOC EOC EOC POWER EOC t t UP CONV DATA CONVERSION CONVERSION CONVERSION CONVERSION ACQUISITION ACQUISITION ACQUISITION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n – 1) UNDEFINED (n) (n) (n + 1) (n + 1) (n + 2) NOTE 1 CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) RDC DATA (n – 3) DATA (n – 2) DATA (n – 1) SDO DATA (n) XXX XXX XXX SCK 1 15 1 15 1 15 1 15 NOTE 2 CNV NOTE 1 DIN CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) RAC DATA (n – 2) DATA (n – 1) SDO DATA (n) DATA (n + 1) XXX XXX 1 1 15 1 15 15 1 SCK NOTE 2 NOTE 1 CNV CFG (n + 2) DIN CFG (n) CFG (n + 1) CFG (n + 3) RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) DATA (n + 1) SDO XXX XXX XXX XXX 1 1n n + 1 15 1 n n + 1 15 1 n n + 1 15 SCK NOTE 2 NOTES 1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR. 2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 37. General Interface Timing for the AD7949 With a Busy Indicator Rev. D | Page 26 of 32 07351-037 Data Sheet AD7949 Busy Indicator section for more details. The sequencer can also CHANNEL SEQUENCER be used with the busy indicator and details for these timings can The AD7949 includes a channel sequencer useful for scanning be found in the General Timing with a Busy Indicator section channels in a repeated fashion. Channels are scanned as singles and the Read/Write Spanning Conversion with a Busy Indicator or pairs, with or without the temperature sensor, after the last section. channel is sequenced. For sequencer operation, the CFG register should be set during The sequencer starts with IN0 and finishes with IN[7:0] set in the (n − 1) phase after power-up. On phase (n), the sequencer CFG[9:7]. For paired channels, the channels are paired depend- setting takes place and acquires IN0. The first valid conversion ing on the last channel set in CFG[9:7]. Note that in sequencer result is available at phase (n + 1). After the last channel set in mode, the channels are always paired with the positive input on CFG[9:7] is converted, the internal temperature sensor data is the even channels (IN0, IN2, IN4, IN6), and with the negative output (if enabled), followed by acquisition of IN0. input on the odd channels (IN1, IN3, IN5, IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive Examples inputs dedicated to IN0, IN2, IN4, and IN6. With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in CFG[2:1] are used to enable the sequencer. After the CFG the following order: register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again. IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, … Note that while operating in a sequence, some bits of the CFG For paired channels with the internal temperature sensor register can be changed. However, if changing CFG[11] (paired enabled, the sequencer scans in the following order: or single channel) or CFG[9:7] (last channel in sequence), the IN0, IN2, IN4, IN6, TEMP, IN0, … sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after Note that IN1, IN3, IN5, and IN7 are referenced to a GND the CFG register is updated. sense or VREF/2, as detailed in the Input Configurations section. Figure 38 details the timing for all three modes without a busy indicator. Refer to the General Timing Without a Busy Indicator section and the Read/Write Spanning Conversion Without a SOC t CYC EOC EOC EOC EOC POWER t t CONV DATA UP CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n), IN0 (n + 1), IN1 (n – 1) UNDEFINED (n), IN0 (n + 1), IN1 (n + 2), IN2 NOTE 1 CNV DIN XXX CFG (n) RDC MSB DATA (n – 3) DATA (n – 2) MSB DATA (n – 1) MSB SDO DATA IN0 XXX XXX XXX XXX XXX IN0 1 1 1 1 SCK 14 14 14 14 NOTE 2 NOTE 1 CNV DIN CFG (n) RAC DATA (n – 2) DATA (n – 1) SDO DATA IN0 DATA IN1 XXX XXX 14 1 1 14 1 14 1 SCK NOTE 2 NOTE 1 CNV CFG (n) CFG (n) DIN RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA IN0 DATA IN0 DATA IN1 SDO XXX XXX XXX XXX 1 1 11nn n + 14 1 n + 114 n n + 114 n SCK NOTE 2 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 38. General Channel Sequencer Timing Without a Busy Indicator Rev. D | Page 27 of 32 07351-038 AD7949 Data Sheet After the conversion is complete, the AD7949 enters the READ/WRITE SPANNING CONVERSION WITHOUT acquisition phase and power-down. When the host brings CNV A BUSY INDICATOR low after t (maximum), the MSB is enabled on SDO. The CONV This mode is used when the AD7949 is connected to any host host also must enable the MSB of the CFG register at this time using an SPI, serial port, or FPGA. The connection diagram is (if necessary) to begin the CFG update. While CNV is low, both shown in Figure 39, and the corresponding timing is given in a CFG update and a data readback take place. The first 14 SCK Figure 40. For the SPI, the host should use CPHA = CPOL = 0. rising edges are used to update the CFG, and the first 13 SCK Reading/writing spanning conversion is shown, which covers falling edges clock out the conversion results starting with all three modes detailed in the Digital Interface section. For this MSB − 1. The restriction for both configuring and reading is mode, the host must generate the data transfer based on the that they both must occur before the t time of the next conver- DATA conversion time. For an interrupt driven transfer that uses a sion elapses. All 14 bits of CFG[13:0] must be written, or they busy indicator, refer to the Read/Write Spanning Conversion are ignored. In addition, if the 14-bit conversion result is not with a Busy Indicator section. read back before tDATA elapses, it is lost. A rising edge on CNV initiates a conversion, forces SDO to The SDO data is valid on both SCK edges. Although the rising high impedance, and ignores data present on DIN. After a edge can be used to capture the data, a digital host using the conversion is initiated, it continues until completion irrespec- SCK falling edge allows a faster reading rate, provided it has an tive of the state of CNV. CNV must be returned high before the th th acceptable hold time. After the 14 (or 28 ) SCK falling edge, or safe data transfer time, t , and then held high beyond the DATA when CNV goes high (whichever occurs first), SDO returns to conversion time, t , to avoid generation of the busy signal CONV high impedance. indicator. If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 28 SCK falling edges is required to return SDO to high impedance if this is enabled. DIGITAL HOST AD7949 CNV SS SDO MISO MOSI DIN SCK SCK FOR SPI USE CPHA = 0, CPOL = 0. Figure 39. Connection Diagram for the AD7949 Without a Busy Indicator Rev. D | Page 28 of 32 07351-039 Data Sheet AD7949 t CYC > t CONV t t CONV CONV t t DATA DATA t CNVH EOC EOC RETURN CNV HIGH RETURN CNV HIGH CNV FOR NO BUSY FOR NO BUSY t ACQ ACQUISITION (QUIET (QUIET CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n - 1) TIME) TIME) t UPDATE (n + 1) SCK UPDATE (n) t SCKH SEE NOTE CFG/SDO CFG/SDO 14/ 14/ SCK 1 12 13 2 12 13 28 28 t t CLSCK SCKL t t SDIN HDIN CFG CFG CFG CFG DIN X X X X MSB – 1 LSB LSB MSB t t t HSDO t END CFG (n + 1) END CFG (n) BEGIN CFG (n + 1) EN EN EN t DSDO SEE NOTE SDO MSB LSB LSB t END DATA (n – 1) t t t DIS END DATA (n – 2) DIS BEGIN DATA (n – 1) DIS DIS NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 13 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 27 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 14TH OR 28TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE. Figure 40. Serial Interface Timing for the AD7949 Without a Busy Indicator Rev. D | Page 29 of 32 07351-040 AD7949 Data Sheet CFG update. While CNV is low, both a CFG update and a data READ/WRITE SPANNING CONVERSION WITH A readback take place. The first 14 SCK rising edges are used to BUSY INDICATOR update the CFG register, and the first 14 SCK falling edges clock This mode is used when the AD7949 is connected to any host out the conversion results starting with the MSB. The restric- using an SPI, serial port, or FPGA with an interrupt input. The tion for both configuring and reading is that they both occur connection diagram is shown in Figure 41, and the correspond- before the tDATA time elapses for the next conversion. All 14 bits of ing timing is given in Figure 42. For the SPI, the host should use CFG[13:0] must be written or they are ignored. Also, if the 14-bit CPHA = CPOL = 1. Reading/writing spanning conversion is conversion result is not read back before t elapses, it is lost. DATA shown, which covers all three modes detailed in the Digital The SDO data is valid on both SCK edges. Although the rising Interface section. edge can be used to capture the data, a digital host using the A rising edge on CNV initiates a conversion, ignores data SCK falling edge allows a faster reading rate, provided it has an present on DIN and forces SDO to high impedance. After the th st acceptable hold time. After the optional 15 (or 29 ) SCK conversion is initiated, it continues until completion irrespec- falling edge, SDO returns to high impedance. Note that if the tive of the state of CNV. CNV must be returned low before the optional SCK falling edge is not used, the busy feature cannot safe data transfer time, tDATA, and then held low beyond the be detected, as described in the General Timing with a Busy conversion time, tCONV, to generate the busy signal indicator. Indicator section. When the conversion is complete, SDO transitions from high If CFG readback is enabled, the CFG register associated with impedance to low (data ready), and with a pull-up to VIO, SDO the conversion result is read back MSB first following the LSB of can be used to interrupt the host to begin data transfer. the conversion result. A total of 29 SCK falling edges is required After the conversion is complete, the AD7949 enters the to return SDO to high impedance if this is enabled. acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin the VIO AD7949 DIGITAL HOST SDO MISO IRQ CNV SS DIN MOSI SCK SCK FOR SPI USE CPHA = 1, CPOL = 1. Figure 41. Connection Diagram for the AD7949 with a Busy Indicator t t CYC CONV t t t ACQ DATA DATA t CNVH CNV CONVERSION (QUIET (QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n – 1) TIME) TIME) (n + 1) t SCK UPDATE (n) UPDATE (n + 1) t SCKH NOTE 1 CFG/SDO CFG/SDO 15/ 15/ SCK 1 13 14 2 13 14 29 29 t t SCKL HDIN t SDIN CFG CFG DIN X X X X X X MSB MSB –1 t END CFG (n) t BEIGN CFG (n + 1) HSDO t t DIS EN DIS END CFG (n + 1) t DSDO LSB MSB LSB SDO LSB MSB LSB + 1 – 1 + 1 NOTE 1 END DATA (n – 2) BEGIN DATA (n – 1) END DATA (n – 1) t t t EN DIS EN NOTES: 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 14 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 28 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 15TH OR 29TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. Figure 42. Serial Interface Timing for the AD7949 with a Busy Indicator Rev. D | Page 30 of 32 07351-041 07351-042 Data Sheet AD7949 APPLICATION HINTS inductances. This is done by placing the reference decoupling LAYOUT ceramic capacitor close to, ideally right up against, the REF and The printed circuit board (PCB) that houses the AD7949 should GND pins and connecting them with wide, low impedance traces. be designed so that the analog and digital sections are separated Finally, the power supplies VDD and VIO of the AD7949 and confined to certain areas of the board. The pinout of the should be decoupled with ceramic capacitors, typically 100 nF, AD7949, with all its analog signals on the left side and all its placed close to the AD7949, and connected using short, wide digital signals on the right side, eases this task. traces to provide low impedance paths and to reduce the effect Avoid running digital lines under the device because these couple of glitches on the power supply lines. noise onto the die unless a ground plane under the AD7949 is used as a shield. Fast switching signals, such as CNV or clocks, EVALUATING AD7949 PERFORMANCE should not run near analog signal paths. Avoid crossover of Other recommended layouts for the AD7949 are outlined in the digital and analog signals. documentation of the evaluation board for the AD7949 (EVAL- At least one ground plane should be used. It can be common or AD7949EDZ). The evaluation board package includes a fully split between the digital and analog sections. In the latter case, assembled and tested evaluation board, documentation, and the planes should be joined underneath the AD7949. software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z. The AD7949 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic Rev. D | Page 31 of 32 AD7949 Data Sheet OUTLINE DIMENSIONS 4.10 0.60 MAX 4.00 SQ 3.90 0.60 MAX 16 20 15 1 PIN 1 0.50 2.65 3.75 EXPOSED INDICATOR BSC BSC SQ PAD 2.50 SQ (BOTTOM VIEW) 2.35 5 11 10 6 0.50 0.25 MIN TOP VIEW 0.40 0.30 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.30 SEATING 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 43. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Notes Temperature Range Package Description Package Option Ordering Quantity AD7949BCPZ –40°C to +85°C 20-Lead LFCSP_VQ CP-20-4 Tray, 490 AD7949BCPZRL7 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-4 Reel, 1,500 EVAL-AD7949EDZ Evaluation Board 2 EVAL-CED1Z Controller Board 1 Z = RoHS Compliant Part. 2 This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED. ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07351-0-3/12(D) Rev. D | Page 32 of 32 PIN 1 INDICATOR 03-08-2012-B