ANALOG DEVICES AD7946

14-Bit, 500 kSPS PulSAR ADC in MSOP AD7946 FEATURES APPLICATION DIAGRAM 0.5V TO 5V 5V 14-bit resolution with no missing codes Throughput: 500 kSPS INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR) SINAD: 85 dB @ 20 kHz VIO 1.8V TO VDD REF VDD 0V TO REF SDI THD: −100 dB @ 20 kHz IN+ SCK AD7946 3- OR 4-WIRE INTERFACE Pseudo differential analog input range IN– (SPI, DAISY CHAIN, CS) SDO 0 V to REF with REF up to VDD GND CNV No pipeline delay Single-supply 5 V operation with Figure 1. 1.8 V/2.5 V/3 V/5 V logic interface GENERAL DESCRIPTION Serial interface, SPI/QSPI/MICROWIRE™/DSP compatible Daisy-chain multiple ADCs and BUSY indicator The AD7946 is a 14-bit, charge redistribution, successive Power dissipation approximation, analog-to-digital converter (ADC) that operates 3.3 mW @ 5 V/100 kSPS from a single 5 V power supply, VDD. It contains a low power, 3.3 μW @ 5 V/100 SPS high speed, 14-bit sampling ADC with no missing codes, an Standby current: 1 nA internal conversion clock, and a versatile serial interface port. 10-lead MSOP (MSOP-8 size) and The part also contains a low noise, wide bandwidth, short 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) aperture delay track-and-hold circuit. On the CNV rising edge, Pin-for-pin compatible with the 16-bit AD7686 it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied APPLICATIONS externally and can be set up to the supply voltage. Battery-powered equipment Its power scales linearly with throughput. Data acquisition Instrumentation The SPI-compatible serial interface also features the ability, Medical instruments using the SDI input, to daisy-chain several ADCs on a single, Process control 3-wire bus, or it provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 1 1 14-Bit AD7940 AD7942 AD7946 1 1 1 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4941 1 1 1 AD7683 AD7687 AD7688 AD7983 ADA4841 1 AD7684 AD7694 AD7693 1 1 1 18-Bit AD7691 AD7690 AD7982 ADA4941 1 AD7984 ADA4841 1 Pin-for-pin compatible. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04656-001 AD7946 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference Input ............................................................ 14 Applications....................................................................................... 1 Power Supply............................................................................... 15 Application Diagram........................................................................ 1 Supplying the ADC from the Reference.................................. 15 General Description ......................................................................... 1 Single-Supply Application......................................................... 15 Revision History ............................................................................... 2 Digital Interface.......................................................................... 16 Specifications..................................................................................... 3 CS MODE 3-Wire, No BUSY Indicator .................................. 17 Timing Specifications .................................................................. 5 CS Mode 3-Wire with BUSY Indicator ................................... 18 Absolute Maximum Ratings............................................................ 6 CS Mode 4-Wire, No BUSY Indicator..................................... 19 ESD Caution.................................................................................. 6 CS Mode 4-Wire with BUSY Indicator ................................... 20 Pin Configurations and Function Descriptions ........................... 7 Chain Mode, No BUSY Indicator ............................................ 21 Typical Performance Characteristics ............................................. 8 Chain Mode with BUSY Indicator........................................... 22 Terminology .................................................................................... 11 Application Guidelines .................................................................. 23 Theory of Operation ...................................................................... 12 Layout .......................................................................................... 23 Circuit Information.................................................................... 12 Evaluating the AD7946’s Performance.................................... 23 Converter Operation.................................................................. 12 Outline Dimensions ....................................................................... 24 Typical Connection Diagram ................................................... 13 Ordering Guide .......................................................................... 24 Analog Input ............................................................................... 13 Driver Amplifier Choice............................................................ 14 REVISION HISTORY 12/07—Rev. 0 to Rev. A QFN Package Available......................................................Universal Changes to Table 1............................................................................ 1 Changes to Table 5............................................................................ 6 Changes to Ordering Guide .......................................................... 24 7/05—Revision 0: Initial Version Rev. A | Page 2 of 24 AD7946 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUT Voltage Range IN+ − IN− 0 REF V Absolute Input Voltage IN+ −0.1 VDD + 0.1 V IN− −0.1 0.1 V Analog Input CMRR fIN = 200 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section ACCURACY No Missing Codes 14 Bits 1 Differential Linearity Error −0.7 ±0.3 +0.7 LSB Integral Linearity Error −1 ±0.4 +1 LSB Transition Noise REF = VDD = 5 V 0.33 LSB 2 Gain Error , TMIN to TMAX ±0.3 ±6 LSB Gain Error Temperature Drift ±1 ppm/°C 2 Offset Error , TMIN to TMAX ±0.3 ±6 LSB Offset Temperature Drift ±1 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.1 LSB THROUGHPUT Conversion Rate 0 500 kSPS Transient Response Full-scale step 400 ns AC ACCURACY 3 Signal-to-Noise f = 20 kHz, REF = 5 V 84.5 85 dB IN f = 20 kHz, REF = 2.5 V 84 dB IN Spurious-Free Dynamic Range fIN = 20 kHz −100 dB Total Harmonic Distortion fIN = 20 kHz −100 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, REF = 5 V 84.5 85 dB f = 20 kHz, REF = 5 V, −60 dB input 25 dB IN 4 Intermodulation Distortion 100 dB 1 LSB means least significant bit. With the 5 V input range, one LSB is 305.2 μV. 2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale. Rev. A | Page 3 of 24 AD7946 VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, T = −40°C to +85°C, unless otherwise noted. A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 500 kSPS, REF = 5 V 100 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 9 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V −0.3 0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 14-bits straight binary Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 4.5 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 1, 2 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V, 100 SPS throughput 3.3 μW VDD = 5 V, 100 kSPS throughput 3.3 3.8 mW VDD = 5 V, 500 kSPS throughput 19 mW 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact sales for extended the temperature range. Rev. A | Page 4 of 24 AD7946 TIMING SPECIFICATIONS TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 1.6 μs Acquisition Time tACQ 400 ns Time Between Conversions tCYC 2 μs CNV Pulse Width (CS Mode) t 10 ns CNVH SCK Period (CS Mode) t 15 ns SCK SCK Period (Chain Mode) tSCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time t 7 ns SCKL SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t 5 ns SSCKCNV SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 5 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns Rev. A | Page 5 of 24 AD7946 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational IN+ , IN− GND − 0.3 V to VDD + 0.3 V or ±130 mA section of this specification is not implied. Exposure to absolute REF GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V ESD CAUTION Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 10-Lead MSOP 200°C/W 10-Lead QFN 48.7°C/W θJC Thermal Impedance 10-Lead MSOP 44°C/W 10-Lead QFN 2.96°C/W Lead Temperature Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Input section. 500µA I OL TO 1.4V SDO C L 50pF 500µA I OH Figure 2. Load Circuit for Digital Interface Timing 70% OVDD 30% VIO t t DELAY DELAY 1 1 2V or OVDD – 0.5V 2V or VIO – 0.5V 2 2 0.8V or 0.5V 0.8V or 0.5V NOTES 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. A | Page 6 of 24 04656-002 04656-003 AD7946 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO REF 1 VIO 10 VDD 2 9 SDI AD7946 VDD 2 9 SDI AD7946 IN+ 3 8 SCK TOP VIEW IN+ 3 TOP VIEW 8 SCK (Not to Scale) IN– 4 7 SDO (Not to Scale) 4 IN– 7 SDO GND 5 6 CNV GND 5 6 CNV Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Figure 4. 10-Lead MSOP Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD, and is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to REF. 4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 24 04656-004 04656-005 AD7946 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 POSITIVE INL = +0.17LSB POSITIVE DNL = +0.20LSB 0.8 NEGATIVE INL = –0.26LSB 0.8 NEGATIVE DNL = –0.13LSB 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 CODE CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 300000 150000 261120 VDD = REF = 5V VDD = REF = 5V 131592 129528 250000 125000 200000 100000 150000 75000 100000 50000 50000 25000 00 0 0 0 0 0 0 0 0 0 0 2009 200A 200B 200C 200D 200E 200F 2059 205A 205B 205C 205D 205E CODE IN HEX CODE IN HEX Figure 7. Histogram of a DC Input at the Code Center Figure 10. Histogram of a DC Input at the Code Transition 0 90 8192 POINT FFT VDD = REF = 5V –20 f = 500kSPS S f = 20.14kHz IN 88 –40 SNR = 85.3dB THD = –105.2dB –60 SECOND HARMONIC = –106dB THIRD HARMONIC = –110dB 86 –80 –100 84 –120 –140 82 –160 –180 80 0 20 40 60 80 100 120 140 160 180 200 220 240 –10 –8–6–4–2 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 8. FFT Plot Figure 11. SNR vs. Input Level Rev. A | Page 8 of 24 COUNTS AMPLITUDE (dB of Full Scale) INL (LSB) 04656-006 04656-008 04656-046 COUNTS DNL (LSB) SNR REFERENCE TO FULL SCALE (dB) 04656-011 04656-009 04656-047 AD7946 90.0 –90 15.0 –95 87.5 14.5 –100 SNR THD 85.0 14.0 –105 SINAD SFDR –110 ENOB 82.5 13.5 –115 80.0 13.0 –120 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD, SFDR vs. Reference Voltage 90.0 –90 REF = 5V REF = 5V 87.5 –100 85.0 –110 82.5 –120 80.0 –130 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature 100 –60 95 –70 90 –80 REF = 5V, –10dB 85 –90 REF = 5V, –1dB 80 REF = 5V, –1dB –100 REF = 5V, –10dB 75 –110 70 –120 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. SINAD vs. Frequency Figure 17. THD vs. Frequency Rev. A | Page 9 of 24 SNR, SINAD (dB) SINAD (dB) SNR (dB) 04656-014 04656-013 04656-012 ENOB (Bits) THD (dB) THD (dB) THD, SFDR (dB) 04656-017 04656-016 04656-015 AD7946 3 1000 f = 100kSPS S 2 750 VDD 1 OFFSET ERROR 500 0 –1 GAIN ERROR 250 –2 VIO –3 0 –55 –35 –15 5 25 45 65 85 105 125 4.50 4.75 5.00 5.25 5.50 TEMPERATURE (°C) SUPPLY (V) Figure 18. Operating Current vs. Supply Figure 21. Offset and Gain Error vs. Temperature 1000 25 20 750 15 500 VDD = 5V, 85°C 10 VDD = 5V, 25°C 250 5 VDD+VIO 0 0 0 2040 6080 100 120 –55 –35 –15 5 25 45 65 85 105 125 SDO CAPACITIVE LOAD (pF) TEMPERATURE (°C) Figure 19. Power-Down Current vs. Temperature Figure 22. tDSDO Delay vs. Capacitance Load and Supply 1000 f = 100kSPS S 750 VDD = 5V 500 250 VIO 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 20. Operating Current vs. Temperature Rev. A | Page 10 of 24 OPERATING CURRENT (µA) POWER-DOWN CURRENT (nA) OPERATING CURRENT (µA) 04656-049 04656-048 04656-050 T DELAY (ns) DSDO OFFSET AND GAIN ERROR (LSB) 04656-021 04656-022 AD7946 TERMINOLOGY Integral Nonlinearity Error (INL) Effective Number of Bits (ENOB) INL refers to the deviation of each individual code from a line ENOB is a measurement of the resolution with a sine wave drawn from negative full scale through positive full scale. The input. It is related to SINAD by the following formula: point used as negative full scale occurs ½ LSB before the first ENOB = (SINADdB − 1.76)/6.02 code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 24). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic Differential Nonlinearity Error (DNL) components to the rms value of a full-scale input signal and is In an ideal ADC, code transitions are 1 LSB apart. DNL is the expressed in dB. maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the Offset Error rms sum of all other spectral components below the Nyquist The first transition should occur at a level ½ LSB above analog frequency, excluding harmonics and dc. The value for SNR is ground (152.6 μV for the 0 V to 5 V range). The offset error is expressed in dB. the deviation of the actual transition from that point. Signal-to-(Noise + Distortion) Ratio (SINAD) Gain Error SINAD is the ratio of the rms value of the actual input signal to The last transition (from 111 … 10 to 111 … 11) should occur the rms sum of all other spectral components below the Nyquist for an analog voltage 1½ LSB below the nominal full scale frequency, including harmonics but excluding dc. The value for (4.999542 V for the 0 V to 5 V range). The gain error is the SINAD is expressed in dB. deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Aperture Delay Aperture delay is the measurement of the acquisition perform- Spurious-Free Dynamic Range (SFDR) ance and is the time between the rising edge of the CNV input SFDR is the difference, in decibels (dB), between the rms and when the input signal is held for a conversion. amplitude of the input signal and the peak spurious signal. Transient Response Transient response is the time required for the ADC to accu- rately acquire its input after a full-scale step function is applied. Rev. A | Page 11 of 24 AD7946 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 8192C 4096C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 8192C 4096C 4C 2C C C MSB LSB SW– CNV IN– Figure 23. ADC Simplified Schematic The control logic toggles these switches, starting with the MSB, CIRCUIT INFORMATION in order to bring the comparator back into a balanced condition. The AD7946 is a fast, low power, single-supply, precise 14-bit After completing this process, the part returns to the acquisition ADC using a successive approximation architecture. phase, and the control logic generates the ADC output code and The AD7946 can convert 500,000 samples per second (500 kSPS) a BUSY signal indicator. and powers down between conversions. When operating at Because the AD7946 has an on-board conversion clock, the 100 SPS, for example, it consumes 3.3 μW typically, ideal for serial clock, SCK, is not required for the conversion process. battery-powered applications. Transfer Functions The AD7946 provides the user with an on-chip track-and-hold The ideal transfer characteristic for the AD7946 is shown in and does not exhibit any pipeline delay or latency, making it Figure 24 and Table 7. ideal for multiple multiplexed channel applications. The AD7946 is specified from 4.5 V to 5.5 V and can be interfaced to any of the 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that 111...111 111...110 combines space savings and allows flexible configurations. 111...101 It is pin-for-pin compatible with the 16-bit ADC AD7686. CONVERTER OPERATION The AD7946 is a successive approximation ADC based on a charge redistribution DAC. Figure 23 shows the simplified schematic of the ADC. The capacitive DAC consists of two 000...010 000...001 identical arrays of 14 binary weighted capacitors, which are 000...000 connected to the two comparator inputs. –FSR –FSR + 1 LSB +FSR – 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB During the acquisition phase, the terminals of the array that are ANALOG INPUT tied to the comparator’s input are connected to GND via SW+ Figure 24. ADC Ideal Transfer Function and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors Table 7. Output Codes and Ideal Input Voltages and acquire the analog signal on the IN+ and IN− inputs. When Analog Input the acquisition phase is complete and the CNV input goes high, REF = 5 V Description Digital Output Code Hexa a conversion phase is initiated. When the conversion phase 1 FSR − 1 LSB 4.999695 V 3FFF begins, SW+ and SW− are opened first. The two capacitor Midscale + 1 LSB 2.500305 V 2001 arrays are then disconnected from the inputs and connected to Midscale 2.5 V 2000 the GND input. Therefore, the differential voltage between the Midscale − 1 LSB 2.499695 V 1FFF inputs IN+ and IN− captured at the end of the acquisition phase −FSR + 1 LSB 305.2 μV 0001 is applied to the comparator inputs, causing the comparator to 2 −FSR 0 V 0000 become unbalanced. By switching each element of the capacitor 1 This is also the code for an overranged analog input (VIN+ − VIN− above REF − VGND). array between GND and REF, the comparator input varies by 2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND). binary weighted voltage steps (REF/2, REF/4 … REF/16,384). Rev. A | Page 12 of 24 ADC CODE (Straight Binary) 04656-023 04656-024 AD7946 TYPICAL CONNECTION DIAGRAM Figure 25 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available. (NOTE 1) V+ REF 5V 10µF 100nF (NOTE 2) 1.8V TO VDD V+ 100nF REF VDD VIO 33Ω SDI IN+ 0V TO REF SCK 3- OR 4-WIRE INTERFACE 2.7nF AD7946 (ADA4841 SDO V– (NOTE 5) OR NOTE 3) IN– (NOTE 4) CNV GND NOTES 1. SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 25. Typical Application Diagram with Multiple Supplies 70 ANALOG INPUT Figure 26 shows an equivalent circuit of the input structure of the AD7946. The two diodes, D1 and D2, provide ESD protection for the 60 analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more VDD = 5V than 0.3 V because this causes these diodes to begin to forward- bias and start conducting current. These diodes can handle a 50 maximum forward-biased current of 130 mA. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to 40 1 10 100 1k 10k protect the part. FREQUENCY (kHz) VDD Figure 27. Analog Input CMRR vs. Frequency D1 C During the acquisition phase, the impedance of the analog IN R IN+ IN OR IN– inputs (IN+ or IN−) can be modeled as a parallel combination C PIN D2 of capacitor, CPIN, and the network formed by the series connec- GND tion of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 Ω and is a lumped component made up of some Figure 26. Equivalent Analog Input Circuit serial resistors and the on resistance of the switches. C is IN The analog input structure allows the sampling of the typically 30 pF and is mainly the ADC sampling capacitor. differential signal between IN+ and IN−. By using this During the conversion phase, when the switches are opened, the differential input, small signals common to both inputs are input impedance is limited to CPIN. RIN and CIN make a 1-pole, rejected, as shown in Figure 27, which represents the typical low-pass filter, which reduces undesirable aliasing effects and CMRR over frequency. For instance, by using IN− to sense a limits the noise. remote signal ground, ground potential differences between the When the source impedance of the driving circuit is low, the sensor and the local ADC ground are eliminated. AD7946 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be Rev. A | Page 13 of 24 04656-026 CMRR (dB) 04656-025 04656-027 AD7946 tolerated. The THD degrades as a function of the source Table 8. Recommended Driver Amplifiers impedance and the maximum input frequency, as shown in Amplifier Typical Application Figure 28. ADA4841 Very low noise, small and low power –80 AD8021 Very low noise and high frequency AD8655 5 V single-supply, low noise, and low power –85 AD8022 Low noise and high frequency OP184 Low power, low noise, and low frequency –90 AD8605, AD8615 5 V single-supply, low power AD8519 Small, low power, and low frequency R = 250Ω S –95 AD8031 High frequency and low power R =100Ω S –100 VOLTAGE REFERENCE INPUT R = 50Ω S R = 33Ω S The AD7946 voltage reference input REF has a dynamic input –105 impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND –110 0 255075 100 pins, as explained in the Layout section. FREQUENCY (kHz) When REF is driven by a very low impedance source, for Figure 28. THD vs. Analog Input Frequency and Source Resistance example, a reference buffer using the AD8031 or the AD8603, a DRIVER AMPLIFIER CHOICE 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. Although the AD7946 is easy to drive, the driver amplifier needs to meet the following requirements: If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, • The noise generated by the driver amplifier needs to be 1206 size) ceramic chip capacitor is appropriate for optimum kept as low as possible to preserve the SNR and transition performance using a low temperature drift ADR43x reference. noise performance of the AD7946. Note that the AD7946 has a noise much lower than most of the other 14-bit If desired, smaller reference decoupling capacitor values down ADCs and, therefore, can be driven by a noisier amplifier to 2.2 μF can be used with a minimal impact on performance, to meet a given system noise specification. The noise especially DNL. coming from the amplifier is filtered by the AD7946 analog Regardless, there is no need for an additional lower value ceramic input circuit 1-pole, low-pass filter made by RIN and CIN or decoupling capacitor (for example, 100 nF) between the REF by the external filter, if one is used. and GND pins. • For ac applications, the driver should have a THD perform- ance commensurate with the AD7946. Figure 17 shows the THD vs. frequency that the driver should exceed. • For multichannel multiplexed applications, the driver amplifier and the AD7946 analog input circuit must settle a full-scale step onto the capacitor array at a 14-bit level (0.006%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. Rev. A | Page 14 of 24 THD (dB) 04656-028 AD7946 POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7946 is specified at 4.5 V to 5.5 V. It uses two power For simplified applications, the AD7946, with its low operating supply pins: a core supply VDD and a digital input/output current, can be supplied directly using the reference circuit interface supply VIO. VIO allows direct interface with any shown in Figure 31. The reference line can be driven by one of logic between 1.8 V and VDD. To reduce the supplies needed, the following: the VIO and VDD can be tied together. The AD7946 is • The system power supply directly. independent of power supply sequencing between VIO and • A reference voltage with enough current output capability, VDD. Additionally, it is very insensitive to power supply such as the ADR43x. variations over a wide frequency range, as shown in Figure 29, which represents PSRR over frequency. • A reference buffer, such as the AD8031 or AD8603, 90 which can also filter the system power supply, as shown in Figure 31. 80 5V VDD = 5V 70 10kΩ 5V 1kΩ 10µF 1µF AD8603 60 1µF 47kΩ (NOTE 1) 50 REF VDD VIO AD7946 40 NOTES 30 1. OPTIONAL REFERENCE BUFFER AND FILTER 1 10 100 1k 10k Figure 31. Example of Application Circuit FREQUENCY (kHz) Figure 29. PSRR vs. Frequency SINGLE-SUPPLY APPLICATION The AD7946 powers down automatically at the end of each Figure 32 shows a typical 14-bit single-supply application. There conversion phase and, therefore, the power scales linearly with are different challenges to doing a single-supply, high resolution the sampling rate, as shown in Figure 30. This makes the part design, and the ADA4841 addresses these nicely. The combina- ideal for low sampling rate (even a few Hz) and low battery- tion of low noise, low power, wide input range, rail-to-rail output, powered applications. and high speed make the ADA4841 a perfect driver solution for low power, single-supply 14-bit ADCs, such as the AD7946. In a single-supply system, one of the main challenges is to use the 1000 VDD = 5V amplifier in buffer mode to have the lowest output noise and still preserve linearity compatible with the ADC. Rail-to-rail 100 input amplifiers usually have higher noise than the ADA4841 VIO 10 and cannot be used on their entire input range in buffer mode because of the nonlinear region around the crossover point of 1 their input stage. The ADA4841, which has no crossover region but has a wide linear input range from ground to 1 V below 0.1 positive rail, solves this issue, as shown in Figure 32, where it 0.01 can accept the 0 V to 4.096 V input range with a supply as low as 5.2 V. This supply allows using a small, low dropout, low 0.001 temperature drift ADR364 reference voltage. Note that, like any 10 100 1k 10k 100k 1M rail-to-rail output amplifier at the low end of its output range SAMPLING RATE (SPS) close to ground, the ADA4841 can exhibit some nonlinearity on Figure 30. Operating Currents vs. Sampling Rate a small region of approximately 25 mV from ground. The ADA4841 drives a 1-pole, low-pass filter. This filter limits the already very low noise contribution from the amplifier to the AD7946. Rev. A | Page 15 of 24 OPERATING CURRENT (µA) PSRR (dB) 04656-051 04656-029 04656-031 AD7946 >5.2V independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. 100nF ADR364 The AD7946, when in chain mode, provides a daisy chain 100nF 10µF feature using the SDI input for cascading multiple ADCs on a 100nF ADA4841 single data line similar to a shift register. REF VDD VIO 0V TO 4.096V 33Ω The operating mode depends on the SDI level when the CNV IN+ SDI rising edge occurs. CS mode is selected if SDI is high, and chain SCK 2.7nF AD7946 mode is selected if SDI is low. The SDI hold time is such that SDO IN– CNV when SDI and CNV are connected, the chain mode is always GND selected. In either mode, the AD7946 offers the flexibility to optionally Figure 32. Example of a Single-Supply Application Circuit force a start bit in front of the data bits. This start bit can be DIGITAL INTERFACE used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, Although the AD7946 has a reduced number of pins, it offers the user must time out the maximum conversion time prior to flexibility in its serial interface modes. readback. The AD7946, when in CS mode, is compatible with SPI, QSPI™, BUSY indicator feature is enabled digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. This interface can use either 3-wire or 4-wire. A • In CS mode, if CNV or SDI is low when the ADC 3-wire interface using the CNV, SCK, and SDO signals mini- conversion ends (see Figure 36 and Figure 40). mizes wiring connections useful, for instance, in isolated • In chain mode, if SCK is high during the CNV rising edge applications. A 4-wire interface using the SDI, CNV, SCK, and (see Figure 44). SDO signals allows CNV, which initiates the conversions, to be Rev. A | Page 16 of 24 04656-052 AD7946 are then clocked by subsequent SCK falling edges. The data is CS MODE 3-WIRE, NO BUSY INDICATOR valid on both SCK edges. Although the rising edge can be used This mode is usually used when a single AD7946 is connected to capture the data, a digital host using the SCK falling edge to an SPI-compatible digital host. The connection diagram is allows a faster reading rate, provided it has an acceptable hold shown in Figure 33 and the corresponding timing is given in th time. After the 14 SCK falling edge or when CNV goes high, Figure 34. whichever is earlier, SDO returns to high impedance. With SDI tied to VIO, a rising edge on CNV initiates a CS conversion, selects the mode, and forces SDO to high CONVERT impedance. Once a conversion is initiated, it continues to DIGITAL HOST CNV completion irrespective of the state of CNV. For instance, it VIO could be useful to bring CNV low to select other SPI devices, SDI SDO DATA IN AD7946 such as analog multiplexers, but CNV must be returned high SCK before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY CLK signal indicator. When the conversion is complete, the AD7946 enters the acquisition phase and powers down. When CNV Figure 33. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High) goes low, the MSB is output onto SDO. The remaining data bits SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 12 3 12 13 14 t t HSDO SCKH t t t EN DSDO DIS SDO D13 D12 D11 D1 D0 CS Figure 34. Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev. A | Page 17 of 24 04656-033 04656-032 AD7946 edges. Although the rising edge can be used to capture the data, CS MODE 3-WIRE WITH BUSY INDICATOR a digital host using the SCK falling edge allows a faster reading This mode is usually used when a single AD7946 is connected rate, provided it has an acceptable hold time. After the optional to an SPI-compatible digital host having an interrupt input. th 15 SCK falling edge, or when CNV goes high, whichever is The connection diagram is shown in Figure 35, and the earlier, SDO returns to high impedance. corresponding timing is given in Figure 36. If multiple AD7946s are selected at the same time, the SDO With SDI tied to VIO, a rising edge on CNV initiates a output pin handles this contention without damage or induced CS conversion, selects the mode, and forces SDO to high latch-up. Meanwhile, it is recommended to keep this contention impedance. SDO is maintained in high impedance until the as short as possible to limit extra power dissipation. completion of the conversion irrespective of the state of CNV. CONVERT Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV VIO DIGITAL HOST CNV must be returned low before the minimum conversion time and VIO 47kΩ held low until the maximum conversion time to guarantee the SDI SDO DATA IN AD7946 generation of the BUSY signal indicator. When the conversion SCK IRQ is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an CLK interrupt signal to initiate the data reading controlled by the digital host. The AD7946 then enters the acquisition phase and CS Figure 35. Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High) powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK SDI = 1 t CYC t CNVH CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 12 3 13 14 15 t t HSDO SCKH t t DSDO DIS SDO D13 D12 D1 D0 Figure 36. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev. A | Page 18 of 24 04656-035 04656-034 AD7946 time and held high until the maximum conversion time to CS MODE 4-WIRE, NO BUSY INDICATOR avoid the generation of the BUSY signal indicator. When the This mode is usually used when multiple AD7946s are conversion is complete, the AD7946 enters the acquisition connected to an SPI-compatible digital host. phase and powers down. Each ADC result can be read by A connection diagram example using two AD7946s is shown in bringing its SDI input low, which consequently outputs the MSB Figure 37, and the corresponding timing is given in Figure 38. onto SDO. The remaining data bits are then clocked by subse- quent SCK falling edges. The data is valid on both SCK edges. With SDI high, a rising edge on CNV initiates a conversion, Although the rising edge can be used to capture the data, a CS selects the mode, and forces SDO to high impedance. In this digital host using the SCK falling edge allows a faster reading mode, CNV must be held high during the conversion phase and th rate, provided it has an acceptable hold time. After the 14 SCK the subsequent data readback (if SDI and CNV are low, SDO is falling edge, or when SDI goes high, whichever is earlier, SDO driven low). Prior to the minimum conversion time, SDI could returns to high impedance and another AD7946 can be read. be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI AD7946 SDO SDI AD7946 SDO SCK SCK DATA IN CLK Figure 37. CS Mode 4-Wire, No BUSY Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 12 13 14 15 16 26 27 28 t t HSDO SCKH t t t EN DSDO DIS SDO D13 D12 D11 D1 D0 D13 D12 D1 D0 CS Figure 38. Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev. A | Page 19 of 24 04656-036 04656-037 AD7946 low. With a pull-up on the SDO line, this transition can be used CS MODE 4-WIRE WITH BUSY INDICATOR as an interrupt signal to initiate the data readback controlled by This mode is usually used when a single AD7946 is connected the digital host. The AD7946 then enters the acquisition phase to an SPI-compatible digital host, which has an interrupt input, and powers down. The data bits are then clocked out, MSB first, and it is desired to keep CNV, which is used to sample the by subsequent SCK falling edges. The data is valid on both SCK analog input, independent of the signal used to select the data edges. Although the rising edge can be used to capture the data, reading. This requirement is particularly important in a digital host using the SCK falling edge allows a faster reading applications where low jitter on CNV is desired. rate, provided it has an acceptable hold time. After the optional th The connection diagram is shown in Figure 39, and the 15 SCK falling edge or SDI going high, whichever is earlier, the corresponding timing is given in Figure 40. SDO returns to high impedance. With SDI high, a rising edge on CNV initiates a conversion, CS1 CONVERT selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and VIO DIGITAL HOST CNV the subsequent data readback (if SDI and CNV are low, SDO is 47kΩ driven low). Prior to the minimum conversion time, SDI could SDI SDO DATA IN AD7946 be used to select other SPI devices, such as analog multiplexers, SCK IRQ but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to CLK guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 123 13 14 15 t t HSDO SCKH t t DSDO DIS t EN SDO D13 D12 D1 D0 CS Figure 40. Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev. A | Page 20 of 24 04656-039 04656-038 AD7946 onto SDO, and the AD7946 enters the acquisition phase and CHAIN MODE, NO BUSY INDICATOR powers down. The remaining data bits stored in the internal This mode can be used to daisy-chain multiple AD7946s on shift register are then clocked by subsequent SCK falling edges. a 3-wire serial interface. This feature is useful for reducing For each ADC, SDI feeds the input of the internal shift register component count and wiring connections, for example, in and is clocked by the SCK falling edge. Each ADC in the chain isolated multiconverter applications or for systems with a outputs its data MSB first, and 14 × N clocks are required to limited interfacing capacity. Data readback is analogous to readback the N ADCs. The data is valid on both SCK edges. clocking a shift register. Although the rising edge can be used to capture the data, a A connection diagram example using two AD7946s is shown in digital host using the SCK falling edge allows a faster reading Figure 41, and the corresponding timing is given in Figure 42. rate and consequently more AD7946s in the chain, provided the digital host has an acceptable hold time. The maximum conver- When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain sion rate may be reduced due to the total readback time. For mode, and disables the BUSY indicator. In this mode, CNV is instance, with a 3 ns digital host setup time and 3 V interface, held high during the conversion phase and the subsequent data up to four AD7946s running at a conversion rate of 360 kSPS readback. When the conversion is complete, the MSB is output can be daisy-chained on a 3-wire port. CONVERT CNV CNV DIGITAL HOST SDI AD7946 SDO SDI AD7946 SDO DATA IN A B SCK SCK CLK Figure 41. Chain Mode, No BUSY Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 12 13 14 15 16 262728 t t t HSCKCNV SSDISCK SCKH t t HSDISCK EN D 13 D 12 D 11 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 13 D 12 D 11 D1D0D 13 D 12 D 1 D 0 SDO B B B B B A A A A B Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing Rev. A | Page 21 of 24 04656-040 04656-041 AD7946 Figure 43) SDO is driven high. This transition on SDO can CHAIN MODE WITH BUSY INDICATOR be used as a BUSY indicator to trigger the data readback This mode can be used to daisy-chain multiple AD7946s on a controlled by the digital host. The AD7946 then enters the 3-wire serial interface while providing a BUSY indicator. This acquisition phase and powers down. The data bits stored in feature is useful for reducing component count and wiring the internal shift register are then clocked out, MSB first, by connections, for example, in isolated multiconverter applications or subsequent SCK falling edges. For each ADC, SDI feeds the for systems with a limited interfacing capacity. Data readback is input of the internal shift register and is clocked by the SCK analogous to clocking a shift register. falling edge. Each ADC in the chain outputs its data MSB first, A connection diagram example using three AD7946s is shown and 14 × N + 1 clocks are required to readback the N ADCs. in Figure 43, and the corresponding timing is given in Figure 44. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the rate and consequently more AD7946s in the chain, provided the chain mode, and enables the BUSY indicator feature. In this digital host has an acceptable hold time. For instance, with a mode, CNV is held high during the conversion phase and the 3 ns digital host setup time and 3 V interface, up to four AD7946s subsequent data readback. When all ADCs in the chain have running at a conversion rate of 360 kSPS can be daisy-chained completed their conversions, the near-end ADC (ADC C in to a single 3-wire port. CONVERT DIGITAL HOST CNV CNV CNV SDI AD7946 SDO SDI AD7946 SDO SDI AD7946 SDO DATA IN A B C SCK SCK SCK IRQ CLK Figure 43. Chain Mode with BUSY Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 413 14 15 16 17 27 28 29 30 31 41 42 43 t t t HSCKCNV SSDISCK SCKL t t DSDOSDI t HSDISCK EN SDO = SDI D 13 D 12 D 11 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 13 D 12 D 11 D1D0D 13 D 12 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 13 D 12 D 11 D1D0D D 13 D 12 D1D0D 13 12 D1D 0 C C C C C B B B B A A A A Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing Rev. A | Page 22 of 24 04656-042 04656-043 AD7946 APPLICATION GUIDELINES LAYOUT The printed circuit board that houses the AD7946 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7946, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7946 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7946s. Figure 45. Example of Layout of the AD7946 (Top Layer) The AD7946 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connecting it with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7946 should be decoupled with ceramic capacitors (typically 100 nF) placed close to the AD7946 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 45 and Figure 46. EVALUATING THE AD7946’S PERFORMANCE Other recommended layouts for the AD7946 are outlined Figure 46. Example of Layout of the AD7946 (Bottom Layer) in the documentation of the evaluation board for the AD7946 (EVAL-AD7946CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. A | Page 23 of 24 04656-045 04656-044 AD7946 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.40 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 47.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.30 3.00 0.23 0.50 BSC BSC SQ 0.18 6 10 PIN 1 INDEX * 1.74 EXPOSED AREA PAD 1.64 (BOTTOM VIEW) 1.49 0.50 0.40 5 1 0.30 TOP VIEW 2.48 2.38 0.80 MAX 2.23 0.80 0.55 NOM 0.05 MAX 0.75 0.02 NOM 0.70 * PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SEATING ELECTRICAL PERFORMANCES PLANE 0.20 REF Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding AD7946BRM −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C1E AD7946BRM-RL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C1E 1 AD7946BRMZ −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C4X 1 AD7946BRMZRL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C4X 1 AD7946BCPZRL7 −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 1,000 C4X 1 AD7946BCPZRL −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 5,000 C4X 1, 2 EVAL-AD7946CBZ Evaluation Board 1, 3 EVAL-CONTROL BRD3Z Evaluation Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3Z for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designator. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04656-0-12/07(A) TTTT Rev. A | Page 24 of 24 PIN 1 INDICATOR (R 0.19) 101207-B