ANALOG DEVICES AD7940

3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 AD7940 FUNCTIONAL BLOCK DIAGRAM FEATURES V Fast throughput rate: 100 kSPS DD Specified for V of 2.5 V to 5.5 V DD Low power 14-BIT SUCCESSIVE V T/H APPROXIMATION 4 mW typ at 100 kSPS with 3 V supplies IN ADC 17 mW typ at 100 kSPS with 5 V supplies Wide input bandwidth: SCLK 81 dB SINAD at 10 kHz input frequency CONTROL AD7940 SDATA LOGIC Flexible power/serial clock speed management CS No pipeline delays High speed serial interface GND SPI®/QSPI™/MICROWIRE™/DSP compatible Figure 1. Standby mode: 0.5 µA max 6-Lead SOT-23 and 8-Lead MSOP packages Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23) APPLICATIONS Type 100 kSPS 250 kSPS 500 kSPS Battery-powered systems 16-Bit True Differential AD7684 AD7687 AD7688 Personal digital assistants 16-Bit Pseudo Differential AD7683 AD7685 AD7686 Medical instruments 16-Bit Unipolar AD7680 Mobile communications 14-Bit True Differential AD7944 AD7947 Instrumentation and control systems 14-Bit Pseudo Differential AD7942 AD7946 Remote data acquisition systems 14-Bit Unipolar AD7940 This part features a standard successive approximation ADC GENERAL DESCRIPTION CS 1 with accurate control of the sampling instant via a input and The AD7940 is a 14-bit, fast, low power, successive once off conversion control. approximation ADC. The part operates from a single 2.50 V to 5.5 V power supply and features throughput rates up to 100 kSPS. PRODUCT HIGHLIGHTS The part contains a low noise, wide bandwidth track-and-hold 1. First 14-bit ADC in a SOT-23 package. amplifier that can handle input frequencies in excess of 7 MHz. 2. High throughput with low power consumption. The conversion process and data acquisition are controlled 3. Flexible power/serial clock speed management. The using CS and the serial clock, allowing the devices to interface conversion rate is determined by the serial clock, allowing with microprocessors or DSPs. The input signal is sampled on the conversion time to be reduced through the serial clock the falling edge of CS and the conversion is also initiated at this speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not point. There are no pipelined delays associated with the part. converting. The part also features a shutdown mode to The AD7940 uses advanced design techniques to achieve very maximize power efficiency at lower throughput rates. low power dissipation at fast throughput rates. The reference for Power consumption is 0.5 µA max when in shutdown. the part is taken internally from V , which allows the widest DD 4. Reference derived from the power supply. dynamic input range to the ADC. Thus, the analog input range 5. No pipeline delay. for this part is 0 V to V . The conversion rate is determined by DD the SCLK frequency. 1 Protected by US. Patent No. 6,681,332. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. 03305-0-001 AD7940 TABLE OF CONTENTS Normal Mode .............................................................................. 13  Table of Contents .............................................................................. 2  Power-Down Mode .................................................................... 14  Specif ica t ions ..................................................................................... 3  Power vs. Throughput Rate ........................................................... 15  Timing Specifications ....................................................................... 5  Serial Interface ................................................................................ 16  Absolute Maximum Ratings ............................................................ 6  Microprocessor Interfacing ........................................................... 17  ESD Caution .................................................................................. 6  AD7940 to TMS320C541 .......................................................... 17  Pin Configurations and Function Descriptions ........................... 7  AD7940 to ADSP-218x .............................................................. 17  Terminology ...................................................................................... 8  AD7940 to DSP563xx ................................................................ 18  Typical Performance Characteristics ............................................. 9  Application Hints ........................................................................... 19  Circuit Information ........................................................................ 11  Grounding and Layout .............................................................. 19  Converter Operation .................................................................. 11  Evaluating the AD7940 Performance ...................................... 19  Analog Input ............................................................................... 11  Outline Dimensions ....................................................................... 20  ADC Transfer Function ................................................................. 12  Ordering Guide .......................................................................... 20  Typical Connection Diagram ................................................... 12  Modes of Operation ....................................................................... 13  REVISION HISTORY 8/11—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 7/04—Revision 0: Initial Version AD7940 1 SPECIFICATIONS V = 2.50 V to 5.5 V, f = 2.5 MHz, f = 100 kSPS, unless otherwise noted; T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 2. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 10 kHz sine wave IN 2 Signal-to-Noise + Distortion (SINAD) 81 dB min 2 Total Harmonic Distortion (THD) −98 dB typ 2 Peak Harmonic or Spurious Noise (SFDR) −95 dB typ 2 Intermodulation Distortion (IMD) Second-Order Terms −94 dB typ Third-Order Terms −100 dB typ Aperture Delay 20 ns max Aperture Jitter 30 ps typ Full Power Bandwidth 7 MHz typ @ −3 dB 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 14 Bits min V = 2.5 V to 4.096 V DD 13 Bits min V > 4.096 V DD 2 Integral Nonlinearity ±1 LSB max V = 2.5 V to 4.096 V DD ±2 LSB max V > 4.096 V DD 2 Offset Error ±6 LSB max 2 Gain Error ±8 LSB max ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±0.3 µA max Input Capacitance 30 pF typ LOGIC INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.4 V max V = 3 V INL DD 0.8 V max V = 5 V DD Input Current, I ±0.3 µA max Typically 10 nA, V = 0 V or V IN IN DD 2, 3 Input Capacitance, C 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V – 0.2 V min I = 200 µA; V = 2.50 V to 5.25 V OH DD SOURCE DD Output Low Voltage, V 0.4 V max I = 200 µA OL SINK Floating-State Leakage Current ±0.3 µA max 2, 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 8 µs max 16 SCLK cycles Track-and-Hold Acquisition Time 500 ns max Full-scale step input 400 ns max Sine wave input ≤ 10 kHz Throughput Rate 100 kSPS max See the Serial Interface section POWER REQUIREMENTS V 2.50/5.5 V min/V max DD I Digital I/P = 0 V or V DD S DD Normal Mode (Static) 5.2 mA max V = 5.5 V; SCLK on or off DD 2 mA max V = 3.6 V; SCLK on or off DD Normal Mode (Operational) 4.8 mA max V = 5.5 V; f = 100 kSPS; 3.3 mA typ DD SAMPLE 1.9 mA max V = 3.6 V; f = 100 kSPS; 1.29 mA typ DD SAMPLE Full Power-Down Mode 0.5 µA max SCLK on or off. V = 5.5 V DD 0.3 µA max SCLK on or off. V = 3.6 V DD Rev. A | Page 3 of 20 AD7940 1 Parameter B Version Unit Test Conditions/Comments 4 Power Dissipation V = 5.5 V DD Normal Mode (Operational) 26.4 mW max V = 5.5 V; f = 100 kSPS DD SAMPLE 6.84 mW max V = 3.6 V; f = 100 kSPS DD SAMPLE Full Power-Down 2.5 µW max V = 5.5 V DD 1.08 µW max V = 3.6 V DD 1 Temperature range for B Version is –40°C to +85°C. 2 See the Terminology section. 3 Sample tested at initial release to ensure compliance. 4 See the Power vs. Throughput Rate section. Rev. A | Page 4 of 20 AD7940 TIMING SPECIFICATIONS Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from DD a voltage level of 1.6 V. V = 2.50 V to 5.5 V; T = T to T , unless otherwise noted. DD A MIN MAX Table 3. Limit at T , T MIN MAX Parameter 3 V 5 V Unit Description 1 f 250 250 kHz min SCLK 2.5 2.5 MHz max t 16 × t 16 × t min CONVERT SCLK SCLK t 50 50 ns min Minimum quiet time required between bus relinquish and start of QUIET next conversion t 10 10 ns min CS Minimum pulse width 1 t 10 10 ns min CS 2 to SCLK setup time 2 t 48 35 ns max CS Delay from until SDATA three-state disabled 3 2 t 120 80 ns max Data access time after SCLK falling edge 4 t 0.4 t 0.4 t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 t 0.4 t ns min SCLK high pulse width 6 SCLK SCLK t 10 10 ns min SCLK to data valid hold time 7 3 t 45 35 ns max SCLK falling edge to SDATA high impedance 8 4 t 1 1 µs typ Power up time from full power-down POWER-UP 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 3 t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated 8 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 8 time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section. 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specification Rev. A | Page 5 of 20 03305-0-002 AD7940 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND −0.3 V to +7 V DD other conditions above those listed in the operational sections Analog Input Voltage to GND −0.3 V to V + 0.3 V DD of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to V + 0.3 V DD device reliability. 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOT-23 Package, Power Dissipation 450 mW θ Thermal Impedance 229.6°C/W JA θ Thermal Impedance 91.99°C/W JC MSOP Package, Power Dissipation 450 mW θ Thermal Impedance 205.9°C/W JA θ Thermal Impedance 43.74°C/W JC Lead Temperature, Soldering Vapor Phase (60 secs) 215°C Infared (15 secs) 220°C ESD 4 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. Rev. A | Page 6 of 20 AD7940 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS MSOP SOT-23 V 1 8 CS DD V 1 6 CS DD AD7490 GND 2 7 SDATA AD7940 GND 2 5 SDATA TOP VIEW TOP VIEW GND 3 6 NC V 3 4 SCLK (Not to Scale) IN (Not to Scale) 4 5 V SCLK IN Figure 3. SOT-23 Pin Configuration NC = NO CONNECT Figure 4. MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Pin No. SOT-23 MSOP Mnemonic Function 1 1 V Power Supply Input. The V range for the AD7940 is from 2.5 V to 5.5 V. DD DD 2 2, 3 GND Analog Ground. Ground reference point for all circuitry on the AD7940. All analog input signals should be referred to this GND voltage. 3 4 V Analog Input. Single-ended analog input channel. The input range is 0 V to V . IN DD 4 5 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock input is also used as the clock source for the AD7940's conversion process. 5 7 SDATA Data Out. Logic output. The conversion result from the AD7940 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7940 consists of two leading zeros followed by 14 bits of conversion data that are provided MSB CS first. This will be followed by four trailing zeroes if is held low for a total of 24 SCLK cycles. See the Serial Interface section. 6 8 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7940 and framing the serial data transfer. N/A 6 NC No Connect. This pin should be left unconnected. Rev. A | Page 7 of 20 03305-0-023 03305-0-003 AD7940 TERMINOLOGY Total Harmonic Distortion (THD) Integral Nonlinearity THD is the ratio of the rms sum of harmonics to the This is the maximum deviation from a straight line passing fundamental. For the AD7940, it is defined as through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 THD(dB)= 20log LSB below the first code transition, and full scale, a point 1/2 V 1 LSB above the last code transition. where V is the rms amplitude of the fundamental and V , V , 1 2 3 Differential Nonlinearity V , V , and V are the rms amplitudes of the second through the 4 5 6 This is the difference between the measured and the ideal 1 LSB sixth harmonics. change between any two adjacent codes in the ADC. Peak Harmonic or Spurious Noise Offset Error Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the first code transition (00 . . . 000) to rms value of the next largest component in the ADC output (00 . . . 001) from the ideal, i.e., AGND + 1 LSB. spectrum (up to f /2, excluding dc) to the rms value of the S Gain Error fundamental. Normally, the value of this specification is This is the deviation of the last code transition (111 . . . 110) to determined by the largest harmonic in the spectrum, but for (111 . . . 111) from the ideal (i.e., V − 1 LSB) after the offset REF ADCs where the harmonics are buried in the noise floor, it will error has been adjusted out. be a noise peak. Track-and-Hold Acquisition Time Intermodulation Distortion The track-and-hold amplifier returns to track mode at the end With inputs consisting of sine waves at two frequencies, fa and fb, of conversion. The track-and-hold acquisition time is the time any active device with nonlinearities will create distortion required for the output of the track-and-hold amplifier to reach products at sum and difference frequencies of mfa ± nfb where m, its final value, within ±1 LSB, after the end of the conversion. n = 0, 1, 2, 3. Intermodulation distortion terms are those for See the Serial Interface section for more details. which neither m nor n are equal to zero. For example, the second- Signal-to-(Noise + Distortion) Ratio order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb). This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the The AD7940 is tested using the CCIF standard where two input fundamental. Noise is the sum of all nonfundamental signals up frequencies near the top end of the input bandwidth are used. to half the sampling frequency (f /2, excluding dc). The ratio S In this case, the second-order terms are usually distanced in depends on the number of quantization levels in the digitization frequency from the original sine waves, while the third-order process; the more levels, the smaller the quantization noise. The terms are usually at a frequency close to the input frequencies. theoretical signal-to-(noise + distortion) ratio for an ideal N-bit As a result, the second- and third-order terms are specified converter with a sine wave input is given by separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB sum of the individual distortion products to the rms amplitude Thus, for a 14-bit converter, this is 86.04 dB. of the sum of the fundamentals expressed in dBs. Rev. A | Page 8 of 20 AD7940 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7 shows a graph of the total harmonic distortion versus Figure 5 shows a typical FFT plot for the AD7940 at 100 kSPS the analog input frequency for various supply voltages, while sample rate and 10 kHz input frequency. Figure 6 shows the Figure 8 shows a graph of the total harmonic distortion versus signal-to-(noise + distortion) ratio performance versus the the analog input frequency for various source impedances (see input frequency for various supply voltages while sampling at the Analog Input section). Figure 9 and Figure 10 show the 100 kSPS with an SCLK of 2.5 MHz. typical INL and DNL plots for the AD7940. 0 110 V = 4.75V DD F = 100kSPS SAMPLE F = 100kSPS SAMPLE T = 25°C A –20 F = 10kHz IN 105 SNR = 84.48dB V = 3.6V SINAD = 84.35dB DD –40 V = 3V DD V = 2.7V THD = –98.97dB DD 100 SFDR = –100.84dB –60 V = 4.3V DD –80 95 –100 V = 5.25V DD 90 V = 4.75V V = 2.5V DD DD –120 85 –140 –160 80 0 10k 20k 30k 40k 50k 10 100 FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 5. AD7940 Dynamic Performance at 100 kSPS Figure 7. AD7940 THD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS 90 110 F = 100kSPS F = 100kSPS SAMPLE SAMPLE T = 25°C T = 25°C A A 105 V = 4.75V DD 100 V = 5.25V V = 4.75V DD DD 85 R = 10Ω IN 95 V = 4.3V DD R = 50Ω IN 90 V = 3.6V DD R = 100Ω IN V = 3V DD 85 80 V = 2.5V V = 2.7V DD DD 80 75 R = 1000Ω IN 75 70 10 100 10 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 8. AD7940 THD vs. Analog Input Frequency Figure 6. AD7940 SINAD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS for Various Source Impedances Rev. A | Page 9 of 20 SINAD (dB) (dB) 03305-0-020 03305-0-019 THD (dB) THD (dB) 03305-0-022 03305-0-021 AD7940 1.0 0.8 V = 3.00V V = 3.00V DD DD TEMP = 25°C TEMP = 25°C 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE CODE Figure 9. AD7940 Typical INL Figure 10. AD7940 Typical DNL Rev. A | Page 10 of 20 INL ERROR (LSB) 03305-0-018 DNL ERROR (LSB) 03305-0-017 AD7940 CIRCUIT INFORMATION The AD7940 is a fast, low power, 14-bit, single-supply ADC. CAPACITIVE DAC The part can be operated from a 2.50 V to 5.5 V supply. When SAMPLING A operated at either 5 V or 3 V supply, the AD7940 is capable of CAPACITOR V IN SW1 throughput rates of 100 kSPS when provided with a 2.5 MHz CONTROL B LOGIC CONVERSION clock. SW2 PHASE COMPARATOR The AD7940 provides the user with an on-chip track-and-hold V /2 DD ADC and a serial interface housed in a tiny 6-lead SOT-23 Figure 12. ADC Conversion Phase package or in an 8-lead MSOP package, which offer the user ANALOG INPUT considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and also Figure 13 shows an equivalent circuit of the analog input provides the clock source for the successive approximation structure of the AD7940. The two diodes, D1 and D2, provide ADC. The analog input range for the AD7940 is 0 V to V . An DD ESD protection for the analog inputs. Care must be taken to external reference is not required for the ADC nor is there a ensure that the analog input signal never exceeds the supply reference on-chip. The reference for the AD7940 is derived from rails by more than 300 mV. This will cause these diodes to the power supply and thus gives the widest dynamic input range. become forward-biased and to start conducting current into the substrate. The maximum current these diodes can conduct The AD7940 also features a power-down option to save power without causing irreversible damage to the part is 10 mA. between conversions. The power-down feature is implemented Capacitor C1 in Figure 13 is typically about 5 pF and primarily across the standard serial interface as described in the Modes of can be attributed to pin capacitance. Resistor R1 is a lumped Operation section. component made up of the on resistance of a switch (track-and- CONVERTER OPERATION hold switch). This resistor is typically about 25 Ω. Capacitor C2 The AD7940 is a 14-bit, successive approximation ADC based is the ADC sampling capacitor and has a capacitance of 25 pF around a capacitive DAC. The AD7940 can convert analog typically. For ac applications, removing high frequency input signals in the 0 V to V range. Figure 11 and Figure 12 DD components from the analog input signal is recommended by show simplified schematics of the ADC. The ADC comprises of use of an RC low-pass filter on the relevant analog input pin. In control logic, SAR, and a capacitive DAC. Figure 11 shows the applications where harmonic distortion and signal-to-noise ADC during its acquisition phase. SW2 is closed and SW1 is in ratio are critical, the analog input should be driven from a low Position A. The comparator is held in a balanced condition and impedance source. Large source impedances will significantly the sampling capacitor acquires the signal on the selected V affect the ac performance of the ADC. This may necessitate the IN channel. use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. When no amplifier is CAPACITIVE used to drive the analog input, the source impedance should be DAC SAMPLING limited to low values. The maximum source impedance will A CAPACITOR V IN depend on the amount of total harmonic distortion (THD) that SW1 CONTROL B can be tolerated. The THD will increase as the source impedance LOGIC ACQUISITION SW2 PHASE increases, and performance will degrade (see Figure 8). COMPARATOR V /2 DD V DD Figure 11. ADC Acquisition Phase C2 D1 30pF R1 When the ADC starts a conversion, SW2 will open and SW1 V IN C1 D2 will move to Position B, causing the comparator to become 4pF CONVERSION PHASE - SWITCH OPEN unbalanced (Figure 12). The control logic and the capacitive TRACK PHASE - SWITCH CLOSED DAC are used to add and subtract fixed amounts of charge Figure 13. Equivalent Analog Input Circuit from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code (see the ADC Transfer Function section). Rev. A | Page 11 of 20 03305-0-004 03305-0-006 03305-0-005 AD7940 ADC TRANSFER FUNCTION In fact, because the supply current required by the AD7940 is so The output coding of the AD7940 is straight binary. The low, a precision reference can be used as the supply source to designed code transitions occur at successive integer LSB the AD7940. For example, a REF19x voltage reference (REF195 values, i.e., 1 LSB, 2 LSBs. The LSB size is V /16384. The ideal DD for 5 V or REF193 for 3 V) or an AD780 can be used to supply transfer characteristic for the AD7940 is shown in Figure 14. the required voltage to the ADC (see Figure 15). This configuration is especially useful if the power supply available is quite noisy, or if the system supply voltages are at some value 111...111 111...110 other than the required operating voltage of the AD7940, e.g., 15 V. The REF19x or AD780 will output a steady voltage to the AD7940. Recommended decoupling capacitors are a 100 nF low 111...000 1 LSB = V /16384 ESR ceramic (Farnell 335-1816) and a 10 µF low ESR tantalum DD 011...111 (Farnell 197-130). 3V 5V REF193 SUPPLY 10µF 0.1µF 10µF 0.1µF 000...010 TANT 000...001 000...000 V 1 LSB +V –1 LSB DD DD SCLK 0V ANALOG INPUT 0V TO V DD V IN SDATA µC/µP INPUT AD7940 Figure 14. AD7940 Transfer Characteristic CS GND TYPICAL CONNECTION DIAGRAM SERIAL Figure 15 shows a typical connection diagram for the AD7940. INTERFACE V is taken internally from V and as such should be well REF DD Figure 15. Typical Connection Diagram decoupled. This provides an analog input range of 0 V to V . DD The conversion result is output in a 16-bit word. This 16-bit Digital Inputs data stream consists of two leading zeros, followed by the 14 The digital inputs applied to the AD7940 are not limited by the bits of conversion data, MSB first. For applications where power maximum ratings that limit the analog inputs. Instead, the consumption is a concern, the power-down mode should be digital inputs applied can go to 7 V and are not restricted by the used between conversions or bursts of several conversions to V + 0.3 V limit as on the analog inputs. For example, if the DD improve power performance (see the Modes of Operation AD7940 were operated with a V of 3 V, 5 V logic levels could DD section). be used on the digital inputs. However, it is important to note that the data output on SDATA will still have 3 V logic levels when V = 3 V. DD Another advantage of SCLK and CS not being restricted by the V + 0.3 V limit is the fact that power supply sequencing issues DD are avoided. If one of these digital inputs is applied before V , DD there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to V . DD Rev. A | Page 12 of 20 03305-0-007 03305-0-008 AD7940 MODES OF OPERATION The conversion is initiated on the falling edge of CS as The mode of operation of the AD7940 is selected by controlling described in the Serial Interface section. To ensure that the part the (logic) state of the CS signal during a conversion. There are remains fully powered up at all times, CS must remain low until two possible modes of operation, normal and power-down. The at least 10 SCLK falling edges have elapsed after the falling edge CS point at which is pulled high after the conversion has been CS CS of . If is brought high any time after the 10th SCLK falling initiated will determine whether or not the AD7940 will enter edge, but before the 16th SCLK falling edge, the part will CS power-down mode. Similarly, if already in power-down, can remain powered up, but the conversion will be terminated and control whether the device will return to normal operation or SDATA will go back into three-state. At least 16 serial clock remain in power-down. These modes of operation are designed cycles are required to complete the conversion and access the to provide flexible power management options. These options complete conversion result. CS may idle high until the next can optimize the power dissipation/throughput rate ratio for CS returns high sometime conversion or may idle low until differing application requirements. CS prior to the next conversion, effectively idling low. NORMAL MODE Once a data transfer is complete (SDATA has returned to three- This mode provides the fastest throughput rate performance state), another conversion can be initiated after the quiet time, because the user does not have to worry about the power-up t , has elapsed by bringing CS low again. QUIET times with the AD7940 remaining fully powered all the time. Figure 16 shows the general diagram of the operation of the AD7940 in this mode. CS 1 12 16 SCLK SDATA 1 LEADING ZERO + CONVERSION RESULT Figure 16. Normal Mode Operation Rev. A | Page 13 of 20 03305-0-009 AD7940 POWER-DOWN MODE In order to exit this mode of operation and power up the This mode is intended for use in applications where slower AD7940 again, a dummy conversion is performed. On the throughput rates are required. Either the ADC is powered down CS falling edge of , the device will begin to power up and will between each conversion, or a series of conversions may be CS continue to power up as long as is held low until after the performed at a high throughput rate, and then the ADC is falling edge of the 10th SCLK. The device will be fully powered powered down for a relatively long duration between these up once at least 16 SCLKs (or approximately 6 µs) have elapsed bursts of several conversions. When the AD7940 is in power- and valid data will result from the next conversion as shown in down, all analog circuitry is powered down. Figure 18. If CS is brought high before the 10th falling edge of To enter power-down, the conversion process must be SCLK, regardless of the SCLK frequency, the AD7940 will go interrupted by bringing CS high anywhere after the second back into power-down again. This avoids accidental power-up falling edge of SCLK and before the 10th falling edge of SCLK CS due to glitches on the line or an inadvertent burst of 8 SCLK CS as shown in Figure 17. Once has been brought high in this CS cycles while is low. So although the device may begin to window of SCLKs, the part will enter power-down, the power-up on the falling edge of CS, it will power down again on conversion that was initiated by the falling edge of CS will be the rising edge of CS as long as it occurs before the 10th SCLK terminated, and SDATA will go back into three-state. If CS is falling edge. brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will CS avoid accidental power-down due to glitches on the line. CS 1 2 10 16 SCLK THREE-STATE SDATA Figure 17. Entering Power-Down Mode THE PART IS FULLY POWERED UP WITH V FULLY ACQUIRED IN THE PART BEGINS TO POWER UP t POWER UP CS 1 10 16 1 16 SCLK INVALID DATA VALID DATA SDATA Figure 18. Exiting Power-Down Mode Rev. A | Page 14 of 20 03305-0-010 03305-0-011 AD7940 POWER VS. THROUGHPUT RATE Figure 19 shows the power dissipation versus the throughput By using the power-down mode on the AD7940 when not rate when using the power-down mode with 3.6 V supplies and converting, the average power consumption of the ADC a 2.5 MHz SCLK. decreases at lower throughput rates. Figure 19 shows how as the 10 throughput rate is reduced, the part remains in its shutdown V = 3.6V DD F = 2.5MHz SCLK state longer, and the average power consumption over time drops accordingly. For example, if the AD7940 is operated in a continuous 1 sampling mode, with a throughput rate of 10 kSPS and an SCLK of 2.5 MHz (V = 3.6 V), and the device is placed in power- DD down mode between conversions, the power consumption is calculated as follows. The maximum power dissipation during 0.1 normal operation is 6.84 mW (V = 3.6 V). If the power-up DD time from power-down is 1 µs, and the remaining conversion time is 6.4 µs, (using a 16 SCLK transfer), then the AD7940 can be said to dissipate 6.84 mW for 7.4 µs during each conversion 0.01 0 5 10 15 20 25 30 35 40 45 50 cycle. With a throughput rate of 10 kSPS, the cycle time is 100 THROUGHPUT (kSPS) µs. For the remainder of the conversion cycle, 92.6 µs, the part Figure 19. Power vs. Throughput Using Power-Down Mode at 3.6 V remains in power-down mode. The AD7940 can be said to dissipate 1.08 µW for the remaining 92.6 µs of the conversion cycle. Therefore, with a throughput rate of 10 kSPS, the average power dissipated during each cycle is (7.4/100) × (6.84 mW) + (92.6/100) × (1.08 µW) = 0.51 mW Rev. A | Page 15 of 20 POWER (mW) 03305-0-012 AD7940 SERIAL INTERFACE microcontroller or DSP. The remaining data is then clocked out Figure 20 shows the detailed timing diagram for serial by subsequent SCLK falling edges beginning with the second interfacing to the AD7940. The serial clock provides the leading zero, thus the first falling clock edge on the serial clock conversion clock and also controls the transfer of information has the first leading zero provided and also clocks out the from the AD7940 during conversion. second leading zero. The data transfer will consist of two CS The signal initiates the data transfer and conversion process. leading zeros followed by the 14 bits of data. The final bit in the CS The falling edge of puts the track-and-hold into hold mode, data transfer is valid on the 16th falling edge, having been takes the bus out of three-state, and samples the analog input. clocked out on the previous (15th) falling edge. The conversion is also initiated at this point and will require at It is also possible to take valid data on each SCLK rising edge least 16 SCLK cycles to complete. Once 15 SCLK falling edges rather than falling edge, since the SCLK cycle time is long have elapsed, the track-and-hold will go back into track mode enough to ensure the data is ready on the rising edge of SCLK. on the next SCLK rising edge as shown in Figure 20 at Point B. CS However, the first leading zero will still be driven by the On the 16th SCLK falling edge, the SDATA line will go back falling edge, and so it can be taken only on the first SCLK CS into three-state. If the rising edge of occurs before 16 SCLKs falling edge. It may be ignored, and the first rising edge of SCLK have elapsed, the conversion will be terminated and the SDATA after the CS falling edge would have the second leading zero line will go back into three-state; otherwise SDATA returns to provided and the 15th rising SCLK edge would have DB0 three-state on the 16th SCLK falling edge as shown in Figure 20. provided. This method may not work with most Sixteen serial clock cycles are required to perform the microcontrollers/DSPs, but could possibly be used with FPGAs conversion process and to access data from the AD7940. CS and ASICs. going low provides the first leading zero to be read in by the CS t CONVERT t t 2 6 B 1 2 3 4 5 13 14 15 16 SCLK t t 5 8 t 7 t t t QUIET 3 4 SDATA 0 ZERO DB13 DB12 DB11 DB10 DB2 DB1 DB0 3-STATE 3-STATE 2 LEADING ZEROS Figure 20. AD7940 Serial Interface Timing Diagram Rev. A | Page 16 of 20 03305-0-013 AD7940 MICROPROCESSOR INTERFACING AD7940 TO ADSP-218x The serial interface on the AD7940 allows the part to be directly connected to a range of many different microprocessors. This The ADSP-218x family of DSPs can be interfaced directly to the section explains how to interface the AD7940 with some of the AD7940 with no glue logic required. The SPORT control regis- more common microcontroller and DSP serial interface ter should be set up as follows: protocols. TFSW = RFSW = 1, Alternate Framing AD7940 TO TMS320C541 INVRFS = INVTFS = 1, Active Low Frame Signal The serial interface on the TMS320C541 uses a continuous DTYPE = 00, Right Justify Data serial clock and frame synchronization signals to synchronize SLEN = 1111, 16-Bit Data-Words the data transfer operations with peripheral devices such as the CS ISCLK = 1, Internal Serial Clock AD7940. The input allows easy interfacing between the TMS320C541 and the AD7940 with no glue logic required. The TFSR = RFSR = 0, Frame First Word serial port of the TMS320C541 is set up to operate in burst IRFS = 0 mode with internal CLKX (TX serial clock) and FSX (TX frame ITFS = 1 sync). The serial port control register (SPC) must have the following setup: To implement power-down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. FO = 0 The connection diagram is shown in Figure 22. The ADSP-218x FSM = 1 has the TFS and RFS of the SPORT tied together, with TFS set MCM = 1 as an output and RFS set as an input. The DSP operates in TXM = 1 alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on The format bit, FO, must be set to 1 to set the word length to the TFS is tied to CS, and, as with all signal processing 8 bits, in order to implement the power-down mode on the AD7940. The connection diagram is shown in Figure 21. It applications, equidistant sampling is necessary. In this example, should be noted that for signal processing applications, it is the timer interrupt is used to control the sampling rate of the imperative that the frame synchronization signal from the ADC. TMS320C541 provide equidistant sampling. ADSP-218x* AD7940* SCLK SCLK TMS320C541* AD7940* SCLK CLKX SDATA DR CLKR CS RFS SDATA DR TFS CS FSX FSR *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Interfacing to the ADSP-218x Figure 21. Interfacing to the TMS320C541 The timer register is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, the values in the transmit autobuffer start to be transmitted and TFS is generated. The TFS is used to control the RFS and, therefore, the reading of data. The data is stored in the receive autobuffer for processing or to be shifted later. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, i.e., TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted, or it may wait until the next clock edge. Rev. A | Page 17 of 20 03305-0-014 03305-0-015 AD7940 For example, if the ADSP-2189 had a 20 MHz crystal, such that AD7940 TO DSP563xx it had a master clock frequency of 40 MHz, the master cycle The connection diagram in Figure 23 shows how the AD7940 time would be 25 ns. If the SCLKDIV register is loaded with the can be connected to the ESSI (synchronous serial interface) of value 7, then a SCLK of 2.5 MHz is obtained, and 16 master the DSP-563xx family of DSPs from Motorola. Each ESSI (two clock periods will elapse for every 1 SCLK period. Depending on board) is operated in synchronous mode (SYN bit in CRB = on the throughput rate selected, if the timer register was loaded 1) with internally generated 1-bit clock period frame sync for with the value 803 (803 + 1 = 804), then 50.25 SCLKs will occur both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Normal between interrupts and subsequently between transmit operation of the ESSI is selected by making MOD = 0 in the instructions. This situation will result in nonequidistant sampling CRB. Set the word length to 16 by setting bits WL1 = 1 and since the transmit instruction is occurring on a SCLK edge. If the WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so number of SCLKs between interrupts is a whole integer figure of N, that the frame sync is negative. It should be noted that for signal then equidistant sampling will be implemented by the DSP. processing applications, it is imperative that the frame synchronization signal from the DSP-563xx provide equidistant sampling. In the example shown in Figure 23, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. DSP-563xx* AD7940* SCLK SCK DOUT SRD CS STD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing to the DSP-563xx Rev. A | Page 18 of 20 03305-0-016 AD7940 APPLICATION HINTS Good decoupling is also very important. All analog supplies GROUNDING AND LAYOUT should be decoupled with 10 µF tantalum in parallel with 0.1 µF The printed circuit board that houses the AD7940 should be capacitors to AGND, as discussed in the Typical Connection designed such that the analog and digital sections are separated Diagram section. To achieve the best performance from these and confined to certain areas of the board. This facilitates the decoupling components, the user should attempt to keep the use of ground planes that can be separated easily. A minimum distance between the decoupling capacitors and the V and DD etch technique is generally best for ground planes, since it gives GND pins to a minimum, with short track lengths connecting the best shielding. Digital and analog ground planes should be the respective pins. joined at only one place. If the AD7940 is in a system where EVALUATING THE AD7940 PERFORMANCE multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground The recommended layout for the AD7940 is outlined in the point that should be established as close as possible to the evaluation board for the AD7940. The evaluation board AD7940. package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the Avoid running digital lines under the device since these will PC via the evaluation board controller. The evaluation board couple noise onto the die. The analog ground plane should be controller can be used in conjunction with the AD7940 allowed to run under the AD7940 to avoid noise coupling. The evaluation board, as well as many other Analog Devices power supply lines to the AD7940 should use as large a trace as evaluation boards ending in the CB designator, to possible to provide low impedance paths and reduce the effects demonstrate/evaluate the ac and dc performance of the of glitches on the power supply line. Fast switching signals, such AD7940. as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals The software allows the user to perform ac (fast Fourier should never be run near the analog inputs. Avoid crossover of transform) and dc (histogram of codes) tests on the AD7940. digital and analog signals. Traces on opposite sides of the board The software and documentation are on a CD shipped with the should run at right angles to each other, which will reduce the evaluation board. effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while the signals are placed on the solder side. Rev. A | Page 19 of 20 AD7940 OUTLINE DIMENSIONS 3.00 2.90 2.80 65 4 3.00 1.70 2.80 1.60 2.60 1.50 12 3 PIN1 INDICATOR 0.95BSC 1.90 BSC 1.30 1.15 0.90 0.20MAX 1.45MAX 0.08MIN 0.95MIN 0.55 0.15MAX 10° 0.45 SEATING 0.60 0.05MIN 4° 0.50MAX 0.35 PLANE BSC 0° 0.30MIN COMPLIANTTOJEDECSTANDARDSMO-178-AB Figure 24. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6). Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-AA Figure 25. 8-Lead Mini Small Outline Package [MSOP] (RM-8). Dimensions shown in millimeters ORDERING GUIDE Linearity Package 1 2 Models Notes Temperature Range Error (LSB) Package Description Option Branding AD7940BRM −40°C to +85°C 14 bits min Mini Small Outline Package (MSOP) RM-8 CRB AD7940BRM-REEL7 −40°C to +85°C 14 bits min Mini Small Outline Package (MSOP) RM-8 CRB AD7940BRMZ −40°C to +85°C 14 bits min Mini Small Outline Package (MSOP) RM-8 C06 AD7940BRMZ-REEL7 −40°C to +85°C 14 bits min Mini Small Outline Package (MSOP) RM-8 C06 AD7940BRJZ-REEL7 −40°C to +85°C 14 bits min Small Outline Transistor Package (SOT-23) RJ-6 C06 3 EVAL-AD7940CBZ Evaluation Board 4 EVAL-CONTROL BRD2 Controller Board 1 Z = RoHS Compliant Part. 2 Linearity error here refers to no missing codes. 3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 4 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7940CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the Evaluation Board application note for more information. ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03305-0-8/11(A) 10-07-2009-B 12-16-2008-A