ANALOG DEVICES AD7939

8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer Data Sheet AD7938/AD7939 FEATURES FUNCTIONAL BLOCK DIAGRAM V AGND DD Throughput rate: 1.5 MSPS Specified for V of 2.7 V to 5.25 V DD AD7938/AD7939 V REFIN/ Power consumption V REFOUT 2.5V 6 mW maximum at 1.5 MSPS with 3 V supplies VREF 13.5 mW maximum at 1.5 MSPS with 5 V supplies V 0 IN CLKIN 12-/10-BIT 8 analog input channels with a sequencer SAR ADC I/P CONVST T/H AND MUX Software-configurable analog inputs CONTROL BUSY V 7 IN 8-channel single-ended inputs 4-channel fully differential inputs 4-channel pseudo differential inputs SEQUENCER 7-channel pseudo differential inputs Accurate on-chip 2.5 V reference PARALLEL INTERFACE/CONTROL REGISTER V DRIVE ±0.2% maximum @ 25°C, 25 ppm/°C maximum 69 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes DB0 DB11 CS RD WR W/B DGND Full shutdown mode: 2 µA maximum Figure 1. 32-lead LFCSP and TQFP packages GENERAL DESCRIPTION The AD7938/AD7939 are 12-bit and 10-bit, high speed, low These parts use advanced design techniques to achieve very power, successive approximation (SAR) analog-to-digital low power dissipation at high throughput rates. They also converters (ADCs). The parts operate from a single 2.7 V to feature flexible power management options. An on-chip control 5.25 V power supply and feature throughput rates up to register allows the user to set up different operating conditions, 1.5 MSPS. The parts contain a low noise, wide bandwidth, including analog input range and configuration, output coding, differential track-and-hold amplifier that can handle input power management, and channel sequencing. frequencies up to 50 MHz. PRODUCT HIGHLIGHTS The AD7938/AD7939 feature eight analog input channels with 1. High throughput with low power consumption. a channel sequencer that allows a preprogrammed selection of 2. Eight analog inputs with a channel sequencer. channels to be converted sequentially. These parts can operate 3. Accurate on-chip 2.5 V reference. with either single-ended, fully differential, or pseudo 4. Single-ended, pseudo differential, or fully differential differential analog inputs. analog inputs that are software selectable. 5. Single-supply operation with V function. The V DRIVE DRIVE The conversion process and data acquisition are controlled function allows the parallel interface to connect directly to using standard control inputs that allow easy interfacing with 3 V or 5 V processor systems independent of V . DD microprocessors and DSPs. The input signal is sampled on the 6. No pipeline delay. CONVST falling edge of and the conversion is also initiated at 7. Accurate control of the sampling instant via a CONVST this point. input and once-off conversion control. The AD7938/AD7939 have an accurate on-chip 2.5 V reference Table 1. Related Devices that can be used as the reference source for the analog-to-digital Device No. of Bits No. of Channels Speed conversion. Alternatively, this pin can be overdriven to provide AD7933/AD7934 12/10 4 1.5 MSPS an external reference. AD7938-6 12 8 625 kSPS AD7934-6 12 4 625 kSPS Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. 03715-001 AD7938/AD7939 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information ........................................................................ 18 Functional Block Diagram .............................................................. 1 Converter Operation .................................................................. 18 General Description ......................................................................... 1 ADC Transfer Function ............................................................. 18 Product Highlights ........................................................................... 1 Typical Connection Diagram ................................................... 19 Revision History ............................................................................... 2 Analog Input Structure .............................................................. 19 Specifications ..................................................................................... 3 Analog Inputs.............................................................................. 20 AD7938 Specifications ................................................................. 3 Analog Input Selection .............................................................. 22 AD7939 Specifications ................................................................. 5 Reference ..................................................................................... 23 Timing Specifications .................................................................. 7 Parallel Interface ......................................................................... 25 Absolute Maximum Ratings ............................................................ 8 Power Modes of Operation ....................................................... 28 ESD Caution .................................................................................. 8 Power vs. Throughput Rate ....................................................... 29 Pin Configuration and Function Descriptions ............................. 9 Microprocessor Interfacing ....................................................... 29 Typical Performance Characteristics ........................................... 11 Application Hints ........................................................................... 31 Terminology .................................................................................... 13 Grounding and Layout .............................................................. 31 On-Chip Registers .......................................................................... 15 PCB Design Guidelines for Chip Scale Package .................... 31 Control Register .......................................................................... 15 Evaluating AD7938/AD7939 Performance ............................ 31 Sequencer Operation ................................................................. 16 Outline Dimensions ....................................................................... 32 Shadow Register .......................................................................... 17 Ordering Guide .......................................................................... 33 REVISION HISTORY Changes to Analog Input Structure Section ............................... 18 10/11—Rev. B to Rev. C Changes to Analog Inputs Section ............................................... 19 Changes to SINAD Specification in Features Section ................. 1 Changes to Figure 17 ...................................................................... 17 Changes to AD7938 Specifications Section .................................. 3 Changes to Figure 20 ...................................................................... 18 Updated Outline Dimensions ....................................................... 32 Changes to Figure 21 ...................................................................... 19 Changes to Ordering Guide .......................................................... 33 Changes to Figure 22 ...................................................................... 19 Changes to Figure 24 ...................................................................... 19 2/07—Rev. A to Rev. B Changes to Figure 28 ...................................................................... 21 Changes to Figure 29 ...................................................................... 21 Updated Format .................................................................. Universal Changes to Figure 41 ...................................................................... 28 Changes to Sequencer Operation Section ................................... 16 Changes to Figure 43 ...................................................................... 28 Updated Outline Dimensions ....................................................... 32 Changes to Figure 44 ...................................................................... 29 7/05—Rev. 0 to Rev. A Changes to Figure 45 ...................................................................... 29 Changes to Figure 46 ...................................................................... 29 Changes to Specifications ................................................................ 3 Updated Outline Dimensions ....................................................... 31 Added Figure 3 .................................................................................. 9 Changes to Ordering Guide .......................................................... 32 Changes to Table 5 .......................................................................... 10 Updated Typical Performance Characteristics ........................... 13 10/04—Revision 0: Initial Version Changes to Table 11 ........................................................................ 16 Rev. C | Page 2 of 36 Data Sheet AD7938/AD7939 SPECIFICATIONS AD7938 SPECIFICATIONS V = V = 2.7 V to 5.25 V, internal/external V = 2.5 V, unless otherwise noted, f = 25.5 MHz, f = 1.5 MSPS; DD DRIVE REF CLKIN SAMPLE T = T to T , unless otherwise noted. A MIN MAX Table 2. 1 Parameter Value Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN 2 Signal-to-Noise and Distortion (SINAD) 69 dB min Differential mode 67 dB min Single-ended mode 2 71 dB min Differential mode Signal-to-Noise Ratio (SNR) 69 dB min Single-ended mode 2 −73 dB max −85 dB typ, differential mode Total Harmonic Distortion (THD) −69.5 dB max −80 dB typ, single-ended mode 2 Peak Harmonic or Spurious Noise (SFDR) −72 dB max −82 dB typ 2 fa = 30 kHz, fb = 50 kHz Intermodulation Distortion (IMD) Second-Order Terms −6 dB typ Third-Order Terms −90 dB typ Channel-to-Channel Isolation −85 dB typ f = 50 kHz, f = 300 kHz IN NOISE 2 5 ns typ Aperture Delay 2 72 ps typ Aperture Jitter 2 Full Power Bandwidth 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 2 ±1 LSB max Differential mode Integral Nonlinearity ±1.5 LSB max Single-ended mode 2 Differential Nonlinearity Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits Single-Ended and Pseudo Differential Input Straight binary output coding 2 ±12 LSB max Offset Error 2 ±3 LSB max Offset Error Match 2 ±3 LSB max Gain Error 2 ±2 LSB max Gain Error Match Fully Differential Input Twos complement output coding 2 ±3 LSB max Positive Gain Error 2 ±1.5 LSB typ Positive Gain Error Match 2 ±9.5 LSB max Zero-Code Error 2 ±1 LSB typ Zero-Code Error Match 2 ±3 LSB max Negative Gain Error 2 Negative Gain Error Match ±1.5 LSB typ ANALOG INPUT Single-Ended Input Range 0 to V V RANGE bit = 0 REF 0 to 2 × V V RANGE bit = 1 REF Pseudo Differential Input Range V 0 to V V RANGE bit = 0 IN+ REF 0 to 2 × V V RANGE bit = 1 REF V −0.3 to +0.7 V typ V = 3 V IN− DD −0.3 to +1.8 V typ VDD = 5 V Fully Differential Input Range 3 VIN+ and VIN− VCM ± VREF/2 V VCM = common-mode voltage = VREF/2 VIN+ and VIN− VCM ± VREF V VCM = VREF, VIN+ or VIN− must remain within GND/VDD 4 DC Leakage Current ±1 µA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold Rev. C | Page 3 of 36 AD7938/AD7939 Data Sheet 1 Parameter Value Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 5 VREF Input Voltage 2.5 V ±1% for specified performance DC Leakage Current ±1 µA max VREFOUT Output Voltage 2.5 V ±0.2% max @ 25°C VREFOUT Temperature Coefficient 25 ppm/°C max 5 ppm/°C typ VREF Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth 130 µV typ 0.1 Hz to 1 MHz bandwidth V Output Impedance 10 Ω typ REF V Input Capacitance 15 pF typ When in track REF 25 pF typ When in hold LOGIC INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or VDRIVE 4 10 pF typ Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH 2.4 V min ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V max ISINK = 200 µA Floating-State Leakage Current ±3 µA max 4 10 pF typ Floating-State Output Capacitance Output Coding Straight (natural) binary CODING bit = 0 Twos complement CODING bit = 1 CONVERSION RATE Conversion Time t2 + 13 tCLKIN ns Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max POWER REQUIREMENTS V 2.7/5.25 V min/max DD V 2.7/5.25 V min/max DRIVE 6 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 0.8 mA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max V = 4.75 V to 5.25 V DD 2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ fSAMPLE = 100 kSPS, VDD = 5 V 160 µA typ Static Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off Power Dissipation Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 µW typ VDD = 5 V 480 µW typ VDD = 3 V Full/Autoshutdown Mode (Static) 10 µW max VDD = 5 V 6 µW max V = 3 V DD 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 For full common-mode range, see Figure 26 and Figure 27. 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to V . See the Reference section for more information. DD 6 Measured with a midscale dc analog input. Rev. C | Page 4 of 36 Data Sheet AD7938/AD7939 AD7939 SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, fCLKIN = 25.5 MHz, fSAMPLE= 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter Value Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 2 Signal-to-Noise and Distortion (SINAD) 61 dB min Differential mode 60 dB min Single-ended mode 2 Total Harmonic Distortion (THD) −70 dB max 2 Peak Harmonic or Spurious Noise (SFDR) −72 dB max 2 Intermodulation Distortion (IMD) fa = 30 kHz, fb = 50 kHz Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ Channel-to-Channel Isolation −75 dB typ f = 50 kHz, f = 300 kHz IN NOISe 2 Aperture Delay 5 ns typ 2 Aperture Jitter 72 ps typ 2 Full Power Bandwidth 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 2 Integral Nonlinearity ±0.5 LSB max 2 Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits Single-Ended and Pseudo Differential Input Straight binary output coding 2 Offset Error ±2 LSB max 2 Offset Error Match ±0.5 LSB max 2 Gain Error ±1.5 LSB max 2 Gain Error Match ±0.5 LSB max Fully Differential Input Twos complement output coding 2 Positive Gain Error ±1.5 LSB max 2 Positive Gain Error Match ±0.5 LSB max 2 Zero-Code Error ±2 LSB max 2 Zero-Code Error Match ±0.5 LSB max 2 Negative Gain Error ±1.5 LSB max 2 Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Single-Ended Input Range 0 to V V RANGE bit = 0 REF 0 to 2 × V V RANGE bit = 1 REF Pseudo Differential Input Range VIN+ 0 to VREF V RANGE bit = 0 0 to 2 × VREF V RANGE bit =1 VIN− −0.3 to +0.7 V typ VDD = 3 V −0.3 to +1.8 V typ V = 5 V DD Fully Differential Input Range 3 V and V V ± V /2 V V = common-mode voltage = V /2 IN+ IN− CM REF CM REF VIN+ and VIN− VCM ± VREF V VCM = VREF, VIN+ or VIN− must remain within GND/VDD 4 DC Leakage Current ±1 µA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold Rev. C | Page 5 of 36 AD7938/AD7939 Data Sheet 1 Parameter Value Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 5 VREF Input Voltage 2.5 V ±1% for specified performance 4 DC Leakage Current ±1 µA max External reference applied to pin V Output Voltage 2.5 V ±0.2% max @ 25°C REFOUT V Temperature Coefficient 25 ppm/°C max REFOUT 5 ppm/°C typ VREF Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth 130 µV typ 0.1 Hz to 1 MHz bandwidth V Output Impedance 10 Ω typ REF V Input Capacitance 15 pF typ When in track REF 25 pF typ When in hold LOGIC INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or VDRIVE 4 Input Capacitance, CIN 10 pF typ LOGIC OUTPUTS Output High Voltage, VOH 2.4 V min ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V max ISINK = 200 µA Floating-State Leakage Current ±3 µA max 4 Floating-State Output Capacitance 10 pF typ Output Coding Straight (natural) binary CODING bit = 0 Twos complement CODING bit =1 CONVERSION RATE Conversion Time t + 13 t ns 2 CLKIN Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max POWER REQUIREMENTS VDD 2.7/5.25 V min/max VDRIVE 2.7/5.25 V min/max 6 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 0.8 mA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V 2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ fSAMPLE = 100 kSPS, VDD = 5 V 160 µA typ Static Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off Power Dissipation Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 µW typ VDD = 5 V 480 µW typ V = 3 V DD Full/Autoshutdown Mode (Static) 10 µW max V = 5 V DD 6 µW max VDD = 3 V 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 For full common-mode range, see Figure 26 and Figure 27. 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to V . See the Reference section for more details. DD 6 Measured with a midscale dc analog input. Rev. C | Page 6 of 36 Data Sheet AD7938/AD7939 TIMING SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX 1 Parameter AD7938 AD7939 Unit Description 2 fCLKIN 700 700 kHz min CLKIN frequency. 25.5 25.5 MHz max tQUIET 30 30 ns min Minimum time between end of read and start of next conversion; in other words, time from when the data bus goes into three-state until the next falling edge of CONVST. t 10 10 ns min CONVST pulse width. 1 t 15 15 ns min CONVST falling edge to CLKIN falling edge setup time. 2 t3 50 50 ns max CLKIN falling edge to BUSY rising edge. t4 0 0 ns min CS to WR setup time. t5 0 0 ns min CS to WR hold time. t 10 10 ns min WR pulse width. 6 t 10 10 ns min Data setup time before WR. 7 t 10 10 ns min Data hold after . 8 WR t9 10 10 ns min New data valid before falling edge of BUSY. t10 0 0 ns min CS to RD setup time. t11 0 0 ns min CS to RD hold time. t 30 30 ns min RD pulse width. 12 3 t 30 30 ns max Data access time after RD. 13 4 t 3 3 ns min Bus relinquish time after . 14 RD 50 50 ns max Bus relinquish time after RD. t15 0 0 ns min HBEN to RD setup time. t 0 0 ns min HBEN to RD hold time. 16 t 10 10 ns min Minimum time between reads/writes. 17 t 0 0 ns min HBEN to setup time. 18 WR t19 10 10 ns min HBEN to WR hold time. t20 40 40 ns max CLKIN falling edge to BUSY falling edge. t21 15.7 15.7 ns min CLKIN low pulse width. t 7.8 7.8 ns min CLKIN high pulse width. 22 1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39). 2 Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the 14 bus loading. Rev. C | Page 7 of 36 AD7938/AD7939 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND/DGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect V to AGND/DGND −0.3 V to V + 0.3 V DRIVE DD device reliability. Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V VDRIVE to VDD −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to V + 0.3 V DRIVE ESD CAUTION V to AGND −0.3 V to V + 0.3 V REFIN DD AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin ±10 mA 1 Except Supplies Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 108.2°C/W (LFCSP) 121°C/W (TQFP) θ Thermal Impedance 32.71°C/W (LFCSP) JC 45°C/W (TQFP) Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) 255°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. C | Page 8 of 36 Data Sheet AD7938/AD7939 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 DB0 1 24 V 1 IN DB0 1 24 V 1 PIN 1 IN DB1 2 23 V 0 PIN 1 IN DB1 2 23 V 0 IN INDICATOR DB2 3 22 V /V DB2 3 22 V /V REFIN REFOUT REFIN REFOUT DB3 4 21 AGND AD7938/AD7939 AD7938/AD7939 4 21 DB3 AGND TOP VIEW DB4 5 20 CS TOP VIEW 5 20 CS DB4 (Not to Scale) DB5 6 (Not to Scale) 19 RD DB6 7 18 WR 6 19 DB5 RD DB7 8 17 CONVST 7 18 DB6 WR 8 17 DB7 CONVST 9 10 11 12 13 14 15 16 NOTES 1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. Figure 2. LFCSP Pin Configuration Figure 3. TQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that at V but should never exceed V by more than 0.3 V. DD DD 10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data. 12 to DB9 to Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the 14 DB11 control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 15 BUSY Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just th prior to the falling edge of BUSY on the 13 rising edge of CLKIN. See Figure 36. 16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock. 17 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up the device. 18 WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. 19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to the internal registers. Rev. C | Page 9 of 36 03715-006 V W/B DRIVE DGND V DD DB8/HBEN V 7 IN DB9 V 6 IN DB10 V 5 IN DB11 V 4 IN BUSY V 3 IN CLKIN V 2 IN 03715-050 V 9 32 W/B DRIVE DGND 10 31 V DD DB8/HBEN 11 30 V 7 IN DB9 12 29 V 6 IN DB10 13 28 V 5 IN DB11 14 27 V 4 IN BUSY 15 26 V 3 IN CLKIN 16 25 V 2 IN AD7938/AD7939 Data Sheet Pin No. Mnemonic Description 21 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 22 V /V Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. REFIN REFOUT The nominal internal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog input range does not exceed VDD + 0.3 V. See the Reference section. 23 to V 0 to V 7 Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and- IN IN 30 hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register appropriately (see Table 10). The analog input channel to be converted can either be selected by writing to the address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be programmed. The input range for all input channels can either be 0 V to V or 0 V to 2 × V , and the coding can REF REF be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 31 VDD Power Supply Input. The VDD range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor. 32 W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND. EPAD Exposed Pad. The exposed pad is located on the underside of the package. Connect the EPAD to the ground plane of the PCB using multiple vias. Rev. C | Page 10 of 36 Data Sheet AD7938/AD7939 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. –60 0 100mV p-p SINE WAVE ON V AND/OR V 4096 POINT FFT DD DRIVE –10 NO DECOUPLING V =5V DD DIFFERENTIAL/SINGLE-ENDED MODE F =1.5MSPS –70 SAMPLE –20 F = 49.62kHz IN SINAD = 70.94dB –30 INT REF THD = –90.09dB –80 DIFFERENTIAL MODE –40 –50 –90 –60 EXT REF –70 –100 –80 –90 –110 –100 –120 –110 10 210 410 610 810 1010 SUPPLY RIPPLE FREQUENCY (kHz) FREQUENCY (kHz) Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 7. AD7938 FFT @ VDD = 5 V –70 1.0 INTERNAL/EXTERNAL REFERENCE V =5V DD V =5V 0.8 DD DIFFERENTIAL MODE –75 0.6 0.4 –80 0.2 0 –85 –0.2 –0.4 –90 –0.6 –0.8 –95 –1.0 0 100 200 300 400 500 600 700 800 0 500 1000 1500 2000 2500 3000 3500 4000 NOISE FREQUENCY (kHz) CODE Figure 5. AD7938 Channel-to-Channel Isolation Figure 8. AD7938 Typical DNL @ V = 5 V DD 80 1.0 V =5V V =5V DD DD 0.8 DIFFERENTIAL MODE 70 0.6 V =3V DD 0.4 60 0.2 50 0 –0.2 40 –0.4 –0.6 30 F =1.5MSPS SAMPLE –0.8 RANGE = 0 TO V REF DIFFERENTIAL MODE –1.0 20 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (kHz) CODE Figure 6. AD7938 SINAD vs. Analog Input Frequency Figure 9. AD7938 Typical INL @ VDD = 5 V for Various Supply Voltages Rev. C | Page 11 of 36 SINAD (dB) ISOLATION (dB) PSRR (dB) 03715-008 03715-021 03715-007 INL ERROR (LSB) DNL ERROR (LSB) AMPLITUDE (dB) 0 100 200 300 400 500 600 700 03715-011 03715-010 03715-009 AD7938/AD7939 Data Sheet 10000 4 9997 INTERNAL DIFFERENTIAL MODE SINGLE-ENDED MODE CODES 9000 REF 8000 3 7000 2 6000 5000 1 4000 POSITIVE DNL 3000 0 2000 1000 NEGATIVE DNL 3 CODES –1 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 2046 2047 2048 2049 2050 V (V) CODE REF Figure 13. AD7938 Histogram of Codes for Figure 10. AD7938 DNL vs. V for V = 3 V REF DD 10k Samples @ VDD = 5 V with the Internal Reference 120 12 DIFFERENTIAL MODE 110 11 V = 5V DD DIFFERENTIAL MODE 100 10 V = 5V DD SINGLE-ENDED MODE 90 9 V = 3V DD SINGLE-ENDED MODE 80 8 V = 3V DD DIFFERENTIAL MODE 70 7 60 6 0 200 400 600 800 1000 1200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 RIPPLE FREQUENCY (kHz) V (V) REF Figure 14. CMRR vs. Ripple Frequency with V = 5 V and 3 V DD Figure 11. AD7938 ENOB vs. VREF 0 V = 5V DD –0.5 –1.0 V = 3V DD –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 SINGLE-ENDED MODE –5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V (V) REF Figure 12. AD7938 Offset vs. V REF Rev. C | Page 12 of 36 OFFSET (LSB) EFFECTIVE NUMBER OF BITS DNL (LSB) 03715-014 03715-013 03715-012 CMRR (dB) ??? 03715-017 03715-015 Data Sheet AD7938/AD7939 TERMINOLOGY Integral Nonlinearity Negative Gain Error This is the maximum deviation from a straight line passing This applies when using the twos complement output coding through the endpoints of the ADC transfer function. The option, in particular to the 2 × VREF input range with −VREF to endpoints of the transfer function are zero scale, 1 LSB below +V biased about the V point. It is the deviation of the first REF REF the first code transition, and full scale, 1 LSB above the last code code transition (100…000) to (100…001) from the ideal (that is, transition. −V + 1 LSB) after the zero-code error has been adjusted out. REFIN Differential Nonlinearity Negative Gain Error Match This is the difference between the measured and the ideal 1 LSB This is the difference in negative gain error between any two change between any two adjacent codes in the ADC. channels. Offset Error Channel-to-Channel Isolation This is the deviation of the first code transition (00…000) to Channel-to-channel isolation is a measure of the level of (00…001) from the ideal (that is, AGND + 1 LSB). crosstalk between channels. It is measured by applying a full- scale sine wave signal to all seven nonselected input channels Offset Error Match and applying a 50 kHz signal to the selected channel. The This is the difference in offset error between any two channels. channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the Gain Error noise signal on the unselected channels that appears in the FFT This is the deviation of the last code transition (111…110) to of this channel. The noise frequency on the unselected channels (111…111) from the ideal (that is, VREF − 1 LSB) after the offset varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × VREF, error has been adjusted out. while the signal amplitude is at 1 × V . See Figure 5. REF Gain Error Match Power Supply Rejection Ratio (PSRR) This is the difference in gain error between any two channels. PSRR is defined as the ratio of the power in the ADC output at Zero-Code Error full-scale frequency, f, to the power of a 100 mV p-p sine wave This applies when using the twos complement output coding applied to the ADC VDD supply of frequency, fS. The frequency option, in particular to the 2 × V input range with −V to REF REF of the noise varies from 1 kHz to 1 MHz. +VREF biased about the VREFIN point. It is the deviation of the PSRR (dB) = 10 log(Pf/PfS) midscale transition (all 0s to all 1s) from the ideal VIN voltage where: (that is, VREF). Pf is the power at frequency f in the ADC output. Zero-Code Error Match Pf is the power at frequency f in the ADC output. S S This is the difference in zero-code error between any two Common-Mode Rejection Ratio (CMRR) channels. CMRR is defined as the ratio of the power in the ADC output at Positive Gain Error full-scale frequency, f, to the power of a 100 mV p-p sine wave This applies when using the twos complement output coding applied to the common-mode voltage of VIN+ and VIN− of option, in particular to the 2 × VREF input range with −VREF to frequency, fS. +VREF biased about the VREFIN point. It is the deviation of the last CMRR (dB) = 10 log(Pf/Pf ) S code transition (011…110) to (011…111) from the ideal (that where: is, V − 1 LSB) after the zero-code error has been adjusted out. REF Pf is the power at frequency f in the ADC output. Positive Gain Error Match PfS is the power at frequency fS in the ADC output. This is the difference in positive gain error between any two channels. Rev. C | Page 13 of 36 AD7938/AD7939 Data Sheet Track-and-Hold Acquisition Time Peak Harmonic or Spurious Noise The track-and-hold amplifier returns to track mode at the end Peak harmonic or spurious noise is defined as the ratio of the of conversion. The track-and-hold acquisition time is the time rms value of the next largest component in the ADC output required for the output of the track-and-hold amplifier to reach spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of its final value, within ±½ LSB, after the end of conversion. the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for Signal-to-Noise and Distortion Ratio (SINAD) ADCs where the harmonics are buried in the noise floor, it is a This is the measured ratio of signal-to-noise and distortion at noise peak. the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up Intermodulation Distortion to half the sampling frequency (f /2), excluding dc. The With inputs consisting of sine waves at two frequencies, fa and SAMPLE ratio is dependent on the number of quantization levels in the fb, any active device with nonlinearities creates distortion digitization process; the more levels, the smaller the products at sum and difference frequencies of mfa ± nfb where quantization noise. m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, The theoretical signal-to-noise and distortion ratio for an ideal the second-order terms include (fa + fb) and (fa − fb), while N-bit converter with a sine wave input is given by the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), SINAD = (6.02 N + 1.76) dB and (fa − 2fb). Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit The AD7938/AD7939 are tested using the CCIF standard where converter, it is 62 dB. two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually Total Harmonic Distortion (THD) distanced in frequency from the original sine waves while the THD is the ratio of the rms sum of harmonics to the third-order terms are usually at a frequency close to the input fundamental. For the AD7938/AD7939, it is defined as frequencies. As a result, the second- and third-order terms are 2 2 2 2 2   specified separately. The intermodulation distortion is V +V +V +V +V 2 3 4 5 6   THD(dB)=−20 log calculated per the THD specification, as the ratio of the rms   V 1   sum of the individual distortion products to the rms amplitude where: of the sum of the fundamentals, expressed in dB. V is the rms amplitude of the fundamental. 1 V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 through the sixth harmonics. Rev. C | Page 14 of 36 Data Sheet AD7938/AD7939 ON-CHIP REGISTERS The AD7938/AD7939 have two on-chip registers that are CONTROL REGISTER necessary for the operation of the device. These are the control The control register on the AD7938/AD7939 is a 12-bit, write- register, which is used to set up different operating conditions, CS only register. Data is written to this register using the and and the shadow register, which is used to program the analog WR pins. The control register is shown in Table 7 and the input channels to be converted. functions of the bits are described in Table 8. At power up, the default bit settings in the control register are all 0s. Table 7. Control Register Bits MSB LSB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PM1 PM0 CODING REF ADD2 ADD1 ADD0 MODE1 MODE0 SHDW SEQ RANGE Table 8. Control Register Bit Function Description Bit No. Mnemonic Description 11, 10 PM1, PM0 Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power-down modes of operation, as shown in Table 9. 9 CODING This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight (natural) binary. If this bit is set to 1, the output coding is twos complement. 8 REF This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an external reference should be applied to the VREF pin. If this bit is Logic 1, the internal reference is selected. See the Reference section. 7 to 5 ADD2 to These three address bits are used to either select which analog input channel is converted in the next conversion if ADD0 the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used, as described in Table 11. The selected input channel is decoded as shown in Table 10. 4, 3 MODE1, The two mode pins select the type of analog input on the eight VIN pins. The AD7938/AD7939 can have either eight MODE0 single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential inputs. See Table 10. 2 SHDW The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and access the SHDW register. See Table 11. 1 SEQ The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and access the SHDW register. See Table 11. 0 RANGE This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, the analog input range extends from 0 V to V . If it is set to 1, the analog input range extends from 0 V to 2 × V . When this range is selected, V must REF REF DD be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. See the Analog Inputs section for more information. Table 9. Power Mode Selection Using the Power Management Bits in the Control Register PM1 PM0 Mode Description 0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times. 0 1 Autoshutdown When operating in autoshutdown mode, the AD7938/AD7939 enter full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. 1 0 Autostandby When the AD7938/AD7939 enter this mode, all circuitry is powered down except for the reference and reference buffer. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 µs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information. 1 1 Full Shutdown When the AD7938/AD7939 enter this mode, all circuitry is powered down. The information in the control register is retained. Rev. C | Page 15 of 36 AD7938/AD7939 Data Sheet periods, the conversion aborts. If a conversion is aborted after SEQUENCER OPERATION applying 12.5 CLKIN periods to the ADC, ensure that a rising The configuration of the SEQ and SHDW bits in the control edge of CONVST or a falling edge of CLKIN is applied to the register allows the user to select a particular mode of operation part before writing to the control register to program the of the sequencer function. Table 11 outlines the four modes of sequencer. If these conditions are not met, the sequencer will operation of the sequencer. not be in the correct state to handle being reprogrammed for another sequence of conversions and the performance of the Writing to the Control Register to Program the Sequencer converter is not guaranteed. The AD7938/AD7939 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN Table 10. Analog Input Type Selection MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1 Eight Single-Ended Four Fully Differential Four Pseudo Differential Input Seven Pseudo Differential Input Channel Address Input Channels Input Channels Channels (Pseudo Mode 1) Channels (Pseudo Mode 2) ADD2 ADD1 ADD0 VIN+ VIN− VIN+ VIN− VIN+ VIN− VIN+ VIN− 0 0 0 V 0 AGND V 0 V 1 V 0 V 1 V 0 V 7 IN IN IN IN IN IN IN 0 0 1 V 1 AGND V 1 V 0 V 1 V 0 V 1 V 7 IN IN IN IN IN IN IN 0 1 0 V 2 AGND V 2 V 3 V 2 V 3 V 2 V 7 IN IN IN IN IN IN IN 0 1 1 V 3 AGND V 3 V 2 V 3 V 2 V 3 V 7 IN IN IN IN IN IN IN 1 0 0 V 4 AGND V 4 V 5 V 4 V 5 V 4 V 7 IN IN IN IN IN IN IN 1 0 1 V 5 AGND V 5 V 4 V 5 V 4 V 5 V 7 IN IN IN IN IN IN IN 1 1 0 VIN6 AGND VIN6 VIN7 VIN6 VIN7 VIN6 VIN7 1 1 1 V 7 AGND V 7 V 6 V 7 V 6 Not Allowed IN IN IN IN IN Table 11. Sequence Selection SEQ SHDW Sequence Type 0 0 This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7938/AD7939 selects the next channel for conversion. 0 1 This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST falling edge. See the Shadow Register section and Table 12. 1 0 If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the channel address bits in the control register. Rev. C | Page 16 of 36 Data Sheet AD7938/AD7939 operating in fully differential mode or Pseudo Mode 1, the SHADOW REGISTER associated pair of channel bits must be set for each pair of The shadow register on the AD7938/AD7939 is an 8-bit, write- analog inputs required in the sequence. With each consecutive only register. Data is loaded from DB0 to DB7 on the rising CONVST pulse after the sequencer has been set up, the WR edge of . The eight LSBs load into the shadow register. The AD7938/AD7939 progress through the selected channels in information is written into the shadow register provided that ascending order, beginning with the lowest channel. This the SEQ and SHDW bits in the control register were set to 0 and continues until a write operation occurs with the SEQ and 1, respectively, in the previous write to the control register. Each SHDW bits configured in any way except 1, 0 (see Table 11). bit represents an analog input from Channel 0 through Channel 7. When a sequence is set up in fully differential mode or Pseudo A sequence of channels can be selected through which the Mode 1, the ADC does not convert on the inverse pairs (that is, AD7938/AD7939 cycles with each consecutive conversion after V 1, V 0). The bit functions of the shadow register are IN IN the write to the shadow register. To select a sequence of outlined in Table 12. See the Analog Input Selection section for channels to be converted, if operating in single-ended mode or further information on using the sequencer. Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When Table 12. Shadow Register Bit Functions MSB LSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 Rev. C | Page 17 of 36 AD7938/AD7939 Data Sheet CIRCUIT INFORMATION The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit, When the ADC starts a conversion (Figure 16), SW3 opens and single-supply, successive approximation analog-to-digital SW1 and SW2 move to Position B, causing the comparator to converters. The parts can operate from a 2.7 V to 5.25 V become unbalanced. Both inputs are disconnected once the power supply and feature throughput rates up to 1.5 MSPS. conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge The AD7938/AD7939 provide the user with an on-chip track- from the sampling capacitor arrays to bring the comparator and-hold, an accurate internal reference, an analog-to-digital back into a balanced condition. When the comparator is converter, and a parallel interface housed in a 32-lead LFCSP or rebalanced, the conversion is complete. The control logic TQFP package. generates the output code of the ADC. The output impedances of the sources driving the VIN+ and the VIN− pins must match; The AD7938/AD7939 have eight analog input channels that otherwise, the two inputs have different settling times, resulting can be configured to be eight single-ended inputs, four fully in errors. differential pairs, four pseudo differential pairs, or seven pseudo differential inputs with respect to one common input. There is CAPACITIVE DAC an on-chip user-programmable channel sequencer that allows the user to select a sequence of channels through which the C B S V IN+ ADC can progress and cycle with each consecutive falling edge A SW1 CONTROL SW3 of . CONVST LOGIC SW2 A V IN– B C S The analog input range for the AD7938/AD7939 is 0 V to V REF V REF COMPARATOR or 0 V to 2 × V , depending on the status of the RANGE bit in REF CAPACITIVE DAC the control register. The output coding of the ADC can be either Figure 16. ADC Conversion Phase binary or twos complement, depending on the status of the CODING bit in the control register. ADC TRANSFER FUNCTION The AD7938/AD7939 provide flexible power management The output coding for the AD7938/AD7939 is either straight options to allow the user to achieve the best power performance binary or twos complement, depending on the status of the for a given throughput rate. These options are selected by CODING bit in the control register. The designed code programming the power management bits, PM1 and PM0, in transitions occur at successive LSB values (1 LSB, 2 LSBs, and the control register. so on) and the LSB size is VREF/4,096 for the AD7938 and VREF/1,024 for the AD7939. The ideal transfer characteristics CONVERTER OPERATION of the AD7938/AD7939 for both straight binary and twos The AD7938/AD7939 are successive approximation ADCs complement output coding are shown in Figure 17 and Figure 18, based around two capacitive digital-to-analog converters respectively. (DACs). Figure 15 and Figure 16 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, an SAR, and two capacitive DACs. 111...111 Both figures show the operation of the ADC in differential/pseudo 111...110 differential mode. Single-ended mode operation is similar but VIN− is internally tied to AGND. In acquisition phase, SW3 is 111...000 closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays 011...111 1 LSB = V /4096 (AD7938) REF 1 LSB = V /1024 (AD7939) REF acquire the differential signal on the input. 000...010 CAPACITIVE DAC 000...001 000...000 C B S 1 LSB +V – 1 LSB REF V 0V IN+ A SW1 ANALOG INPUT CONTROL SW3 LOGIC SW2 A NOTES V IN– 1. V IS EITHER V OR 2 × V . B REF REF REF C S V REF COMPARATOR Figure 17. AD7938/AD7939 Ideal Transfer Characteristic CAPACITIVE with Straight Binary Output Coding DAC Figure 15. ADC Acquisition Phase Rev. C | Page 18 of 36 03715-023 ADC CODE 03715-025 03715-024 Data Sheet AD7938/AD7939 ANALOG INPUT STRUCTURE 1LSB = 2× V /4096 (AD7938) REF 1LSB = 2× V /1024 (AD7939) REF 011...111 Figure 20 shows the equivalent circuit of the analog input 011...110 structure of the AD7938/AD7939 in differential/pseudo differential mode. In single-ended mode, VIN− is internally tied to AGND. The four diodes provide ESD protection for the 000...001 analog inputs. Care must be taken to ensure that the analog 000...000 111...111 input signals never exceed the supply rails by more than 300 mV. Doing so causes these diodes to become forward- biased and start conducting into the substrate. These diodes can 100...010 conduct up to 10 mA without causing irreversible damage to 100...001 100...000 the part. –V +1LSB V +V –1LSB REF REF REF The C1 capacitors in Figure 20 are typically 4 pF and can Figure 18. AD7938/AD7939 Ideal Transfer Characteristic primarily be attributed to pin capacitance. The resistors are with Twos Complement Output Coding and 2 × VREF Range lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. TYPICAL CONNECTION DIAGRAM The C2 capacitors are the sampling capacitors of the ADC and Figure 19 shows a typical connection diagram for the typically have a capacitance of 45 pF. AD7938/AD7939. The AGND and DGND pins are connected together at the device for good noise suppression. The For ac applications, removing high frequency components from VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 μF the analog input signal is recommended by the use of an RC capacitor to avoid noise pickup if the internal reference is used. low-pass filter on the relevant analog input pins. In applications Alternatively, VREFIN/VREFOUT can be connected to an external where harmonic distortion and signal-to-noise ratio are critical, reference source. In this case, the reference pin should be the analog input should be driven from a low impedance decoupled with a 0.1 μF capacitor. In both cases, the analog source. Large source impedances significantly affect the ac input range can either be 0 V to V (RANGE bit = 0) or 0 V to REF performance of the ADC. This may necessitate the use of an 2 × V (RANGE bit = 1). The analog input configuration can REF input buffer amplifier. The choice of the op amp is a function of be either eight single-ended inputs, four differential pairs, four the particular application. pseudo differential pairs, or seven pseudo differential inputs V DD (see Table 10). The VDD pin is connected to either a 3 V or 5 V supply. The voltage applied to the VDRIVE input controls the D R1 C2 V voltage of the digital interface. Here, it is connected to the same IN+ D 3 V supply of the microprocessor to allow a 3 V logic interface C1 (see the Digital Inputs section). 3V/5V V DD + + SUPPLY 0.1µF 10µF D R1 C2 V IN– V DD AD7938/AD7939 D C1 W/B V 0 IN CLKIN 0 TO V / CS REF Figure 20. Equivalent Analog Input Circuit, 0 TO 2 × V REF RD Conversion Phase: Switches Open, Track Phase: Switches Closed WR V 7 IN BUSY When no amplifier is used to drive the analog input, the source CONVST impedance should be limited to low values. The maximum DB0 AGND source impedance depends on the amount of THD that can be DGND DB11/DB9 tolerated. The THD increases as the source impedance increases V /V REFIN REFOUT V DRIVE + + and performance degrades. Figure 21 and Figure 22 show a 0.1µF 10µF 3V graph of the THD vs. source impedance with a 50 kHz input 2.5V SUPPLY V REF tone for both VDD = 5 V and 3 V in single-ended mode and fully + 0.1µF EXTERNAL V REF 0.47µF INTERNAL V REF differential mode, respectively. Figure 19. Typical Connection Diagram Rev. C | Page 19 of 36 ADC CODE MICROCONTROLLER/ MICROPROCESSOR 03715-026 03715-027 03715-028 AD7938/AD7939 Data Sheet –40 F = 50kHz ANALOG INPUTS IN –45 The AD7938/AD7939 have software-selectable analog input –50 configurations. The user can choose eight single-ended inputs, V = 3V DD –55 four fully differential pairs, four pseudo differential pairs, or –60 seven pseudo differential inputs. The analog input –65 configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see Table 10). –70 –75 Single-Ended Mode V = 5V DD –80 The AD7938/AD7939 can have eight single-ended analog input –85 channels by setting the MODE0 and MODE1 bits in the control –90 register to 0. In applications where the signal source has a high 10 100 1k impedance, it is recommended to buffer the analog input before R (Ω) SOURCE applying it to the ADC. An op amp suitable for this function is Figure 21. THD vs. Source Impedance in Single-Ended Mode the AD8021. The analog input range of the AD7938/AD7939 can be programmed to be either 0 V to VREF or 0 V to 2 × VREF. –60 If the analog input signal to be sampled is bipolar, the internal F = 50kHz IN –65 reference of the ADC can be used to externally bias up this signal to make it the correct format for the ADC. –70 Figure 24 shows a typical connection diagram when operating –75 the ADC in single-ended mode. This diagram shows a bipolar –80 signal of amplitude ±1.25 V being preconditioned before it is applied to the AD7938/AD7939. In cases where the analog –85 V = 3V DD input amplitude is ±2.5 V, the 3R resistor can be replaced with a –90 resistor of value R. The resultant voltage on the analog input of V = 5V DD the AD7938/AD7939 is a signal ranging from 0 V to 5 V. In this –95 case, the 2 × V mode can be used. REF –100 10 100 1k +2.5V R R (Ω) SOURCE +1.25V 0V Figure 22. THD vs. Source Impedance in Fully Differential Mode R 0V V IN V 0 –1.25V 3R IN AD7938/ Figure 23 shows a graph of the THD vs. the analog input AD7939* R frequency for various supplies while sampling at 1.5 MHz with an SCLK of 25.5 MHz. In this case, the source impedance V 7 IN V REFOUT is 10 Ω. R –50 0.47µF V = 3V DD –60 SINGLE-ENDED MODE *ADDITIONAL PINS OMITTED FOR CLARITY. V = 5V –70 DD Figure 24. Single-Ended Mode Connection Diagram SINGLE-ENDED MODE –80 Differential Mode V = 5V/3V DD –90 The AD7938/AD7939 can have four differential analog input DIFFERENTIAL MODE pairs by setting the MODE0 and MODE1 bits in the control –100 register to 0 and 1, respectively. –110 Differential signals have some benefits over single-ended F = 1.5MSPS SAMPLE RANGE = 0 TO V REF signals, including noise immunity based on the device’s –120 0 100 200 300 400 500 600 700 common-mode rejection and improvements in distortion INPUT FREQUENCY (kHz) performance. Figure 25 defines the fully differential analog Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages input of the AD7938/AD7939. Rev. C | Page 20 of 36 THD (dB) THD (dB) THD (dB) 03715-020 03715-019 03715-018 03715-031 Data Sheet AD7938/AD7939 4.5 T = 25°C A V REF V 4.0 IN+ p-p AD7938/ 3.5 AD7939* V REF V IN– p-p 3.0 COMMON-MODE VOLTAGE 2.5 2.0 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 25. Differential Input Definition 1.5 1.0 The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− pins in each 0.5 differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be 0 0.1 0.6 1.1 1.6 2.1 2.6 simultaneously driven by two signals each of amplitude VREF (or V (V) REF 2 × VREF depending on the range chosen) that are 180° out of Figure 27. Input Common-Mode Range vs. V (2 × V Range, V = 5 V) REF REF DD phase. The amplitude of the differential signal is therefore −V REF to +V peak-to-peak (that is, 2 × V ). This is regardless of REF REF Driving Differential Inputs the common mode (CM). The common mode is the average of Differential operation requires that VIN+ and VIN− be the two signals (that is, (VIN+ + VIN−)/2) and is therefore the simultaneously driven with two equal signals that are 180° out voltage on which the two inputs are centered. This results in the of phase. The common mode must be set up externally and has span of each input being CM ± VREF/2. This voltage has to be set a range that is determined by VREF, the power supply, and the up externally and its range varies with the reference value VREF. particular amplifier used to drive the analog inputs. Differential As the value of VREF increases, the common-mode range modes of operation with either an ac or dc input provide the decreases. When driving the inputs with an amplifier, the actual best THD performance over a wide frequency range. Since not common-mode range is determined by the amplifier’s output all applications have a signal preconditioned for differential voltage swing. operation, there is often a need to perform single-ended-to- differential conversion. Figure 26 and Figure 27 show how the common-mode range typically varies with VREF for a 5 V power supply using the 0 V Using an Op Amp Pair to VREF range or 2 × VREF range, respectively. The common An op amp pair can be used to directly couple a differential mode must be in this range to guarantee the functionality of signal to one of the analog input pairs of the AD7938/AD7939. the AD7938/AD7939. The circuit configurations shown in Figure 28 and Figure 29 When a conversion takes place, the common mode is rejected, show how a dual op amp can be used to convert a single-ended resulting in a virtually noise-free signal of amplitude −V to signal into a differential signal for both a bipolar and unipolar REF +V , corresponding to the digital codes of 0 to 4096 for the input signal, respectively. REF AD7938 and 0 to 1024 for the AD7939. If the 2 × VREF range is The voltage applied to Point A sets up the common-mode used, the input signal amplitude extends from −2 VREF to +2 VREF voltage. In both diagrams, it is connected in some way to the after conversion. reference, but any value in the common-mode range can be 3.5 input here to set up the common mode. A suitable dual op amp T = 25°C A that can be used in this configuration to provide differential 3.0 drive to the AD7938/AD7939 is the AD8022. 2.5 Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. 2.0 The driver circuits in Figure 28 and Figure 29 are optimized for 1.5 dc coupling applications requiring best distortion performance. 1.0 The differential op amp driver circuit in Figure 28 is configured to convert and level shift a single-ended, ground-referenced 0.5 (bipolar) signal to a differential signal centered at the VREF level 0 of the ADC. 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF The circuit configuration shown in Figure 29 converts a Figure 26. Input Common-Mode Range vs. V (0 V to V Range, V = 5 V) REF REF DD unipolar, single-ended signal into a differential signal. Rev. C | Page 21 of 36 COMMON-MODE RANGE (V) 03715-032 03715-033 COMMON-MODE RANGE (V) 03715-034 AD7938/AD7939 Data Sheet 220Ω The benefit of pseudo differential inputs is that they separate 2 × V p-p REF V+ the analog input signal ground from the ADC ground, allowing 440Ω 3.75V GND 27Ω dc common-mode voltages to be cancelled. Typically, this range 2.5V 1.25V can extend from −0.3 V to +0.7 V when VDD = 3 V or −0.3 V to V– V IN+ +1.8 V when VDD = 5 V. Figure 30 shows a connection diagram 220Ω 220Ω AD7938/ for pseudo differential mode. 220Ω AD7939 V V+ IN– V REF 3.75V V p-p REF V 2.5V IN+ 27Ω A 1.25V V– AD7938/ AD7939* 0.47µF V + IN– 10kΩ 20kΩ V REF DC INPUT Figure 28. Dual Op Amp Circuit to Convert a Single-Ended VOLTAGE + 0.47µF Bipolar Signal into a Differential Unipolar Signal *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 30. Pseudo Differential Mode Connection Diagram 220Ω V p-p REF ANALOG INPUT SELECTION V V+ REF 440Ω 3.75V 27Ω 2.5V As shown in Table 10, users can set up their analog input GND 1.25V configuration by setting the values in the MODE0 and MODE1 V– V IN+ bits in the control register. Assuming the configuration has been 220Ω AD7938/ chosen, there are different ways of selecting the analog input to 220Ω AD7939 V be converted depending on the state of the SEQ and SHDW bits V+ IN– V REF 3.75V in the control register. 2.5V 27Ω 1.25V A V– Traditional Multichannel Operation (SEQ = SHDW = 0) 0.47µF Any one of eight analog input channels or four pairs of channels + 10kΩ 20kΩ can be selected for conversion in any order by setting the SEQ and SHDW bits in the control register to 0. The channel to be Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal converted is selected by writing to the address bits, ADD2 to into a Differential Signal ADD0, in the control register to program the multiplexer prior Another method of driving the AD7938/AD7939 is to use the to the conversion. This mode of operation is that of a traditional AD8138 differential amplifier. The AD8138 can be used as a multichannel ADC where each data write selects the next single-ended-to-differential amplifier or as a differential-to- channel for conversion. Figure 31 shows a flowchart of this differential amplifier. The device is as easy to use as an op amp mode of operation. The channel configurations are shown in and greatly simplifies differential signal amplification and Table 10. driving. POWER ON Pseudo Differential Mode WRITE TO THE CONTROL REGISTER TO The AD7938/AD7939 can have four pseudo differential pairs SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION. (Pseudo Mode 1) or seven pseudo differential inputs (Pseudo SET SEQ = SHDW = 0. SELECT THE DESIRED CHANNEL TO CONVERT (ADD2 TO ADD0). Mode 2) by setting the MODE0 and MODE1 bits in the control register to 1, 0 and 1, 1, respectively. In the case of the four ISSUE CONVST PULSE TO INITIATE A CONVERSION pseudo differential pairs, V is connected to the signal source, IN+ ON THE SELECTED CHANNEL. INITIATE A READ CYCLE TO READ THE DATA which must have an amplitude of V (or 2 × V depending REF REF FROM THE SELECTED CHANNEL. on the range chosen) to make use of the full dynamic range of INITIATE A WRITE CYCLE TO SELECT THE NEXT the part. A dc input is applied to the VIN− pin. The voltage CHANNEL TO BE CONVERTED BY CHANGING THE VALUES OF BITS ADD2 TO ADD0 applied to this input provides an offset from ground or a pseudo IN THE CONTROL REGISTER. SEQ = SHDW = 0. ground for the VIN+ input. In the case of the seven pseudo Figure 31. Traditional Multichannel Operation Flow Chart differential inputs, the seven analog input signals inputs are referred to a dc voltage applied to V . IN7 Rev. C | Page 22 of 36 03715-035 03715-036 03715-038 03715-037 Data Sheet AD7938/AD7939 Using the Sequencer: Programmable Sequence Consecutive Sequence (SEQ = 1, SHDW = 1) (SEQ = 0, SHDW = 1) A sequence of consecutive channels can be converted beginning The AD7938/AD7939 can be configured to automatically cycle with Channel 0 and ending with a final channel selected by through a number of selected channels using the on-chip writing to the ADD2 to ADD0 bits in the control register. This programmable sequencer by setting SEQ = 0 and SHDW = 1 in is done by setting the SEQ and SHDW bits in the control the control register. The analog input channels to be converted register to 1. In this mode, the sequencer can be used without are selected by setting the relevant bits in the shadow register having to write to the shadow register. To set this mode up, the to 1 (see Table 12). next conversion, once the control register is written to, is on Channel 0, then Channel 1, and so on, until the channel Once the shadow register has been programmed with the selected by the address bits (ADD2 to ADD0) is reached. The required sequence, the next conversion executed is on the cycle begins again provided the WR input is tied high. If low, lowest channel programmed in the SHDW register. The next the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to conversion executed is on the next highest channel in the continue its preprogrammed sequence uninterrupted. Figure 33 sequence and so on. When the last channel in the sequence shows the flowchart of the consecutive sequence mode. is converted, the internal multiplexer returns to the first channel selected in the shadow register and commences the POWER ON sequence again. WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT It is not necessary to write to the control register again once a AND OUTPUT CONFIGURATION SELECT FINAL CHANNEL (ADD2 TO ADD0) IN sequencer operation has been initiated. The WR input must be CONSECUTIVE SEQUENCE. SET SEQ = 1 SHDW = 1. kept high to ensure that the control register is not accidentally overwritten or that a sequence operation is not interrupted. If CONTINUOUSLY CONVERT A CONSECUTIVE the control register is written to at any time during the sequence, SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY ensure that the SEQ and SHDW bits are set to 1, 0 to avoid SELECTED FINAL CHANNEL ON ADD2 TO ADD0 WITH EACH CONVST PULSE. interrupting the conversion sequence. The sequence program SEQ BIT = 1 remains in force until such time as the AD7938/AD7939 is SHDW BIT = 0 written to and the SEQ and SHDW bits are configured with any CONTINUOUSLY CONVERT bit combination except 1, 0. Figure 32 shows a flow chart of the CONSECUTIVE CHANNELS SELECTED WITH EACH CONVST PULSE BUT programmable sequence operation. ALLOWS THE RANGE, CODING, ANALOG INPUT TYPE, ETC. BITS IN THE CONTROL REGISTER TO BE CHANGED WITHOUT INTERRUPTING POWER ON THE SEQUENCE. WRITE TO THE CONTROL REGISTER TO Figure 33. Consecutive Sequence Mode Flow Chart SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SET SEQ = 0 SHDW = 1. REFERENCE The AD7938/AD7939 can operate with either the on-chip INITIATE A WRITE CYCLE. THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER. reference or external reference. The internal reference is SET RELEVANT BITS TO SELECT THE CHANNELS TO BE INCLUDED IN THE SEQUENCE. selected by setting the REF bit in the internal control register WR = HIGH SEQ BIT = 1 SEQ BIT = 0 SHDW BIT = 0 to 1. A block diagram of the internal reference circuitry is SHDW BIT = 1 shown in Figure 34. The internal reference circuitry includes an CONTINUOUSLY CONVERT CONTINUOUSLY CONVERT on-chip 2.5 V band gap reference and a reference buffer. When CONSECUTIVE CONSECUTIVE CHANNELS SELECTED CHANNELS SELECTED using the internal reference, the VREFIN/VREFOUT pin should be IN THE SHADOW REGISTER WITH EACH CONVST PULSE WITH EACH CONVST PULSE. BUT ALLOWS THE RANGE, decoupled to AGND with a 0.47 μF capacitor. This internal CODING, ANALOG INPUT TYPE, ETC BITS IN THE CONTROL reference not only provides the reference for the analog-to- REGISTER TO BE CHANGED WITHOUT INTERRUPTING digital conversion, but it can also be used externally in the THE SEQUENCE. system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere Figure 32. Programmable Sequence Flow Chart in the system. BUFFER REFERENCE V / REFIN V REFOUT AD7938/ ADC AD7939 Figure 34. Internal Reference Circuit Block Diagram Rev. C | Page 23 of 36 04751-039 03715-041 03715-040 AD7938/AD7939 Data Sheet Alternatively, an external reference can be applied to the V / REFIN Digital Inputs V pin of the AD7938/AD7939. An external reference REFOUT The digital inputs applied to the AD7938/AD7939 are not input is selected by setting the REF bit in the internal control limited by the maximum ratings that limit the analog inputs. register to 0. The external reference input range is 0.1 V to VDD. Instead, the digital inputs applied can go to 7 V and are not It is important to ensure that, when choosing the reference restricted by the VDD + 0.3 V limit as on the analog inputs. value, the maximum analog input range (VIN MAX) is never greater than VDD + 0.3 V, to comply with the maximum ratings Another advantage of the digital inputs not being restricted by of the device. For example, if operating in differential mode and the V + 0.3 V limit is the fact that power supply sequencing DD the reference is sourced from V , the 0 V to 2 × V range DD REF issues are avoided. If any of these inputs are applied before V , DD cannot be used. This is because the analog input signal range there is no risk of latch-up as there would be on the analog now extends to 2 × VDD, which exceeds the maximum rating inputs if a signal greater than 0.3 V was applied prior to VDD. conditions. In the pseudo differential modes, the user must V Input DRIVE ensure that VREF + (VIN−) ≤ VDD when using the 0 V to VREF range, or when using the 2 × VREF range that 2 × VREF + (VIN−) ≤ VDD. The AD7938/AD7939 have a V feature. V controls the DRIVE DRIVE voltage at which the parallel interface operates. V allows the DRIVE In all cases, the specified reference is 2.5 V. ADC to easily interface to 3 V and 5 V processors. The performance of the part with different reference values is For example, if the AD7938/AD7939 are operated with an VDD shown in Figure 10 to Figure 12. The value of the reference sets of 5 V and the VDRIVE pin is powered from a 3 V supply, the the analog input span and the common-mode voltage range. AD7938/AD7939 have better dynamic performance with an Errors in the reference source result in gain errors in the VDD of 5 V while still being able to interface directly to 3 V AD7938/AD7939 transfer function and add to specified full- processors. Care should be taken to ensure V does not DRIVE scale errors on the part. exceed V by more than 0.3 V (see the Absolute Maximum DD Ratings section). Table 13 lists examples of suitable voltage references available from Analog Devices that can be used. Figure 35 shows a typical connection diagram for an external reference. Table 13. Examples of Suitable Voltage References Output Initial Accuracy Operating Reference Voltage (V) (% Max) Current (µA) AD780 2.5/3 0.04 1000 ADR421 2.5 0.04 500 ADR420 2.048 0.05 500 AD7938/ AD780 AD7939* V NC 1 O/P SELECT 8 NC REF V DD 2 +V 7 NC IN 2.5V 3 TEMP V 6 OUT 0.1µF 10nF 0.1µF 0.1µF 4 GND TRIM 5 NC NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. Typical V Connection Diagram REF Rev. C | Page 24 of 36 03715-029 Data Sheet AD7938/AD7939 PARALLEL INTERFACE At the end of the conversion, BUSY goes low and can be used to CS RD activate an interrupt service routine. The and lines are The AD7938/AD7939 have a flexible, high speed, parallel then activated in parallel to read the 12- or 10-bits of conversion interface. This interface is 12-bits (AD7938) or 10-bits data. When power supplies are first applied to the device, a (AD7939) wide and is capable of operating in either word rising edge on CONVST is necessary to put the track-and-hold B B CONVST (W/ tied high) or byte (W/ tied low) mode. The into track. The acquisition time of 125 ns minimum must be signal is used to initiate conversions; when operating in allowed before CONVST is brought low to initiate a conversion. autoshutdown or autostandby mode, it is used to initiate CONVST The ADC then goes into hold on the falling edge of power-up. th and back into track on the 13 rising edge of CLKIN after this A falling edge on the CONVST signal is used to initiate (see Figure 36). When operating the device in autoshutdown or conversions and it puts the ADC track-and-hold into track. autostandby mode, where the ADC powers down at the end of Once the CONVST signal goes low, the BUSY signal goes high each conversion, a rising edge on the CONVST signal is used to for the duration of the conversion. In between conversions, power up the device. CONVST must be brought high for a minimum time of t1. This th must happen after the 14 falling edge of CLKIN; otherwise, the conversion is aborted and the track-and-hold goes back into track. B t 1 A CONVST t CONVERT 12 3 4 5 12 13 14 t 2 CLKIN t 20 t 3 BUSY t 9 INTERNAL t ACQUISITION TRACK/HOLD CS t t 11 10 RD t 12 t t 13 14 THREE-STATE DB0 TO DB11 DATA THREE-STATE t QUIET WITH CS AND RD TIED LOW DB0 TO DB11 OLD DATA DATA Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1) Rev. C | Page 25 of 36 03715-004 AD7938/AD7939 Data Sheet Reading Data from the AD7938/AD7939 CS RD The and signals are gated internally and the level is CS triggered active low. In either word mode or byte mode, and With the W/B pin tied logic high, the AD7938/AD7939 RD can be tied together because the timing specifications for t interface operates in word mode. In this case, a single read 10 operation from the device accesses the conversion data-word and t11 are 0 ns minimum. This means the bus is constantly on Pins DB0/DB2 to Pin DB11. The DB8/HBEN pin assumes driven by the AD7938/AD7939. B its DB8 function. With the W/ pin tied to logic low, the The data is placed onto the data bus a time t after both CS and 13 AD7938/AD7939 interface operates in byte mode. In this case, RD RD go low. The rising edge can be used to latch data out of the DB8/HBEN pin assumes its HBEN function. Conversion the device. After a time, t , the data lines become three-stated. 14 data from the AD7938/AD7939 must be accessed in two read operations with eight bits of data provided on DB0 to DB7 for CS RD Alternatively, and can be tied permanently low and the each of the read operations. The HBEN pin determines whether conversion data is valid and placed onto the data bus a time, t , 9 the read operation accesses the high byte or the low byte of the before the falling edge of BUSY. 12-bit or 10-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For 10-bit operation, the two Note that if RD is pulsed during the conversion time, this LSBs of the low byte are 0s, followed by six bits of conversion causes a degradation in linearity performance of approximately data. For a high byte read, DB0 to DB3 provide the four MSBs CS 0.25 LSB. Reading during conversion by way of tying and of the 12-bit or10-bit word. DB5 to DB7 of the high byte RD low does not cause any degradation. provide the channel ID. Figure 36 shows the read cycle timing diagram for a 12-bit or 10-bit transfer. When operating in word mode, the HBEN input does not exist, and only the first read operation is required to access data from the device. When operating in byte mode, the two read cycles shown in Figure 37 are required to access the full data-word from the device. HBEN/DB8 t t 15 16 t t 15 16 CS t t 10 11 t 17 t 12 RD t t 13 14 DB0 TO DB7 LOW BYTE HIGH BYTE B Figure 37. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0) Rev. C | Page 26 of 36 03715-005 Data Sheet AD7938/AD7939 Writing Data to the AD7938/AD7939 Figure 38 shows the write cycle timing diagram of the AD7938/AD7939 in word mode. When operating in word With W/B tied logic high, a single write operation transfers the mode, the HBEN input does not exist and only one write full data-word on DB0 to DB11 to the control register on the operation is required to write the word of data to the device. AD7938/AD7939. The DB8/HBEN pin assumes its DB8 Data should be provided on DB0 to DB11. When operating in function. Data written to the AD7938/AD7939 should be byte mode, the two write cycles shown in Figure 39 are required provided on the DB0 to DB11 inputs, with DB0 being the LSB to write the full data-word to the AD7938/AD7939. In Figure 39, B of the data-word. With W/ tied logic low, the the first write transfers the lower eight bits of the data-word AD7938/AD7939 requires two write operations to transfer a full from DB0 to DB7, and the second write transfers the upper four 12-bit word. DB8/HBEN assumes its HBEN function. Data bits of the data-word. When writing to the AD7938/AD7939, the written to the AD7938/AD7939 should be provided on the DB0 top four bits in the high byte must be 0s. to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word The data is latched into the device on the rising edge of WR. should be written first with DB0 being the LSB of the full data- The data needs to be setup a time, t , before the WR rising edge 7 word. For the high byte write, HBEN should be high and the and held for a time, t , after the WR rising edge. The CS and 8 data on the DB0 input should be data Bit 8 of the 12-bit word. WR signals are gated internally. CS and WR can be tied In both word and byte mode, a single write operation to the together as the timing specifications for t and t are 0 ns 4 5 shadow register is always sufficient since it is only eight bits CS RD minimum (assuming and have not already been tied wide. together). CS t t 4 5 WR t 6 t 8 t 7 DB0TODB11 DATA B Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1) HBEN/DB8 t t 18 19 t t 18 19 CS t t 4 5 t 17 t 6 WR t t 7 8 DB0TODB11 LOWBYTE HIGHBYTE B Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0) Rev. C | Page 27 of 36 03715-002 03715-003 AD7938/AD7939 Data Sheet Autostandby (PM1 = 1; PM0 = 0) POWER MODES OF OPERATION In this mode of operation, the AD7938/AD7939 automatically The AD7938/AD7939 have four different power modes of enter standby mode at the end of each conversion, which is operation. These modes are designed to provide flexible power shown as Point A in Figure 36. When this mode is entered, all management options. Different options can be chosen to circuitry on the AD7938/AD7939 is powered down except for optimize the power dissipation/throughput rate ratio for the reference and reference buffer. The track-and-hold goes into differing applications. The mode of operation is selected by the hold at this point also and remains in hold as long as the device power management bits, PM1 and PM0, in the control register, is in standby. The parts remain in standby until the next rising as detailed in Table 9. When power is first applied to the CONVST edge of powers up the device. The power-up time AD7938/AD7939, an on-chip, power-on reset circuit ensures that the default power-up condition is normal mode. required depends on whether the internal or external reference is used. With an external reference, the power-up time required Note that, after power-on, the track-and-hold is in hold mode is a minimum of 600 ns, while when using the internal CONVST and the first rising edge of places the track-and-hold reference, the power-up time required is a minimum of 7 μs. into track mode. The user should ensure this power-up time has elapsed before initiating another conversion as shown in Figure 40. This Normal Mode (PM1 = PM0 = 0) CONVST rising edge of also places the track-and-hold back This mode is intended for the fastest throughput rate into track mode. performance because the user does not have to worry about any power-up times associated with the AD7938/AD7939. It Full Shutdown Mode (PM1 =1; PM0 = 1) remains fully powered up at all times. At power-on reset, this When this mode is programmed, all circuitry on the mode is the default setting in the control register. AD7938/AD7939 is powered down upon completion of the WR write operation, that is, on the rising edge of . The track- Autoshutdown (PM1 = 0; PM0 = 1) and-hold enters hold mode at this point. The parts retain In this mode of operation, the AD7938/AD7939 automatically the information in the control register while the part is in enter full shutdown at the end of each conversion, which is shutdown. The AD7938/AD7939 remain in full shutdown shown at Point A in Figure 36 and Figure 40. In shutdown mode, with the track-and-hold in hold mode, until the power mode, all internal circuitry on the device is powered down. management bits (PM1 and PM0) in the control register are The parts retain information in the control register during changed. If a write to the control register occurs while the part shutdown. The track-and-hold also goes into hold at this point is in full shutdown mode, and the power management bits are and remains in hold as long as the device is in shutdown. The changed to PM0 = PM1 = 0 (normal mode), the part begins to AD7938/AD7939 remains in shutdown mode until the next WR power up on the rising edge and the track-and-hold returns rising edge of CONVST (see Point B in Figure 36 or Figure 40). to track. To ensure the part is fully powered up before a conversion In order to keep the device in shutdown for as long as possible, is initiated, the power-up time of 10 ms minimum should be CONVST should idle low between conversions, as shown in allowed before the next CONVST falling edge; otherwise, Figure 40. On this rising edge, the part begins to power-up and invalid data is read. the track-and-hold returns to track mode. The power-up time required is 10 ms minimum regardless of whether the user is Note that all power-up times quoted apply with a 470 nF operating with the internal or external reference. The user capacitor on the V pin. REFIN should ensure that the power-up time has elapsed before initiating a conversion. t POWER-UP B A CONVST 1 14 1 14 CLKIN BUSY Figure 40. Autoshutdown/Autostandby Mode Rev. C | Page 28 of 36 03715-049 Data Sheet AD7938/AD7939 10 POWER vs. THROUGHPUT RATE T = 25°C A 9 A considerable advantage of powering the ADC down after a 8 V = 5V DD conversion is that the power consumption of the part is 7 significantly reduced at lower throughput rates. When using the 6 different power modes, the AD7938/AD7939 are only powered up for the duration of the conversion. Therefore, the average 5 power consumption per cycle is significantly reduced. Figure 41 4 shows a plot of the power vs. throughput rate when operating in V = 3V DD 3 autostandby mode for both VDD = 5 V and 3 V. For example, if 2 the maximum CLKIN frequency of 25.5 MHz is used to 1 minimize the conversion time, this accounts for only 0.525 µs of 0 the overall cycle time while the AD7938/AD7939 remains in 0 200 400 600 800 1000 1200 1400 1600 THROUGHPUT (kSPS) standby mode for the remainder of the cycle. If the devices run at a throughput rate of 10 kSPS, for example, the overall cycle Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference time is 100 µs. MICROPROCESSOR INTERFACING Figure 42 shows a plot of the power vs. throughput rate when AD7938/AD7939 to ADSP-21xx Interface operating in normal mode for both VDD = 5 V and VDD = 3 V. In Figure 43 shows the AD7938/AD7939 interfaced to the ADSP- both plots, the figures apply when using the internal reference. 21xx series of DSPs as a memory-mapped device. A single wait If an external reference is used, the power-up time reduces to state may be necessary to interface the AD7938/AD7939 to the 600 ns; therefore, the AD7938/AD7939 remain in standby for a ADSP-21xx depending on the clock speed of the DSP. The wait greater time in every cycle. Additionally, the current consumption, state can be programmed via the data memory wait state when converting, should be lower than the specified maximum control register of the ADSP-21xx (see the ADSP-21xx family of 2.7 mA with VDD = 5 V, or 2.0 mA with VDD = 3 V. User’s Manual for details). The following instruction reads from 1.8 the AD7938/AD7939: T = 25°C A 1.6 MR = DM (ADC) 1.4 V = 5V DD where ADC is the address of the AD7938/AD7939. 1.2 DSP/USER SYSTEM 1.0 0.8 CONVST A0 TO A15 ADDRESS BUS V = 3V AD7938/ DD 0.6 ADSP-21xx* AD7939* ADDRESS DMS CS 0.4 DECODER IRQ2 BUSY 0.2 WR WR 0 0 20 40 60 80 100 120 140 RD RD THROUGHPUT (kSPS) DB0 TO DB11 Figure 41. Power vs. Throughput in Autostandby Mode Using Internal Reference D0 TO D23 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 43. Interfacing to the ADSP-21xx Rev. C | Page 29 of 36 POWER (mW) 03715-042 POWER (mW) 03715-043 03715-045 AD7938/AD7939 Data Sheet DSP/USER SYSTEM AD7938/AD7939 to ADSP-21065L Interface Figure 44 shows a typical interface between the CONVST A0 TO A15 ADDRESS BUS AD7938/AD7939 and the ADSP-21065L SHARC® processor. TMS32020/ AD7938/ TMS320C25/ This interface is an example of one of three DMA handshake AD7939* TMS320C50* ADDRESS MS modes. The X control line is actually three memory select IS EN CS DECODER MS lines. Internal ADDR25-24 are decoded into 3 to 0, and these READY DMAR lines are then asserted as chip selects. The 1 (DMA TMS320C25 ONLY MSC request 1) is used in this setup as the interrupt to signal the end STRB WR of conversion. The rest of the interface is a standard R/W handshaking operation. RD DSP/USER SYSTEM INT BUSY X CONVST DMD0 TO DMD15 DATA BUS DB11 TO DB0 ADDR TO ADDR ADDRESS BUS 0 23 *ADDITIONAL PINS OMITTED FOR CLARITY. ADDRESS AD7938/ MS Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x X LATCH AD7939* ADDRESS BUS AD7938/AD7939 to 80C186 Interface ADSP-21065L* ADDRESS CS DECODER Figure 46 shows the AD7938/AD7939 interfaced to the 80C186 DMAR BUSY microprocessor. The 80C186 DMA controller provides two 1 RD RD independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer WR WR consumes two bus cycles, one cycle to fetch data and the other DB0 TO DB11 to store data. After the AD7938/AD7939 finish a conversion, D0 TO D31 DATA BUS the BUSY line generates a DMA request to Channel 1 (DRQ1). *ADDITIONAL PINS OMITTED FOR CLARITY. Because of the interrupt, the processor performs a DMA read Figure 44. Interfacing to the ADSP-21065L operation that also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA AD7938/AD7939 to TMS32020, TMS320C25, and request is serviced before the completion of the next conversion. TMS320C5x Interface MICROPROCESSOR/ USER SYSTEM Parallel interfaces between the AD7938/AD7939 and the TMS32020, TMS320C25, and TMS320C5x family of DSPs are CONVST AD0 TO AD15 ADDRESS/DATA BUS shown in Figure 45. The memory mapped address chosen for A16 TO A19 the AD7938/AD7939 should be chosen to fall in the I/O ADDRESS AD7938/ ALE memory space of the DSPs. The parallel interface on the LATCH AD7939* AD7938/AD7939 is fast enough to interface to the TMS32020 ADDRESS BUS with no extra wait states. If high speed glue logic, such as 74AS 80C186* ADDRESS CS DECODER RD WR devices, is used to drive the and the lines when DRQ1 Q R interfacing to the TMS320C25, no wait states are necessary. However, if slower logic is used, data accesses can be slowed S BUSY RD RD sufficiently when reading from, and writing to, the part to require the insertion of one wait state. Extra wait states are WR WR DATA BUS DB0 TO DB11 necessary when using the TMS320C5x at their fastest clock *ADDITIONAL PINS OMITTED FOR CLARITY. speeds (see the TMS320C5x User’s Guide for details). Figure 46. Interfacing to the 80C186 Data is read from the ADC using the following instruction IN D, ADC where: D is the data memory address. ADC is the AD7938/AD7939 address. Rev. C | Page 30 of 36 03715-046 03715-047 03715-048 Data Sheet AD7938/AD7939 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The printed circuit board that houses the AD7938/AD7939 should be designed so that the analog and digital sections are The lands on the chip scale package (CP-32-2) are rectangular. separated and confined to certain areas of the board. This The printed circuit board pad for these should be 0.1 mm facilitates the use of ground planes that can be easily separated. longer than the package land length and 0.05 mm wider than Generally, a minimum etch technique is best for ground planes the package land width. The land should be centered on the since it gives the best shielding. Digital and analog ground pad. This ensures that the solder joint size is maximized. The planes should be joined in only one place, and the connection bottom of the chip scale package has a thermal pad. The should be a star ground point established as close to the ground thermal pad on the printed circuit board should be at least as pins on the AD7938/AD7939 as possible. Avoid running digital large as this exposed pad. On the printed circuit board, there lines under the device as this couples noise onto the die. The should be a clearance of at least 0.25 mm between the thermal analog ground plane should be allowed to run under the pad and the inner edges of the pad pattern. This ensures that AD7938/AD7939 to avoid noise coupling. The power supply shorting is avoided. Thermal vias can be used on the printed lines to the AD7938/AD7939 should use as large a trace as circuit board thermal pad to improve thermal performance of possible to provide low impedance paths and reduce the effects the package. If vias are used, they should be incorporated in the of glitches on the power supply line. thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be Fast switching signals, such as clocks, should be shielded with plated with 1 oz copper to plug the via. The user should connect digital ground to avoid radiating noise to other sections of the the printed circuit board thermal pad to AGND. board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on EVALUATING AD7938/AD7939 PERFORMANCE opposite sides of the board should run at right angles to each The recommended layout for the AD7938/AD7939 is outlined other. This reduces the effects of feedthrough through the in the evaluation board documentation. The evaluation board board. A microstrip technique is by far the best but is not package includes a fully assembled and tested evaluation board, always possible with a double-sided board. In this technique, documentation, and software for controlling the board from the the component side of the board is dedicated to ground planes, PC via the evaluation board controller. The evaluation board while signals are placed on the solder side. controller can be used in conjunction with the AD7938/AD7939 evaluation board, as well as many other Analog Devices evaluation Good decoupling is also important. All analog supplies should boards ending in the CB designator, to demonstrate and be decoupled with 10 µF tantalum capacitors in parallel with evaluate the ac and dc performance of the AD7938/AD7939. 0.1 µF capacitors to GND. To achieve the best performance from these decoupling components, they must be placed as The software allows the user to perform ac (fast Fourier close as possible to the device, ideally right up against the transform) and dc (histogram of codes) tests on the device. The 0.1 µF capacitors should have low effective series AD7938/AD7939. The software and documentation are on the resistance (ESR) and effective series inductance (ESI), such as CD that ships with the evaluation board. the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. C | Page 31 of 36 AD7938/AD7939 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 25 32 INDICATOR 1 24 0.50 PIN 1 4.75 BSC 3.25 INDICATOR BSC SQ EXPOSED 3.10 SQ PAD 2.95 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.80 MAX 0.30 3.50 REF 12° MAX 1.00 0.65 TYP 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY 0.30 SEATING FUNCTION DESCRIPTIONS 0.08 PLANE 0.25 0.20 REF SECTION OF THIS DATA SHEET. 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters 1.20 0.75 MAX 9.00 BSC SQ 0.60 0.45 25 32 1 24 PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN) 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 8 17 3.5° 0.15 0° 9 16 SEATING 0.08 MAX 0.05 PLANE COPLANARITY VIEW A 0.80 0.45 BSC 0.37 LEAD PITCH VIEW A 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ABA Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters Rev. C | Page 32 of 36 020607-A 05-25-2011-A Data Sheet AD7938/AD7939 ORDERING GUIDE 1 2 Model Temperature Range Linearity Error (LSB) Package Description Package Option AD7938BCPZ –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7938BCPZ-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7938BSUZ –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSUZ-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 EVAL-AD7938CBZ Evaluation Board AD7939BCPZ –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7939BCPZ-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7939BSUZ –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSUZ-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 1 Z = RoHS Compliant Part. 2 Linearity error here refers to integral linearity error. Rev. C | Page 33 of 36 AD7938/AD7939 Data Sheet NOTES Rev. C | Page 34 of 36 Data Sheet AD7938/AD7939 NOTES Rev. C | Page 35 of 36 AD7938/AD7939 Data Sheet NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03715-0-10/11(C) Rev. C | Page 36 of 36