ANALOG DEVICES AD7933

4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer AD7933/AD7934 FEATURES FUNCTIONAL BLOCK DIAGRAM V AGND Throughput rate: 1.5 MSPS DD Specified for V of 2.7 V to 5.25 V DD AD7933/AD7934 V REFIN/ Low power V REFOUT 2.5V 6 mW maximum at 1.5 MSPS with 3 V supplies VREF 13.5 mW maximum at 1.5 MSPS with 5 V supplies V 0 IN CLKIN 12-/10-BIT 4 analog input channels with a sequencer SAR ADC I/P CONVST T/H AND MUX Software configurable analog inputs CONTROL BUSY V 3 4-channel single-ended inputs IN 2-channel fully differential inputs 2-channel pseudo differential inputs SEQUENCER Accurate on-chip 2.5 V reference ±0.2% maximum @ 25°C, 25 ppm/°C maximum (AD7934) PARALLEL INTERFACE/CONTROL REGISTER V DRIVE 70 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes Full shutdown mode: 2 μA maximum DB0 DB11 CS RD WR W/B DGND 28-lead TSSOP package Figure 1. GENERAL DESCRIPTION The AD7933/AD7934 are 10-bit and 12-bit, high speed, low These parts use advanced design techniques to achieve very low power, successive approximation (SAR) analog-to-digital power dissipation at high throughput rates. They also feature converters (ADCs). The parts operate from a single 2.7 V to flexible power management options. An on-chip control 5.25 V power supply and feature throughput rates up to 1.5 MSPS. register allows the user to set up different operating conditions, The parts contain a low noise, wide bandwidth, differential track- including analog input range and configuration, output coding, and-hold amplifier that handles input frequencies up to 50 MHz. power management, and channel sequencing. PRODUCT HIGHLIGHTS The AD7933/AD7934 feature four analog input channels with a channel sequencer that allows a preprogrammed selection of 1. High throughput with low power consumption. channels to be sequentially converted. These parts can accept 2. Four analog inputs with a channel sequencer. either single-ended, fully differential, or pseudo differential 3. Accurate on-chip 2.5 V reference. analog inputs. 4. Single-ended, pseudo differential or fully differential analog inputs that are software selectable. The conversion process and data acquisition are controlled 5. Single-supply operation with VDRIVE function. using standard control inputs that allow for easy interfacing to The VDRIVE function allows the parallel interface to connect microprocessors and DSPs. The input signal is sampled on the directly to 3 V or 5 V processor systems independent of V . DD falling edge of CONVST, and the conversion is also initiated at 6. No pipeline delay. this point. CONVST 7. Accurate control of the sampling instant via a The AD7933/AD7934 has an accurate on-chip 2.5 V reference input and once-off conversion control. that is used as the reference source for the analog-to-digital Table 1. Related Devices conversion. Alternatively, this pin can be overdriven to provide Device No. of Bits No. of Channels Speed an external reference. AD7938/AD7939 12/10 8 1.5 MSPS AD7938-6 12 8 625 kSPS AD7934-6 12 4 625 kSPS Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03713-001 AD7933/AD7934 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 17 Functional Block Diagram .............................................................. 1 ADC Transfer Function............................................................. 17 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 18 Product Highlights ........................................................................... 1 Analog Input Structure.............................................................. 18 Revision History ............................................................................... 2 Analog Inputs ............................................................................. 19 Specifications..................................................................................... 3 Analog Input Selection .............................................................. 21 AD7933 Specifications................................................................. 3 Reference ..................................................................................... 22 AD7934 Specifications................................................................. 5 Parallel Interface......................................................................... 23 Timing Specifications .................................................................. 7 Power Modes of Operation ....................................................... 26 Absolute Maximum Ratings............................................................ 8 Power vs. Throughput Rate....................................................... 27 ESD Caution.................................................................................. 8 Microprocessor Interfacing....................................................... 27 Pin Configuration and Function Descriptions............................. 9 Application Hints ........................................................................... 29 Typical Performance Characteristics ........................................... 11 Grounding and Layout .............................................................. 29 Terminology .................................................................................... 13 Evaluating the AD7933/AD7934 Performance...................... 29 Control Register.............................................................................. 15 Outline Dimensions....................................................................... 30 Sequencer Operation ................................................................. 16 Ordering Guide .......................................................................... 30 Circuit Information........................................................................ 17 REVISION HISTORY 2/07—Rev. A to Rev B Changes to Timing Specifications.................................................. 7 Changes to Figure 13...................................................................... 12 12/05—Rev. 0 to Rev. A Replaced Figures.................................................................Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Added Table 1.................................................................................... 1 Changes to Specifications Section.................................................. 3 Changes to Table 5............................................................................ 9 Changes to Terminology Section.................................................. 13 Changes to Control Register Section ........................................... 15 Changes to Circuit Information Section ..................................... 17 Changes to Application Hints Section......................................... 29 1/05—Revision 0: Initial Version Rev. B | Page 2 of 32 AD7933/AD7934 SPECIFICATIONS AD7933 SPECIFICATIONS V = V = 2.7 V to 5.25 V, internal/external V = 2.5 V, unless otherwise noted. f = 25.5 MHz, f = 1.5 MSPS; T = T to DD DRIVE REF CLKIN SAMPLE A MIN 1 T , unless otherwise noted. MAX Table 2. 1 Parameter Value Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 2 Signal-to-Noise + Distortion (SINAD) 61 dB min Differential mode 60 dB min Single-ended mode 2 Total Harmonic Distortion (THD) −70 dB max 2 Peak Harmonic or Spurious Noise (SFDR) −72 dB max 2 Intermodulation Distortion (IMD) fa = 30 kHz, fb = 50 kHz Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ Channel-to-Channel Isolation −75 dB typ f = 50 kHz, f = 300 kHz IN NOISE 2 Aperture Delay 5 ns typ 2 Aperture Jitter 72 ps typ 2 Full Power Bandwidth 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 2 Integral Nonlinearity ±0.5 LSB max 2 Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits Single-Ended and Pseudo Differential Straight binary output coding Input 2 Offset Error ±2 LSB max 2 Offset Error Match ±0.5 LSB max 2 Gain Error ±1.5 LSB max 2 Gain Error Match ±0.5 LSB max Fully Differential Input Twos complement output coding 2 Positive Gain Error ±1.5 LSB max 2 Positive Gain Error Match ±0.5 LSB max 2 Zero-Code Error ±2 LSB max 2 Zero-Code Error Match ±0.5 LSB max 2 Negative Gain Error ±1.5 LSB max 2 Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Single-Ended Input Range 0 to VREF V RANGE bit = 0 0 to 2 × VREF V RANGE bit = 1 Pseudo Differential Input Range V 0 to V V RANGE bit = 0 IN+ REF 0 to 2 × V V RANGE bit = 1 REF V −0.3 to +0.7 V typ V = 3 V IN− DD −0.3 to +1.8 V typ VDD = 5 V 3 Fully Differential Input Range VIN+ and VIN− VCM ± VREF/2 V VCM = VREF/2, RANGE bit = 0 V and V V ± V V V = V , RANGE bit = 1 IN+ IN− CM REF CM REF 4 DC Leakage Current ±1 μA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold Rev. B | Page 3 of 32 AD7933/AD7934 1 Parameter Value Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 5 VREF Input Voltage 2.5 V ±1% specified performance 4 DC Leakage Current ±1 μA max V Output Voltage 2.5 V ±0.2% max @ 25°C REFOUT V Temperature Coefficient 25 ppm/°C max REFOUT 5 ppm/°C typ VREF Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth 130 μV typ 0.1 Hz to 1 MHz bandwidth V Output Impedance 10 Ω typ REF V Input Capacitance 15 pF typ When in track REF 25 pF typ When in hold LOGIC INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or VDRIVE 4 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 2.4 V min ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±3 μA max 4 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CODING bit = 0 Twos complement CODING bit = 1 CONVERSION RATE Conversion Time t + 13 t ns 2 CLK Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max POWER REQUIREMENTS VDD 2.7/5.25 V min/max VDRIVE 2.7/5.25 V min/max 6 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 0.8 mA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V 2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ FSAMPLE = 100 kSPS, VDD = 5 V 160 μA typ Static Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off Power Dissipation Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 μW typ VDD = 5 V 480 μW typ V = 3 V DD Full/Autoshutdown Mode 10 μW max V = 5 V DD 6 μW max V = 3 V DD 1 Temperature range is −40°C to +85°C. 2 See Terminology section. 3 V is the common-mode voltage. For full common-mode range, see Figure 25 and Figure 26. V and V must always remain within GND/V . CM IN+ IN− DD 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to V . See the Reference section for more information. DD 6 Measured with a midscale dc analog input. Rev. B | Page 4 of 32 AD7933/AD7934 AD7934 SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter Value Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 2 Signal-to-Noise + Distortion (SINAD) 70 dB min Differential mode 68 dB min Single-ended mode 2 71 dB min Differential mode Signal-to-Noise Ratio (SNR) 69 dB min Single-ended mode 2 −73 dB max −85 dB typ, differential mode Total Harmonic Distortion (THD) −70 dB max −80 dB typ, single-ended mode 2 Peak Harmonic or Spurious Noise (SFDR) −73 dB max −82 dB typ 2 fa = 30 kHz, fb = 50 kHz Intermodulation Distortion (IMD) Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ Channel-to-Channel Isolation −85 dB typ fIN = 50 kHz, fNOISE = 300 kHz 2 5 ns typ Aperture Delay 2 72 ps typ Aperture Jitter 2 Full Power Bandwidth 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 2 ±1 LSB max Differential mode Integral Nonlinearity ±1.5 LSB max Single-ended mode 2 Differential Nonlinearity Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits Single-Ended and Pseudo Differential Input Straight binary output coding 2 Offset Error ±6 LSB max 2 ±1 LSB max Offset Error Match 2 ±3 LSB max Gain Error 2 Gain Error Match ±1 LSB max Twos complement output coding Fully Differential Input 2 ±3 LSB max Positive Gain Error 2 Positive Gain Error Match ±1 LSB max 2 Zero-Code Error ±6 LSB max 2 Zero-Code Error Match ±1 LSB max 2 Negative Gain Error ±3 LSB max 2 ±1 LSB max Negative Gain Error Match ANALOG INPUT Single-Ended Input Range 0 to V V RANGE bit = 0 REF 0 to 2 × V V RANGE bit = 1 REF Pseudo Differential Input Range V 0 to V V RANGE bit = 0 IN+ REF 0 to 2 × VREF V RANGE bit = 1 VIN− −0.3 to +0.7 V typ VDD = 3 V −0.3 to +1.8 V typ V = 5 V DD 3 Fully Differential Input Range V and V V ± V/2 V V = V /2, RANGE bit = 0 IN+ IN− CM REF CM REF VIN+ and VIN− VCM ± VREF V VCM = VREF, RANGE bit = 1 4 DC Leakage Current ±1 μA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold Rev. B | Page 5 of 32 AD7933/AD7934 1 Parameter Value Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 5 V Input Voltage 2.5 V ±1% specified performance REF DC Leakage Current ±1 μA max V Output Voltage 2.5 V ±0.2% max @ 25°C REFOUT V Temperature Coefficient 25 ppm/°C max REFOUT 5 ppm/°C typ V Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth REF 130 μV typ 0.1 Hz to 1 MHz bandwidth VREF Output Impedance 10 Ω typ V Input Capacitance 15 pF typ When in track-and-hold REF 25 pF typ When in track-and-hold LOGIC INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or VDRIVE 4 10 pF max Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH 2.4 V min ISOURCE = 200 μA Output Low Voltage, V 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±3 μA max 4 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CODING bit = 0 Twos complement CODING bit = 1 CONVERSION RATE Conversion Time t + 13 t ns 2 CLK Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max POWER REQUIREMENTS VDD 2.7/5.25 V min/max V 2.7/5.25 V min/max DRIVE 6 IDD Digital inputs = 0 V or VDRIVE Normal Mode (Static) 0.8 mA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max V = 4.75 V to 5.25 V DD 2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ f = 100 kSPS, V = 5 V SAMPLE DD 160 μA typ Static Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off Power Dissipation Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max V = 3 V DD Autostandby Mode (Static) 800 μW typ VDD = 5 V 480 μW typ VDD = 3 V Full/Autoshutdown Mode 10 μW max V = 5 V DD 6 μW max VDD = 3 V 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 V is the common-mode voltage. For full common-mode range, see Figure 25 and Figure 26. V and V must always remain within GND/V . CM IN+ IN− DD 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to V . See the Reference section for more information. DD 6 Measured with a midscale dc analog input. Rev. B | Page 6 of 32 AD7933/AD7934 TIMING SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX 1 Parameter AD7933 AD7934 Unit Description 2 f 700 700 kHz min CLKIN frequency CLKIN 25.5 25.5 MHz max tQUIET 30 30 ns min Minimum time between end of read and start of next conversion, that is, the time from when the data bus goes into three-state until the next falling edge of CONVST t 10 10 ns min CONVST pulse width 1 t 15 15 ns min CONVST falling edge to CLKIN falling edge setup time 2 t3 50 50 ns max CLKIN falling edge to BUSY rising edge t4 0 0 ns min CS to WR setup time t5 0 0 ns min CS to WR hold time t 10 10 ns min WR pulse width 6 t 10 10 ns min Data setup time before WR 7 t 10 10 ns min Data hold after WR 8 t9 10 10 ns min New data valid before falling edge of BUSY t10 0 0 ns min CS to RD setup time t11 0 0 ns min CS to RD hold time t 30 30 ns min RD pulse width 12 3 t 30 30 ns max Data access time after RD 13 4 t 3 3 ns min RD 14 Bus relinquish time after 50 50 ns max Bus relinquish time after RD t15 0 0 ns min HBEN to RD setup time t16 0 0 ns min HBEN to RD hold time t 10 10 ns min Minimum time between reads/writes 17 t 0 0 ns min HBEN to WR setup time 18 t19 10 10 ns min HBEN to WR hold time t20 40 40 ns max CLKIN falling edge to BUSY falling edge t21 15.7 15.7 ns min CLKIN low pulse width t 7.8 7.8 ns min CLKIN high pulse width 22 1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications are with a 25 pF load capacitance (see Figure 34, Figure 35, Figure 36, and Figure 37). 2 Minimum CLKIN for specified performance; with slower SCLK frequencies, performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the 14 bus loading. Rev. B | Page 7 of 32 AD7933/AD7934 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND/DGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect V to AGND/DGND −0.3 V to V + 0.3 V DRIVE DD device reliability. Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V VDRIVE to VDD −0.3 V to VDD + 0.3 V Digital Output Voltage to AGND −0.3 V to V + 0.3 V DRIVE ESD CAUTION V to AGND −0.3 V to V + 0.3 V REFIN DD AGND to DGND −0.3 V to +0.3 V 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (TSSOP) 97.9°C/W θJC Thermal Impedance (TSSOP) 14°C/W Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) 255°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 32 AD7933/AD7934 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 V 3 DD IN 2 27 W/B V 2 IN DB0 3 26 V 1 IN DB1 4 25 V 0 IN AD7933/ 5 24 DB2 V /V REFIN REFOUT AD7934 6 23 DB3 AGND TOP VIEW (Not to Scale) DB4 7 22 CS DB5 8 21 RD DB6 9 20 WR DB7 10 19 CONVST 11 18 V CLKIN DRIVE 12 17 DGND BUSY 13 16 DB8/HBEN DB11 14 15 DB9 DB10 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. 2 W/B Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off unused data lines to DGND. 3 to 10 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the V input. When reading from the AD7933, the two LSBs (DB0 and DRIVE DB1) are always 0, and the LSB of the conversion result is available on DB2. 11 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at VDD but should never exceed VDD by more than 0.3 V. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 13 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device, DB4 and DB5 contain the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining six bits are conversion data. 14 to DB9 to Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the 16 DB11 control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the V input. DRIVE 17 BUSY Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode th just prior to the falling edge of BUSY, on the 13 rising edge of CLKIN (see Figure 34). 18 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7933/AD7934 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock. 19 CONVST Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following power- down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up the device. Rev. B | Page 9 of 32 03713-006 AD7933/AD7934 Pin No. Mnemonic Description 20 WR Write Input. Active low logic input used in conjunction with CS to write data to the control register. 21 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 22 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to the control register. 23 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 24 VREFIN/VREFOUT Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V, and this appears at this pin. It is recommended to decouple the V /V pin to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input REFIN REFOUT voltage range for the external reference is 0.1 V to VDD; however, ensure that the analog input range does not exceed VDD + 0.3 V. See the Reference section. 25 to VIN0 to VIN3 Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-and- 28 hold. The analog inputs can be programmed as four single-ended inputs, two fully differential pairs, or two pseudo differential pairs by appropriately setting the MODE bits in the control register (see Table 10). Select the analog input channel to be converted either by writing to Address Bit ADD1 and Address Bit ADD0 in the control register prior to the conversion, or by using the on-chip sequencer. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. To avoid noise pickup, connect any unused input channels to AGND. Rev. B | Page 10 of 32 AD7933/AD7934 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. –60 0 100mV p-p SINE WAVE ON V AND/OR V 4096 POINT FFT DD DRIVE –10 NO DECOUPLING V =5V DD DIFFERENTIAL/SINGLE-ENDED MODE F =1.5MSPS –70 SAMPLE –20 F = 49.62kHz IN SINAD = 70.94dB –30 INT REF THD = –90.09dB –80 DIFFERENTIAL MODE –40 –50 –90 –60 EXT REF –70 –100 –80 –90 –110 –100 –120 –110 10 210 410 610 810 1010 SUPPLY RIPPLE FREQUENCY (kHz) FREQUENCY (kHz) Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 6. AD7934 FFT @ V = 5 V DD –70 1.0 INTERNAL/EXTERNAL REFERENCE V =5V DD 0.8 V =5V DIFFERENTIAL MODE DD –75 0.6 0.4 0.2 –80 0 –85 –0.2 –0.4 –90 –0.6 –0.8 –1.0 –95 0 100 200 300 400 500 600 700 800 0 500 1000 1500 2000 2500 3000 3500 4000 NOISE FREQUENCY (kHz) CODE Figure 4. Channel-to-Channel Isolation Figure 7. AD7934 Typical DNL @ VDD = 5 V 80 1.0 V =5V V =5V DD DD 0.8 DIFFERENTIAL MODE 70 0.6 V =3V DD 0.4 60 0.2 50 0 –0.2 40 –0.4 –0.6 30 F = 1.5MSPS SAMPLE –0.8 RANGE = 0 TO V REF DIFFERENTIAL MODE –1.0 20 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE FREQUENCY (kHz) Figure 8. AD7934 Typical INL @ VDD = 5 V Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages Rev. B | Page 11 of 32 SINAD (dB) NOISE ISOLATION (dB) PSRR (dB) 03713-008 03713-021 03713-007 INL ERROR (LSB) DNL ERROR (LSB) AMPLITUDE (dB) 0 100 200 300 400 500 600 700 03713-011 03713-010 03713-009 AD7933/AD7934 10000 4 9997 INTERNAL DIFFERENTIAL MODE SINGLE-ENDED MODE CODES 9000 REF 8000 3 7000 2 6000 5000 1 4000 POSITIVE DNL 3000 0 2000 1000 NEGATIVE DNL 3CODES –1 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 2046 2047 2048 2049 2050 V (V) CODE REF Figure 9. AD7934 DNL vs. VREF for VDD = 3 V Figure 12. AD7934 Histogram of Codes for 10,000 Samples @ VDD = 5 V with Internal Reference 12 120 DIFFERENTIAL MODE 110 11 V =5V DD DIFFERENTIAL MODE 100 10 V =5V DD SINGLE-ENDED MODE 90 9 V =3V DD SINGLE-ENDED MODE 80 8 V =3V DD DIFFERENTIAL MODE 70 7 6 60 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 200 400 600 800 1000 1200 V (V) RIPPLE FREQUENCY (kHz) REF Figure 10. AD7934 ENOB vs. VREF Figure 13. CMRR vs. Common-Mode Ripple with VDD = 5 V and 3 V 0 V =5V DD –0.5 –1.0 V =3V –1.5 DD –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 SINGLE-ENDED MODE –5.0 00.5 1.0 1.5 2.0 2.5 3.0 3.5 V (V) REF Figure 11. AD7934 Offset vs. VREF Rev. B | Page 12 of 32 OFFSET (LSB) EFFECTIVE NUMBER OF BITS DNL (LSB) 03713-014 03713-013 03713-012 CMRR (dB) ??? 03713-017 03713-015 AD7933/AD7934 TERMINOLOGY Integral Nonlinearity (INL) Negative Gain Error The maximum deviation from a straight line passing through This applies when using the twos complement output coding the endpoints of the ADC transfer function. The endpoints of option, in particular to the 2 × VREF input range with −VREF to the transfer function are zero scale, 1 LSB below the first code +VREF biased about the VREF point. It is the deviation of the first transition, and full scale, 1 LSB above the last code transition. code transition (100…000) to (100…001) from the ideal (that is, −V + 1 LSB) after the zero-code error has been adjusted out. REFIN Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB Negative Gain Error Match change between any two adjacent codes in the ADC. The difference in negative gain error between any two channels. Offset Error Channel-to-Channel Isolation The deviation of the first code transition (00…000) to (00…001) Channel-to-channel isolation is a measure of the level of from the ideal (that is, AGND + 1 LSB). crosstalk between channels. It is measured by applying a full- scale sine wave signal to the three nonselected input channels Offset Error Match and applying a 50 kHz signal to the selected channel. The The difference in offset error between any two channels. channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the Gain Error noise signal on the unselected channels that appears in the FFT The deviation of the last code transition (111…110) to of this channel. The noise frequency on the unselected channels (111…111) from the ideal (that is, VREF – 1 LSB) after the offset varies from 40 kHz to 740 kHz. The noise amplitude is at error has been adjusted out. 2 × VREF, while the signal amplitude is at 1 × VREF. See Figure 4. Gain Error Match Power Supply Rejection Ratio (PSRR) The difference in gain error between any two channels. PSRR is defined as the ratio of the power in the ADC output at Zero-Code Error full-scale frequency, f, to the power of a 100 mV p-p sine wave This applies when using the twos complement output coding applied to the ADC V supply of frequency, f . The frequency DD S option, in particular to the 2 × V input range with −V to REF REF of the input varies from 1 kHz to 1 MHz. +V biased about the V point. It is the deviation of the REF REFIN PSRR (dB) = 10 log(Pf/PfS) midscale transition (all 0s to all 1s) from the ideal VIN voltage (that is, VREF). where: Zero-Code Error Match Pf is the power at frequency f in the ADC output. The difference in zero-code error between any two channels. Pf is the power at frequency f in the ADC output. S S Positive Gain Error Common-Mode Rejection Ratio (CMRR) This applies when using the twos complement output coding CMRR is defined as the ratio of the power in the ADC output at option, in particular to the 2 × V input range with −V to +V REF REF REF full-scale frequency, f, to the power of a 100 mV p-p sine wave biased about the V point. It is the deviation of the last REFIN applied to the common-mode voltage of VIN+ and VIN− of code transition (011…110) to (011…111) from the ideal (that is, frequency, fS. +VREF – 1 LSB) after the zero-code error has been adjusted out. CMRR (dB) = 10 log(Pf/PfS) Positive Gain Error Match The difference in positive gain error between any two channels. where: Pf is the power at frequency f in the ADC output. Pf is the power at frequency f in the ADC output. S S Rev. B | Page 13 of 32 AD7933/AD7934 Track-and-Hold Acquisition Time Peak Harmonic or Spurious Noise The track-and-hold amplifier returns to track mode at the end Peak harmonic or spurious noise is defined as the ratio of the of conversion. The track-and-hold acquisition time is the time rms value of the next largest component in the ADC output required for the output of the track-and-hold amplifier to reach spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of its final value, within ±½ LSB, after the end of conversion. the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for Signal-to-(Noise + Distortion) Ratio (SINAD) ADCs where the harmonics are buried in the noise floor, it is a This is the measured ratio of signal-to-noise and distortion at noise peak. the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up Intermodulation Distortion to half the sampling frequency (f /2), excluding dc. The With inputs consisting of sine waves at two frequencies, fa and SAMPLE ratio is dependent on the number of quantization levels in the fb, any active device with nonlinearities create distortion products digitization process; the more levels, the smaller the at sum and difference frequencies of mfa ± nfb where m, n = 0, quantization noise. 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the The theoretical signal-to-noise and distortion ratio for an ideal second-order terms include (fa + fb) and (fa − fb), while the N-bit converter with a sine wave input is given by third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). SINAD = (6.02 N + 1.76) dB The AD7933/AD7934 is tested using the CCIF standard where Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit two input frequencies near the top end of the input bandwidth converter, SINAD is 62 dB. are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the Total Harmonic Distortion (THD) third-order terms are usually at a frequency close to the input THD is the ratio of the rms sum of harmonics to the fundamen- frequencies. As a result, the second- and third-order terms are tal. For the AD7933/AD7934, it is defined as specified separately. The intermodulation distortion is calculated per the THD specification, as the ratio of the rms 2 2 2 2 2 ⎛ ⎞ V +V +V +V +V 2 3 4 5 6 ⎜ ⎟ THD() dB =−20 log sum of the individual distortion products to the rms amplitude ⎜ ⎟ V 1 of the sum of the fundamentals, expressed in dB. ⎝ ⎠ where: V is the rms amplitude of the fundamental. 1 V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Rev. B | Page 14 of 32 AD7933/AD7934 CONTROL REGISTER register are all 0s. When writing to the control register between The control register on the AD7933/AD7934 is a 12-bit, write- conversions, ensure that CONVST returns high before only register. Data is written to this register using the CS and performing the write. WR pins. The functions of the control register bits are described in Table 8. At power-up, the default bit settings in the control Table 7. Control Register Bits MSB LSB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PM1 PM0 CODING REF ZERO ADD1 ADD0 MODE1 MODE0 SEQ1 SEQ0 RANGE Table 8. Control Register Bit Function Description Bit No. Mnemonic Description 11, 10 PM1, PM0 Power Management Bits. Use these two bits to select the power mode of operation. The user can choose between normal mode or various power-down modes of operation as shown in Table 9. 9 CODING This bit selects the output coding of the conversion result. If the CODING bit is set to 0, the output coding is straight (natural) binary. If the CODING bit is set to 1, the output coding is twos complement. 8 REF This bit selects whether the internal or external reference is used to perform the conversion. If the REF bit is Logic 0, an external reference should be applied to the V pin, and if it is Logic 1, the internal reference is REF selected. See the Reference section. 7 ZERO This bit is not used; therefore, it should always be set to Logic 0. 6, 5 ADD1, Use these two address bits to select which analog input channel is to be converted in the next conversion, if the ADD0 sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used (see Table 11 for more information). The selected input channel is decoded as shown in Table 10. 4, 3 MODE1, The two mode pins select the type of analog input on the four V pins. The AD7933/AD7934 have either four IN MODE0 single-ended inputs, two fully differential inputs, or two pseudo differential inputs (see Table 10). 2 SEQ1 The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function (see Table 11). 1 SEQ0 The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function (see Table 11). 0 RANGE This bit selects the analog input range of the AD7933/AD7934. If RANGE is set to 0, the analog input range extends from 0 V to VREF. If RANGE is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, VDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. See the Analog Inputs section for more information. Table 9. Power Mode Selection Using the Power Management Bits in the Control Register PM1 PM0 Mode Description 0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times. 0 1 Autoshutdown When operating in autoshutdown mode, the AD7933/AD7934 enters full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. 1 0 Autostandby When the AD7933/AD7934 enters this mode, the reference remains fully powered, the reference buffer is partially powered down, and all other circuitry is fully powered down. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 μs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information. 1 1 Full Shutdown When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control register is retained. Rev. B | Page 15 of 32 AD7933/AD7934 aborted after applying 12.5 CLKIN periods to the ADC, ensure SEQUENCER OPERATION CONVST that a rising edge of or a falling edge of CLKIN is The configuration of the SEQ0 and SEQ1 bits in the control applied to the part before writing to the control register to register allows use of the sequencer function. Table 11 outlines program the sequencer. If these conditions are not met, the the two sequencer modes of operation. sequencer will not be in the correct state to handle being reprogrammed for another sequence of conversions and the Writing to the Control Register to Program the Sequencer performance of the converter is not guaranteed. The AD7933 and AD7934 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN periods, the conversion aborts. If a conversion is Table 10. Analog Input Type Selection MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1 Four Single-Ended Two Fully Differential Two Pseudo Differential Channel Address Input Channels Input Channels Input Channels Not Used ADD1 ADD0 VIN+ VIN− VIN+ VIN− VIN+ VIN− 0 0 V 0 AGND V 0 V 1 V 0 V 1 IN IN IN IN IN 0 1 VIN1 AGND VIN1 VIN0 VIN1 VIN0 1 0 VIN2 AGND VIN2 VIN3 VIN2 VIN3 1 1 VIN3 AGND VIN3 VIN2 VIN3 VIN2 Table 11. Sequence Selection Modes SEQ0 SEQ1 Sequence Type 0 0 Select this configuration when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of ADD1 and ADD0, the channel address bits, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without using the sequencer function, where each write to the AD7933/AD7934 selects the next channel for conversion. 0 1 Not used. 1 0 Not used. 1 1 Use this configuration in conjunction with ADD1 and ADD0, the channel address bits, to program continuous conversions on a consecutive sequence of channels. The sequence of channels extends from Channel 0 through to a selected final channel as determined by the channel address bits in the control register. When in differential or pseudo differential mode, inverse channels (for example, VIN1, VIN0) are not converted. Rev. B | Page 16 of 32 AD7933/AD7934 CIRCUIT INFORMATION The AD7933/AD7934 are fast, 4-channel, 10-bit and 12-bit, When the ADC starts a conversion (see Figure 15), SW3 opens single-supply, successive approximation analog-to-digital and SW1 and SW2 move to Position B, causing the comparator converters. The parts operate from a 2.7 V to 5.25 V power to become unbalanced. Both inputs are disconnected once the supply and feature throughput rates up to 1.5 MSPS. conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge The AD7933/AD7934 provide the user with an on-chip from the sampling capacitor arrays to bring the comparator track-and-hold, an internal accurate reference, an analog-to- back into a balanced condition. When the comparator is digital converter, and a parallel interface housed in a 28-lead rebalanced, the conversion is complete. The control logic TSSOP package. generates the output code of the ADC. The output impedances of the sources driving the VIN+ and the VIN− pins must match; The AD7933/AD7934 have four analog input channels that otherwise, the two inputs have different settling times, resulting can be configured to be four single-ended inputs, two fully in errors. differential pairs, or two pseudo differential pairs. There is an on-chip channel sequencer that allows the user to select a CAPACITIVE DAC consecutive sequence of channels through which the ADC can COMPARATOR CONVST cycle with each falling edge of . C B S V IN+ A SW1 The analog input range for the AD7933/AD7934 is 0 V to V CONTROL REF SW3 LOGIC SW2 A or 0 V to 2 × VREF, depending on the status of the RANGE bit in V IN– B C S the control register. The output coding of the ADC can be either V REF binary or twos complement, depending on the status of the CAPACITIVE DAC CODING bit in the control register. Figure 15. ADC Conversion Phase The AD7933/AD7934 provide flexible power management options to allow users to achieve the best power performance ADC TRANSFER FUNCTION for a given throughput rate. These options are selected by The output coding for the AD7933/AD7934 is either straight programming PM1 and PM0, the power management bits, in binary or twos complement, depending on the status of the the control register. CODING bit in the control register. The designed code transitions occur at successive LSB values (1 LSB, 2 LSBs, and so on), and CONVERTER OPERATION the LSB size is V /1024 for the AD7933 and V /4096 for the REF REF The AD7933/AD7934 are successive approximation ADCs AD7934. The ideal transfer characteristics of the AD7933/AD7934 based around two capacitive digital-to-analog converters (DACs). for both straight binary and twos complement output coding are Figure 14 and Figure 15 show simplified schematics of the ADC shown in Figure 16 and Figure 17, respectively. in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo 111...111 differential modes. Single-ended mode operation is similar but 111...110 V is internally tied to AGND. In acquisition phase, SW3 is IN− closed, SW1 and SW2 are in Position A, the comparator is held 111...000 in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 011...111 1LSB = V /4096 (AD7934) REF 1LSB = V /1024 (AD7933) REF CAPACITIVE DAC 000...010 COMPARATOR C 000...001 B S V IN+ 000...000 A SW1 1LSB +V –1LSB REF CONTROL 0V SW3 LOGIC ANALOG INPUT SW2 A V IN– B C NOTES S V REF 1. V IS EITHER V OR 2 × V . REF REF REF CAPACITIVE DAC Figure 16. AD7933/AD7934 Ideal Transfer Characteristic with Straight Binary Output Coding Figure 14. ADC Acquisition Phase Rev. B | Page 17 of 32 03713-023 ADC CODE 03713-025 03713-024 AD7933/AD7934 1LSB = 2× V /4096 (AD7934) REF ANALOG INPUT STRUCTURE 1LSB = 2× V /1024 (AD7933) REF 011...111 Figure 19 shows the equivalent circuit of the analog input 011...110 structure of the AD7933/AD7934 in differential/pseudo differential modes. In single-ended mode, VIN− is internally 000...001 tied to AGND. The four diodes provide ESD protection for the 000...000 analog inputs. Ensure that the analog input signals never exceed 111...111 the supply rails by more than 300 mV; doing so causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without 100...010 100...001 causing irreversible damage to the part. 100...000 –V +1LSB V +V –1 LSB REF REF REF The C1 capacitors in Figure 19 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are Figure 17. AD7933/AD7934 Ideal Transfer Characteristic lumped components made up of the on resistance of the with Twos Complement Output Coding and 2 × VREF Range switches. The value of these resistors is typically about 100 Ω. TYPICAL CONNECTION DIAGRAM The C2 capacitors are the sampling capacitors of the ADC and Figure 18 shows a typical connection diagram for the typically have a capacitance of 45 pF. AD7933/AD7934. The AGND and DGND pins are connected For ac applications, removing high frequency components from together at the device for good noise suppression. If the internal the analog input signal is recommended by using an RC low- reference is used, the VREFIN/VREFOUT pin is decoupled to AGND pass filter on the relevant analog input pins. In applications with a 0.47 μF capacitor to avoid noise pickup. Alternatively, where harmonic distortion and signal-to-noise ratio are critical, VREFIN/VREFOUT can be connected to an external reference source. drive the analog input from a low impedance source. Large In this case, decouple the reference pin with a 0.1 μF capacitor. source impedances significantly affect the ac performance of the In both cases, the analog input range can either be 0 V to V REF ADC. This may necessitate the use of an input buffer amplifier. (RANGE bit = 0) or 0 V to 2 × V (RANGE bit = 1). The REF The choice of the op amp is a function of the particular analog input configuration can be either four single-ended application. inputs, two differential pairs, or two pseudo differential pairs V (see Table 10). The VDD pin is connected to either a 3 V or 5 V DD supply. The voltage applied to the VDRIVE input controls the D R1 C2 voltage of the digital interface. As shown in Figure 18, it is V IN+ connected to the same 3 V supply of the microprocessor to D C1 allow a 3 V logic interface (see the Digital Inputs section). 3V/5V + + SUPPLY V DD 0.1µF 10µF D R1 C2 V V DD IN– AD7933/AD7934 D C1 W/B V 0 CLKIN IN CS 0 TO V / REF Figure 19. Equivalent Analog Input Circuit, RD 0 TO 2 × V REF V 3 IN Conversion Phase: Switches Open, Track Phase: Switches Closed WR BUSY CONVST When no amplifier is used to drive the analog input, limit the AGND DB0 source impedance to low values. The maximum source DGND DB11/DB9 impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases V /V REFIN REFOUT V DRIVE + + 0.1µF 10µF and performance degrades. Figure 20 and Figure 21 show a 3V 2.5V graph of the THD vs. source impedance with a 50 kHz input SUPPLY V REF + 0.1µF EXTERNAL V REF tone for both V = 5 V and 3 V in single-ended mode and fully DD 0.47µF INTERNAL V REF differential mode, respectively. Figure 18. Typical Connection Diagram Rev. B | Page 18 of 32 ADC CODE MICROCONTROLLER/ MICROPROCESSOR 03713-026 03713-027 03713-028 AD7933/AD7934 –40 F = 50kHz ANALOG INPUTS IN –45 The AD7933/AD7934 have software selectable analog input –50 configurations. Users can choose from among the following V =3V DD –55 configurations: four single-ended inputs, two fully differential –60 pairs, or two pseudo differential pairs. The analog input –65 configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see Table 10). –70 –75 Single-Ended Mode V =5V DD –80 The AD7933/AD7934 can have four single-ended analog input –85 channels by setting the MODE0 and MODE1 bits in the control –90 register to 0. In applications where the signal source has a high 10 100 1k impedance, it is recommended to buffer the analog input before R (Ω) SOURCE applying it to the ADC. An amplifier suitable for this function is Figure 20. THD vs. Source Impedance in Single-Ended Mode the AD8021. The analog input range of the AD7933/AD7934 –60 can be programmed to be either 0 V to VREF, or 0 V to 2 × VREF. F = 50kHz IN –65 If the analog input signal to be sampled is bipolar, the internal –70 reference of the ADC can be used to externally bias up this signal to make it the correct format for the ADC. –75 Figure 23 shows a typical connection diagram when operating –80 the ADC in single-ended mode. This diagram shows a bipolar –85 signal of amplitude ±1.25 V being preconditioned before it is V =3V DD applied to the AD7933/AD7934. In cases where the analog –90 V =5V input amplitude is ±2.5 V, the 3R resistor can be replaced with a DD –95 resistor of value R. The resultant voltage on the analog input of –100 the AD7933/AD7934 is a signal ranging from 0 V to 5 V. In this 10 100 1k case, the 2 × V mode can be used. REF R (Ω) SOURCE Figure 21. THD vs. Source Impedance in Fully Differential Mode +2.5V R +1.25V 0V R Figure 22 shows a graph of the THD vs. the analog input fre- 0V V IN V 0 quency for various supplies, while sampling at 1.5 MHz with an –1.25V 3R IN AD7933/ AD7934* SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω. R –50 V 3 IN V REFOUT V =3V DD –60 SINGLE-ENDED MODE V =5V 0.47µF –70 DD SINGLE-ENDED MODE –80 *ADDITIONAL PINS OMITTED FOR CLARITY. V =5V/3V DD Figure 23. Single-Ended Mode Connection Diagram –90 DIFFERENTIAL MODE Differential Mode –100 The AD7933/AD7934 can have two differential analog input –110 pairs by setting the MODE0 and MODE1 bits in the control F = 1.5MSPS SAMPLE RANGE = 0 TO V REF register to 0 and 1, respectively. –120 0 100 200 300 400 500 600 700 INPUT FREQUENCY (kHz) Differential signals have some benefits over single-ended Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages signals, including noise immunity based on the device’s common-mode rejection and improvements in distortion performance. Figure 24 defines the fully differential analog input of the AD7933/AD7934. Rev. B | Page 19 of 32 THD (dB) THD (dB) THD (dB) 03713-020 03713-019 03713-018 03713-031 AD7933/AD7934 4.5 T = 25°C A V REF V 4.0 IN+ p-p AD7933/ 3.5 AD7934* V REF V IN– p-p 3.0 COMMON-MODE VOLTAGE 2.5 2.0 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 24. Differential Input Definition 1.5 1.0 The amplitude of the differential signal is the difference between the signals applied to the V and V pins in each IN+ IN− 0.5 differential pair (that is, V − V ). V and V should be IN+ IN− IN+ IN− 0 0.1 0.6 1.1 1.6 2.1 2.6 simultaneously driven by two signals, each of amplitude V (V) REF VREF (or 2 × VREF depending on the range chosen) that are Figure 26. Input Common-Mode Range vs. V REF 180° out of phase. The amplitude of the differential signal is, (2 × V Range, V = 5 V) REF DD therefore, −VREF to +VREF peak-to-peak (that is, 2 × VREF). This is Driving Differential Inputs regardless of the common mode (CM). The common mode is the average of the two signals (that is (V + V )/2) and is, IN+ IN− Differential operation requires that V and V be simultane- IN+ IN− therefore, the voltage on which the two inputs are centered. ously driven with two equal signals that are 180° out of phase. This results in the span of each input being CM ± V /2. This REF The common mode must be set up externally and has a range voltage has to be set up externally and its range varies with the that is determined by VREF, the power supply, and the particular reference value, VREF. As the value of VREF increases, the amplifier used to drive the analog inputs. Differential modes of common-mode range decreases. When driving the inputs with operation with either an ac or dc input provide the best THD an amplifier, the actual common-mode range is determined by performance over a wide frequency range. Since not all applica- the output voltage swing of the amplifier. tions have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential Figure 25 and Figure 26 show how the common-mode range conversion. typically varies with V for a 5 V power supply using the 0 V REF to V range or 2 × V range, respectively. The common REF REF Using an Op Amp Pair mode must be in this range to guarantee the functionality of the An op amp pair can be used to directly couple a differential AD7933/AD7934. signal to one of the analog input pairs of the AD7933/AD7934. The circuit configurations shown in Figure 27 and Figure 28 When a conversion takes place, the common mode is rejected, show how a dual op amp converts a single-ended signal into a resulting in a virtually noise-free signal of amplitude −VREF to differential signal for both a bipolar and unipolar input signal, +V corresponding to the digital codes of 0 to 1024 for the REF respectively. AD7933, and 0 to 4096 for the AD7934. If the 2 × V range is REF used, the input signal amplitude extends from −2 V to REF The voltage applied to Point A sets up the common-mode +2 V . REF voltage. In both diagrams, it is connected in some way to the 3.5 reference, but any value in the common-mode range can be T = 25°C A input here to set up the common mode. The AD8022 is a 3.0 suitable dual op amp that can be used in this configuration to provide differential drive to the AD7933/AD7934. 2.5 Take care when choosing the op amp; the selection depends on 2.0 the required power supply and system performance objectives. 1.5 The driver circuits in Figure 27 and Figure 28 are optimized for dc coupling applications requiring best distortion performance. 1.0 The circuit configuration shown in Figure 27 is configured to 0.5 convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level 0 00.5 1.0 1.5 2.0 2.5 3.0 of the ADC. V (V) REF Figure 25. Input Common-Mode Range vs. VREF The circuit in Figure 28 converts a unipolar, single-ended signal (0 V to VREF Range, VDD = 5 V) into a differential signal. Rev. B | Page 20 of 32 COMMON-MODE RANGE (V) 03713-032 03713-033 COMMON-MODE RANGE (V) 03713-034 AD7933/AD7934 220Ω V p-p REF 2×V p-p REF V IN+ V+ 440Ω 3.75V GND 27Ω AD7933/ 2.5V AD7934* 1.25V V V– IN– V IN+ 220Ω 220Ω V REF AD7933/ DC INPUT 220Ω AD7934 VOLTAGE + 0.47µF V V+ IN– V REF 3.75V 2.5V 27Ω 1.25V A *ADDITIONAL PINS OMITTED FOR CLARITY. V– Figure 29. Pseudo Differential Mode Connection Diagram 0.47µF + 10kΩ 20kΩ ANALOG INPUT SELECTION As shown in Table 10, users can set up their analog input Figure 27. Dual Op Amp Circuit to Convert a Single-Ended configuration by setting the values in the MODE0 and MODE1 Bipolar Signal into a Unipolar Differential Signal bits in the control register. Assuming the configuration has been chosen, there are two different ways of selecting the analog input to be converted depending on the state of the SEQ0 and 220Ω V p-p REF SEQ1 bits in the control register. V V+ REF 440Ω 3.75V 27Ω Traditional Multichannel Operation (SEQ0 = SEQ1 = 0) 2.5V GND 1.25V Any one of four analog input channels or two pairs of channels V– V IN+ can be selected for conversion in any order by setting the SEQ0 220Ω AD7933/ and SEQ1 bits in the control register to 0. The channel to be 220Ω AD7934 V converted is selected by writing to the address bits, ADD1 and V+ IN– V REF 3.75V ADD0, in the control register to program the multiplexer prior 2.5V 27Ω 1.25V A to the conversion. This mode of operation is that of a traditional V– multichannel ADC where each data write selects the next 0.47µF channel for conversion. Figure 30 shows a flowchart of this 10kΩ mode of operation. The channel configurations are shown in Table 10. Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal POWER ON Another method of driving the AD7933/AD7934 is to use the AD8138 differential amplifier. The AD8138 can be used as a WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT single-ended-to-differential amplifier, or differential-to-differential AND OUTPUT CONFIGURATION SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED amplifier. The device is as easy to use as an op amp and greatly CHANNEL TO CONVERT ON (ADD1 TO ADD0). simplifies differential signal amplification and driving. ISSUE CONVST PULSE TO INITIATE A CONVERSION ON THE SELECTED CHANNEL. Pseudo Differential Mode INITIATE A READ CYCLE TO READ THE DATA FROM THE SELECTED CHANNEL. The AD7933/AD7934 can have two pseudo differential pairs by setting the MODE0 and MODE1 bits in the control register to 1 INITIATE A WRITE CYCLE TO SELECT THE NEXT CHANNEL TO BE CONVERTED ON BY and 0, respectively. VIN+ is connected to the signal source and CHANGING THE VALUES OF BITS ADD2 TO ADD0 IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0. must have an amplitude of VREF (or 2 × VREF depending on the Figure 30. Traditional Multichannel Operation Flow Chart range chosen) to make use of the full dynamic range of the part. A dc input is applied to the V pin. The voltage applied to this IN− Using the Sequencer: Consecutive Sequence input provides an offset from ground or a pseudo ground for (SEQ0 = 1, SEQ1 = 1) the VIN+ input. The benefit of pseudo differential inputs is that A sequence of consecutive channels can be converted beginning they separate the analog input signal ground from the ADC with Channel 0 and ending with a final channel selected by ground, allowing the cancellation of dc common-mode writing to the ADD1 and ADD0 bits in the control register. This voltages. Typically, this range can extend to −0.3 V to +0.7 V is done by setting the SEQ0 and SEQ1 bits in the control when V = 3 V, or −0.3 V to +1.8 V when V = 5 V. Figure 29 DD DD register both to 1. Once the control register is written to, the shows a connection diagram for pseudo differential mode. next conversion is on Channel 0, then Channel 1, and so on until the channel selected by the Address Bit ADD1 and Address Bit ADD0 is reached. The ADC then returns to Channel 0 and Rev. B | Page 21 of 32 03713-035 03713-036 03713-038 03713-037 AD7933/AD7934 WR The performance of the part with different reference values is starts the sequence again. The input must be kept high to shown in Figure 9 to Figure 11. The value of the reference sets ensure that the control register is not accidentally overwritten the analog input span and the common-mode voltage range. and the sequence interrupted. This pattern continues until the Errors in the reference source result in gain errors in the AD7933/AD7934 is written to. Figure 31 shows the flowchart of AD7933/AD7934 transfer function and add to the specified the consecutive sequence mode. full-scale errors on the part. POWER ON Table 12 lists suitable voltage references available from Analog WRITE TO THE CONTROL REGISTER TO Devices that can be used. Figure 33 shows a typical connection SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SELECT diagram for an external reference. FINAL CHANNEL (ADD1 AND ADD0) IN CONSECUTIVE SEQUENCE. SET SEQ0 = 1 SEQ1 = 1. Table 12. Examples of Suitable Voltage References Output Initial Accuracy Operating CONTINUOUSLY CONVERT ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 Reference Voltage (V) (% maximum) Current (μA) UP TO AND INCLUDING THE PREVIOUSLY SELECTED FINAL CHANNEL ON ADD1 AND ADD0 AD780 2.5/3 0.04 1000 WITH EACH CONVST PULSE. ADR4212.5 0.04 500 Figure 31. Consecutive Sequence Mode Flow Chart ADR420 2.048 0.05 500 REFERENCE The AD7933/AD7934 can operate with either the on-chip AD7933/ AD780 AD7934* reference or an external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. V NC 1 O/P SELECT 8 NC REF V A block diagram of the internal reference circuitry is shown in 2 +V 7 NC DD IN 2.5V 3 TEMP V 6 Figure 32. The internal reference circuitry includes an on-chip OUT 0.1µF 10nF 0.1µF 0.1µF 4 GND 5 TRIM NC 2.5 V band gap reference and a reference buffer. When using the internal reference, decouple the V /V pin to AGND with a REFIN REFOUT NC = NO CONNECT 0.47 μF capacitor. This internal reference not only provides the *ADDITIONAL PINS OMITTED FOR CLARITY. reference for the analog-to-digital conversion, but it can also be Figure 33. Typical V Connection Diagram REF used externally in the system. It is recommended that the reference output is buffered using an external precision op amp Digital Inputs before applying it anywhere in the system. The digital inputs applied to the AD7933/AD7934 are not BUFFER limited by the maximum ratings that limit the analog inputs. REFERENCE Instead, the digital inputs applied can go to 7 V and are not V / REFIN V REFOUT restricted by the VDD + 0.3 V limit that is on the analog inputs. Another advantage of the digital inputs not being restricted by AD7933/ ADC AD7934 the V + 0.3 V limit is the fact that power supply sequencing DD issues are avoided. If any of these inputs are applied before V , DD Figure 32. Internal Reference Circuit Block Diagram there is no risk of latch-up as there would be on the analog inputs Alternatively, an external reference can be applied to the if a signal greater than 0.3 V was applied prior to V . DD VREFIN/VREFOUT pin of the AD7933/AD7934. An external V Input DRIVE reference input is selected by setting the REF bit in the internal The AD7933/AD7934 have a VDRIVE feature. VDRIVE controls the control register to 0. The external reference input range is 0.1 V voltage at which the parallel interface operates. V allows the to V . It is important to ensure that, when choosing the DRIVE DD ADC to easily interface to 3 V and 5 V processors. reference value, the maximum analog input range (V ) is IN MAX never greater than VDD + 0.3 V to comply with the maximum For example, if the AD7933/AD7934 are operated with a V DD ratings of the device. For example, if operating in differential of 5 V, and the VDRIVE pin is powered from a 3 V supply, the mode and the reference is sourced from VDD, the 0 V to 2 × VREF AD7933/AD7934 have better dynamic performance with a range cannot be used. This is because the analog input signal VDD of 5 V while still being able to interface to 3 V processors. range now extends to 2 × V , which exceeds the maximum DD Ensure that VDRIVE does not exceed VDD by more than 0.3 V (see rating conditions. In the pseudo differential modes, the user the Absolute Maximum Ratings section). must ensure that V + V ≤ V when using the 0 V to V REF IN− DD REF range, or when using the 2 × V range that 2 × V + V ≤ V . REF REF IN− DD In all cases, the specified reference is 2.5 V. Rev. B | Page 22 of 32 03713-040 03713-039 03713-041 AD7933/AD7934 PARALLEL INTERFACE At the end of the conversion, BUSY goes low and can be used to CS RD activate an interrupt service routine. The and lines are The AD7933/AD7934 have a flexible, high speed, parallel then activated in parallel to read the 10 bits or 12 bits of interface. This interface is 10 bits (AD7933) or 12 bits (AD7934) conversion data. When power supplies are first applied to the B wide and is capable of operating in either word (W/ tied high) device, a rising edge on CONVST is necessary to put the track- B CONVST or byte (W/ tied low) mode. The signal is used to and-hold into track. The acquisition time of 125 ns minimum initiate conversions and, when operating in autoshutdown or must be allowed before CONVST is brought low to initiate a autostandby mode, it is used to initiate power-up. conversion. The ADC then goes into hold on the falling edge of th A falling edge on the CONVST signal is used to initiate CONVST and back into track on the 13 rising edge of CLKIN conversions, and it also puts the ADC track-and-hold into after this (see Figure 34). When operating the device in track. Once the CONVST signal goes low, the BUSY signal goes autoshutdown or autostandby mode, where the ADC powers high for the duration of the conversion. In between conversions, down at the end of each conversion, a rising edge on the CONVST must be brought high for a minimum time of t1. This CONVST signal is used to power up the device. th must happen after the 14 falling edge of CLKIN; otherwise, the conversion is aborted and the track-and-hold goes back into track. B t 1 A CONVST t CONVERT 12 3 4 5 12 13 14 t 2 CLKIN t 20 t 3 BUSY t 9 INTERNAL t TRACK/HOLD ACQUISITION CS t t 10 11 RD t 12 t t 13 14 THREE-STATE DB0 TO DB11 DATA THREE-STATE t QUIET WITH CS AND RD TIED LOW DB0 TO DB11 OLD DATA DATA B Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/ = 1) Rev. B | Page 23 of 32 03713-004 AD7933/AD7934 Reading Data from the AD7933/AD7934 CS RD The and signals are gated internally and the level is CS triggered active low. In either word mode or byte mode, and With the W/B pin tied logic high, the AD7933/AD7934 RD can be tied together as the timing specifications for t10 and interface operates in word mode. In this case, a single read operation from the device accesses the conversion data-word on t11 are 0 ns minimum. This means the bus is constantly driven Pin DB0 to Pin DB11 (12-bit word) and Pin DB2 to DB11 by the AD7933/AD7934. (10-bit word). The DB8/HBEN pin assumes its DB8 function. The data is placed onto the data bus a time t after both CS and 13 B With the W/ pin tied to logic low, the AD7933/AD7934 RD go low. The RD rising edge can be used to latch data out of interface operates in byte mode. In this case, the DB8/HBEN the device. After a time, t14, the data lines become three-stated. pin assumes its HBEN function. CS RD Alternatively, and can be tied permanently low, and the Conversion data from the AD7933/AD7934 must be accessed in conversion data is valid and placed onto the data bus a time, t , 9 two read operations with eight bits of data provided on DB0 to before the falling edge of BUSY. DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low Note that if RD is pulsed during the conversion time, this byte of the 12- or 10-bit word. For a low byte read, DB0 to DB7 causes a degradation in linearity performance of approximately provide the eight LSBs of the 12-bit word. For 10-bit operation, 0.25 LSB. Reading during conversion, by way of tying CS and the two LSBs of the low byte are 0s and are followed by six bits RD low, does not cause any degradation. of conversion data. For a high byte read, DB0 to DB3 provide the four MSBs of the 12-/10-bit word. DB4 and DB5 of the high byte provide the Channel ID. DB6 and DB7 are always 0. Figure 34 shows the read cycle timing diagram for a 12- or 10-bit transfer. When operating in word mode, the HBEN input does not exist and only the first read operation is required to access data from the device. When operating in byte mode, the two read cycles shown in Figure 35 are required to access the full data-word from the device. HBEN/DB8 t t 15 16 t t 15 16 CS t t 10 11 t 17 t 12 RD t t 13 14 DB0 TO DB7 LOW BYTE HIGH BYTE Figure 35. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0) Rev. B | Page 24 of 32 03713-005 AD7933/AD7934 Writing Data to the AD7933/AD7934 Figure 36 shows the write cycle timing diagram of the AD7933/AD7934 in word mode. When operating in word With W/B tied logic high, a single write operation transfers the mode, the HBEN input does not exist and only one write full data-word on DB0 to DB11 to the control register on the operation is required to write the word of data to the device. AD7933/AD7934. The DB8/HBEN pin assumes its DB8 Provide data on DB0 to DB11. When operating in byte mode, function. Data written to the AD7933/AD7934 should be the two write cycles shown in Figure 37 are required to write the provided on the DB0 to DB11 inputs, with DB0 being the LSB full data-word to the AD7933/AD7934. In Figure 37, the first B of the data-word. With W/ tied logic low, the AD7933/AD7934 write transfers the lower eight bits of the data-word from DB0 requires two write operations to transfer a full 12-bit word. to DB7, and the second write transfers the upper four bits of the DB8/HBEN assumes its HBEN function. Data written to the data-word. AD7933/AD7934 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte When writing to the AD7933/AD7934, the top four bits in the or low byte data. The low byte of the data-word has DB0 being high byte must be 0s. the LSB of the full data-word. For the high byte write, HBEN should be high and the data on the DB0 input should be Data The data is latched into the device on the rising edge of WR. Bit 8 of the 12-bit word. The data needs to be set up a time, t , before the WR rising 7 WR CS edge and held for a time, t8, after the rising edge. The WR CS WR and signals are gated internally. and can be tied together as the timing specifications for t and t are 0 ns 4 5 CS RD minimum (assuming and have not already been tied together). CS t t 4 5 WR t 6 t 8 t 7 DB0 TO DB11 DATA B Figure 36. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1) HBEN/DB8 t t 18 19 t t 18 19 CS t t 4 5 t 17 t 6 WR t t 7 8 DB0 TO DB7 LOW BYTE HIGH BYTE B Figure 37. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0) Rev. B | Page 25 of 32 03713-002 03713-003 AD7933/AD7934 Autostandby (PM1 = 1; PM0 = 0) POWER MODES OF OPERATION In this mode of operation, the AD7933/AD7934 automatically The AD7933/AD7934 have four different power modes of enter standby mode at the end of each conversion, shown as operation. These modes are designed to provide flexible power Point A in Figure 34. When this mode is entered, all circuitry management options. Different options can be chosen to optimize on the AD7933/AD7934 is powered down except for the the power dissipation/throughput rate ratio for differing applica- reference and reference buffer. The track-and-hold goes into tions. The mode of operation is selected by PM1 and PM0, the hold at this point and remains in hold as long as the device is in power management bits, in the control register (see Table 9 for standby. The part remains in standby until the next rising edge details). When power is first applied to the AD7933/AD7934, an CONVST of powers up the device. The power-up time required on-chip, power-on reset circuit ensures the default power-up condition is normal mode. depends on whether the internal or external reference is used. With an external reference, the power-up time required is a Note that, after power-on, track-and-hold is in hold mode, and minimum of 600 ns, while using the internal reference, the CONVST the first rising edge of places the track-and-hold into power-up time required is a minimum of 7 μs. The user should track mode. ensure this power-up time has elapsed before initiating another CONVST conversion as shown in Figure 38. This rising edge of Normal Mode (PM1 = PM0 = 0) also places the track-and-hold back into track mode. This mode is intended for the fastest throughput rate performance wherein the user does not have to worry about any power-up Full Shutdown Mode (PM1 = 1; PM0 = 1) times because the AD7933/AD7934 remain fully powered up at When this mode is entered, all circuitry on the AD7933/AD7934 all times. At power-on reset, this mode is the default setting in is powered down upon completion of the write operation, that the control register. WR is, on the rising edge of . The track-and-hold enters hold mode at this point. The part retains the information in the Autoshutdown (PM1 = 0; PM0 = 1) control register while in shutdown. The AD7933/AD7934 In this mode of operation, the AD7933/AD7934 automatically remain in full shutdown mode, with the track-and-hold in hold enter full shutdown at the end of each conversion, shown at mode, until the power management bits (PM1 and PM0) in the Point A in Figure 34 and Figure 38. In shutdown mode, all control register are changed. If a write to the control register internal circuitry on the device is powered down. The part occurs while the part is in full shutdown mode, and the power retains information in the control register during shutdown. management bits are changed to PM0 = PM1 = 0 (normal The track-and-hold also goes into hold at this point and remains in WR mode), the part begins to power up on the rising edge, and hold as long as the device is in shutdown. The AD7933/AD7934 the track-and-hold returns to track. To ensure the part is fully remains in shutdown mode until the next rising edge of CONVST powered up before a conversion is initiated, the power-up time (see Point B in Figure 34 and Figure 38). In order to keep the of 10 ms minimum should be allowed before the CONVST CONVST device in shutdown for as long as possible, should falling edge; otherwise, invalid data is read. idle low between conversions, as shown in Figure 38. On this rising edge, the part begins to power up and the track-and-hold Note that all power-up times quoted apply with a 470 nF returns to track mode. The power-up time required is 10 ms capacitor on the VREFIN pin. minimum regardless of whether the user is operating with the internal or external reference. The user should ensure that the power-up time has elapsed before initiating a conversion. t POWER-UP B A CONVST 1 14 1 14 CLKIN BUSY Figure 38. Autoshutdown/Autostandby Mode Rev. B | Page 26 of 32 03713-048 AD7933/AD7934 POWER vs. THROUGHPUT RATE 10 A considerable advantage of powering the ADC down after a T = 25°C A 9 conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the 8 V =5V DD different power modes, the AD7933/AD7934 are only powered 7 up for the duration of the conversion. Therefore, the average 6 power consumption per cycle is significantly reduced. Figure 39 5 shows a plot of power vs. throughput rate when operating in 4 autostandby mode for both VDD = 5 V and 3 V. For example, if V =3V DD 3 the device runs at a throughput rate of 10 kSPS, the overall cycle time is 100 μs. If the maximum CLKIN frequency of 25.5 MHz 2 is used, the conversion time accounts for only 0.525 μs of the 1 overall cycle time while the AD7933/AD7934 remains in 0 0 200 400 600 800 1000 1200 1400 1600 standby mode for the remainder of the cycle. THROUGHPUT (kSPS) Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference Figure 40 shows a plot of the power vs. the throughput rate when operating in normal mode for both VDD = 5 V and 3 V. MICROPROCESSOR INTERFACING In both plots, the figures apply when using the internal AD7933/AD7934 to ADSP-21xx Interface reference. If an external reference is used, the power-up time reduces to 600 ns; therefore, the AD7933/AD7934 remains in Figure 41 shows the AD7933/AD7934 interfaced to the standby for a greater time in every cycle. Additionally, the ADSP-21xx series of DSPs as a memory-mapped device. current consumption, when converting, should be lower than A single wait state may be necessary to interface the AD7933/ the specified maximum of 2.7 mA with V = 5 V, or 2.0 mA DD AD7934 to the ADSP-21xx, depending on the clock speed of with V = 3 V, respectively. DD the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx 1.8 T = 25°C A family User’s Manual for details). The following instruction 1.6 reads from the AD7933/AD7934: 1.4 V =5V DD MR = DM (ADC) 1.2 where ADC is the address of the AD7933/AD7934. 1.0 DSP/USER SYSTEM 0.8 V =3V DD 0.6 CONVST A0 TO A15 ADDRESS BUS AD7933/ 0.4 ADSP-21xx* AD7934* ADDRESS DMS CS DECODER 0.2 IRQ2 BUSY 0 0 20 406080 100 120 140 WR WR THROUGHPUT (kSPS) RD RD Figure 39. Power vs. Throughput in Autostandby Mode Using Internal Reference DB0 TO DB11 D0 TO D23 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 41. Interfacing to the ADSP-21xx Rev. B | Page 27 of 32 POWER (mW) 03713-042 POWER (mW) 03713-043 03713-044 AD7933/AD7934 DSP/USER SYSTEM AD7933/AD7934 to ADSP-21065L Interface Figure 42 shows a typical interface between the AD7933/AD7934 CONVST A0 TO A15 ADDRESS BUS and the ADSP-21065L SHARC® processor. This interface is an TMS32020/ AD7933/ TMS320C25/ example of one of three DMA handshake modes. The MS AD7934* X TMS320C50* ADDRESS control line is actually three memory select lines. Internal IS EN CS DECODER MS ADDR25 to 24 are decoded into 3 to 0, these lines are then READY DMAR asserted as chip selects. The 1 (DMA Request 1) is used TMS320C25 MSC ONLY in this setup as the interrupt to signal the end of the conversion. STRB The rest of the interface is standard handshaking operation. WR R/W DSP/USER SYSTEM RD CONVST INT BUSY X ADDR TO ADDR ADDRESS BUS 0 23 DMD0 TO DMD15 DB11 TO DB0 DATA BUS ADDRESS AD7933/ *ADDITIONAL PINS OMITTED FOR CLARITY. MS X LATCH AD7934* Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x ADDRESS BUS ADSP-21065L* ADDRESS CS AD7933/AD7934 to 80C186 Interface DECODER DMAR BUSY Figure 44 shows the AD7933/AD7934 interfaced to the 80C186 1 RD RD microprocessor. The 80C186 DMA controller provides two independent, high speed DMA channels where data transfers WR WR can occur between memory and I/O spaces. Each data transfer DB0 TO DB11 consumes two bus cycles, one cycle to fetch data and the other D0 TO D31 DATA BUS to store data. After the AD7933/AD7934 finish a conversion, *ADDITIONAL PINS OMITTED FOR CLARITY. the BUSY line generates a DMA request to Channel 1 (DRQ1). Figure 42. Interfacing to the ADSP-21065L Because of the interrupt, the processor performs a DMA read operation, which also resets the interrupt latch. Sufficient AD7933/AD7934 to TMS32020, TMS320C25, and priority must be assigned to the DMA channel to ensure that TMS320C5x Interface the DMA request is serviced before the completion of the next Parallel interfaces between the AD7933/AD7934 and the conversion. TMS32020, TMS320C25 and TMS320C5x family of DSPs are MICROPROCESSOR/ USER SYSTEM shown in Figure 43. Select the memory-mapped address for the AD7933/AD7934 to fall in the I/O memory space of the DSPs. CONVST AD0 TO AD15 ADDRESS/DATA BUS The parallel interface on the AD7933/AD7934 is fast enough to A16 TO A19 interface to the TMS32020 with no extra wait states. If high ADDRESS AD7933/ ALE speed glue logic, such as 74AS devices, is used to drive the LATCH AD7934* RD and the WR lines when interfacing to the TMS320C25, no ADDRESS BUS 80C186* ADDRESS wait states are necessary. However, if slower logic is used, data CS DECODER accesses may be slowed sufficiently when reading from, and DRQ1 QR writing to, the part to require the insertion of one wait state. S Extra wait states are necessary when using the TMS320C5x at BUSY RD RD their fastest clock speeds (see the TMS320C5x User’s Guide WR WR for details). DATA BUS DB0 TO DB11 Data is read from the ADC using the following instruction: *ADDITIONAL PINS OMITTED FOR CLARITY. IN D, ADC Figure 44. Interfacing to the 80C186 where: D is the data memory address. ADC is the AD7933/AD7934 address. Rev. B | Page 28 of 32 03713-045 03713-046 03713-047 AD7933/AD7934 APPLICATION HINTS GROUNDING AND LAYOUT Good decoupling is also important. Decouple all analog supplies with 10 μF tantalum capacitors in parallel with 0.1 μF Design the printed circuit board that houses the AD7933/AD7934 capacitors to GND. To achieve the best performance from these so that the analog and digital sections are separated and con- decoupling components, they must be placed as close as fined to certain areas of the board. This facilitates the use of possible to the device, ideally right up against the device. The ground planes that can be easily separated. Generally, a minimum 0.1 μF capacitors should have a low effective series resistance etch technique is best for ground planes because it offers (ESR) and effective series inductance (ESI), such as the optimum shielding. Join digital and analog ground planes in common ceramic types or surface-mount types. These types of only one place, establishing a star ground point connection as capacitors provide a low impedance path to ground at high close as possible to the ground pins on the AD7933/AD7934. frequencies to handle transient currents due to internal logic Avoid running digital lines under the device because this switching. couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7933/AD7934 to avoid EVALUATING THE AD7933/AD7934 noise coupling. To provide low impedance paths and reduce the PERFORMANCE effects of glitches on the power supply line, use as large a trace The recommended layout for the AD7933/AD7934 is outlined as possible on the power supply lines to the AD7933/AD7934. in the evaluation board documentation. The evaluation board Shield fast switching signals, such as clocks, with digital ground package includes a fully assembled and tested evaluation board, to avoid radiating noise to other sections of the board, and documentation, and software for controlling the board from the never run clock signals near the analog inputs. Avoid crossover PC via the evaluation board controller. The evaluation board of digital and analog signals. To reduce the effects of feedthrough controller can be used in conjunction with the AD7933/AD7934 through the board, run traces on opposite sides of the board at evaluation board, as well as many other Analog Devices evalua- right angles to each other. A microstrip technique is by far the tion boards ending in the CB designator, to demonstrate and best, but it is not always possible with a double-sided board. In evaluate the ac and dc performance of the AD7933/AD7934. this technique, the component side of the board is dedicated to The software allows the user to perform ac (fast Fourier transform) ground planes, while signals are placed on the solder side. and dc (histogram of codes) tests on the AD7933/AD7934. The software and documentation are on the CD that ships with the evaluation board. Rev. B | Page 29 of 32 AD7933/AD7934 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 SEATING COPLANARITY 0.19 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Linearity Error (LSB) Package Description Package Option AD7933BRU −40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7933BRU-REEL –40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7933BRU-REEL7 –40°C to +85°C ±1 28-Lead TSSOP RU-28 2 AD7933BRUZ –40°C to +85°C ±1 28-Lead TSSOP RU-28 2 AD7933BRUZ-REEL7 –40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRU −40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRU-REEL –40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRU-REEL7 –40°C to +85°C ±1 28-Lead TSSOP RU-28 2 AD7934BRUZ –40°C to +85°C ±1 28-Lead TSSOP RU-28 2 AD7934BRUZ-REEL7 –40°C to +85°C ±1 28-Lead TSSOP RU-28 3 EVAL-AD7933CB Evaluation Board 3 EVAL-AD7934CB Evaluation Board 4 EVAL-CONTROL-BRD2 Controller Board 1 Linearity error here refers to integral linearity error. 2 Z = Pb-free part. 3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. 4 The evaluation board controller is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the letters CB. The following needs to be ordered to obtain a complete evaluation kit: the ADC evaluation board (for example, EVAL-AD7934CB), the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See the relevant evaluation board data sheet for more details. Rev. B | Page 30 of 32 AD7933/AD7934 NOTES Rev. B | Page 31 of 32 AD7933/AD7934 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03713-0-2/07(B) Rev. B | Page 32 of 32