ANALOG DEVICES AD7923

4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP AD7923 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 200 kSPS AV DD Specified for AVDD of 2.7 V to 5.25 V REF IN Low power 3.6 mW max at 200 kSPS with 3 V supply V 0 IN T/H • 7.5 mW max at 200 kSPS with 5 V supply 12-BIT • SUCCESSIVE 4 (single-ended) inputs with sequencer • • APPROXIMATION Wide input bandwidth • ADC • I/P 70 dB Min SNR at 50 kHz input frequency • MUX • Flexible power/serial clock speed management • • No pipeline delays • • ® TM High speed serial interface SPI -/QSPI -/ • V 3 TM IN MICROWIRE -/DSP-compatible SCLK Shutdown mode: 0.5 μA max DOUT 16-lead TSSOP package SEQUENCER CONTROL LOGIC DIN Qualified for automotive applications CS AD7923 GENERAL DESCRIPTION V DRIVE The AD7923 is a 12-bit, high speed, low power, 4-channel, suc- GND cessive approximation (SAR) ADC. It operates from a single Figure 1. 2.7 V to 5.25 V power supply and features throughput rates up to PRODUCT HIGHLIGHTS 200 kSPS. It contains a low noise, wide bandwidth track-and-hold 1. High Throughput with Low Power Consumption. amplifier that can handle input frequencies in excess of 8 MHz. The AD7923 offers up to 200 kSPS throughput rates. At the The conversion process and data acquisition are controlled by maximum throughput rate with 3 V supplies, the AD7923 CS and the serial clock, allowing the device to easily interface dissipates just 3.6 mW of power. with microprocessors or DSPs. The input signal is sampled on 2. Four Single-Ended Inputs with a Channel Sequencer. CS the falling edge of ; the conversion is also initiated at this 3. Single-Supply Operation with V Function. DRIVE point. The V function allows the serial interface to connect DRIVE directly to either 3 V or 5 V processor systems independent The AD7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At of AVDD. maximum throughput rates, it consumes 1.2 mA maximum 4. Flexible Power/Serial Clock Speed Management. with 3 V supplies and 1.5 mA maximum with 5 V supplies. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the Through the configuration of the control register, the analog serial clock speed increase. The part also features various input range can be selected as 0 V to REF or 0 V to 2 × REF , IN IN shutdown modes to maximize power efficiency at lower with either straight binary or twos complement output coding. throughput rates. Current consumption is 0.5 μA The AD7923 features four single-ended analog inputs with a maximum when in full shutdown. channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. 5. No Pipeline Delay. The part features a SAR ADC with accurate control of the The conversion time for the AD7923 is determined by the serial sampling instant via a CS input and once off conversion clock, SCLK, frequency, since this is used as the master clock to control. control the conversion. The conversion time can be as short as 800 ns with a 20 MHz SCLK. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved. 03086-001 AD7923 TABLE OF CONTENTS Specifications..................................................................................... 3 Typical Connection Diagram ................................................... 16 Timing Specifications....................................................................... 5 Modes of Operation ................................................................... 17 Absolute Maximum Ratings............................................................ 6 Powering Up the AD7923 ......................................................... 18 ESD Caution.................................................................................. 6 Power vs. Throughput Rate....................................................... 19 Pin Configuration and Function Description .............................. 7 Serial Interface ............................................................................ 20 Typical Performance Characteristics ............................................. 8 Microprocessor Interfacing....................................................... 21 Terminology .................................................................................... 10 Application Hints ........................................................................... 23 Control Register Descriptions ...................................................... 12 Grounding and Layout .............................................................. 23 Sequencer Operation ................................................................. 13 Evaluating the AD7923 Performance ...................................... 23 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 24 Circuit Information.................................................................... 14 Ordering Guide .......................................................................... 24 Converter Operation.................................................................. 14 Automotive Products................................................................. 24 ADC Transfer Function............................................................. 15 REVISION HISTORY 5/11—Rev. B to Rev. C Changes to Features Section............................................................ 1 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 Added to Automotive Products Section...................................... 24 12/08—Rev. A to Rev. B Changes to ESD Parameter, Table 3 ............................................... 6 Changes to Ordering Guide .......................................................... 24 8/05—Rev. 0 to Rev. A Update Format ....................................................................Universal Change to Table 1 ............................................................................. 3 Change to Table 3 ............................................................................. 6 Change to Reference Section ........................................................ 16 Changes to Ordering Guide .......................................................... 24 11/02—Revision 0: Initial Version Rev. C | Page 2 of 24 AD7923 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK 2 Signal-to-(Noise + Distortion) (SINAD) 70 dB min @ 5 V, –40°C to +85°C 69 dB min @ 5 V, 85°C to 125°C, typ 70 dB 69 dB min @ 3 V typ 70 dB, –40°C to +125°C 2 Signal-to-Noise (SNR) 70 dB min 2 Total Harmonic Distortion (THD) −77 dB max @ 5 V typ, −84 dB −73 dB max @ 3 V typ,−77 dB Peak Harmonic or Spurious Noise −78 dB max @ 5 V typ, −86 dB 2 (SFDR) −76 dB max @ 3 V typ, −80 dB 2 Intermodulation Distortion (IMD) fA = 40.1 kHz, fB = 41.5 kHz Second Order Terms −90 dB typ Third Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB 2 DC ACCURACY Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding Offset Error ±8 LSB max Typ ±0.5 LSB Offset Error Match ±0.5 LSB max Gain Error ±1.5 LSB max Gain Error Match ±0.5 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with twos IN IN IN IN complement output coding Positive Gain Error ±1.5 LSB max Positive Gain Error Match ±0.5 LSB max Zero-Code Error ±8 LSB max Typ ±0.8 LSB Zero-Code Error Match ±0.5 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REF V Range bit set to 1 IN 0 to 2 × REFIN V Range bit set to 0, AVDD = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 200 kSPS IN SAMPLE LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typ 10 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance, CIN 10 pF max Rev. C | Page 3 of 24 AD7923 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE – 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Twos Complement Coding bit set to 0 Straight (Natural) Coding bit set to 1 Binary CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz 300 ns max Sinewave input 300 ns max Full-scale step Input Throughput Rate 200 kSPS max See Serial Interface section POWER REQUIREMENTS AV 2.7/5.25 V min/max DD V 2.7/5.25 V min/max DRIVE 4 IDD Digital I/Ps = 0 V or VDRIVE During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2.0 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) f = 200 kSPS 1.5 mA max AV = 4.75 V to 5.25 V, f = 20 MHz SAMPLE DD SCLK 1.2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900 μA typ AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS 650 μA typ AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS Auto Shutdown (Static) 0.5 μA max SCLK on or off (20 nA typ) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) fSAMPLE = 200 kSPS 7.5 mW max AVDD = 5 V, fSCLK = 20 MHz 3.6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown (Static) 2.5 μW max AVDD = 5 V 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature range: B Version: −40°C to +125°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. C | Page 4 of 24 AD7923 TIMING SPECIFICATIONS 1 AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter AV = 3 V AV = 5 V Unit Description DD DD 2 f 10 10 kHz min SCLK 20 20 MHz max t 16 × t 16 × t CONVERT SCLK SCLK tQUIET 50 50 ns min CS Minimum quiet time required between rising edge and start of next conversion t2 10 10 ns min CS to SCLK set-up time 3 t 35 30 ns max CS 3 Delay from until DOUT three-state disabled 3 t 40 40 ns max Data access time after SCLK falling edge 4 t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to DOUT valid hold time 4 t 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance 8 t 10 10 ns min DIN set-up time prior to SCLK falling edge 9 t 5 5 ns min DIN hold time after SCLK falling edge 10 t11 20 20 ns min CS Sixteenth SCLK falling edge to high t12 1 1 μs max Power-Up time from full power-down/auto shutdown mode 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 The mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V . DRIVE 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t , is the true bus relinquish 8 time of the part and is independent of the bus loading. 200μAI OL TO OUTPUT 1.6V PIN C L 50pF 200μAI OH Figure 2. Load Circuit for Digital Output Timing Specification Rev. C | Page 5 of 24 03086-002 AD7923 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AV to AGND −0.3 V to +7 V DD rating only and functional operation of the device at these or V to AGND −0.3 V to AV + 0.3 V DRIVE DD any other conditions above those indicated in the operational Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V section of this specification is not implied. Exposure to absolute Digital Input Voltage to AGND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V device reliability. REF to AGND −0.3 V to AV + 0.3 V IN DD Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range Commercial (B Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 150.4°C/W (TSSOP) θJC Thermal Impedance 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Pb-free Temperature, Soldering Reflow 260(+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latchup. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 24 AD7923 PIN CONFIGURATION AND FUNCTION DESCRIPTION SCLK 1 16 AGND DIN 2 15 V DRIVE CS 3 14 DOUT AD7923 TOP VIEW AGND 4 13 AGND (Not to Scale) AV 5 12 V 0 DD IN AV 6 11 V 1 DD IN 7 10 REF V 2 IN IN 8 9 AGND V 3 IN Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock input is also used as the clock source for the AD7923 conversion process. 2 DIN Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register Descriptions section). 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923 and framing the serial data transfer. 4, 8, AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input signals and any 13, 16 external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AV Analog Power Supply Input. The AV range for the AD7923 is from 2.7 V to 5.25 V. For the 0 V to 2 × REF range, DD DD IN AV should be from 4.75 V to 5.25 V. DD 7 REF IN Reference Input for the AD7923. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 12 to 9 VIN0 to VIN3 Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on- chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REF or from 0 V to 2 × REF as IN IN selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. 14 DOUT Data Out. Logic Output. The conversion result from the AD7923 is provided on this output pin as a serial data stream. The AD7923 serial data stream consists of two leading 0s, and two address bits indicating which channel the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked out of the AD7923 on the SCLK falling edge. 15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface operates. Rev. C | Page 7 of 24 03086-003 AD7923 TYPICAL PERFORMANCE CHARACTERISTICS –50 4096 POINT FFT f = 200kSPS –10 SAMPLE AV = 4.75V DD T = 25°C –55 A f = 200kSPS SAMPLE RANGE = 0V TO REF IN f = 50 kHz IN SINAD = 70.714dB –30 –60 THD = –82.853dB SFDR = –84.815dB –65 –50 –70 AV = V = 2.7V DD DRIVE AV = V = 3.6V –70 –75 DD DRIVE –80 –90 –85 AV = V = 4.75V DD DRIVE AV = V = 5.25V DD DRIVE –110 –90 0 10 203040 50 60 708090 100 10 100 FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 4. Dynamic Performance at 200 kSPS Figure 7. THD vs. Analog Input Frequency for Various Supply Voltages at 200 kSPS 75 –55 f = 200kSPS SAMPLE T = 25°C –60 A AV = V = 5.25V AV = 5.25V DD DD DRIVE RANGE = 0V TO REF AV = V = 4.75V IN DD DRIVE –65 70 –70 R = 1000Ω IN AV = V = 3.6V DD DRIVE –75 AV = V = 2.7V DD DRIVE –80 R = 100Ω IN 65 R = 10Ω IN –85 f = 200kSPS SAMPLE T = 25°C A –90 RANGE = 0V TO REF IN R = 50Ω IN 60 –95 0 100 10 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages at Figure 8. THD vs. Analog Input Frequency for Various Source Impedances 200 kSPS 0 1.0 AV = V = 5V DD DRIVE AV = 5V DD 0.8 TEMP = 25°C –10 200mV p-p SINE WAVE ON AV DD REF = 2.5V, 1μF CAPACITOR IN 0.6 T = 25°C –20 A 0.4 –30 0.2 –40 0 –50 –0.2 –60 –0.4 –70 –0.6 –80 –0.8 –1.0 –90 0 512 1024 1536 2048 2560 3072 3584 4096 0 20 40 60 80 100 120 140 160 180 200 CODE SUPPLY RIPPLE FREQUENCY (kHz) Figure 9. Typical INL Figure 6. PSRR vs. Supply Ripple Frequency Rev. C | Page 8 of 24 PSRR (dB) SINAD (dB) SNR (dB) 03086-006 03086-005 03096-004 INL ERROR (LSB) THD (dB) THD (dB) 03096-009 03086-008 03086-007 AD7923 1.0 AV = V = 5V DD DRIVE 0.8 TEMP = 25°C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Figure 10. Typical DNL Rev. C | Page 9 of 24 DNL ERROR (LSB) 03096-010 AD7923 TERMINOLOGY Integral Nonlinearity Positive Gain Error Match This is the maximum deviation from a straight line passing This is the difference in positive gain error between any two through the endpoints of the ADC transfer function. The channels. endpoints of the transfer function are zero scale, a point 1 LSB Negative Gain Error below the first code transition, and full scale, a point 1 LSB This applies when using the twos complement output coding above the last code transition. option, in particular, with the 2 × REF input range when IN Differential Nonlinearity −REF to +REF is biased around the REF point. It is the IN IN IN This is the difference between the measured and the ideal 1 LSB deviation of the first code transition (100 ... 000) to (100 ... 001) change between any two adjacent codes in the ADC. from the ideal (that is, −REFIN + 1 LSB) after the zero-code error has been adjusted. Offset Error This is the deviation of the first code transition (00 ... 000) to Negative Gain Error Match (00 ... 001) from the ideal, that is, AGND + 1 LSB. This is the difference in negative gain error between any two channels. Offset Error Match This is the difference in offset error between any two channels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of cross- Gain Error talk between channels. It is measured by applying a full-scale This is the deviation of the last code transition (111 ... 110) to 400 kHz sine wave signal to all three nonselected input channels (111 ... 111) from the ideal (that is, REFIN – 1 LSB) after the and determining how much that signal is attenuated in the offset error has been adjusted. selected channel with a 50 kHz signal. The figure is given in the worst-case across all four channels for the AD7923. Gain Error Match This is the difference in gain error between any two channels. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition, but Zero-Code Error not the converter’s linearity. Power supply rejection is the maxi- This applies when using the twos complement output coding mum change in the full-scale transition point from a change in option, in particular, with the 2 × REF input range when IN power supply voltage from the nominal value. −REFIN to +REFIN is biased around the REFIN point. It defined as the deviation of the midscale transition (all 0s to all 1s) from Figure 6 shows the power supply rejection ratio vs. supply ripple the ideal VIN voltage, that is, REFIN – 1 LSB. frequency for the AD7923 with no decoupling. The power sup- ply rejection ratio is defined as the ratio of the power in the Zero-Code Error Match ADC output at full-scale frequency, f, to the power of a 200 mV This is the difference in zero-code error between any two p-p sine wave applied to the ADC AV supply of frequency f : DD S channels. PSSR (dB) = 10log(Pf/Pf ) S Positive Gain Error This applies when using the twos complement output coding Pf is equal to the power at frequency f in the ADC output; PfS is option, in particular, with the 2 × REFIN input range when equal to the power at frequency fS coupled onto the ADC AVDD −REFIN to +REFIN is biased around the REFIN point. It is the supply. deviation of the last code transition (011 ... 110) to (011 ... 111) from the ideal (that is, +REF – 1 LSB) after the zero-code Track-and-Hold Acquisition Time IN error has been adjusted. The track-and-hold amplifier returns into track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion. Rev. C | Page 10 of 24 AD7923 Signal-to-(Noise + Distortion) (SINAD) Ratio Total Harmonic Distortion (THD) This is the measured ratio of SINAD at the output of the ADC. THD is the ratio of the rms sum of harmonics to the The signal is the rms amplitude of the fundamental. Noise is the fundamental. For the AD7923, it is defined as sum of all nonfundamental signals up to half the sampling 2 2 2 2 2 frequency (fS/2), excluding dc. The ratio is dependent on the V + V + V + V + V 2 3 4 5 6 THD(dB)= 20log number of quantization levels in the digitization process, the V 1 more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input where V1 is the rms amplitude of the fundamental and V2, V3, is given by V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. SINAD = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. Rev. C | Page 11 of 24 AD7923 CONTROL REGISTER DESCRIPTIONS AD7923 configuration for the next conversion. This requires The control register on the AD7923 is a 12-bit, write-only 16 serial clocks for every data transfer. Only the information register. Data is loaded from the DIN pin of the AD7923 on the provided on the first 12 falling clock edges (after CS falling falling edge of SCLK. The data is transferred on the DIN line at edge) is loaded to the control register. MSB denotes the first bit the same time that the conversion result is read from the part. in the data stream. The bit functions are outlined in Table 5. The data transferred on the DIN line corresponds to the Table 5. Control Register Bit Functions MSB LSB WRITE SEQ1 DONTC DONTC ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE CODING Table 6. Bit Name Description 11 WRITE The value written to this bit of the control register determines whether the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the remaining 11 bits are not loaded to the control register and it remains unchanged. 10 SEQ1 The SEQ1 bit in the control register is used with the SEQ0 bit to control the use of the sequencer function (see Table 9). 7–6 ADD1 These two address bits are loaded at the end of the present conversion and select which analog input channel is ADD0 converted in the next serial transfer, or they can also be used to select the final channel in a consecutive sequence, as described in Table 9. The selected input channel is decoded, as shown in Table 7. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. Channel address bits corresponding to the conversion result are also output on the DOUT serial data stream prior to the 12 bits of data (see the Serial Interface section). 5, 4 PM1 Power management bits. These two bits decode the mode of operation of the AD7923, as shown in Table 8. PM0 3 SEQ0 The SEQ0 bit in the control register is used with the SEQ1 bit to control the use of the sequencer function. (see Table 9). 2, 9–8 DONTC Don’t care. 1 RANGE This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range extends from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For the 0 V to 2 × REF range, AV = 4.75 V to 5.25 V. IN DD 0 CODING This bit selects the type of output coding the AD7923 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). Table 7. Channel Selection ADD1 ADD0 Analog Input Channel 0 0 VIN0 0 1 VIN1 1 0 V 2 IN 1 1 V 3 IN Rev. C | Page 12 of 24 AD7923 Table 8. Power Mode Selection PM1 PM0 Mode 1 1 Normal operation. In this mode, the AD7923 remains in full power mode, regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7923. 1 0 Full shutdown. In this mode, the AD7923 is in full shutdown mode with all circuitry on the AD7923 powering down. The AD7923 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 1 Auto shutdown. In this mode, the AD7923 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs, and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 Invalid selection. This configuration is not allowed. SEQUENCER OPERATION The configuration of the SEQ1 and SEQ0 bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 9 outlines the three modes of operation of the sequencer. Table 9. Sequence Selection SEQ1 SEQ0 Sequence Type 0 X This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of Channel Address Bits ADD1 and ADD0 in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC without the sequencer function being used, where each write to the AD7923 selects the next channel for conversion (see Figure 11). 1 0 If the SEQ1 and SEQ0 bits are set in this way, the sequence function is not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 This configuration is used in conjunction with Channel Address Bits ADD1 and ADD0 to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the control register (see Figure 12). Figure 11 reflects the traditional operation of a multichannel ADC, POWER-ON where each serial transfer selects the next channel for conversion. In this mode of operation the sequencer function is not used. DUMMY CONVERSION Figure 12 shows how to program the AD7923 to continuously DIN: WRITE TO CONTROL REGISTER, convert on a sequence of consecutive channels from Channel 0 WRITE BIT = 1, CS SELECT CODING, RANGE, AND POWER MODE. to a selected final channel. To exit this mode of operation and SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 1, SEQ0 = 1 revert back to the traditional mode of operation of a multi- channel ADC (as outlined in Figure 11), ensure that the write bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer. DOUT: CONVERSION RESULT FROM CHANNEL 0 POWER-ON CONTINUOUSLY CONVERTS ON THE SELECTED CS SEQUENCE OF CHANNELS FROM CHANNEL 0 UP WRITE BIT = 0 TO AND INCLUDING THE PREVIOUSLY SELECTED DUMMY CONVERSION A1, A0 IN THE CONTROL REGISGER DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, CS SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A1, A0 FOR CONVERSION. CONTINUOUSLY CONVERTS ON THE SELECTED SEQ1 = 0, SEQ0 = x SEQUENCE OF CHANNELS BUT WILL ALLOW CS RANGE, CODING, ETC., TO CHANGE IN THE CON- TROL REGISTER WITHOUT INTERRUPTING THE WRITE BIT = 1, SEQUENCY, PROVIDED SEQ =1, SEQ0 = 0 SEQ1 = 1, SEQ0 = 0 DOUT: CONVERSION RESULT FROM Figure 12. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart PREVIOUSLY SELECTED CHANNEL A1, A0 DIN: WRITE TO CONTROL REGISTER, CS WRITE BIT = 1, WRITE BIT = 1, SEQ1 = 0, SELECT CODING, RANGE, AND POWER MODE. SEQ0 = x SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x Figure 11. SEQ1 Bit = 0, SEQ0 Bit = X Flowchart Rev. C | Page 13 of 24 03086-011 03086-012 AD7923 THEORY OF OPERATION When the comparator is rebalanced, the conversion is complete. CIRCUIT INFORMATION The control logic generates the ADC output code. Figure 16 and The AD7923 is a high speed, 4-channel, 12-bit single-supply Figure 17 show the ADC transfer functions. ADC. The part can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7923 is CAPACITIVE DAC capable of throughput rates of 200 kSPS. The conversion time A 4kΩ can be as short as 800 ns when provided with a 20 MHz clock. V 0 IN CONTROL SW1 B LOGIC SW2 The AD7923 provides the user with an on-chip track-and-hold V 3 IN COMPARATOR ADC and with a serial interface housed in a 16-lead TSSOP AGND package. The AD7923 has four, single-ended input channels with a channel sequencer, allowing the user to select a channel Figure 14. ADC Conversion Phase sequence through which the ADC can cycle with each conse- Analog Input CS utive falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and Figure 15 shows an equivalent circuit of the analog input provides the clock source for the successive approximation structure of the AD7923. The two diodes D1 and D2 provide ADC. The analog input range is 0 V to REFIN or 0 V to 2 × ESD protection for the analog inputs. Care must be taken to REFIN, depending on the status of the RANGE bit in the control ensure that the analog input signal never exceeds the supply register. For the 0 to 2 × REF range, the part must be operated IN rails by more than 200 mV; otherwise these diodes become from a 4.75 V to 5.25 V AV supply. DD forward-biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct The AD7923 provides flexible power management options to without causing irreversible damage to the part. Capacitor C1, allow the user to achieve the best power performance for a shown in Figure 15, is typically around 4 pF and can primarily given throughput rate. These options are selected by program- be attributed to pin capacitance. The resistor R1 is a lumped ming the power management bits, PM1 and PM0, in the control component made up of the on resistance of the track-and-hold register. switch and includes the on resistance of the input multiplexer. The total resistance is typically about 400 Ω. Capacitor C2 is the CONVERTER OPERATION ADC sampling capacitor and has a capacitance of 30 pF typi- The AD7923 is a 12-bit successive approximation ADC based cally. For ac applications, removing high frequency components around a capacitive DAC. It can convert analog input signals in from the analog input signal is recommended by using an RC the range 0 V to REFIN or 0 V to 2 × REFIN. Figure 13 and low-pass filter on the relevant analog input pin. In applications Figure 14 show simplified schematics of the ADC. The ADC is where harmonic distortion and the signal-to-noise ratio are comprised of a control logic, SAR, and capacitive DAC, which critical, the analog input should be driven from a low impe- are used to add and subtract fixed amounts of charge from the dance source. Large source impedances significantly affect the sampling capacitor to bring the comparator back into a balanced ac performance of the ADC. This may necessitate the use of an condition. Figure 13 shows the ADC during its acquisition phase. input buffer amplifier. The choice of the op amp is a function of SW2 is closed and SW1 is in Position A. The comparator is held the particular application. in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum CAPACITIVE source impedance depends on the amount of THD that can be DAC tolerated. The THD increases as the source impedance increases A 4kΩ V 0 IN and performance degrades (see Figure 8). CONTROL SW1 B LOGIC SW2 AV DD V 3 IN COMPARATOR AGND C2 D1 30pF R1 Figure 13. ADC Acquisition Phase V IN C1 D2 CONVERSION PHASE: SWITCH OPEN When the ADC starts a conversion (see Figure 14), SW2 opens 4pF TRACK PHASE: SWITCH CLOSED and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the Figure 15. Equivalent Analog Input Circuit sampling capacitor to bring the comparator back into balance. Rev. C | Page 14 of 24 03086-013 03086-015 03086-014 AD7923 ADC TRANSFER FUNCTION 011...111 The output coding of the AD7923 is either straight binary or 011...110 • twos complement, depending on the status of the LSB in the • 000...001 control register. The designed code transitions occur at succes- 000...000 sive LSB values (for example, 1 LSB, 2 LSBs). The LSB size is 111...111 • REF /4096 for the AD7923. The ideal transfer characteristic IN • 1LSB = 2 × V /4096 REF 100...010 for the AD7923 when straight binary coding is selected is 100...001 shown in Figure 16 and the ideal transfer characteristic for the 100...000 AD7923 when twos complement coding is selected is shown in –V + 1LSB +V – 1LSB REF REF V – 1LSB REF Figure 17. ANALOG INPUT Figure 17. Twos Complement Transfer Characteristic 111...111 with REF ± REF Input Range IN IN 111...110 • Handling Bipolar Input Signals • 111...000 Figure 18 shows how useful the combination of the 2 × REF IN • 011...111 input range and the twos complement output coding scheme is 1LSB = V /4096 REF • • for handling bipolar input signals. If the bipolar input signal is 000...010 biased around REFIN and twos complement output coding is 000...001 000...000 selected, then REFIN becomes the zero-code point, −REFIN is 1LSB +V – 1LSB REF 0V ANALOG INPUT negative full scale, and + REFIN becomes positive full scale with a dynamic range of 2 × REFIN. NOTES 1. V IS EITHER REF OR 2× REF REF IN IN Figure 16. Straight Binary Transfer Characteristic V DD V REF 0.1μF AV DD REF IN V DD V DRIVE R4 AD7923 DSP/μP V R3 TWOS COMPLEMENT V 0 DOUT R2 IN V 0V • 011...111 • (= 2× REF ) IN +REF IN V 3 IN R1 R1 = R2 = R3 = R4 000...000 REF IN (= 0V) –REF 100...000 IN Figure 18. Handling Bipolar Signals Rev. C | Page 15 of 24 ADC CODE 03086-016 ADC CODE 03086-018 03086-017 AD7923 the control register again once a sequencer operation has been TYPICAL CONNECTION DIAGRAM initiated. The write bit must be set to 0 or the DIN line must be Figure 19 shows a typical connection diagram for the AD7923. set low to ensure that the control register is not accidentally In this setup the AGND pin is connected to the analog ground overwritten or the sequence operation is interrupted. If the plane of the system. In Figure 19, REFIN is connected to a control register is written to at any time during the sequence, decoupled 2.5 V supply from a reference source, the AD780, to the user must ensure that the SEQ1 and SEQ0 bits are set to 1, 0 provide an analog input range of 0 V to 2.5 V (if the range bit is to avoid interrupting the automatic conversion sequence. This 1) or 0 V to 5 V (if the range bit is 0). Although the AD7923 is pattern continues until the AD7923 is written to and the SEQ1 connected to AVDD of 5 V, the serial interface is connected to a and SEQ0 bits are configured with any bit combination except 3 V microprocessor. The VDRIVE pin of the AD7923 is connected 1, 0, resulting in the termination of the sequence. If uninter- to the same 3 V supply of the microprocessor to allow a 3 V rupted, however (write bit = 0, or write bit = 1 and SEQ1 and logic interface (see the Digital Inputs section). The conversion SEQ0 bits are set to 1, 0), then upon completion of the result is output in a 16-bit word. This 16-bit data stream sequence, the AD7923 sequencer returns to Channel 0 and consists of two leading 0s, two address bits indicating which commences the sequence again. channel the conversion result corresponds to, followed by the 12 bits of conversion data. For applications where power Regardless of which channel selection method is used, the consumption is a concern, the power-down modes should be 16-bit word output from the AD7923 during each conversion used between conversions or bursts of several conversions to always contains two leading 0s, and two channel address bits improve power performance. See the Modes of Operation that the conversion result corresponds to, followed by the 12-bit section. conversion result. (see the Serial Interface section). 5V SUPPLY Digital Inputs 0.1μF 10μF SERIAL The digital inputs applied to the AD7923 are not limited by the INTERFACE maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AV DD V 0 SCLK IN AV + 0.3 V limit as on the analog inputs. • DD 0VTOREF DOUT IN • μC/μP AD7923 V 3 CS IN Another advantage of SCLK, DIN, and CS not being restricted AGND DIN REF V IN DRIVE by the AVDD + 0.3 V limit is that possible power supply sequencing issues are avoided. If CS, DIN, or SCLK are applied before AVDD, there is no risk of latchup as there would be on the 2.5V 0.1μF 0.1μF 10μF AD780 3V analog inputs if a signal greater than 0.3 V were applied prior to SUPPLY AV . DD NOTES 1. ALL UNUSED INPUT CHANNELS MUST BE CONNECTED TO AGND. V DRIVE Figure 19. Typical Connection Diagram The AD7923 also has the VDRIVE feature. VDRIVE controls the voltage at which the serial interface operates. VDRIVE allows the Analog Input Selection ADC to easily interface to both 3 V and 5 V processors. For Any one of four analog input channels can be selected for example, if the AD7923 were operated with an AV of 5 V, the DD conversion by programming the multiplexer with Address Bits V pin could be powered from a 3 V supply. The AD7923 DRIVE ADD1 and ADD0 in the control register. The channel has a larger dynamic range with an AV of 5 V while still being DD configurations are shown in Table 7. able to interface to 3 V processors. Care should be taken to ensure that VDRIVE does not exceed AVDD by more than 0.3 V The AD7923 can also be configured to automatically cycle (see the Absolute Maximum Ratings section). through selected channels. The sequencer feature is accessed via the SEQ1 and SEQ0 bits in the control register (see Table 9). Reference The AD7923 can be programmed to continuously convert on a An external reference source should be used to supply the 2.5 V number of consecutive channels in ascending order from reference to the AD7923. Errors in the reference source result in Channel 0 to a selected final channel as determined by Channel gain errors in the AD7923 transfer function and add to the Address Bits ADD1 and ADD0. This is possible if the SEQ1 and specified full-scale errors of the part. A capacitor of at least SEQ0 bits are set to 1, 1. The next serial transfer then acts on 0.1 μF should be placed on the REFIN pin. Suitable reference the sequence programmed by executing a conversion on sources for the AD7923 include the AD780, REF 192, and the Channel 0. The next serial transfer results in a conversion on AD1582. Channel 1, and so on, until the channel selected via Address Bits ADD1 and ADD0 is reached. It is not necessary to write to Rev. C | Page 16 of 24 03086-019 AD7923 CS If 2.5 V is applied to the REF pin, the analog input range can IN be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of 1 12 16 SCLK the range bit in the control register. 2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS DOUT MODES OF OPERATION + CONVERSION RESULT The AD7923 has a number of different modes of operation, DIN DATA INTO CONTROL REGISTER which are designed to provide flexible power management CONTROL REGISTER DATA IS LOADED options. These options can be chosen to optimize the power ON THE FIRST 12 SCLK CYCLES. dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7923 is Figure 20. Normal Mode Operation controlled by the power management bits, PM1 and PM0, in Full Shutdown (PM1 = 1, PM0 = 0) the control register, as detailed in Table 8. When power supplies In this mode, all internal circuitry on the AD7923 is powered are first applied to the AD7923, care should be taken to ensure down. The part retains information in the control register that the part is placed in the required mode of operation (see during full shutdown. The AD7923 remains in full shutdown the Powering Up the AD7923 section). until the power management bits in the control register, PM1 Normal Mode (PM1 = PM0 = 1) and PM0, are changed. This mode is intended for the fastest throughput rate perfor- If a write to the control register occurs while the part is in full mance where the user does not have to worry about power-up shutdown, with the power management bits changed to PM0 = time since the AD7923 remains fully powered at all times. PM1 = 1, normal mode, the part begins to power up on the CS Figure 20 shows the general diagram of the operation of the rising edge. The track-and-hold that was in hold while the part AD7923 in this mode. was in full shutdown returns to tracking on the 14th SCLK falling edge. A full 16-SCLK transfer must occur to ensure that The conversion is initiated on the falling edge of CS and the the control register contents are updated; however, the DOUT track-and-hold enters hold mode, as described in the Serial line is not driven during this wake-up transfer. Interface section. The data presented to the AD7923 on the DIN line during the first 12 clock cycles of the data transfer is To ensure that the part is fully powered up, t (t ) should POWER UP 12 loaded into the control register (provided the write bit is set to have elapsed before the next CS falling edge; otherwise invalid 1). The part remains fully powered up in normal mode at the data is read if a conversion is initiated before this time. end of the conversion as long as PM1 and PM0 are set to 1 in Figure 21 shows the general diagram for this sequence. the write transfer during that same conversion. To ensure continued operation in normal mode, PM1 and PM0 must both Auto Shutdown (PM1 = 0, PM0 = 1) be loaded with 1 on every data transfer, assuming a write In this mode, the AD7923 automatically enters shutdown at the operation is taking place. If the write bit is set to 0, the power end of each conversion when the control register is updated. When management bits are left unchanged and the part remains in the part is in shutdown, the track-and-hold is in hold mode. normal mode. Figure 22 shows the general diagram of the operation of the AD7923 in this mode. In shutdown mode all internal circuitry Sixteen serial clock cycles are required to complete the conver- on the AD7923 is powered down. The part retains information sion and access the conversion result. The track-and-hold go in the control register during shutdown. The AD7923 remains back into track on the 14th SCLK falling edge. CS may then idle CS in shutdown until the next falling edge it receives. On this high until the next conversion or may idle low until sometime CS falling edge, the track-and-hold that was in hold while the prior to the next conversion (effectively idling CS low). part was in shutdown returns to tracking. Wake-up time from For specified performance, the throughput rate should not auto shutdown is 1 μs maximum, and the user should ensure exceed 200 kSPS, which means there should be no less than 5 μs that 1 μs has elapsed before attempting a valid conversion. When CS between consecutive falling edges of when converting. The running the AD7923 with a 20 MHz clock, one dummy 16 SCLK actual frequency of the SCLK used determines the duration of transfer should be sufficient to ensure that the part is fully powered the conversion within this 5 μs cycle; however, once a conver- up. During this dummy transfer, the contents of the control register should remain unchanged, therefore the write bit should be 0 sion is complete, and CS has returned high, a minimum of the on the DIN line. Depending on the SCLK frequency used, this quiet time, t , must elapse before bringing CS low again to QUIET dummy transfer may affect the achievable throughput rate of the initiate another conversion. part, with every other data transfer being a valid conversion result. If, for example, the maximum SCLK frequency of 20 MHz is used, the auto shut-down mode could be used at the full through- out rate of 200 kSPS without affecting the throughput rate at all. Rev. C | Page 17 of 24 03086-020 AD7923 Only a portion of the cycle time is taken up by the conversion If the desired mode of operation is full shutdown, then again time and the dummy transfer for wakeup. In this mode, the only one dummy cycle is required after supplies are applied. In power con-sumption of the part is greatly reduced because the this dummy cycle, the user simply sets the power management part enters shutdown at the end of each conversion. When the bits, PM1, PM0 = 1, 0, and upon the rising edge of CS at the control register is programmed to move into auto shutdown, it end of that serial transfer, the part enters full shutdown. If the does so at the end of the conversion. The user can move the desired mode of operation is auto shutdown after supplies are CS ADC in and out of the low power state by controlling the applied, two dummy cycles are required, the first with DIN tied signal. high and the second dummy cycle to set the power manage- CS ment bits PM1 and PM0 = 0,1. On the second rising edge POWERING UP THE AD7923 after the supplies are applied, the control register contains the When supplies are first applied to the AD7923, the ADC can correct information and the part enters auto shutdown mode as power up in any of the operating modes of the part. To ensure programmed. If power consumption is of critical concern, then that the part is placed into the required operating mode, the in the first dummy cycle the user may set PM1, PM0 = 1, 0, that user should perform a dummy cycle operation, as outlined in is, full shutdown, and then place the part into auto shutdown in Figure 23 through Figure 25. the second dummy cycle. For illustration purposes, Figure 25 is shown with DIN tied high on the first dummy cycle in this case. The dummy conversion operation must be performed to place the part into the desired mode of operation. To ensure that the Figure 23, Figure 24, and Figure 25 each show the required part is in normal mode, this dummy cycle operation can be dummy cycle(s) after supplies are applied in the case of normal performed with the DIN line tied high, that is, PM1, PM0 = 1, 1 mode, full shutdown mode, and auto shutdown mode, respect- (depending on other required settings in the control register), ively, being the desired mode of operation. but the minimum power-up time of 1 μs must be allowed from CS the rising edge of , where the control register is updated, before attempting the first valid conversion. This is to allow for the possibility that the part initially powered up in shutdown. PART IS IN FULL PART BEGINS TO POWER UP ON THE PART IS FULLY POWERED UP SHUTDOWN CS RISING EDGE AS PM1 = PM0 =1 ONCE t HAS ELAPSED POWER UP t 12 CS 1 14 16 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER DIN CONTROL REGISTER IS LOADED ONTHE TO KEEPTHE PART IN NORMAL MODE, LOAD FIRST 12 CLOCKS. PM1 = 1, PM0 = 1 PM1 = PM0 = 1 IN CONTROL REGISTER Figure 21. Full Shutdown Mode Operation PART ENTERS PART ENTERS PART BEGINS SHUTDOWN ON CS SHUTDOWN ON CS TO POWER RISING EDGE AS RISING EDGE AS UP ON CS PART IS FULLY POWERED UP PM1 = 0, PM0 =1 PM1 = 0, PM0 =1 FALLING EDGE CS DUMMY CONVERSION 1 12 1611 1261 12 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE CONTROL REGISTER CONTENTS SHOULD TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1 FIRST 12 CLOCKS, PM1 = 0, PM0 = 1 NOT CHANGE, WRITE BIT = 0 IN CONTROL REGISTER OR SET WRITE BIT = 0 Figure 22. Auto Shutdown Mode Operation Rev. C | Page 18 of 24 03086-022 03086-021 AD7923 PART IS IN IF IN SHUTDOWN AT POWER-ON UNKNOWN MODE PART BEGINS TO POWER UP ON ALLOW t TO ELAPSE AFTER POWER-ON CS RISING EDGE AS PM1 = PM0 = 1 POWER t 12 CS 1 14 16 1 14 16 SCLK DOUT INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA INTO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 23. Placing the AD7923 into Normal Mode after Supplies are First Applied PART IS IN PART ENTERS SHUTDOWN ON UNKNOWN MODE CS RISING EDGE AS PM1 = PM0 = 0 AFTER POWER-ON CS 11416 SCLK DOUT INVALID DATA DIN DATA INTO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0 Figure 24. Placing the AD7923 into Full Shutdown Mode after Supplies are First Applied PART IS IN UNKNOWN MODE PART ENTERS AUTO SHUTDOWN ON AFTER POWER-ON CS RISING EDGE AS PM1 = 0, PM0 = 1 CS 1 14 16 1 14 16 SCLK DOUT INVALID DATA INVALID DATA DIN DATA INTO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 0, PM0 = 1 Figure 25. Placing the AD7923 into Auto Shutdown Mode after Supplies are First Applied cycle time is 5 μs when the sampling rate is at a maximum of POWER vs. THROUGHPUT RATE 200 kSPS. If the AD7923 is placed into shutdown for the In auto shutdown mode, the average power consumption of the remainder of the cycle time, then on average far less power is ADC can be reduced at any given throughput rate. The power consumed in every cycle compared to leaving the device in saving depends on the SCLK frequency used, that is, conversion normal mode. Furthermore, Figure 26 shows how, as the time. In some cases where the conversion time is a large propor- throughput rate is reduced, the part remains in its shutdown tion of the cycle time, the throughput rate needs to be reduced longer and the average power consumption drops accordingly to take advantage of the power-down modes. Assuming a over time. 20 MHz SCLK is used, the conversion time is 800 ns, but the Rev. C | Page 19 of 24 03086-024 03086-025 03086-023 AD7923 For example, if the AD7923 is operated in a continuous samp- Sixteen serial clock cycles are required to perform the conver- ling mode, with a throughput rate of 200 kSPS and an SCLK of sion process and to access data from the AD7923. For the 20 MHz (AV = 5 V), and the device is placed in auto shut- AD7923, the 12 bits of data are preceded by two leading 0s and DD down mode, that is, if PM1 = 0 and PM0 = 1, then the power Channel Address Bits ADD1 and ADD0, identifying which consumption is calculated as follows: channel the result corresponds to. CS going low clocks out the first leading 0 to be read by the microcontroller or DSP on the The maximum power dissipation during conversion is 13.5 mW first falling edge of SCLK. The first falling edge of SCLK also (IDD = 2.7 mA max, AVDD = 5 V). If the power-up time from auto clocks out the second leading 0 to be read by the microcon- shutdown is one dummy cycle, that is 1 μs, and the remaining troller or DSP on the second SCLK falling edge, and so on. The conversion time is another cycle, that is, 800 ns, then the remaining two address bits and 12 data bits are then clocked out AD7923 can be said to dissipate 13.5 mW for 1.8 μs during each by subsequent SCLK falling edges, beginning with the first conversion cycle. For the remainder of the conversion cycle, Address Bit ADD1, thus the second falling clock edge on the 3.2 μs, the part remains in shutdown. The AD7923 can be said serial clock has the second leading 0 and also clocks out to dissipate 2.5 μW for the remaining 3.2 μs of the conver-sion Address Bit ADD1. The final bit in the data transfer is valid on cycle. If the throughput rate is 200 kSPS, the cycle time is the 16th falling edge, having been clocked out on the previous 5 μs and the average power dissipated during each cycle is (15th) falling edge. (1.8/5) × (13.5 mW) + (3.2/5) × (2.5 μW) = 4.8616 mW. Writing information to the control register takes place on the Figure 26 shows the maximum power vs. throughput rate when first 12 falling edges of SCLK in a data transfer, assuming the using the auto shutdown mode with 5 V and 3 V supplies. MSB, that is, the write bit, has been set to 1. 10 The 16-bit word read from the AD7923 always contain two leading 0s, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. AV = 5V DD AV = 3V DD 1 Writing Between Conversions As outlined in the operating modes section, not less than 5 μs should be left between consecutive valid conversions. There is one exception, however: consider the case when writing to the 0.1 AD7923 to power it up from shutdown prior to a valid conver- sion. The user must write to the part to tell it to power up before it can convert successfully. Once the serial write to power up has finished, the user might want to perform the conversion as 0.01 06 20 400 80 100 120 140 160 180 100 soon as possible without waiting an additional 5 μs before THROUGHPUT (kSPS) CS bringing low for the conversion. In this case, as long as there Figure 26. Power vs. Throughput Rate is a minimum of 5 μs between each valid conversion, only the SERIAL INTERFACE quiet time between the CS rising edge at the end of the write to power up and the next CS falling edge needs to be met. Figure 27 shows the detailed timing diagrams for serial inter- Figure 28 illustrates this point. Note that when writing to the facing to the AD7923. The serial clock provides the conversion AD7923 between these valid conversions, the DOUT line is not clock and controls the transfer of information to and from the driven during the extra write operation. AD7923 during each conversion. It is critical that an extra write operation as outlined above is CS The signal initiates the data transfer and conversion process. never issued between valid conversions when the AD7923 is The falling edge of CS puts the track-and-hold into hold mode executing a sequence function, because the falling edge of CS in and takes the bus out of three-state; the analog input is sampled the extra write moves the mux to the next channel in the at this point. The conversion is also initiated at this point and sequence. This means that when the next valid conversion takes requires 16 SCLK cycles to complete. The track-and-hold returns place a channel result would be missed. to track mode at Point B on the 14th SCLK falling edge, as shown in Figure 27. On the 16th SCLK falling edge the DOUT CS line returns to three-state. If the rising edge of occurs before 16 SCLKs have elapsed, the conversion is terminated, the DOUT line returns to three-state, and the control register is not updated; otherwise DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 27. Rev. C | Page 20 of 24 POWER (mW) 03086-026 AD7923 CS t CONVERT t t B 2 6 1 2 3 4 5 6 11 12 13 14 15 16 SCLK t 5 t 11 t t 3 7 t t t QUIET 4 8 ZERO ADD1 ADD0 DB11 DB10 DB4 DB3 DB2 DB1 DB0 DOUT THREE- THREE- 2 IDENTIFICATION STATE STATE ZERO BITS t t 10 9 WRITE SEQ1 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC DIN Figure 27. Serial Interface Timing Diagram t 5s MIN CYCLE t MIN QUIET CS 116 1 16 116 SCLK DOUT VALID DATA VALID DATA DIN POWER-UP Figure 28. General Timing Diagram MICROPROCESSOR INTERFACING 1 1 The serial interface on the AD7923 allows the part to be directly TMS320C541 AD7923 connected to a range of many different microprocessors. This section explains how to interface the AD7923 with some of the SCLK CLKX more common microcontroller and DSP serial interface protocols. CLKR DOUT DR AD7923-to-TMS320C541 DIN DT The serial interface on the TMS320C541 uses a continuous FSX CS serial clock and frame synchronization signals to synchronize FSR V DRIVE the data transfer operations with peripheral devices like the CS AD7923. The input allows easy interfacing between the TMS320C541 and the AD7923 without any glue logic required. 1 ADDITIONAL PINS REMOVED FOR CLARITY. V DD The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (Tx serial clock on Serial Port 0) Figure 29. Interfacing to the TMS320C541 and FSX0 (Tx frame sync from Serial Port 0). The serial port AD7923-to-ADSP-21xx control register (SPC) must have the following setup: FO = 0, The ADSP-21xx family of DSPs is interfaced directly to the FSM = 1, MCM = 1, and TXM = 1. The connection diagram is AD7923 without any glue logic required. The V pin of the shown in Figure 29. It should be noted that for signal processing DRIVE AD7923 takes the same supply voltage as the ADSP-218x, applications, it is imperative that the frame synchronization which allows the ADC to operate at a higher voltage than the signal from the TMS320C541 provides equidistant sampling. serial interface, that is, ADSP-218x, if necessary. The VDRIVE pin of the AD7923 takes the same supply voltage as the TMS320C541. This allows the ADC to operate at a higher The SPORT0 control register should be set up as follows: voltage than the serial interface, that is, the TMS320C541, if necessary. TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right justify data SLEN = 1111, 16-bit data-words ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0 ITFS = 1 Rev. C | Page 21 of 24 03086-028 03086-027 03086-029 AD7923 The connection diagram is shown in Figure 30. The ADSP-218x the value 803, 100.5 SCLKs occur between interrupts and has the TFS and RFS of the SPORT tied together, with TFS set subsequently between transmit instructions. This situation as an output and RFS set as an input. The DSP operates in results in nonequidistant sampling since the transmit instruction occurs on a SCLK edge. If the number of SCLKs alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on between interrupts is an integer of N, equidistant sampling is the TFS is tied to CS and, as with all signal processing applica- implemented by the DSP. tions, equidistant sampling is necessary. However, in this AD7923-to-DSP563xx example, the timer interrupt is used to control the sampling rate The connection diagram in Figure 31 shows how the AD7923 of the ADC, and under certain conditions equidistant sampling can be connected to the synchronous serial interface (ESSI) of might not be achieved. the DSP563xx family of DSPs from Motorola. Each ESSI (two 1 1 ADSP-218x AD7923 on board) is operated in synchronous mode (SYN bit in CRB = 1), with an internally generated word length frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal SCLK SCLK operation of the ESSI is selected by making MOD = 0 in the DOUT DR CRB. Set the word length to 16 by setting bits WL1 = 1 and CS RFS WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so TFS the frame sync is negative. It should be noted that for signal DIN DT V DRIVE processing applications, it is imperative that the frame synchro- nization signal from the DSP563xx provides equidistant sampling. 1 ADDITIONAL PINS REMOVED FOR CLARITY. V DD In the example shown in Figure 31, the serial clock is taken from the ESSI, therefore the SCK0 pin must be set as an output, Figure 30. Interfacing to the ADSP-218x SCKD = 1. The V pin of the AD7923 takes the same supply DRIVE The timer register, for instance, is loaded with a value that voltage as the DSP563xx, which allows the ADC to operate at a provides an interrupt at the required sample interval. When an higher voltage than the serial interface, that is, DSP563xx, if interrupt is received, a value is transmitted with TFS/DT (ADC necessary. control word). The TFS is used to control the RFS and therefore 1 the reading of data. The frequency of the serial clock is set in 1 DSP563xx AD7923 the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is SCLK SCK checked. The DSP waits until the SCLK has gone high, low, and DOUT SRD high before the transmission starts. If the timer and SCLK DIN STD values are chosen such that the instruction to transmit occurs CS SC2 V DRIVE on or near the rising edge of SCLK, the data can be transmitted, or it can wait until the next clock edge. 1 ADDITIONAL PINS REMOVED FOR CLARITY. For example, if the ADSP-2189 has a 20 MHz crystal such that it V DD has a master clock frequency of 40 MHz, then the master cycle Figure 31. Interfacing to the DSP563xx time is 25 ns. If the SCLKDIV register is loaded with the value 3, then a SCLK of 5 MHz is obtained, and eight master clock periods elapse for every SCLK period. Depending on the throughput rate selected, if the timer registers are loaded with Rev. C | Page 22 of 24 03086-030 03086-031 AD7923 APPLICATION HINTS GROUNDING AND LAYOUT Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF capa- The AD7923 has very good immunity to noise on the power citors to AGND. To achieve the best results from these supplies as can be seen by the PSRR vs. supply ripple frequency decoupling components, they must be placed as close as pos- plot, Figure 6. However, care should still be taken in grounding sible to the device, ideally right up against the device. The 0.1 and layout. μF capacitors should have low effective series resistance (ESR) The printed circuit board that houses the AD7923 should be and low effective series inductance (ESI), such as the common designed such that the analog and digital sections are separated ceramic types or surface mount types, which provide a low and confined to certain areas of the board. This facilitates the impedance path to ground at high frequencies to handle use of ground planes that can be separated easily. A minimum transient currents from internal logic switching. etch technique is generally best for ground planes since it gives EVALUATING THE AD7923 PERFORMANCE the best shielding. All three AGND pins of the AD7923 should be sunk into the AGND plane. Digital and analog ground The recommended layout for the AD7923 is outlined in the planes should be joined at only one place. If the AD7923 is in a evaluation board for the AD7923. The evaluation board pack- system where multiple devices require an AGND to DGND age includes a fully assembled and tested evaluation board, connection, the connection should still be made at one point documentation, and software for controlling the board from the only, a star ground point that should be established as close as PC via the EVAL-CONTROL BRD2. The EVAL-CONTROL possible to the AD7923. BRD2 can be used with the AD7923 evaluation board and many other Analog Devices evaluation boards ending in the CB Avoid running digital lines under the device since they couple designator to demonstrate and evaluate the ac and dc noise onto the die. The analog ground plane should be allowed performance of the AD7923. to run under the AD7923 to avoid noise coupling. The power supply lines to the AD7923 should use as large a trace as The software allows the user to perform ac (fast Fourier possible to provide low impedance paths and reduce the effects transform) and dc (histogram of codes) tests on the AD7923. of glitches on the power supply line. Fast switching signals, like The software and documentation are on a CD shipped with the clocks, should be shielded with digital ground to avoid radiating evaluation board. noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best technique, but is not always possible with a double- sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Rev. C | Page 23 of 24 AD7923 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1, 2, 3, 4 5 Model Temperature Range Linearity Error (LSB) Package Option Package Description AD7923BRU −40°C to +125°C ±1 RU-16 16-Lead TSSOP AD7923BRUZ −40°C to +125°C ±1 RU-16 16-Lead TSSOP AD7923BRUZ-REEL −40°C to +125°C ±1 RU-16 16-Lead TSSOP AD7923BRUZ-REEL7 −40°C to +125°C ±1 RU-16 16-Lead TSSOP AD7923WYRUZ-REEL7 −40°C to +125°C ±1 RU-16 16-Lead TSSOP EVAL-AD7923CBZ Evaluation Board EVAL-CONTROL BRD2 Controller Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 The EVAL-AD7923CBZ can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes. 4 The EVAL-CONTROL BRD2 is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, order the particular ADC evaluation board, for example, the EVAL-AD7923CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board application note for more information. 5 Linearity error refers to integral linearity error. AUTOMOTIVE PRODUCTS The AD7923W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03086-0-5/11(C) Rev. C | Page 24 of 24