ANALOG DEVICES AD7918

8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP AD7908/AD7918/AD7928 FEATURES FUNCTIONAL BLOCK DIAGRAM AV Fast throughput rate: 1 MSPS DD Specified for AVDD of 2.7 V to 5.25 V REF IN Low power V 0 6.0 mW max at 1 MSPS with 3 V supply IN T/H • 13.5 mW max at 1 MSPS with 5 V supply 8-/10-/12-BIT • SUCCESSIVE • APPROXIMATION Eight (single-ended) inputs with sequencer • ADC • Wide input bandwidth • I/P • MUX AD7928, 70 dB min SINAD at 50 kHz input frequency • • Flexible power/serial clock speed management • • No pipeline delays • • High speed serial interface SPI®/QSPI™/ V 7 IN MICROWIRE™/DSP compatible SCLK Shutdown mode: 0.5 μA max DOUT CONTROL LOGIC SEQUENCER 20-lead TSSOP package DIN CS Qualified for automotive applications AD7908/AD7918/AD7928 V DRIVE GENERAL DESCRIPTION GND The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and Figure 1. 12-bit, high speed, low power, 8-channel, successive approximation PRODUCT HIGHLIGHTS ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts 1. High Throughput with Low Power Consumption. The AD7908/ contain a low noise, wide bandwidth track-and-hold amplifier that AD7918/AD7928 offer up to 1 MSPS throughput rates. At the can handle input frequencies in excess of 8 MHz. maximum throughput rate with 3 V supplies, the AD7908/ AD7918/AD7928 dissipate just 6 mW of power maximum. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface 2. Eight Single-Ended Inputs with a Channel Sequencer. with microprocessors or DSPs. The input signal is sampled on the A sequence of channels can be selected, through which CS falling edge of and conversion is also initiated at this point. the ADC cycles and converts on. There are no pipeline delays associated with the part. 3. Single-Supply Operation with VDRIVE Function. The AD7908/ The AD7908/AD7918/AD7928 use advanced design techniques to AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply. achieve very low power dissipation at maximum throughput rates. The VDRIVE function allows the serial interface to connect directly At maximum throughput rates, the AD7908/AD7918/AD7928 to either 3 V or 5 V processor systems independent of AV . DD consume 2 mA maximum with 3 V supplies; with 5 V supplies, the 4. Flexible Power/Serial Clock Speed Management. The conversion current consumption is 2.7 mA maximum. rate is determined by the serial clock, allowing the conversion Through the configuration of the control register, the analog input time to be reduced through the serial clock speed increase. The range for the part can be selected as 0 V to REF or 0 V to 2 × IN parts also feature various shutdown modes to maximize power REF , with either straight binary or twos complement output IN efficiency at lower throughput rates. Current consumption is coding. The AD7908/AD7918/AD7928 each feature eight single- 0.5 μA max when in full shutdown. ended analog inputs with a channel sequencer to allow a 5. No Pipeline Delay. The parts feature a standard successive preprogrammed selection of channels to be converted sequentially. approximation ADC with accurate control of the sampling The conversion time for the AD7908/AD7918/AD7928 is CS instant via a input and once off conversion control. determined by the SCLK frequency, which is also used as the master clock to control the conversion. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 03089-001 AD7908/AD7918/AD7928 TABLE OF CONTENTS Features .............................................................................................. 1 Control Register.............................................................................. 15 General Description ......................................................................... 1 Sequencer Operation ................................................................. 16 Functional Block Diagram .............................................................. 1 SHADOW Register .................................................................... 17 Product Highlights ........................................................................... 1 Circuit Information.................................................................... 18 Revision History ............................................................................... 2 Converter Operation.................................................................. 18 Specifications..................................................................................... 3 ADC Transfer Function............................................................. 19 AD7908 Specifications................................................................. 3 Handling Bipolar Input Signals ................................................ 19 AD7918 Specifications................................................................. 5 Typical Connection Diagram ................................................... 19 AD7928 Specifications................................................................. 7 Modes of Operation ................................................................... 21 Timing Specifications .................................................................. 9 Power vs. Throughput Rate....................................................... 23 Absolute Maximum Ratings.......................................................... 10 Serial Interface ............................................................................ 23 ESD Caution................................................................................ 10 Microprocessor Interfacing....................................................... 24 Pin Configuration and Function Descriptions........................... 11 Application Hints ....................................................................... 27 Terminology .................................................................................... 12 Outline Dimensions....................................................................... 28 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 29 Performance Curves................................................................... 13 Automotive Products................................................................. 29 REVISION HISTORY 12/10—Rev. C to Rev. D 6/06—Rev. A to Rev. B Changes to Features Section............................................................ 1 Updated Format..................................................................Universal Added Automotive SINAD and SNR Parameters (Table 1)........ 3 Changes to Reference Section....................................................... 21 Added Automotive SINAD and SNR Parameters (Table 2)........ 5 9/03—Rev. 0 to Rev. A Added Automotive SINAD and SNR Parameters (Table 3)........ 7 Changes to Figure 3........................................................................ 15 Added Automotive Temperature Range (Table 5) ....................... 7 Changes to Reference section ....................................................... 18 Added Automotive Products Section .......................................... 28 Changes to Ordering Guide .......................................................... 28 11/08—Rev. B to Rev. C Changes to ESD Parameter, Table 5 ............................................. 10 Rev. D | Page 2 of 32 AD7908/AD7918/AD7928 SPECIFICATIONS AD7908 SPECIFICATIONS AV = V = 2.7 V to 5.25 V, REF = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. DD DRIVE IN SCLK A MIN MAX Table 1. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz 2 Signal-to-(Noise + Distortion) (SINAD) 49 dB min B models 48.5 dB min W models 2 Signal-to-Noise Ratio (SNR) 49 dB min B models 48.5 dB min W models 2 Total Harmonic Distortion (THD) −66 dB max 2 Peak Harmonic or Spurious Noise (SFDR) −64 dB max 2 Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ f = 400 kHz IN Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB 2 DC ACCURACY Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed no missed codes to 8 bits 0 V to REFIN Input Range Straight binary output coding Offset Error ±0.5 LSB max Offset Error Match ±0.05 LSB max Gain Error ±0.2 LSB max Gain Error Match ±0.05 LSB max 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error ±0.2 LSB max Positive Gain Error Match ±0.05 LSB max Zero Code Error ±0.5 LSB max Zero Code Error Match ±0.1 LSB max Negative Gain Error ±0.2 LSB max Negative Gain Error Match ±0.05 LSB max ANALOG INPUT Input Voltage Ranges 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AV /V = 4.75 V to DD DRIVE 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE 3 Input Capacitance, C 10 pF max IN Rev. D | Page 3 of 32 AD7908/AD7918/AD7928 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AVDD 2.7/5.25 V min/max V 2.7/5.25 V min/max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK On or Off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Using Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature ranges as follows: B version: −40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. D | Page 4 of 32 AD7908/AD7918/AD7928 AD7918 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK 2 Signal-to-(Noise + Distortion) (SINAD) 61 dB min B models 60.5 dB min W models 2 Signal-to-Noise Ratio (SNR) 61 dB min B models 60.5 dB min W models 2 Total Harmonic Distortion (THD) −72 dB max 2 Peak Harmonic or Spurious Noise (SFDR) −74 dB max 2 Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB 2 DC ACCURACY Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 0 V to REF Input Range Straight binary output coding IN Offset Error ±2 LSB max Offset Error Match ±0.2 LSB max Gain Error ±0.5 LSB max Gain Error Match ±0.2 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with twos IN IN IN IN complement output coding Positive Gain Error ±0.5 LSB max Positive Gain Error Match ±0.2 LSB max Zero Code Error ±2 LSB max Zero Code Error Match ±0.2 LSB max Negative Gain Error ±0.5 LSB max Negative Gain Error Match ±0.2 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF V RANGE bit set to 1 IN 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance, CIN 10 pF max Rev. D | Page 5 of 32 AD7908/AD7918/AD7928 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AVDD 2.7/5.25 V min/max V 2.7/5.25 V min/max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Using Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature ranges as follows: B version: –40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. D | Page 6 of 32 AD7908/AD7918/AD7928 AD7928 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK 2 Signal-to-(Noise + Distortion) (SINAD) 70 dB min @ 5 V, B models 69.5 dB min @ 5 V, W models 69 dB min @ 3 V typically 70 dB 2 Signal-to-Noise Ratio (SNR) 70 dB min B models 69.5 dB min W models 2 Total Harmonic Distortion (THD) −77 dB max @ 5 V typically −84 dB −73 dB max @ 3 V typically −77 dB Peak Harmonic or Spurious Noise −78 dB max @ 5 V typically −86 dB 2 (SFDR) −76 dB max @ 3 V typically −80 dB 2 Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ f = 400 kHz IN Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB 2 DC ACCURACY Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding Offset Error ±8 LSB max Typically ±0.5 LSB Offset Error Match ±0.5 LSB max Gain Error ±1.5 LSB max Gain Error Match ±0.5 LSB max 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error ±1.5 LSB max Positive Gain Error Match ±0.5 LSB max Zero Code Error ±8 LSB max Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to REFIN V RANGE bit set to 1 0 to 2 × REF V RANGE bit set to 0, AV /V = 4.75 V to 5.25 V IN DD DRIVE DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE 3 Input Capacitance, C 10 pF max IN Rev. D | Page 7 of 32 AD7908/AD7918/AD7928 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AVDD 2.7/5.25 V min/max V 2.7/5.25 V min/max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Using Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature ranges as follows: B Version: −40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. D | Page 8 of 32 AD7908/AD7918/AD7928 TIMING SPECIFICATIONS 1 AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX AD7908/AD7918/AD7928 Parameter AV = 3 V AV = 5 V Unit Description DD DD 2 f 10 10 kHz min SCLK 20 20 MHz max t 16 × t 16 × t CONVERT SCLK SCLK tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next conversion 10 10 ns min CS to SCLK setup time t2 3 t Delay from CS until DOUT three-state disabled 3 35 30 ns max 3 t 40 40 ns max Data access time after SCLK falling edge 4 t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to DOUT valid hold time 4 t 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance 8 t 10 10 ns min DIN setup time prior to SCLK falling edge 9 t 5 5 ns min DIN hold time after SCLK falling edge 10 th t 20 20 ns min 16 SCLK falling edge to CS high 11 t12 1 1 μs max Power-up time from full power-down/auto shutdown mode 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V . DRIVE 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 8 time of the part and is independent of the bus loading. I 200µA OL TO OUTPUT 1.6V PIN C L 50pF I 200µA OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 9 of 32 03089-002 AD7908/AD7918/AD7928 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any AV to AGND −0.3 V to +7 V DD other conditions above those indicated in the operational V to AGND −0.3 V to AV + 0.3 V DRIVE DD section of this specification is not implied. Exposure to absolute Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V maximum rating conditions for extended periods may affect Digital Input Voltage to AGND −0.3 V to +7 V device reliability. Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V REF to AGND −0.3 V to AV + 0.3 V IN DD Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Automotive Temperature Range −40°C to +125°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 143°C/W (TSSOP) θJC Thermal Impedance 45°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 10 of 32 AD7908/AD7918/AD7928 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 20 AGND DIN 2 19 V DRIVE 3 18 CS DOUT AD7908/ AGND 4 17 AGND AD7918/ AV 5 16 V 0 AD7928 DD IN AV 615 V 1 DD IN TOP VIEW (Not to Scale) V 2 REF714 IN IN 813 V 3 AGND IN V 4 V 7 9 12 IN IN 10 11 V 5 V 6 IN IN Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7908/AD7918/AD7928. 2 DIN Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7908/AD7918/AD7928, and also frames the serial data transfer. 4, 8, 17, 20 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AV DD Analog Power Supply Input. The AVDD range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. 7 REFIN Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 16 to 9 V 0 to V 7 Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are IN IN multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. 18 DOUT Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 19 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of DRIVE the AD7908/AD7918/AD7928 operates. Rev. D | Page 11 of 32 03089-003 AD7908/AD7918/AD7928 TERMINOLOGY Integral Nonlinearity Negative Gain Error Match This is the maximum deviation from a straight line passing This is the difference in negative gain error between any two through the endpoints of the ADC transfer function. The channels. endpoints of the transfer function are zero scale, a position 1 LSB Channel-to-Channel Isolation below the first code transition, and full scale, a position 1 LSB Channel-to-channel isolation is a measure of the level of above the last code transition. crosstalk between channels. It is measured by applying a full- Differential Nonlinearity scale 400 kHz sine wave signal to all seven nonselected input This is the difference between the measured and the ideal 1 LSB channels and determining how much that signal is attenuated change between any two adjacent codes in the ADC. in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/ Offset Error AD7928. This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition, but Offset Error Match not the converter’s linearity. Power supply rejection is the This is the difference in offset error between any two channels. maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value (see the Gain Error Performance Curves section). This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, REFIN – 1 LSB) after the Track-and-Hold Acquisition Time offset error has been adjusted out. The track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time Gain Error Match required for the output of the track-and-hold amplifier to reach This is the difference in gain error between any two channels. its final value, within ±1 LSB, after the end of conversion. Zero Code Error Signal-to-(Noise + Distortion) Ratio This applies when using the twos complement output coding This is the measured ratio of signal-to-(noise + distortion) at option, in particular to the 2 × REF input range with −REF IN IN the output of the ADC. The signal is the rms amplitude of the to +REFIN biased about the REFIN point. It is the deviation of the fundamental. Noise is the sum of all nonfundamental signals up midscale transition (all 0s to all 1s) from the ideal VIN voltage, to half the sampling frequency (fS/2), excluding dc. The ratio is that is, REFIN − 1 LSB. dependent on the number of quantization levels in the Zero Code Error Match digitization process; the more levels, the smaller the This is the difference in zero code error between any two quantization noise. The theoretical signal-to-(noise + channels. distortion) ratio for an ideal N-bit converter with a sine wave input is given by Positive Gain Error Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with −REFIN Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter, to +REFIN biased about the REFIN point. It is the deviation of the this is 62 dB; and for an 8-bit converter, this is 50 dB. last code transition (011. . .110) to (011 . . . 111) from the ideal (that is, +REF − 1 LSB) after the zero code error has been Total Harmonic Distortion IN adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/ Positive Gain Error Match AD7928, it is defined as: This is the difference in positive gain error between any two channels. 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD() dB= 20log Negative Gain Error V 1 This applies when using the twos complement output coding where V1 is the rms amplitude of the fundamental and V2, V3, option, in particular to the 2 × REFIN input range with −REFIN V4, V5, and V6 are the rms amplitudes of the second through the to +REF biased about the REF point. It is the deviation of the IN IN sixth harmonics. first code transition (100 . . . 000) to (100 . . . 001) from the ideal (that is, −REF + 1 LSB) after the zero code error has been IN adjusted out. Rev. D | Page 12 of 32 AD7908/AD7918/AD7928 TYPICAL PERFORMANCE CHARACTERISTICS PERFORMANCE CURVES Figure 7 shows a graph of total harmonic distortion vs. analog input frequency for various supply voltages, and Figure 8 shows a Figure 4 shows a typical FFT plot for the AD7928 at 1 MSPS graph of total harmonic distortion vs. analog input frequency sample rate and 50 kHz input frequency. Figure 5 shows the for various source impedances. See the Analog Input section. signal-to-(noise + distortion) ratio performance vs. input frequency for various supply voltages while sampling at 1 MSPS Figure 9 and Figure 10 show typical INL and DNL plots for the with an SCLK of 20 MHz. AD7928. Figure 6 shows the power supply rejection ratio vs. supply ripple 0 AV = 5V DD frequency for the AD7928 when no decoupling is used. The –10 200mV p-p SINEWAVE ON AV DD REF = 2.5V, 1µF CAPACITOR power supply rejection ratio is defined as the ratio of the power IN T = 25°C A –20 in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AV supply of –30 DD frequency f S –40 PSRR(dB) = 10 log(Pf/Pfs) –50 –60 Pf is equal to the power at frequency f in ADC output; PfS is equal to the power at frequency fS coupled onto the ADC AVDD –70 supply. Here a 200 mV p-p sine wave is coupled onto the AVDD –80 supply. –90 0 100 200 300 400 500 600 700 800 900 1000 4096 POINT FFT –10 SUPPLY RIPPLE FREQUENCY (kHz) AV = 5V DD f = 1MSPS Figure 6. AD7928 PSRR vs. Supply Ripple Frequency SAMPLE f = 50kHz IN –30 SINAD = 71.147dB –50 THD = –87.229dB f = 1MSPS SAMPLE SFDR = –90.744dB T = 25°C A –55 RANGE = 0V TO REF –50 IN AV = V = 2.70V DD DRIVE –60 –70 –65 AV = V = 3.60V DD DRIVE –70 –90 –75 –110 –80 0 50 100 150 200 250 300 350 400 450 500 AV = V = 4.75V DD DRIVE FREQUENCY (kHz) –85 Figure 4. AD7928 Dynamic Performance at 1 MSPS AV = V = 5.25V DD DRIVE –90 75 10 100 1000 INPUT FREQUENCY (kHz) AV = V = 5.25V DD DRIVE AV = V = 4.75V Figure 7. AD7928 THD vs. Analog Input Frequency for DD DRIVE Various Supply Voltages at 1 MSPS 70 AV = V = 3.60V DD DRIVE 65 60 f = 1MSPS SAMPLE T = 25°C AV = V = 2.70V A DD DRIVE RANGE = 0V TO REF IN 55 10 100 1000 INPUT FREQUENCY (kHz) Figure 5. AD7928 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS Rev. D | Page 13 of 32 SINAD (dB) SNR (dB) 03089-005 03089-004 THD (dB) PSRR (dB) 03089-007 03089-006 AD7908/AD7918/AD7928 –50 1.0 f = 1MSPS R = 1000Ω SAMPLE IN AV = V = 5V DD DRIVE T = 25°C A 0.8 –55 TEMPERATURE = 25°C RANGE = 0V TO REF IN AV = 5.25V 0.6 DD –60 0.4 –65 0.2 R = 100Ω IN –70 0 R = 50Ω IN –75 –0.2 –0.4 R = 10Ω IN –80 –0.6 –85 –0.8 –90 –1.0 10 100 1000 0 512 1024 1536 2048 2560 3072 3584 4096 INPUT FREQUENCY (kHz) CODE Figure 8. AD7928 THD vs. Analog Input Frequency for Figure 10. AD7928 Typical DNL Various Source Impedances 1.0 AV = V = 5V DD DRIVE 0.8 TEMPERATURE = 25°C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Figure 9. AD7928 Typical INL Rev. D | Page 14 of 32 INL ERROR (LSB) THD (dB) 03089-009 03089-008 DNL ERROR (LSB) 03089-010 AD7908/AD7918/AD7928 CONTROL REGISTER The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 7. MSB LSB WRITE SEQ DON’TCARE ADD2 ADD1 ADD0 PM1 PM0 SHADOW DON’TCARE RANGE CODING Table 7. Control Register Bit Functions Bit Mnemonic Comment 11 WRITE The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged. 10 SEQ The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the SHADOW register (see the SHADOW register bit map). 9 DON’TCARE 8 to 6 ADD2 to These three address bits are loaded at the end of the present conversion sequence and select which analog input ADD0 channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. 5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in Table 9. 3 SHADOW The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the SHADOW register (see Table 10). 2 DON’TCARE 1 RANGE This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input range extends from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For 0 V to 2 × REF , AV = 4.75 V to 5.25 V. IN DD 0 CODING This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). Table 8. Channel Selection ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 VIN0 0 0 1 V 1 IN 0 1 0 V 2 IN 0 1 1 V 3 IN 1 0 0 VIN4 1 0 1 VIN5 1 1 0 VIN6 1 1 1 V 7 IN Rev. D | Page 15 of 32 AD7908/AD7918/AD7928 Table 9. Power Mode Selection PM1 PM0 Mode 1 1 Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928. 1 0 Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 1 Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 Invalid Selection. This configuration is not allowed. SEQUENCER OPERATION The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 10 outlines the four modes of operation of the sequencer. Table 10. Sequence Selection SEQ SHADOW Sequence Type 0 0 This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see Figure 11). 0 1 This configuration selects the SHADOW register for programming. The following write operation loads the contents of the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive valid CS falling edge (see the SHADOW Register section, SHADOW register bit map, and Figure 12). The channels selected need not be consecutive. 1 0 If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence, without terminating the cycle. 1 1 This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the control register (see Figure 13). Rev. D | Page 16 of 32 AD7908/AD7918/AD7928 SHADOW REGISTER MSB LSB VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Sequence One Sequence Two The SHADOW register on the AD7908/AD7918/AD7928 is a POWER-ON 16-bit, write-only register. Data is loaded from the DIN pin of DUMMY CONVERSION the AD7908/AD7918/AD7928 on the falling edge of SCLK. The DIN = ALL 1s data is transferred on the DIN line at the same time that a conversion result is read from the part. This requires 16 serial DIN: WRITE TO CONTROL REGISTER, CS WRITE BIT = 1, SELECT CODING, RANGE, clock falling edges for the data transfer. The information is AND POWER MODE. SELECT A2 TO A0 FOR CONVERSION. clocked into the SHADOW register, provided that the SEQ and SEQ = SHADOW = 0 SHADOW bits were set to 0,1, respectively, in the previous write to the control register. MSB denotes the first bit in the DOUT: CONVERSION RESULT FROM data stream. Each bit represents an analog input from Channel 0 PREVIOUSLY SELECTED CHANNEL A2 TO A0. CS to Channel 7. Through programming the SHADOW register, WRITE BIT = 1, DIN: WRITE TO CONTROL REGISTER, SEQ = SHADOW = 0 two sequences of channels can be selected, through which the WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. AD7908/AD7918/AD7928 cycle with each consecutive SELECT A2 TO A0 FOR CONVERSION. SEQ = SHADOW = 0 conversion after the write to the SHADOW register. Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart Sequence One is performed first and then Sequence Two. If the user does not wish to perform a second sequence option, then all 0s must be written to the last 8 LSBs of the SHADOW POWER-ON register. To select a sequence of channels, the associated channel bit must be set for each analog input. The AD7908/AD7918/ DUMMY CONVERSION DIN = ALL 1s AD7928 continuously cycle through the selected channels in ascending order beginning with the lowest channel, until a DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, CS write operation occurs (that is, the WRITE bit is set to 1) with AND POWER MODE. SELECT CHANNEL A2 TO A0 the SEQ and SHADOW bits configured in any way except 1, 0, FOR CONVERSION. SEQ = 0 SHADOW = 1 (see Table 10). The bit functions are outlined in the SHADOW register bit map. DOUT: CONVERSION RESULT FROM Figure 11 reflects the traditional operation of a multichannel PREVIOUSLY SELECTED CHANNEL A2 TO A0. CS ADC, where each serial transfer selects the next channel for DIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO conversion. In this mode of operation the sequencer function is CONVERT ON; CHANNELS SELECTED NEED NOT BE CONSECUTIVE not used. CHANNELS WRITE BIT = 0 WRITE BIT = 1 Figure 12 shows how to program the AD7908/AD7918/AD7928 SEQ = 1, SHADOW = 0 to continuously convert on a particular sequence of channels. CONTINUOUSLY CONTINUOUSLY To exit this mode of operation and revert back to the traditional CONVERTS ON CONVERTS ON THE CS THE SELECTED SELECTED SEQUENCE mode of operation of a multichannel ADC (as outlined in SEQUENCE OF OF CHANNELS BUT WILL CHANNELS ALLOW RANGE, CODING, Figure 11), ensure that the WRITE bit = 1 and the SEQ = AND SO ON, TO CHANGE IN THE CONTROL SHADOW = 0 on the next serial transfer. Figure 13 shows how REGISTER WITHOUT INTERRUPTING THE a sequence of consecutive channels can be converted on without SEQUENCE, PROVIDED WRITE BIT = 0 SEQ = 1 SHADOW = 0 having to program the SHADOW register or write to the part WRITE BIT = 0 WRITE BIT = 1 on each serial transfer. Again, to exit this mode of operation and SEQ = 1, SHADOW = 0 revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 11), ensure the WRITE bit = 1 and Figure 12. SEQ Bit = 0, SHADOW Bit = 1 Flowchart the SEQ = SHADOW = 0 on the next serial transfer. Rev. D | Page 17 of 32 03089-012 03089-011 AD7908/AD7918/AD7928 POWER-ON REF or 0 V to 2 × REF . Figure 14 and Figure 15 show IN IN simplified schematics of the ADC. The ADC is comprised of DUMMY CONVERSION control logic, SAR, and a capacitive DAC, which are used to add DIN = ALL 1s and subtract fixed amounts of charge from the sampling DIN: WRITE TO CONTROL REGISTER, capacitor to bring the comparator back into a balanced WRITE BIT = 1, SELECT CODING, RANGE, CS AND POWER MODE. condition. Figure 14 shows the ADC during its acquisition SELECT CHANNEL A2 TO A0 FOR CONVERSION. phase. SW2 is closed and SW1 is in Position A. The comparator SEQ = 1 SHADOW = 1 is held in a balanced condition and the sampling capacitor acquires the signal on the selected V channel. IN DOUT: CONVERSION RESULT FROM CHANNEL 0. CAPACITIVE DAC CONTINUOUSLY CONVERTS ON A CS CONSECUTIVE SEQUENCE OF WRITE BIT = 0 CHANNELS FROM CHANNEL 0 UP TO, A 4kΩ AND INCLUDING, THE PREVIOUSLY V 0 IN SELECTED A2 TO A0 IN THE CONTROL CONTROL SW1 REGISTER. LOGIC B SW2 V 7 IN COMPARATOR AGND CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS Figure 14. ADC Acquisition Phase BUT WILL ALLOW RANGE, CODING, AND CS SO ON, TO CHANGE IN THE CONTROL WRITE BIT = 1 REGISTER WITHOUT INTERRUPTING When the ADC starts a conversion (see Figure 15), SW2 opens SEQ = 1, SHADOW = 0 THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0 and SW1 moves to Position B, causing the comparator to Figure 13. SEQ Bit = 1, SHADOW Bit = 1 Flowchart become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the CIRCUIT INFORMATION sampling capacitor to bring the comparator back into a The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit, balanced condition. When the comparator is rebalanced, the 10-bit, and 12-bit, single-supply ADCs, respectively. The parts conversion is complete. The control logic generates the ADC can be operated from a 2.7 V to 5.25 V supply. When operated output code. Figure 17 and Figure 18 show the ADC transfer from either a 5 V or 3 V supply, the AD7908/AD7918/AD7928 functions. are capable of throughput rates of 1 MSPS when provided with CA CAP PA ACI CIT TIIV VE E DA DAC C a 20 MHz clock. A 4kΩ The AD7908/AD7918/AD7928 provide the user with an on- V 0 IN CONTROL SW1 chip, track-and-hold ADC, and a serial interface housed in a LOGIC B SW2 20-lead TSSOP package. The AD7908/AD7918/ AD7928 each V 7 IN COMPARATOR have eight single-ended input channels with a channel AGND sequencer, allowing the user to select a channel sequence that Figure 15. ADC Conversion Phase CS the ADC can cycle through with each consecutive falling edge. The serial clock input accesses data from the part, controls Analog Input the transfer of data written to the ADC, and provides the clock Figure 16 shows an equivalent circuit of the analog input source for the successive approximation ADC. The analog input structure of the AD7908/AD7918/AD7928. The two diodes (D1 range for the AD7908/AD7918/ AD7928 is 0 V to REFIN or 0 V and D2) provide ESD protection for the analog inputs. Care to 2 × REFIN, depending on the status of Bit 1 in the control must be taken to ensure that the analog input signal never register. For the 0 to 2 × REFIN range, the part must be operated exceeds the supply rails by more than 300 mV. This causes these from a 4.75 V to 5.25 V supply. diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes The AD7908/AD7918/AD7928 provide flexible power can conduct without causing irreversible damage to the part. management options to allow the user to achieve the best power The Capacitor C1 in Figure 16 is typically about 4 pF and can performance for a given throughput rate. These options are primarily be attributed to pin capacitance. The Resistor R1 is a selected by programming the PM1 and PM0 power lumped component made up of the on resistance of the track- management bits in the control register. and-hold switch and also includes the on resistance of the input CONVERTER OPERATION multiplexer. The total resistance is typically about 400 Ω. The Capacitor C2 is the ADC sampling capacitor and has a The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit capacitance of 30 pF typically. For ac applications, removing successive approximation analog-to-digital converters based high frequency components from the analog input signal is around a capacitive DAC, respectively. The AD7908/AD7918/ recommended by use of an RC lowpass filter on the relevant AD7928 can convert analog input signals in the range 0 V to analog input pin. In applications where harmonic distortion Rev. D | Page 18 of 32 03089-013 03089-015 03089-014 AD7908/AD7918/AD7928 and signal-to-noise ratio are critical, the analog input should be 011…111 driven from a low impedance source. Large source impedances 011…110 • significantly affect the ac performance of the ADC. This can • 000…001 necessitate the use of an input buffer amplifier. The choice of 000…000 111…111 the op amp is a function of the particular application. • • 1LSB = 2 × V /256 AD7908 REF When no amplifier is used to drive the analog input, the source 100…010 1LSB = 2 × V /1024 AD7918 REF 100…001 1LSB = 2 × V /4096 AD7928 REF impedance should be limited to low values. The maximum 100…000 source impedance depends on the amount of total harmonic –V + 1 LSB +V – 1 LSB REF REF V – 1 LSB distortion (THD) that can be tolerated. The THD increases as REF ANALOG INPUT the source impedance increases, and performance degrades (see Figure 8). Figure 18. Twos Complement Transfer Characteristic AV DD with REF ± REF Input Range IN IN HANDLING BIPOLAR INPUT SIGNALS C2 D1 30pF R1 Figure 19 shows how useful the combination of the 2 × REF IN V IN C1 input range and the twos complement output coding scheme is D2 CONVERSION PHASE: SWITCH OPEN 4pF TRACK PHASE: SWITCH CLOSED for handling bipolar input signals. If the bipolar input signal is biased about REFIN and twos complement output coding is selected, then REFIN becomes the zero code point, −REFIN is Figure 16. Equivalent Analog Input Circuit negative full scale and +REF becomes positive full scale, with IN a dynamic range of 2 × REF . IN ADC TRANSFER FUNCTION The output coding of the AD7908/AD7918/AD7928 is either TYPICAL CONNECTION DIAGRAM straight binary or twos complement, depending on the status of Figure 20 shows a typical connection diagram for the the LSB in the control register. The designed code transitions AD7908/AD7918/AD7928. In this setup, the AGND pin is occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so connected to the analog ground plane of the system. In Figure 20, on). The LSB size is REFIN/256 for the AD7908, REFIN/1024 for REF is connected to a decoupled 2.5 V supply from a reference IN the AD7918, and REF /4096 for the AD7928. The ideal transfer IN source, the AD780, to provide an analog input range of 0 V to characteristic for the AD7908/AD7918/AD7928 when straight 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). binary coding is selected is shown in Figure 17, and the ideal Although the AD7908/AD7918/AD7928 is connected to a VDD transfer characteristic for the AD7908/AD7918/AD7928 when of 5 V, the serial interface is connected to a 3 V microprocessor. twos complement coding is selected is shown in Figure 18. The V pin of the AD7908/AD7918/ AD7928 is connected DRIVE to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion 111…111 111…110 result is output in a 16-bit word. This 16-bit data stream • • consists of a leading zero, three address bits indicating which 111…000 channel the conversion result corresponds to, followed by the 12 • 011…111 bits of conversion data for the AD7928 (10 bits of data for the • 1LSB = V /256 AD7908 REF • AD7918 and 8 bits of data for the AD7908, each followed by 1LSB = V /1024 AD7918 REF 000…010 1LSB = V /4096 AD7928 REF two and four trailing zeros, respectively). For applications 000…001 000…000 where power consumption is of concern, the power-down 1 LSB +V – 1 LSB REF 0V modes should be used between conversions or bursts of several ANALOG INPUT NOTE conversions to improve power performance (see the Modes of 1. V IS EITHER REF OR 2 × REF REF IN IN. Operation section). Figure 17. Straight Binary Transfer Characteristic Rev. D | Page 19 of 32 ADC CODE 03089-017 03089-016 ADC CODE 03089-018 AD7908/AD7918/AD7928 V DD V REF 0.1µF AV DD REF IN V V DD DRIVE AD7908/ R4 AD7918/ DSP/µP V AD7928 R3 TWOS COMPLEMENT V 0 DOUT IN R2 V 0V • 011…111 • +REF (= 2 × REF R1 IN IN) V 7 IN R1 = R2 = R3 = R4 REF IN 000…000 (= 0V) –REF IN 100…000 Figure 19. Handling Bipolar Signals during the sequence, then it must be ensured that the SEQ and 5V SERIAL SHADOW bits are set to 1, 0 to avoid interrupting the 0.1µF 10µF SUPPLY INTERFACE automatic conversion sequence. This pattern continues until such time as the AD7908/AD7918/AD7928 is written to and the AV DD SCLK V 0 IN SEQ and SHADOW bits are configured with any bit combination AD7908/ • DOUT 0V TO REF AD7918/ IN µC/µP • except 1, 0. On completion of the sequence, the AD7908/ AD7928 CS V 7 IN AD7918/AD7928 sequencer returns to the first selected channel DIN REF V AGND IN DRIVE in the SHADOW register and commence the sequence again. 0.1µF 2.5V Rather than selecting a particular sequence of channels, a 0.1µF 10µF AD780 3V number of consecutive channels beginning with Channel 0 can SUPPLY NOTE also be programmed via the control register alone, without 1. ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND. needing to write to the SHADOW register. This is possible if the Figure 20. Typical Connection Diagram SEQ and SHADOW bits are set to 1,1. The channel address bits Analog Input Selection ADD2 through ADD0 then determine the final channel in the consecutive sequence. The next conversion is on Channel 0, Any one of eight analog input channels can be selected for then Channel 1, and so on until the channel selected via the conversion by programming the multiplexer with the Address address bits ADD2 through ADD0 is reached. The cycle begins Bit ADD2 to Address Bit ADD0 in the control register. The again on the next serial transfer, provided the WRITE bit is set channel configurations are shown in Table 8. The AD7908/ to low, or if high, that the SEQ and SHADOW bits are set to AD7918/AD7928 can also be configured to automatically cycle 1, 0; then the ADC continues its preprogrammed automatic through a number of channels as selected. The sequencer sequence uninterrupted. feature is accessed via the SEQ and SHADOW bits in the control register (see Table 10). Regardless of which channel selection method is used, the 16-bit word output from the AD7928 during each conversion always The AD7908/AD7918/AD7928 can be programmed to contains a leading zero, three channel address bits that the continuously convert on a selection of channels in ascending conversion result corresponds to, followed by the 12-bit order. The analog input channels to be converted on are conversion result. The AD7918 outputs a leading zero, three selected through programming the relevant bits in the channel address bits that the conversion result corresponds to, SHADOW register (see the SHADOW Register section). The followed by the 10-bit conversion result and two trailing zeros; next serial transfer then acts on the sequence programmed by the AD7908 outputs a leading zero, three channel address bits executing a conversion on the lowest channel in the selection. that the conversion result corresponds to, followed by the 8-bit The next serial transfer results in a conversion on the next conversion result and four trailing zeros. (See the Serial highest channel in the sequence, and so on. Interface section.) It is not necessary to write to the control register once a Digital Inputs sequencer operation has been initiated. The WRITE bit must be The digital inputs applied to the AD7908/AD7918/AD7928 are set to zero or the DIN line tied low to ensure the control register is not accidentally overwritten, or the sequence operation not limited by the maximum ratings that limit the analog interrupted. If the control register is written to at any time Rev. D | Page 20 of 32 03089-020 03089-019 AD7908/AD7918/AD7928 inputs. Instead, the digital inputs applied can go to 7 V and are CS The conversion is initiated on the falling edge of and the not restricted by the AV + 0.3 V limit as on the analog inputs. DD track-and-hold enters hold mode as described in the Serial Interface section. The data presented to the AD7908/AD7918/ CS Another advantage of SCLK, DIN, and not being restricted AD7928 on the DIN line during the first 12 clock cycles of the by the AVDD + 0.3 V limit is the fact that power supply data transfer are loaded into the control register (provided sequencing issues are avoided. If CS, DIN, or SCLK are applied WRITE bit is set to 1). If data is to be written to the SHADOW before AVDD, there is no risk of latch-up as there would be on register (SEQ = 0, SHADOW = 1 on previous write), data the analog inputs if a signal greater than 0.3 V was applied prior presented on the DIN line during the first 16 SCLK cycles is to AVDD. loaded into the SHADOW register. The part remains fully powered up in normal mode at the end of the conversion as V DRIVE long as PM1 and PM0 are both loaded with 1 on every data The AD7908/AD7918/AD7928 also have the VDRIVE feature. transfer. VDRIVE controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V Sixteen serial clock cycles are required to complete the processors. For example, if the AD7908/AD7918/AD7928 were conversion and access the conversion result. The track-and- operated with an AV of 5 V, the V pin could be powered DD DRIVE hold goes back into track on the 14th SCLK falling edge. CS can from a 3 V supply. The AD7908/AD7918/AD7928 have better then idle high until the next conversion or can idle low until dynamic performance with an AV of 5 V while still being able DD CS sometime prior to the next conversion, effectively idling low. to interface to 3 V processors. Care should be taken to ensure Once a data transfer is complete (DOUT has returned to three- VDRIVE does not exceed AVDD by more than 0.3 V. See the state), another conversion can be initiated after the quiet time, Absolute Maximum Ratings section. t , has elapsed by bringing CS low again. QUIET Reference CS An external reference source should be used to supply the 2.5 V reference to the AD7908/AD7918/AD7928. Errors in the 1 12 16 SCLK reference source results in gain errors in the AD7908/ AD7918/AD7928 transfer function and adds to the specified 1 LEADING ZERO + 3 CHANNEL DOUT IDENTIFIER BITS + CONVERSION RESULT full-scale errors of the part. A capacitor of at least 0.1 μF should be placed on the REFIN pin. Suitable reference sources for the DIN DATA IN TO CONTROL/SHADOW REGISTER AD7908/AD7918/AD7928 include the AD780, REF192, NOTES AD1582, ADR03, ADR381, ADR391, and ADR421. 1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES. 2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES. If 2.5 V is applied to the REF pin, the analog input range can IN Figure 21. Normal Mode Operation either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of Full Shutdown Mode (PM1 = 1, PM0 = 0) the RANGE bit in the control register. In this mode, all internal circuitry on the AD7908/AD7918/ MODES OF OPERATION AD7928 is powered down. The part retains information in the The AD7908/AD7918/AD7928 have a number of different control register during full shutdown. The AD7908/AD7918/ modes of operation. These modes are designed to provide AD7928 remains in full shutdown until the power management flexible power management options. These options can be bits in the control register, PM1 and PM0, are changed. chosen to optimize the power dissipation/throughput rate ratio If a write to the control register occurs while the part is in full for differing application requirements. The mode of operation shutdown, with the power management bits changed to PM0 = of the AD7908/AD7918/AD7928 is controlled by the power PM1 = 1, normal mode, the part begins to power up on the CS management bits, PM1 and PM0, in the control register, as rising edge. The track-and-hold that was in hold while the part was detailed in Table 9. When power supplies are first applied to the in full shutdown returns to track on the 14th SCLK falling edge. AD7908/AD7918/AD7928, care should be taken to ensure that the part is placed in the required mode of operation (see To ensure that the part is fully powered up, tPOWER UP, should Powering Up the AD7908/AD7918/AD7928 section). CS have elapsed before the next falling edge. Figure 22 shows Normal Mode (PM1 = PM0 = 1) the general diagram for this sequence. This mode is intended for the fastest throughput rate Auto Shutdown Mode (PM1 = 0, PM0 = 1) performance, as the user does not have to worry about any In this mode, the AD7908/AD7918/AD7928 automatically power-up times with the AD7908/AD7918/AD7928 remaining enters shutdown at the end of each conversion when the control fully powered at all times. Figure 21 shows the general diagram register is updated. When the part is in shutdown, the track and of the operation of the AD7908/AD7918/AD7928 in this mode. hold is in hold mode. Figure 23 shows the general diagram of Rev. D | Page 21 of 32 03089-021 AD7908/AD7918/AD7928 the operation of the AD7908/AD7918/AD7928 in this mode. In other conversion result being valid. In this mode, the power shutdown mode, all internal circuitry on the AD7908/AD7918/ consumption of the part is greatly reduced with the part AD7928 is powered down. The part retains information in the entering shutdown at the end of each conversion. When the control register is programmed to move into auto shutdown, it control register during shutdown. The AD7908/AD7918/ AD7928 remains in shutdown until the next CS falling edge it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS receives. On this CS falling edge, the track-and-hold that was in signal. hold while the part was in shutdown returns to track. Wakeup time from auto shutdown is 1 μs, and the user should ensure Powering Up the AD7908/AD7918/AD7928 that 1 μs has elapsed before attempting a valid conversion. When supplies are first applied to the AD7908/AD7918/ When running the AD7908/AD7918/AD7928 with a 20 MHz AD7928, the ADC can power up in any of the operating modes clock, one dummy cycle should be sufficient to ensure the part of the part. To ensure the part is placed into the required is fully powered up. During this dummy cycle the contents of operating mode, the user should perform a dummy cycle the control register should remain unchanged; therefore the operation as outlined in Figure 24. WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part, with every PART IS IN PART BEGINSTO POWER UP ON THE PART IS FULLY POWERED UP FULL SHUTDOWN CS RISING EDGE AS PM1 = PM0 = 1 ONCE t HAS ELAPSED POWER UP t 12 CS 14 16 1 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL REGISTER DIN DATA IN TO CONTROL/SHADOW REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. TO KEEPTHE PART IN NORMAL MODE, PM1 = 1, PM0 = 1 LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 22. Full Shutdown Mode Operation PART ENTERS SHUTDOWN PART BEGINS TO POWER PART ENTERS SHUTDOWN ON CS PART IS FULLY ON CS RISING EDGE UP ON CS FALLING EDGE RISING EDGE AS PM1 = 0, PM0 = 1 POWERED UP AS PM1 = 0, PM0 = 1 CS DUMMY CONVERSION 1 12 16 1 12 16 1 12 16 SCLK CHANNEL IDENTIFIER CHANNEL IDENTIFIER DOUT INVALID DATA BITS + CONVERSION RESULT BITS + CONVERSION RESULT DIN DATA IN TO CONTROL/SHADOW REGISTER DATA IN TO CONTROL/SHADOW REGISTER CONTROL REGISTER IS LOADED ON THE TO KEEP PART IN THIS MODE, LOAD PM1 = 0, CONTROL REGISTER CONTENTS SHOULD FIRST 12 CLOCKS, PM1 = 0, PM0 = 1 PM0 = 1 IN CONTROL REGISTER OR SET WRITE BIT = 0 NOT CHANGE. WRITE BIT = 0 Figure 23. Auto Shutdown Mode Operation Rev. D | Page 22 of 32 03089-023 03089-022 AD7908/AD7918/AD7928 CORRECT VALUE IN CONTROL REGISTER, VALID DATA FROM NEXT CONVERSION, USER CAN WRITE TO SHADOW REGISTER IN NEXT CONVERSION CS DUMMY CONVERSION DUMMY CONVERSION 1 12 16 1 12 16 1 12 16 SCLK DOUT INVALID DATA INVALID DATA INVALID DATA DATA IN TO CONTROL REGISTER DIN KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCK EDGES Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied 10 POWER VS. THROUGHPUT RATE By operating in auto shutdown mode on the AD7908/AD7918/ AD7928, the average power consumption of the ADC decreases AV = 5V DD AV = 3V at lower throughput rates. Figure 25 shows how as the DD 1 throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. 0.1 For example, if the AD7928 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (AV = 5 V), and the device is placed in auto DD shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the 0.01 power consumption is calculated as follows: 0 50 100 150 200 250 300 350 THROUGHPUT (kSPS) The maximum power dissipation during normal operation is Figure 25. AD7928 Power vs. Throughput Rate 13.5 mW (AVDD = 5 V). If the power-up time from auto shutdown is one dummy cycle, that is, 1 μs, and the remaining SERIAL INTERFACE conversion time is another cycle, that is, 1 μs, then the AD7928 Figure 26, Figure 27, and Figure 28 show the detailed timing can be said to dissipate 13.5 mW for 2 μs during each diagrams for serial interfacing to the AD7908, AD7918, and conversion cycle. For the remainder of the conversion cycle, AD7928, respectively. The serial clock provides the conversion 8 μs, the part remains in auto shutdown mode. The AD7928 can clock and also controls the transfer of information to and from be said to dissipate 2.5 μW for the remaining 8 μs of the the AD7908/AD7918/AD7928 during each conversion. conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is CS The signal initiates the data transfer and conversion process. CS The falling edge of puts the track-and-hold into hold mode, (2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW takes the bus out of three-state; the analog input is sampled at this point. The conversion is also initiated at this point and Figure 25 shows the maximum power vs. throughput rate when requires 16 SCLK cycles to complete. The track-and-hold goes using the auto shutdown mode with 3 V and 5 V supplies. back into track on the 14th SCLK falling edge as shown in Figure 26, Figure 27, and Figure 28 at Point B, except when the write is to the SHADOW register, in which case the track-and- CS hold does not return to track until the rising edge of , that is, Point C in Figure 29. On the 16th SCLK falling edge, the DOUT CS line goes back into three-state. If the rising edge of occurs before 16 SCLKs have elapsed, the conversion is terminated, the DOUT line goes back into three-state, and the control register is not updated; otherwise DOUT returns to three-state on the 16th SCLK falling edge as shown in Figure 26, Figure 27, and Figure 28. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7908/ AD7918/AD7928. For the AD7908/AD7918/AD7928, the Rev. D | Page 23 of 32 POWER (mW) 03089-025 03089-024 AD7908/AD7918/AD7928 8/10/12 bits of data are preceded by a leading zero and the MICROPROCESSOR INTERFACING 3-channel address bits (ADD2 to ADD0) identify which The serial interface on the AD7908/AD7918/AD7928 allows the CS channel the result corresponds to. going low provides the part to be directly connected to a range of many different leading zero to be read in by the microcontroller or DSP. The microprocessors. This section explains how to interface the three remaining address bits and data bits are then clocked out AD7908/AD7918/AD7928 with some of the more common by subsequent SCLK falling edges beginning with the first microcontroller and DSP serial interface protocols. address bit (ADD2). Thus the first falling clock edge on the AD7908/AD7918/AD7928 to TMS320C541 serial clock has a leading zero provided and also clocks out Address Bit ADD2. The final bit in the data transfer is valid on The serial interface on the TMS320C541 uses a continuous the 16th falling edge, having been clocked out on the previous serial clock and frame synchronization signals to synchronize (15th) falling edge. the data transfer operations with peripheral devices like the CS AD7908/AD7918/AD7928. The input allows easy Writing of information to the control register takes place on the interfacing between the TMS320C541 and the AD7908/ first 12 falling edges of SCLK in a data transfer, assuming the AD7918/AD7928 without any glue logic required. The serial MSB, that is, the WRITE bit, has been set to 1. If the control port of the TMS320C541 is set up to operate in burst mode with register is programmed to use the SHADOW register, then internal CLKX0 (Tx serial clock on Serial Port 0) and FSX0 (Tx writing of information to the SHADOW register takes place on frame sync from Serial Port 0). The serial port control register all 16 SCLK falling edges in the next serial transfer, as shown for (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, example on the AD7928 in Figure 29. Two sequence options and TXM = 1. The connection diagram is shown in Figure 30. It can be programmed in the SHADOW register. If the user does should be noted that for signal processing applications, it is not want to program a second sequence, then the eight LSBs imperative that the frame synchronization signal from the should be filled with zeros. The SHADOW register is updated TMS320C541 provides equidistant sampling. The V DRIVE pin of upon the rising edge of CS and the track-and-hold begins to the AD7908/AD7918/AD7928 takes the same supply voltage as track the first channel selected in the sequence. that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, that is, TMS320C541, if The AD7908 outputs a leading zero and three channel address necessary. bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. The AD7918 outputs a leading zero and three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros. The 16-bit word read from the AD7928 always contains a leading zero and three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. Rev. D | Page 24 of 32 AD7908/AD7918/AD7928 CS t CONVERT t 2 t B 6 11 12 13 14 15 16 1234 56 SCLK t 5 t 11 t t 3 7 t 4 t t 8 QUIET DOUT ADD2 ADD1 ADD0 DB7 DB6 DB0 ZERO ZERO ZERO ZERO THREE-STATE THREE-STATE THREE IDENTIFICATION BITS FOUR TRAILING ZEROS ZERO t t 10 9 CODING DIN WRITE SEQ1 DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DONTC Figure 26. AD7908 Serial Interface Timing Diagram CS t CONVERT t 2 t B 6 11 12 13 14 15 16 123 456 SCLK t 5 t 11 t t 7 3 t 4 t t 8 QUIET ADD2 ADD1 ADD0 DB7 DB6 DB2 DB1 DB0 ZERO ZERO DOUT THREE-STATE THREE-STATE THREE IDENTIFICATION BITS TWO TRAILING ZEROS ZERO t t 9 10 WRITE SEQ DONTC ADD2 ADD1 ADD0 CODING DONTC DONTC DONTC DONTC DIN Figure 27. AD7918 Serial Interface Timing Diagram CS t CONVERT t B t t QUIET 2 6 13 16 12 3 4 5 6 SCLK 14 15 t t 5 11 t t 7 3 t 8 t 4 DOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE THREE IDENTIFICATION BITS t ZERO 10 t 9 DIN WRITE SEQ DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 28. AD7928 Serial Interface Timing Diagram C CS t CONVERT t 2 t 6 13 16 SCLK 123 4 5 6 14 15 t t 11 5 t t 3 7 t t 8 4 DOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE THREE IDENTIFICATION BITS t t 10 ZERO 9 V0V1V2V3V4V5V6V 7 DIN IN IN IN IN IN IN IN IN SEQUENCE 1 SEQUENCE 2 Figure 29. AD7928 Writing to SHADOW Register Timing Diagram Rev. D | Page 25 of 32 03089-029 03089-028 03089-027 03089-026 AD7908/AD7918/AD7928 1 TMS320C541 AD7908/ The timer register, for example, is loaded with a value that AD7918/ 1 provides an interrupt at the required sample interval. When an AD7928 interrupt is received, a value is transmitted with TFS/DT (ADC CLKX SCLK control word). The TFS is used to control the RFS and thus the CLKR DOUT DR reading of data. The frequency of the serial clock is set in the DIN DT SCLKDIV register. When the instruction to transmit with TFS FSX CS is given (that is, AX0 = TX0), the state of the SCLK is checked. FSR V The DSP waits until the SCLK has gone high, low, and high DRIVE before transmission can start. If the timer and SCLK values are 1 chosen, such that the instruction to transmit occurs on or near ADDITIONAL PINS REMOVED FOR CLARITY. V DD the rising edge of SCLK, then the data can be transmitted or it Figure 30. Interfacing to the TMS320C541 can wait until the next clock edge. AD7908/AD7918/AD7928 to ADSP-21xx For example, if the ADSP-2189 had a 20 MHz crystal such that The ADSP-21xx family of DSPs are interfaced directly to the it had a master clock frequency of 40 MHz, then the master AD7908/AD7918/AD7928 without any glue logic required. The cycle time would be 25 ns. If the SCLKDIV register was loaded V pin of the AD7908/AD7918/AD7928 takes the same DRIVE with the value 3, then an SCLK of 5 MHz is obtained, and eight supply voltage as that of the ADSP-21xx. This allows the ADC master clock periods elapse for every one SCLK period. to operate at a higher voltage than the serial interface, that is, Depending on the throughput rate selected, if the timer register ADSP-21xx, if necessary. is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs occur between interrupts and subsequently between transmit The SPORT0 control register should be set up as follows: instructions. This situation results in nonequidistant sampling TFSW = RFSW = 1, alternate framing as the transmit instruction is occurring on a SCLK edge. If the INVRFS = INVTFS = 1, active low frame signal number of SCLKs between interrupts is a whole integer figure DTYPE = 00, right justify data of N, then equidistant sampling is implemented by the DSP. SLEN = 1111, 16-bit data-words ISCLK = 1, internal serial clock AD7908/AD7918/AD7928 to DSP563xx TFSR = RFSR = 1, frame every word The connection diagram in Figure 32 shows how the IRFS = 0 AD7908/AD7918/AD7928 can be connected to the synchronous ITFS = 1 serial interface (ESSI) of the DSP563xx family of DSPs from The connection diagram is shown in Figure 31. The ADSP-21xx Motorola. Each ESSI (two on board) is operated in synchronous has the TFS and RFS of the SPORT tied together, with TFS set mode (SYN bit in CRB = 1) with internally generated word as an output and RFS set as an input. The DSP operates in length frame sync for both Tx and Rx (Bit FSL1 = 0 and alternate framing mode and the SPORT control register is set Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected up as described. The frame synchronization signal generated on by making MOD = 0 in the CRB. Set the word length to 16 by CS the TFS is tied to , as with all signal processing applications setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should where equidistant sampling is necessary. However, in this be noted that for signal processing applications, it is imperative example the timer interrupt is used to control the sampling rate that the frame synchronization signal from the DSP563xx of the ADC, and under certain conditions equidistant sampling provides equidistant sampling. cannot be achieved. 1 ADSP-21xx In the example shown in Figure 32, the serial clock is taken AD7908/ AD7918/ from the ESSI so the SCK0 pin must be set as an output, SCKD 1 AD7928 = 1. The VDRIVE pin of the AD7908/AD7918/AD7928 takes the SCLK SCLK same supply voltage as that of the DSP563xx. This allows the DOUT DR ADC to operate at a higher voltage than the serial interface, that RFS CS is, DSP563xx, if necessary. TFS DIN DT V DRIVE 1 ADDITIONAL PINS REMOVED FOR CLARITY. V DD Figure 31. Interfacing to the ADSP-21xx Rev. D | Page 26 of 32 03089-031 03089-030 AD7908/AD7918/AD7928 1 supply line. Fast switching signals, like clocks, should be DSP563xx AD7908/ AD7918/ shielded with digital ground to avoid radiating noise to other 1 AD7928 sections of the board, and clock signals should never be run SCK SCLK near the analog inputs. Avoid crossover of digital and analog SRD DOUT signals. Traces on opposite sides of the board should run at DIN STD right angles to each other. This reduces the effects of SC2 CS feedthrough through the board. A microstrip technique is by far V DRIVE the best, but is not always possible with a double sided board. In this technique, the component side of the board is dedicated to 1 ADDITIONAL PINS REMOVED FOR CLARITY. V DD ground planes while signals are placed on the solder side. Figure 32. Interfacing to the DSP563xx Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF APPLICATION HINTS capacitors to AGND. To achieve the best performance from Grounding and Layout these decoupling components, they must be placed as close as The AD7908/AD7918/AD7928 have very good immunity to possible to the device, ideally right up against the device. The noise on the power supplies, as can be seen by the PSRR vs. 0.1 μF capacitors should have low effective series resistance Supply Ripple Frequency plot, Figure 6. However, care should (ESR) and effective series inductance (ESI), such as the still be taken with regard to grounding and layout. common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle The printed circuit board that houses the AD7908/AD7918/ transient currents due to internal logic switching. AD7928 should be designed so that the analog and digital sections are separated and confined to certain areas of the Evaluating the AD7908/AD7918/AD7928 Performance board. This facilitates the use of ground planes that can be The recommended layout for the AD7908/AD7918/AD7928 is separated easily. A minimum etch technique is generally best outlined in the AD7908/AD7918/AD7928 evaluation board. for ground planes as it gives the best shielding. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for All four AGND pins of the AD7908/AD7918/AD7928 should controlling the board from the PC via the eval-board controller. be sunk in the AGND plane. If the AD7908/AD7918/AD7928 is in a system where multiple devices require an AGND to The eval-board controller can be used in conjunction with the DGND connection, the connection should be made at only one AD7908/AD7918/AD7928 evaluation board, as well as many point in the plane. Using a star ground point, the connection other Analog Devices evaluation boards ending in the CB should be established as close as possible to the AD7908/ designator, to demonstrate/evaluate the ac and dc performance AD7918/AD7928. of the AD7908/AD7918/AD7928. Avoid running digital lines under the device, as these couple The software allows the user to perform ac (fast Fourier noise onto the die. The analog ground plane should be allowed transform) and dc (histogram of codes) tests on the to run under the AD7908/AD7918/AD7928 to avoid noise AD7908/AD7918/AD7928. The software and documentation coupling. The power supply lines to the AD7908/AD7918/ are on a CD shipped with the evaluation board. AD7928 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power Rev. D | Page 27 of 32 03089-032 AD7908/AD7918/AD7928 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 8° 0.60 0.30 0° 0.45 COPLANARITY 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. D | Page 28 of 32 AD7908/AD7918/AD7928 ORDERING GUIDE 1, 2, 3, 4 5 Model Temperature Range Linearity Error (LSB) Package Description Package Option AD7908BRU-REEL −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRU-REEL7 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL7 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908WYRUZ-REEL7 −40°C to +125°C ±0.2 20-Lead TSSOP RU-20 AD7918BRU-REEL7 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL7 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918WYRUZ-REEL7 −40°C to +125°C ±0.5 20-Lead TSSOP RU-20 AD7928BRU −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRU-REEL −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL7 −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928WYRUZ-REEL7 −40°C to +125°C ±1 20-Lead TSSOP RU-20 EVAL-AD79x8CBZ Evaluation Board EVAL-CONTROL BRD Controller Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 The EVAL-AD79x8CBZ can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes. The board comes with one chip of each the AD7908, AD7918, and AD7928. 4 The EVAL-CONTROL BRD is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, order the particular ADC evaluation board, such as the EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board technical note for more information. 5 Linearity error here refers to integral linearity error. AUTOMOTIVE PRODUCTS The AD72x8W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. D | Page 29 of 32 AD7908/AD7918/AD7928 NOTES Rev. D | Page 30 of 32 AD7908/AD7918/AD7928 NOTES Rev. D | Page 31 of 32 AD7908/AD7918/AD7928 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03089-0-12/10(D) Rev. D | Page 32 of 32