ANALOG DEVICES AD7914

4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP AD7904/AD7914/AD7924 FEATURES FUNCTIONAL BLOCK DIAGRAM AV DD Fast throughput rate: 1 MSPS Specified for AV of 2.7 V to 5.25 V DD REF IN Low power: V 0 IN 6 mW maximum at 1 MSPS with 3 V supplies T/H 8-/10-/12-BIT 13.5 mW maximum at 1 MSPS with 5 V supplies SUCCESSIVE V 1 IN APPROXIMATION 4 single-ended inputs with sequencer ADC I/P MUX Wide input bandwidth V 2 IN AD7924, 70 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management V 3 IN No pipeline delays SCLK High speed serial interface: SPI/QSPI™/ DOUT MICROWIRE™/DSP compatible SEQUENCER CONTROL LOGIC DIN Shutdown mode: 0.5 μA maximum CS 16-lead TSSOP package AD7904/AD7914/AD7924 Qualified for automotive applications V DRIVE AGND Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7904/AD7914/AD7924 are, respectively, 8-bit, 10-bit, and 1. High Throughput with Low Power Consumption. 12-bit, high speed, low power, 4-channel successive approxi- The AD7904/AD7914/AD7924 offer throughput rates mation ADCs. The parts operate from a single 2.7 V to 5.25 V up to 1 MSPS. At the maximum throughput rate with 3 V power supply and feature throughput rates up to 1 MSPS. The supplies, the AD7904/AD7914/AD7924 dissipate only parts contain a low noise, wide bandwidth track-and-hold 6 mW of power maximum. amplifier that can handle input frequencies in excess of 8 MHz. 2. Four Single-Ended Inputs with Channel Sequencer. A consecutive sequence of channels can be selected, The conversion process and data acquisition are controlled using through which the ADC will cycle and convert on. CS and the serial clock signal, allowing the device to easily inter- 3. Single-Supply Operation with V Function. DRIVE face with microprocessors or DSPs. The input signal is sampled The AD7904/AD7914/AD7924 operate from a single 2.7 V CS on the falling edge of and conversion is initiated at this to 5.25 V supply. The VDRIVE function allows the serial inter- point. There are no pipeline delays associated with the part. face to connect directly to 3 V or 5 V processor systems, The AD7904/AD7914/AD7924 use advanced design techniques independent of VDD. to achieve very low power dissipation at maximum throughput 4. Flexible Power/Serial Clock Speed Management. rates. At maximum throughput rates, the AD7904/AD7914/ The conversion rate is determined by the serial clock, AD7924 consume 2 mA maximum with 3 V supplies; with 5 V allowing the conversion time to be reduced by increasing supplies, the current consumption is 2.7 mA maximum. the serial clock speed. The parts also feature two shutdown modes to maximize power efficiency at lower throughput Through the configuration of the control register, the analog rates. Current consumption is 0.5 μA maximum when in input range for the part can be selected as 0 V to REF or 0 V to IN full shutdown. 2 × REFIN, with either straight binary or twos complement output 5. No Pipeline Delay. coding. The AD7904/AD7914/AD7924 each feature four single- The parts feature a standard successive approximation ended analog inputs with a channel sequencer to allow a pre- ADC with accurate control of the sampling instant via programmed selection of channels to be converted sequentially. CS the input and once-off conversion control. The conversion time for the AD7904/AD7914/AD7924 is determined by the SCLK frequency, which is also used as the master clock to control the conversion. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03087-001 AD7904/AD7914/AD7924 TABLE OF CONTENTS Features .............................................................................................. 1  Converter Operation.................................................................. 18  Functional Block Diagram .............................................................. 1  ADC Transfer Function............................................................. 19  General Description ......................................................................... 1  Typical Connection Diagram ................................................... 20  Product Highlights ........................................................................... 1  Modes of Operation ....................................................................... 22  Revision History ............................................................................... 2  Normal Mode (PM1 = PM0 = 1) ............................................. 22  Specifications..................................................................................... 3  Full Shutdown Mode (PM1 = 1, PM0 = 0) ............................. 22  AD7904 Specifications................................................................. 3  Auto Shutdown Mode (PM1 = 0, PM0 = 1) ........................... 22  AD7914 Specifications................................................................. 5  Powering Up the AD7904/AD7914/AD7924......................... 23  AD7924 Specifications................................................................. 7  Power vs. Throughput Rate........................................................... 25  Timing Specifications .................................................................. 9  Serial Interface ............................................................................ 25  Absolute Maximum Ratings.......................................................... 10  Applications Information .............................................................. 27  ESD Caution................................................................................ 10  Microprocessor Interfacing....................................................... 27  Pin Configuration and Function Descriptions........................... 11  Grounding and Layout .............................................................. 28  Typical Performance Characteristics ........................................... 12  Evaluating AD7904/AD7914/AD7924 Performance ............ 29  Terminology .................................................................................... 14  Outline Dimensions....................................................................... 30  Control Register.............................................................................. 15  Ordering Guide .......................................................................... 30  Sequencer Operation ................................................................. 16  Automotive Products................................................................. 30  Circuit Information........................................................................ 18  REVISION HISTORY 7/11—Rev. A to Rev. B Changes to Features Section............................................................ 1 2/09—Rev. 0 to Rev. A Changes to Signal to (Noise + Distortion) (SINAD) Parameter Updated Format..................................................................Universal and Signal-to-Noise Ratio (SNR) Parameter in Table 1 .............. 3 Moved Figure 2 ..................................................................................9 Changes to Signal to (Noise + Distortion) (SINAD) Parameter Change to Table 5 ........................................................................... 10 and Signal-to-Noise Ratio (SNR) Parameter in Table 2 .............. 5 Changes to Typical Performance Characteristics Section ........ 12 Changes to Signal to (Noise + Distortion) (SINAD) Parameter Moved Terminology Section......................................................... 14 and Signal-to-Noise Ratio (SNR) Parameter in Table 3 .............. 7 Updated Outline Dimensions....................................................... 30 Changes to Table 5.......................................................................... 10 Changes to Ordering Guide .......................................................... 30 Changes to Ordering Guide .......................................................... 30 Added Automotive Products Section .......................................... 30 11/02—Revision 0: Initial Version Rev. B | Page 2 of 32 AD7904/AD7914/AD7924 SPECIFICATIONS AD7904 SPECIFICATIONS AV = V = 2.7 V to 5.25 V, REF = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. DD DRIVE IN SCLK A MIN MAX Table 1. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz 2 Signal to (Noise + Distortion) (SINAD) 49 dB min B models 48.5 dB min W models Signal-to-Noise Ratio (SNR) 49 dB min B models 48.5 dB min W models 2 Total Harmonic Distortion (THD) −66 dB max Peak Harmonic or Spurious Noise (SFDR) −64 dB max Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 8 Bits 2 Integral Nonlinearity (INL) ±0.2 LSB max 2 Differential Nonlinearity (DNL) ±0.2 LSB max Guaranteed no missed codes to 8 bits 0 V to REFIN Input Range Straight binary output coding 2 Offset Error ±0.5 LSB max 2 Offset Error Match ±0.05 LSB max 2 Gain Error ±0.2 LSB max 2 Gain Error Match ±0.05 LSB max 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding 2 Positive Gain Error ±0.2 LSB max 2 Positive Gain Error Match ±0.05 LSB max 2 Zero Code Error ±0.5 LSB max 2 Zero Code Error Match ±0.1 LSB max 2 Negative Gain Error ±0.2 LSB max 2 Negative Gain Error Match ±0.05 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE 3 Input Capacitance, CIN 10 pF max Rev. B | Page 3 of 32 AD7904/AD7914/AD7924 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz 2 Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max V 2.7/5.25 V min/V max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section. Rev. B | Page 4 of 32 AD7904/AD7914/AD7924 AD7914 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK 2 Signal to (Noise + Distortion) (SINAD) 61 dB min B models 60.5 dB min W models Signal-to-Noise Ratio (SNR) 61 dB min B models 60.5 dB min W models 2 Total Harmonic Distortion (THD) −72 dB max Peak Harmonic or Spurious Noise (SFDR) −74 dB max Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 2 Integral Nonlinearity (INL) ±0.5 LSB max 2 Differential Nonlinearity (DNL) ±0.5 LSB max Guaranteed no missed codes to 10 bits 0 V to REF Input Range Straight binary output coding IN 2 Offset Error ±2 LSB max 2 Offset Error Match ±0.2 LSB max 2 Gain Error ±0.5 LSB max 2 Gain Error Match ±0.2 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with twos IN IN IN IN complement output coding 2 Positive Gain Error ±0.5 LSB max 2 Positive Gain Error Match ±0.2 LSB max 2 Zero Code Error ±2 LSB max 2 Zero Code Error Match ±0.2 LSB max 2 Negative Gain Error ±0.5 LSB max 2 Negative Gain Error Match ±0.2 LSB max ANALOG INPUT Input Voltage Range 0 to REF V RANGE bit set to 1 IN 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 10 pF max IN Rev. B | Page 5 of 32 AD7904/AD7914/AD7924 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz 2 Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max V 2.7/5.25 V min/V max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section. Rev. B | Page 6 of 32 AD7904/AD7914/AD7924 AD7924 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK 2 Signal to (Noise + Distortion) (SINAD) 70 dB min @ 5 V, B models 69.5 dB min @ 5 V, W models 69 dB min @ 3 V, typically 69.5 dB Signal-to-Noise Ratio (SNR) 70 dB min B models 69.5 dB min W models 2 Total Harmonic Distortion (THD) −77 dB max @ 5 V, typically −84 dB −73 dB max @ 3 V, typically −77 dB Peak Harmonic or Spurious Noise (SFDR) −78 dB max @ 5 V, typically −86 dB Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 2 Integral Nonlinearity (INL) ±1 LSB max 2 Differential Nonlinearity (DNL) −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding 2 Offset Error ±8 LSB max Typically ±0.5 LSB 2 Offset Error Match ±0.5 LSB max 2 Gain Error ±1.5 LSB max 2 Gain Error Match ±0.5 LSB max 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding 2 Positive Gain Error ±1.5 LSB max 2 Positive Gain Error Match ±0.5 LSB max 2 Zero Code Error ±8 LSB max Typically ±0.8 LSB 2 Zero Code Error Match ±0.5 LSB max 2 Negative Gain Error ±1 LSB max 2 Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE 3 Input Capacitance, CIN 10 pF max Rev. B | Page 7 of 32 AD7904/AD7914/AD7924 1 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz 2 Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max V 2.7/5.25 V min/V max DRIVE 4 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) 4 Power Dissipation Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section. Rev. B | Page 8 of 32 AD7904/AD7914/AD7924 TIMING SPECIFICATIONS AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX 1 Parameter Description AVDD = 3 V AVDD = 5 V Unit 2 f 10 10 kHz min SCLK 20 20 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between the CS rising edge and the start of the next conversion t 10 10 ns min CS to SCLK setup time 2 3 t 35 30 ns max Delay from CS until DOUT three-state disabled 3 3 t4 40 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t 10 10 ns min SCLK to DOUT valid hold time 7 4 t 15/45 15/35 ns min/ns max SCLK falling edge to DOUT high impedance 8 t 10 10 ns min DIN setup time prior to SCLK falling edge 9 t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min 16th SCLK falling edge to CS high t12 1 1 μs max Power-up time from full shutdown/auto shutdown modes 1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V . DRIVE 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 8 time of the part and is independent of the bus loading. I 200µA OL TO OUTPUT 1.6V PIN C L 50pF I 200µA OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. B | Page 9 of 32 03087-002 AD7904/AD7914/AD7924 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational AV to AGND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to AV + 0.3 V DRIVE DD maximum rating conditions for extended periods may affect Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V device reliability. Digital Input Voltage to AGND −0.3 V to +7 V Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V REF to AGND −0.3 V to AV + 0.3 V ESD CAUTION IN DD Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range Commercial (B Version) −40°C to +85°C Automotive (W Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 150.4°C/W (TSSOP) θJC Thermal Impedance 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) 215°C Infrared (15 secs) 220°C ESD 1.5 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. Rev. B | Page 10 of 32 AD7904/AD7914/AD7924 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 SCLK 1 AGND 2 DIN 15 V DRIVE AD7904/ 3 14 CS DOUT AD7914/ AD7924 4 AGND 13 AGND 5 TOP VIEW 12 AV V 0 DD IN (Not to Scale) 6 11 AV V 1 DD IN 7 10 REF V 2 IN IN 8 9 AGND V 3 IN Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7904/AD7914/AD7924 conversion process. 2 DIN Data In, Logic Input. Data to be written to the control register of the AD7904/AD7914/AD7924 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7904/AD7914/AD7924 and frames the serial data transfer. 4, 8, 13, 16 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AV Analog Power Supply Input. The AV range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V. For the 0 V DD DD to 2 × REF range, AV should be from 4.75 V to 5.25 V. IN DD 7 REFIN Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 9, 10, 11, VIN3, VIN2, Analog Input 0 through Analog Input 3. The four single-ended analog input channels are multiplexed into the 12 V 1, V 0 on-chip track-and-hold. The analog input channel to be converted is selected using the address bits ADD1 and IN IN ADD0 of the control register. The address bits, in conjunction with the SEQ1 and SEQ0 bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REF or from 0 V to 2 × REF IN IN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 14 DOUT Data Out, Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7904 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first. The data stream from the AD7914 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, provided MSB first. The data stream from the AD7924 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the serial interface of the AD7904/AD7914/AD7924 operates. Rev. B | Page 11 of 32 03087-003 AD7904/AD7914/AD7924 TYPICAL PERFORMANCE CHARACTERISTICS –50 4096 POINT FFT –10 f = 1MSPS SAMPLE AV = 5V DD T = 25°C A –55 f = 1MSPS AV = V = 2.7V SAMPLE DD DRIVE RANGE = 0V TO REF IN f = 50kHz IN –30 SINAD = 71.147dB –60 THD = –87.229dB SFDR = –90.744dB –65 –50 AV = V = 3.6V DD DRIVE –70 –70 –75 –80 –90 AV = V = 4.75V DD DRIVE –85 AV = V = 5.25V DD DRIVE –110 –90 0 50 100 150 200 250 300 350 400 450 500 10 100 1000 FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 4. AD7924 Dynamic Performance at 1 MSPS Figure 7. AD7924 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS 75 –50 f = 1MSPS SAMPLE AV = V = 5.25V T = 25°C DD DRIVE A –55 RANGE = 0V TO REF IN AV = V = 4.75V DD DRIVE AV = 5.25V DD 70 –60 R = 1000Ω IN –65 AV = V = 3.6V DD DRIVE 65 –70 R = 100Ω IN R = 50Ω IN –75 60 –80 R = 10Ω IN f = 1MSPS SAMPLE –85 AV = V = 2.7V T = 25°C DD DRIVE A RANGE = 0V TO REF IN 55 –90 10 100 1000 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 5. AD7924 SINAD vs. Analog Input Frequency for Various Supply Figure 8. AD7924 THD vs. Analog Input Frequency for Various Source Voltages at 1 MSPS, SCLK = 20 MHz Impedances 0 1.0 AV = 5V T = 25°C DD A 200mV p-p SINE WAVE ON AV 0.8 AV = V = 5V –10 DD DD DRIVE REF = 2.5V, 1µF CAPACITOR IN T = 25°C 0.6 A –20 0.4 –30 0.2 –40 0 –50 –0.2 –60 –0.4 –70 –0.6 –80 –0.8 –90 –1.0 01 100 200 300 400 500 600 700 800 900000 04 512 1024 1536 2048 2560 3072 3584096 SUPPLY RIPPLE FREQUENCY (kHz) CODE Figure 6. AD7924 PSRR vs. Supply Ripple Frequency (No Decoupling) Figure 9. AD7924 Typical INL Rev. B | Page 12 of 32 PSRR (dB) SINAD (dB) SNR (dB) 03087-004 03087-006 03087-005 INL ERROR (LSB) THD (dB) THD (dB) 03087-009 03087-008 03087-007 AD7904/AD7914/AD7924 1.0 T = 25°C A 0.8 AV = V = 5V DD DRIVE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 04 512 1024 1536 2048 2560 3072 3584096 CODE Figure 10. AD7924 Typical DNL Rev. B | Page 13 of 32 DNL ERROR (LSB) 03087-010 AD7904/AD7914/AD7924 TERMINOLOGY Channel-to-Channel Isolation Integral Nonlinearity (INL) Channel-to-channel isolation is a measure of the level of cross- INL is the maximum deviation from a straight line passing through talk between channels. It is measured by applying a full-scale the endpoints of the ADC transfer function. The endpoints of the 400 kHz sine wave signal to all three nonselected input channels transfer function are zero scale, a point 1 LSB below the first code and determining how much that signal is attenuated in the transition, and full scale, a point 1 LSB above the last code transition. selected channel with a 50 kHz signal. The figure is given worst Differential Nonlinearity (DNL) case across all four channels for the AD7904/AD7914/AD7924. DNL is the difference between the measured and the ideal Power Supply Rejection (PSR) 1 LSB change between any two adjacent codes in the ADC. Variations in power supply affect the full-scale transition but not Offset Error the linearity of the converter. PSR is the maximum change in Offset error is the deviation of the first code transition (00 … 000 the full-scale transition point due to a change in power supply to 00 … 001) from the ideal, that is, AGND + 1 LSB. voltage from the nominal value (see Figure 6). Offset Error Match Power Supply Rejection Ratio (PSRR) Offset error match is the difference in offset error between any PSRR is the ratio of the power in the ADC output at full-scale two channels. frequency, f, to the power of a 200 mV p-p sine wave applied to Gain Error the ADC AV supply of frequency f . DD S Gain error is the deviation of the last code transition (111 … 110 PSRR(dB) = 10 log(Pf/Pfs) to 111 … 111) from the ideal, that is, REFIN − 1 LSB, after the offset error has been adjusted out. where: Pf is the power at frequency f in the ADC output. Gain Error Match Pf is the power at frequency f coupled onto the ADC AV supply. S S DD Gain error match is the difference in gain error between any two channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end Zero Code Error of a conversion. Track-and-hold acquisition time is the time Zero code error is the deviation of the midscale transition (all required for the output of the track-and-hold amplifier to reach 0s to all 1s) from the ideal VIN voltage, that is, REFIN − 1 LSB. It its final value, within ±1 LSB, after the end of a conversion. applies when using the twos complement output coding option with the 2 × REFIN input range (−REFIN to +REFIN biased about Signal to (Noise + Distortion) (SINAD) Ratio the REFIN point). SINAD is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the Zero Code Error Match fundamental. Noise is the sum of all nonfundamental signals up Zero code error match is the difference in zero code error to half the sampling frequency (f /2), excluding dc. The ratio is S between any two channels. dependent on the number of quantization levels in the digitiza- Positive Gain Error tion process: the more levels, the smaller the quantization noise. Positive gain error is the deviation of the last code transition The theoretical SINAD ratio for an ideal N-bit converter with a (011 … 110 to 011 … 111) from the ideal, that is, +REFIN − 1 LSB, sine wave input is given by after the zero code error is adjusted out. It applies when using Signal to (Noise + Distortion) = (6.02 N +1.76) dB the twos complement output coding option with the 2 × REFIN input range (−REF to +REF biased about the REF point). Thus, for a 12-bit converter, SINAD is 74 dB, for a 10-bit IN IN IN converter, it is 62 dB, and for an 8-bit converter, it is 50 dB. Positive Gain Error Match Positive gain error match is the difference in positive gain error Total Harmonic Distortion (THD) between any two channels. THD is the ratio of the rms sum of harmonics to the funda- mental. For the AD7904/AD7914/AD7924, it is defined as Negative Gain Error Negative gain error is the deviation of the first code transition 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 (100 … 000 to 100 … 001) from the ideal, that is, −REFIN + 1 LSB, THD(dB)= 20 log V 1 after the zero code error is adjusted out. It applies when using the twos complement output coding option with the 2 × REF IN where: input range (−REF to +REF biased about the REF point). IN IN IN V1 is the rms amplitude of the fundamental. V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 Negative Gain Error Match through the sixth harmonics. Negative gain error match is the difference in negative gain error between any two channels. Rev. B | Page 14 of 32 AD7904/AD7914/AD7924 CONTROL REGISTER The control register of the AD7904/AD7914/AD7924 is a loaded to the control register. MSB denotes the first bit in the 12-bit, write-only register. Data is loaded from the DIN pin of data stream. The bit functions are outlined in Table 8. the AD7904/AD7914/AD7924 on the falling edge of SCLK. The Table 7. Channel Selection data is transferred on the DIN line at the same time that the ADD1 ADD0 Analog Input Channel conversion result is read from the part. The data transferred on 0 0 V 0 IN the DIN line corresponds to the AD7904/AD7914/AD7924 0 1 VIN1 configuration for the next conversion. This requires 16 serial 1 0 VIN2 clocks for every data transfer. Only the information provided 1 1 VIN3 on the first 12 falling clock edges (after the CS falling edge) is Table 8. Control Register Bit Functions MSB LSB 11 10 9 8 7 6 5 4 3 2 1 0 WRITE SEQ1 DONTC DONTC ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE CODING Bit Mnemonic Description 11 WRITE The value written to this bit determines whether the following 11 bits will be loaded to the control register. If this bit is set to 1, the following 11 bits will be written to the control register; if this bit is set to 0, the remaining 11 bits are not loaded to the control register, which remains unchanged. 10 SEQ1 The SEQ1 bit is used in conjunction with the SEQ0 bit to control the use of the sequencer function (see Table 10). [9:8] DONTC Don’t care bits. [7:6] ADD1, The two address bits are loaded at the end of the present conversion sequence and select which analog input ADD0 channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table 10. The selected input channel is decoded as shown in Table 7. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section). The next channel to be converted on will be selected by the mux on the 14th SCLK falling edge. [5:4] PM1, PM0 The two power management bits decode the mode of operation of the AD7904/AD7914/AD7924 as described in Table 9. 3 SEQ0 The SEQ0 bit is used in conjunction with the SEQ1 bit to control the use of the sequencer function (see Table 10). 2 DONTC Don’t care bit. 1 RANGE This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0, the analog input range will extend from 0 V to 2 × REF . If it is set to 1, the analog input range will extend from 0 V to REF (for the next IN IN conversion). For the 0 V to 2 × REFIN input range, VDD = 4.75 V to 5.25 V. 0 CODING This bit selects the type of output coding that the AD7904/AD7914/AD7924 will use for the conversion result. If this bit is set to 0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the part will be straight binary (for the next conversion). Table 9. Power Mode Selection PM1 PM0 Mode Description 1 1 Normal In normal operation mode, the AD7904/AD7914/AD7924 remain in full power mode regardless of operation the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7904/AD7914/AD7924. 1 0 Full In full shutdown mode, the AD7904/AD7914/AD7924 are in full shutdown with all circuitry on the shutdown device powering down. The AD7904/AD7914/AD7924 retain the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 1 Auto In auto shutdown mode, the AD7904/AD7914/AD7924 automatically enter full shutdown mode at the shutdown end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs; the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 Invalid Invalid selection. This configuration is not allowed. Rev. B | Page 15 of 32 AD7904/AD7914/AD7924 SEQUENCER OPERATION Figure 12 shows how to program the AD7904/AD7914/AD7924 The SEQ1 and SEQ0 bits in the control register allow the user to to continuously convert on a sequence of consecutive channels select a mode of operation for the sequencer function. Table 10 from Channel 0 to a selected final channel. To exit this mode of outlines the three modes of operation of the sequencer. operation and revert to the traditional mode of operation of a Figure 11 shows the traditional operation of a multichannel multichannel ADC (as shown in Figure 11), ensure that the ADC, where each serial transfer selects the next channel for WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer. conversion. In this mode of operation, the sequencer function is not used. Table 10. Sequence Selection SEQ1 SEQ0 Sequencer Function Description 0 X Not used The sequencer function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each previous write operation. This mode of operation reflects the traditional operation of a multi- channel ADC, without using the sequencer function, where each write to the AD7904/AD7914/ AD7924 selects the next channel for conversion (see Figure 11). 1 0 Used (not interrupted The sequencer function is not interrupted upon completion of the write operation. This config- upon completion) uration allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 Continuous This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to conversions program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel that is specified by the channel address bits in the control register (see Figure 12). POWER ON DUMMY CONVERSION DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, CS SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL ADD1, ADD0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL ADD1, ADD0 CS DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SEQ1 = 0, SEQ0 = x SELECT ADD1, ADD0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x Figure 11. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart Rev. B | Page 16 of 32 03087-011 AD7904/AD7914/AD7924 POWER ON DUMMY CONVERSION DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, CS SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL ADD1, ADD0 FOR CONVERSION. SEQ1 = 1, SEQ0 = 1 DOUT: CONVERSION RESULT FROM CHANNEL 0 CONTINUOUSLY CONVERTS ON A CONSECUTIVE CS SEQUENCE OF CHANNELS FROM CHANNEL 0 UP WRITE BIT = 0 TO AND INCLUDING THE PREVIOUSLY SELECTED ADD1, ADD0 IN THE CONTROL REGISTER CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW CS RANGE, CODING, AND SO FORTH, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING WRITE BIT = 1, THE SEQUENCE, PROVIDED SEQ1 = 1, SEQ0 = 0 SEQ1 = 1, SEQ0 = 0 Figure 12. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart Rev. B | Page 17 of 32 03087-012 AD7904/AD7914/AD7924 CIRCUIT INFORMATION The AD7904/AD7914/AD7924 are, respectively, 8-bit, 10-bit, condition. When the comparator is rebalanced, the conversion and 12-bit, high speed, 4-channel, single-supply ADCs. The parts is complete. The control logic generates the ADC output code. can be operated from a 2.7 V to 5.25 V supply. When operated Figure 16 and Figure 17 show the ADC transfer functions. from either a 5 V or 3 V supply, the AD7904/AD7914/AD7924 CAPACITIVE are capable of throughput rates of 1 MSPS when provided with DAC a 20 MHz clock. A 4kΩ V 0 IN CONTROL The AD7904/AD7914/AD7924 provide the user with an on-chip SW1 LOGIC B SW2 track-and-hold ADC and serial interface housed in a 16-lead V 3 IN COMPARATOR TSSOP package. The AD7904/AD7914/AD7924 each have four AGND single-ended input channels with a channel sequencer, allowing Figure 14. ADC Conversion Phase the user to select a channel sequence through which the ADC CS can cycle with each consecutive falling edge. The serial clock Analog Input input accesses data from the part, controls the transfer of data Figure 15 shows an equivalent circuit of the analog input structure written to the ADC, and provides the clock source for the succes- of the AD7904/AD7914/AD7924. The two diodes, D1 and D2, sive approximation ADC. The analog input range for the AD7904/ provide ESD protection for the analog inputs. Care must be AD7914/AD7924 is 0 V to REFIN or 0 V to 2 × REFIN, depending on taken to ensure that the analog input signal never exceeds the the status of Bit 1 in the control register. For the 0 V to 2 × REFIN supply rails by more than 200 mV. This will cause these diodes range, the part must be operated from a 4.75 V to 5.25 V supply. to become forward-biased and start conducting current into the substrate. The maximum current that these diodes can conduct The AD7904/AD7914/AD7924 provide flexible power management without causing irreversible damage to the part is 10 mA. options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by pro- Capacitor C1 in Figure 15 is typically about 4 pF and can primarily gramming the power management bits, PM1 and PM0, in the be attributed to pin capacitance. The resistor, R1, is a lumped control register. component made up of the on resistance of a track-and-hold switch and the on resistance of the input multiplexer. The total CONVERTER OPERATION resistance is typically about 400 Ω. Capacitor C2 is the ADC The AD7904/AD7914/AD7924 are 8-, 10-, and 12-bit SAR ADCs, sampling capacitor and has a capacitance of 30 pF typically. respectively, based around a capacitive DAC. The AD7904/ For ac applications, removing high frequency components from AD7914/AD7924 can convert analog input signals in the range the analog input signal is recommended by use of a low-pass RC of 0 V to REFIN or 0 V to 2 × REFIN. Figure 13 and Figure 14 filter on the relevant analog input pin. In applications where show simplified schematics of the ADC. The AD7904/AD7914/ harmonic distortion and signal-to-noise ratio are critical, the AD7924 include control logic, the SAR ADC, and a capacitive analog input should be driven from a low impedance source. DAC, which are used to add and subtract fixed amounts of charge Large source impedances significantly affect the ac performance from the sampling capacitor to bring the comparator back into of the ADC. This may necessitate the use of an input buffer a balanced condition. Figure 13 shows the ADC during its amplifier. The choice of the op amp is a function of the acquisition phase. SW2 is closed and SW1 is in Position A. The particular application. comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source CAPACITIVE DAC impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source A 4kΩ V 0 IN CONTROL impedance increases, and performance will degrade (see Figure 8). SW1 LOGIC B SW2 AV DD V 3 IN COMPARATOR AGND C2 D1 Figure 13. ADC Acquisition Phase 30pF R1 V IN When the ADC starts a conversion (see Figure 14), SW2 opens C1 D2 CONVERSION PHASE: SWITCH OPEN 4pF TRACK PHASE: SWITCH CLOSED and SW1 moves to position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the Figure 15. Equivalent Analog Input Circuit sampling capacitor to bring the comparator back into a balanced Rev. B | Page 18 of 32 03087-013 03087-015 03087-014 AD7904/AD7914/AD7924 ADC TRANSFER FUNCTION The output coding of the AD7904/AD7914/AD7924 is either 011…111 straight binary or twos complement, depending on the status of 011…110 • the LSB in the control register. The designed code transitions • occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so on). 000…001 000…000 For the 0 V to REF input range, the LSB size is REF /256 for IN IN 111…111 • the AD7904, REF /1024 for the AD7914, and REF /4096 for IN IN 1LSB = 2 × V /256 AD7904 REF • 1LSB = 2 × V /1024 AD7914 REF 100…010 the AD7924. For the 0 V to 2 × REFIN input range, the LSB size 1LSB = 2 × V /4096 AD7924 REF 100…001 is 2 × REFIN/256 for the AD7904, 2 × REFIN/1024 for the AD7914, 100…000 and 2 × REFIN/4096 for the AD7924. The ideal transfer charac- –V + 1LSB +V – 1LSB REF REF V – 1LSB REF teristic for the AD7904/AD7914/AD7924 when straight binary ANALOG INPUT coding is selected is shown in Figure 16; the ideal transfer Figure 17. Twos Complement Transfer Characteristic characteristic for the AD7904/AD7914/AD7924 when twos with 0 V to 2 × REFIN Input Range complement coding is selected is shown in Figure 17. Handling Bipolar Input Signals Figure 18 shows how the combination of the 0 V to 2 × REFIN 111…111 input range and the twos complement output coding scheme is 111…110 • particularly useful for handling bipolar input signals. If the • 111…000 bipolar input signal is biased about REF and twos complement IN • 1LSB = V /256 AD7904 output coding is selected, REF becomes the zero code point, 011…111 REF IN 1LSB = V /1024 AD7914 • REF −REF is negative full scale, and +REF becomes positive full 1LSB = V /4096 AD7924 IN IN • REF 000…010 scale, with a dynamic range of 2 × REF . IN 000…001 000…000 1LSB +V – 1LSB 0V REF ANALOG INPUT NOTES 1. V IS EITHER REF OR 2 × REF . REF IN IN Figure 16. Straight Binary Transfer Characteristic V DD V REF 0.1µF AV DD REF IN V V DD DRIVE AD7904/ DSP/ R4 MICRO- AD7914/ V PROCESSOR AD7924 R3 TWOS COMPLEMENT V 0 DOUT R2 IN 0V V 011…111 (= 2 × REF ) +REF IN IN V 3 IN R1 R1 = R2 = R3 = R4 000…000 REF IN (= 0V) –REF IN 100…000 Figure 18. Handling Bipolar Signals Rev. B | Page 19 of 32 ADC CODE 03087-016 ADC CODE 03087-018 03087-017 AD7904/AD7914/AD7924 Analog Input Selection TYPICAL CONNECTION DIAGRAM Any one of four analog input channels can be selected for Figure 19 shows a typical connection diagram for the AD7904/ conversion by programming the multiplexer with the address AD7914/AD7924. In this setup, the AGND pin is connected to bits ADD1 and ADD0 in the control register. The channel the analog ground plane of the system. In Figure 19, the REFIN configurations are shown in Table 7. pin is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to The AD7904/AD7914/AD7924 can also be configured to auto- 2.5 V (if the RANGE bit is set to 1) or 0 V to 5 V (if the RANGE matically cycle through a number of selected channels. The bit is set to 0). sequencer feature is accessed via the SEQ1 and SEQ0 bits in the control register (see Table 10). The AD7904/AD7914/AD7924 Although the AD7904/AD7914/AD7924 are connected to a VDD can be programmed to continuously convert on a number of of 5 V, the serial interface is connected to a 3 V microprocessor. consecutive channels in ascending order from Channel 0 to a The VDRIVE pin of the AD7904/AD7914/AD7924 is connected to selected final channel as determined by the channel address the same 3 V supply as the microprocessor to allow a 3 V logic bits, ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 interface (see the Digital Inputs section). The conversion result bits are set to 11. The next serial transfer will then act on the is output in a 16-bit word. This 16-bit data stream consists of sequence programmed by executing a conversion on Channel 0. two leading zeros, two address bits indicating which channel the The next serial transfer will result in a conversion on Channel 1, conversion result corresponds to, followed by the 12 bits of and so on, until the channel selected via the address bits, ADD1 conversion data for the AD7924 (10 bits of data for the AD7914 and ADD0, is reached. and 8 bits of data for the AD7904, each followed by two and four trailing zeros, respectively). For applications where power It is not necessary to write to the control register again after a consumption is of concern, the power-down modes should be sequence operation has been initiated. To ensure that the control used between conversions or bursts of several conversions to register is not accidently overwritten or the sequence operation improve power performance (see the Modes of Operation interrupted, the WRITE bit must be set to 0 or the DIN line section). must be tied low. If the control register is written to at any time 5V during the sequence, the SEQ1 and SEQ0 bits must be set to 10 SUPPLY 0.1µF 10µF to avoid interrupting the automatic conversion sequence. This SERIAL pattern continues until the AD7904/AD7914/AD7924 are INTERFACE written to and the SEQ1 and SEQ0 bits are configured with a bit AV DD combination other than 10, resulting in the termination of the V 0 SCLK IN MICRO- AD7904/ 0V TO REF sequence. If the sequence is uninterrupted (WRITE bit = 0, or DOUT IN CONTROLLER/ AD7914/ MICRO- WRITE bit = 1 and SEQ1 and SEQ0 bits are set to 10), then upon V 3 CS AD7924 IN PROCESSOR completion of the sequence, the AD7904/AD7914/AD7924 DIN AGND REF V IN DRIVE sequencer returns to Channel 0 and restarts the sequence. Regardless of the channel selection method used, the 16-bit 0.1µF 0.1µF 10µF 2.5V 3V SUPPLY word output from the AD7924 during each conversion always AD780 NOTES contains two leading zeros, two channel address bits that the 1. ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND. conversion result corresponds to, followed by the 12-bit con- Figure 19. Typical Connection Diagram version result; the AD7914 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7904 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros (see the Serial Interface section). Rev. B | Page 20 of 32 03087-019 AD7904/AD7914/AD7924 Digital Inputs from a 3 V supply. The AD7904/AD7914/AD7924 have better dynamic performance with a V of 5 V while still being able to DD The digital inputs applied to the AD7904/AD7914/AD7924 can interface to 3 V processors. Care should be taken to ensure that go to 7 V and are not restricted by the AVDD + 0.3 V limit on the VDRIVE does not exceed AVDD by more than 0.3 V (see the analog inputs. Absolute Maximum Ratings section). CS inputs are not restricted by the Because the SCLK, DIN, and Reference AV + 0.3 V limit, power supply sequencing issues are avoided. DD An external reference source should be used to supply the 2.5 V CS If , DIN, or SCLK is applied before AVDD, there is no risk of reference to the AD7904/AD7914/AD7924. Errors in the refer- latch-up as there would be on the analog inputs if a signal ence source result in gain errors in the AD7904/AD7914/ greater than 0.3 V is applied prior to AV . DD AD7924 transfer function and add to the specified full-scale V DRIVE errors of the part. A capacitor of at least 0.1 μF should be placed The AD7904/AD7914/AD7924 also include the V feature. DRIVE on the REFIN pin. Suitable reference sources for the AD7904/ V controls the voltage at which the serial interface operates. DRIVE AD7914/AD7924 include the AD780, REF193, and AD1582. VDRIVE allows the ADC to easily interface to both 3 V and 5 V If 2.5 V is applied to the REF pin, the analog input range can IN processors. For example, if the AD7904/AD7914/AD7924 are be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of operated with a VDD of 5 V, the VDRIVE pin can be powered the RANGE bit in the control register. Rev. B | Page 21 of 32 AD7904/AD7914/AD7924 MODES OF OPERATION The AD7904/AD7914/AD7924 have three modes of operation. FULL SHUTDOWN MODE (PM1 = 1, PM0 = 0) These modes are designed to provide flexible power management In full shutdown mode, all internal circuitry on the AD7904/ options. These options can be chosen to optimize the power AD7914/AD7924 is powered down. The part retains information dissipation/throughput rate ratio for differing application require- in the control register during full shutdown. The AD7904/AD7914/ ments. The mode of operation of the AD7904/AD7914/AD7924 AD7924 remain in full shutdown until the power management is controlled by the power management bits, PM1 and PM0, in bits in the control register, PM1 and PM0, are changed. the control register (see Table 9). When power supplies are first If a write to the control register occurs while the part is in full applied to the AD7904/AD7914/AD7924, care should be taken to shutdown, and the power management bits are changed to ensure that the part is placed in the required mode of operation PM0 = PM1 = 1 (that is, normal mode), the part will begin to (see the Powering Up the AD7904/AD7914/AD7924 section). CS power up on the rising edge. The track-and-hold, which was NORMAL MODE (PM1 = PM0 = 1) in hold mode while the part was in full shutdown, returns to Normal mode is intended for the fastest throughput rate perfor- track mode on the 14th SCLK falling edge. mance. Because the AD7904/AD7914/AD7924 remain fully To ensure that the part is fully powered up, tPOWER-UP (t12) should powered up at all times, the user does not need to worry about have elapsed before the next CS falling edge. Figure 21 shows power-up times. Figure 20 shows the general diagram of the the general diagram for this sequence. operation of the AD7904/AD7914/AD7924 in this mode. AUTO SHUTDOWN MODE (PM1 = 0, PM0 = 1) CS In auto shutdown mode, the AD7904/AD7914/AD7924 auto- 1 12 16 matically enter shutdown at the end of each conversion when SCLK the control register is updated. When the part is in auto shutdown, 2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS DOUT + CONVERSION RESULT the track-and-hold is in hold mode. Figure 22 shows the general diagram of the operation of the AD7904/AD7914/AD7924 in DIN DATA IN TO CONTROL REGISTER this mode. NOTES 1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES. In auto shutdown mode, all internal circuitry on the AD7904/ Figure 20. Normal Mode Operation AD7914/AD7924 is powered down. The part retains information in the control register during auto shutdown. The AD7904/ CS The conversion is initiated on the falling edge of ; the track- AD7914/AD7924 remain in shutdown until the next CS falling and-hold enters hold mode as described in the Serial Interface edge that it receives. On this CS falling edge, the track-and-hold, section. The data presented to the AD7904/AD7914/AD7924 which was in hold mode while the part was in shutdown, returns on the DIN line during the first 12 clock cycles of the data to track mode. Wake-up time from auto shutdown is 1 μs max- transfer is loaded into the control register (provided that the imum, and the user should ensure that 1 μs has elapsed before WRITE bit is set to 1). In normal mode, the part remains fully attempting a valid conversion. powered up at the end of the conversion as long as the PM1 and PM0 bits are set to 1 in the write transfer during that same When running the AD7904/AD7914/AD7924 with a 20 MHz conversion. To ensure continued operation in normal mode, clock, one 16 SCLK dummy cycle should be sufficient to ensure PM1 and PM0 must both be set to 1 on every data transfer, that the part is fully powered up. During this dummy cycle, the assuming that a write operation is taking place. If the WRITE contents of the control register should remain unchanged; bit is set to 0, the power management bits are left unchanged, therefore, the WRITE bit should be set to 0 on the DIN line. and the part remains in normal mode. This dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. In auto Sixteen serial clock cycles are required to complete the conversion shutdown mode, the power consumption of the part is greatly and to access the conversion result. The track-and-hold returns reduced because the part enters shutdown at the end of each CS to track mode on the 14th SCLK falling edge. may then idle conversion. When the control register is programmed to move high until the next conversion or it may idle low until some into auto shutdown mode, it does so at the end of the con- time prior to the next conversion (effectively idling CS low). version. The user can move the ADC in and out of the low When a data transfer is complete (DOUT has returned to three- CS power state by controlling the signal. state), another conversion can be initiated after the quiet time, CS tQUIET, has elapsed by bringing low again. Rev. B | Page 22 of 32 03087-020 AD7904/AD7914/AD7924 PART BEGINS TO POWER UP ON THE PART IS FULLY POWERED UP PART IS IN FULL CS RISING EDGE AS PM1 = PM0 = 1 ONCE t HAS ELAPSED SHUTDOWN POWER UP t 12 CS 1 14 16 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA IN TO CONTROL REGISTER DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE TO KEEP THE PART IN NORMAL MODE, LOAD FIRST 12 CLOCKS. PM1 = 1, PM0 = 1 PM1 = PM0 = 1 IN CONTROL REGISTER Figure 21. Full Shutdown Mode Operation PART ENTERS PART BEGINS PART ENTERS SHUTDOWN ON CS TO POWER SHUTDOWN ON CS RISING EDGE AS UP ON CS RISING EDGE AS PART IS FULLY PM1 = 0, PM0 = 1 FALLING EDGE POWERED UP PM1 = 0, PM0 = 1 DUMMY CONVERSION CS 11 126 1 12 16 1 12 16 SCLK CHANNEL IDENTIFIER BITS + CONVERSION RESULT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DOUT INVALID DATA DIN DATA IN TO CONTROL REGISTER DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE CONTROL REGISTER CONTENTS SHOULD TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1 FIRST 12 CLOCKS, PM1 = 0, PM0 = 1 NOT CHANGE, WRITE BIT = 0 IN CONTROL REGISTER OR SET WRITE BIT = 0 Figure 22. Auto Shutdown Mode Operation POWERING UP THE AD7904/AD7914/AD7924 When supplies are first applied to the AD7904/AD7914/AD7924, If the desired mode of operation after supplies are applied is the ADC may power up in any of the operating modes of the auto shutdown mode, two dummy cycles are required: the first part. To ensure that the part is placed into the required operating dummy cycle with DIN tied high, and the second to set the mode, the user should perform a dummy cycle operation as CS power management bits, PM1 and PM0, to 01. On the second shown in Figure 23, Figure 24, and Figure 25. rising edge after the supplies are applied, the control register contains the correct information and the part enters auto The dummy conversion operation must be performed to place shutdown mode as programmed. If power consumption is of the part into the desired mode of operation. To ensure that the critical concern, then in the first dummy cycle, the user can set part is in normal mode, this dummy cycle operation can be PM1 and PM0 to 10, that is, full shutdown mode, and then place performed with the DIN line tied high, that is, the PM1 and the part into auto shutdown mode in the second dummy cycle. PM0 bits are set to 11 (depending on other required settings in For illustration purposes, Figure 25 is shown with DIN tied the control register). However, the minimum power-up time of high on the first dummy cycle in this case. CS 1 μs must be allowed from the rising edge of , where the control register is updated, before attempting the first valid Figure 23, Figure 24, and Figure 25 show the required dummy conversion. This power-up time allows for the possibility that cycles after supplies are applied for normal mode, full shutdown the part was initially powered up in shutdown mode. mode, and auto shutdown mode, respectively. If the desired mode of operation is full shutdown, one dummy cycle is required after supplies are applied. In this dummy cycle, the user simply sets the power management bits, PM1 and PM0, CS to 10 and, upon the rising edge of at the end of that serial transfer, the part enters full shutdown mode. Rev. B | Page 23 of 32 03087-022 03087-021 AD7904/AD7914/AD7924 PART IS IN IF IN SHUTDOWN AT POWER-ON, UNKNOWN MODE PART BEGINS TO POWER UP ON ALLOW t TO ELAPSE POWER AFTER POWER-ON CS RISING EDGE AS PM1 = PM0 = 1 t 12 CS 11 146 1 14 16 SCLK DOUT INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA IN TO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 23. Placing the AD7904/AD7914/AD7924 into Normal Mode After Supplies Are First Applied PART IS IN UNKNOWN MODE PART ENTERS SHUTDOWN ON AFTER POWER-ON CS RISING EDGE AS PM1 = 1, PM0 = 0 CS 11416 SCLK DOUT INVALID DATA DATA IN TO CONTROL REGISTER DIN CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0 Figure 24. Placing the AD7904/AD7914/AD7924 into Full Shutdown Mode After Supplies Are First Applied PART IS IN UNKNOWN MODE PART ENTERS AUTO SHUTDOWN ON AFTER POWER-ON CS RISING EDGE AS PM1 = 0, PM0 = 1 CS 11416 11416 SCLK DOUT INVALID DATA INVALID DATA DIN DATA IN TO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 0, PM0 = 1 Figure 25. Placing the AD7904/AD7914/AD7924 into Auto Shutdown Mode After Supplies Are First Applied Rev. B | Page 24 of 32 03087-024 03087-025 03087-023 AD7904/AD7914/AD7924 POWER vs. THROUGHPUT RATE By operating the AD7904/AD7914/AD7924 in auto shutdown The CS signal initiates the data transfer and conversion process. mode, the average power consumption of the ADC decreases at The falling edge of CS puts the track-and-hold into hold mode lower throughput rates. Figure 26 shows how, as the throughput and takes the bus out of three-state; the analog input is sampled rate is reduced, the part remains in its shutdown state longer, and at this point. The conversion is also initiated at this point and the average power consumption over time drops accordingly. requires 16 SCLK cycles to complete. The track-and-hold returns to track mode on the 14th SCLK falling edge, as shown by Point B For example, if the AD7924 is operated in continuous sampling in Figure 27, Figure 28, and Figure 29. On the 16th SCLK falling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz edge, the DOUT line returns to three-state. If the rising edge of (AV = 5 V), and the device is placed into auto shutdown mode DD CS occurs before 16 SCLKs have elapsed, the conversion is (PM1 = 0 and PM0 = 1), the power consumption is calculated terminated, the DOUT line returns to three-state, and the as described in this section. control register is not updated; otherwise, DOUT returns to The maximum power dissipation during normal operation is three-state on the 16th SCLK falling edge, as shown in Figure 27, 13.5 mW (AVDD = 5 V). If the power-up time from auto shutdown Figure 28, and Figure 29. is one dummy cycle, that is, 1 μs, and the remaining conversion Sixteen serial clock cycles are required to perform the conversion time is another cycle, that is, 1 μs, then the AD7924 can be said process and to access data from the AD7904/AD7914/AD7924. to dissipate 13.5 mW for 2 μs during each conversion cycle. For For the AD7904/AD7914/AD7924, the 8/10/12 bits of data are the remainder of the conversion cycle, 8 μs, the part remains in preceded by two leading zeros and the two channel address bits, shutdown. The AD7924 can be said to dissipate 2.5 μW for the ADD1 and ADD0, which identify the channel that the result remaining 8 μs of the conversion cycle. If the throughput rate is corresponds to. CS going low clocks out the first leading zero to 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is ((2/10) × 13.5 mW) + ((8/10) × 2.5 μW) = be read in by the microcontroller or DSP on the first falling edge of 2.702 mW. SCLK. The first falling edge of SCLK also clocks out the second leading zero to be read in by the microcontroller or DSP on the Figure 26 shows the maximum power vs. throughput rate when second SCLK falling edge, and so on. The two address bits and using the auto shutdown mode with 5 V and 3 V supplies. the 8/10/12 data bits are then clocked out by subsequent SCLK 10 falling edges beginning with the first address bit, ADD1; thus, the second falling clock edge on the serial clock has the second AV = 5V DD leading zero provided and also clocks out the address bit ADD1. AV = 3V DD The final bit in the data transfer is valid on the 16th falling edge, 1 having been clocked out on the previous (15th) falling edge. The writing of information to the control register takes place on the first 12 falling edges of SCLK in a data transfer, assuming 0.1 that the MSB (the WRITE bit) has been set to 1. The AD7904 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. The AD7914 0.01 outputs two leading zeros, two channel address bits that the 0 50 100 150 200 250 300350 THROUGHPUT (kSPS) conversion result corresponds to, followed by the 10-bit Figure 26. AD7924 Power vs. Throughput Rate conversion result and two trailing zeros. The 16-bit word read from the AD7924 always contains two leading zeros, two SERIAL INTERFACE channel address bits that the conversion result corresponds to, Figure 27, Figure 28, and Figure 29 show the detailed timing followed by the 12-bit conversion result. diagrams for serial interfacing to the AD7904, AD7914, and AD7924, respectively. The serial clock provides the conversion clock and controls the transfer of information to and from the AD7904/AD7914/AD7924 during each conversion. Rev. B | Page 25 of 32 POWER (mW) 03087-026 AD7904/AD7914/AD7924 CS t CONVERT t t B 2 6 123456 11 12 13 14 15 16 SCLK t t 5 11 t t 3 7 t t 4 8 t QUIET DOUT DB0 ZERO ZERO ZERO ZERO ZERO ADD1 ADD0 DB7 DB6 THREE- THREE- 2 IDENTIFICATION 4 TRAILING ZEROS STATE STATE BITS ZERO t t 9 10 DIN WRITE SEQ1 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC Figure 27. AD7904 Serial Interface Timing Diagram CS t CONVERT t t B 2 6 123456 11 12 13 14 15 16 SCLK t 5 t 11 t t 3 7 t t 4 8 t QUIET DOUT ZERO ADD1 ADD0 DB9 DB8 DB2 DB1 DB0 ZERO ZERO THREE- THREE- 2 IDENTIFICATION 2 TRAILING ZEROS STATE STATE BITS ZERO t t 9 10 DIN WRITE SEQ1 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC Figure 28. AD7914 Serial Interface Timing Diagram CS t CONVERT t t B 2 6 123456 11 12 13 14 15 16 SCLK t t 5 11 t t 3 7 t t 4 8 t QUIET DOUT ZERO ADD1 ADD0 DB11 DB10 DB4 DB3 DB2 DB1 DB0 THREE- THREE- 2 IDENTIFICATION STATE STATE BITS ZERO t t 9 10 DIN WRITE SEQ1 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC Figure 29. AD7924 Serial Interface Timing Diagram Rev. B | Page 26 of 32 03087-029 03087-028 03087-027 AD7904/AD7914/AD7924 APPLICATIONS INFORMATION The SPORT0 control register of the ADSP-218x should be set MICROPROCESSOR INTERFACING up as follows: The serial interface of the AD7904/AD7914/AD7924 allows the part to be directly connected to a range of different TFSW = RFSW = 1, alternate framing microprocessors. This section explains how to interface the INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right justify data AD7904/AD7914/AD7924 to some of the more common SLEN = 1111, 16-bit data-words microcontroller and DSP serial interface protocols. ISCLK = 1, internal serial clock AD7904/AD7914/AD7924 to TMS320C541 TFSR = RFSR = 1, frame every word The serial interface of the TMS320C541 uses a continuous serial IRFS = 0 clock and frame synchronization signals to synchronize the data ITFS = 1 transfer operations with peripheral devices such as the AD7904/ The connection diagram is shown in Figure 31. The ADSP-218x AD7914/AD7924. The CS input allows easy interfacing between has the TFS and RFS of the SPORT tied together, with TFS set the TMS320C541 and the AD7904/AD7914/AD7924 without any as an output and RFS set as an input. The DSP operates in alter- glue logic required. The serial port of the TMS320C541 is set up nate framing mode and the SPORT0 control register is set up as to operate in burst mode with internal CLKX0 (TX serial clock described. The frame synchronization signal generated on the on Serial Port 0) and FSX0 (TX frame sync from Serial Port 0). TFS is tied to CS and, as with all signal processing applications, The serial port control (SPC) register must have the following equidistant sampling is necessary. However, in this example, the setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection timer interrupt is used to control the sampling rate of the ADC, diagram is shown in Figure 30. Note that for signal processing and under certain conditions equidistant sampling may not be applications, it is imperative that the frame synchronization achieved. signal from the TMS320C541 provide equidistant sampling. The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same ADSP-218x* AD7904/ AD7914/ supply voltage as the TMS320C541. This allows the ADC to AD7924* operate at a higher voltage than the serial interface, that is, the SCLK SCLK TMS320C541, if necessary. DOUT DR CS RFS TMS320C541* AD7904/ TFS AD7914/ AD7924* DIN DT V SCLK CLKX DRIVE CLKR DOUT DR DIN DT V DD CS FSX *ADDITIONAL PINS REMOVED FOR CLARITY. FSR V Figure 31. Interfacing to the ADSP-218x DRIVE The timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. When an V DD *ADDITIONAL PINS REMOVED FOR CLARITY. interrupt is received, a value is transmitted with TFS/DT (ADC Figure 30. Interfacing to the TMS320C541 control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the AD7904/AD7914/AD7924 to ADSP-218x SCLKDIV register. When the instruction to transmit with TFS The ADSP-218x family of DSPs interfaces directly to the is given (that is, AX0 = TX0), the state of the SCLK is checked. AD7904/AD7914/AD7924 without any glue logic required. The DSP waits until SCLK goes high, low, and high again before The V pin of the AD7904/AD7914/AD7924 takes the same DRIVE transmission starts. If the timer and SCLK values are chosen in supply voltage as the ADSP-218x. This allows the ADC to such a way that the instruction to transmit occurs on or near operate at a higher voltage than the serial interface, that is, the the rising edge of SCLK, the data may be transmitted or it may ADSP-218x, if necessary. wait until the next clock edge. For example, if the ADSP-2189 has a 20 MHz crystal so that its master clock frequency is 40 MHz, then the master cycle time is 25 ns. If the SCLKDIV register is loaded with the value 3, then an SCLK of 5 MHz is obtained and eight master clock periods elapse for every one SCLK period. Rev. B | Page 27 of 32 03087-030 03087-031 AD7904/AD7914/AD7924 Depending on the throughput rate selected, if the timer register GROUNDING AND LAYOUT is loaded with a value such as 803 (803 + 1 = 804), then 100.5 The AD7904/AD7914/AD7924 have very good immunity to SCLKs will occur between interrupts and subsequently between noise on the power supplies (see Figure 6). However, care transmit instructions. This setup results in nonequidistant should be taken with regard to grounding and layout. sampling because the transmit instruction occurs on an SCLK The PCB that houses the AD7904/AD7914/AD7924 should be edge. If the number of SCLKs between interrupts is a whole designed such that the analog and digital sections are separated integer value N, equidistant sampling is implemented by the DSP. and confined to certain areas of the board. This facilitates the AD7904/AD7914/AD7924 to DSP563xx use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it The connection diagram in Figure 32 shows how the AD7904/ provides the best shielding. All four AGND pins of the AD7904/ AD7914/AD7924 can be connected to the ESSI (synchronous AD7914/AD7924 should be sunk in the AGND plane. Digital serial interface) of the DSP563xx family of DSPs from Motorola. and analog ground planes should be joined at only one place. If Each ESSI (two on board) is operated in synchronous mode the AD7904/AD7914/AD7924 are in a system where multiple (SYN bit in CRB = 1) with internally generated 1-bit clock devices require an AGND-to-DGND connection, the connection period frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = should still be made at one point only: a star ground point 0 in CRB). Normal operation of the ESSI is selected by setting established as close as possible to the AD7904/AD7914/AD7924. MOD = 0 in the CRB. Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should Avoid running digital lines under the device because these lines be set to 1 so that the frame sync is negative. Note that for signal couple noise onto the die. The analog ground plane should be processing applications, it is imperative that the frame synchroni- allowed to run under the AD7904/AD7914/AD7924 to avoid zation signal from the DSP563xx provide equidistant sampling. noise coupling. The power supply lines to the AD7904/AD7914/ AD7924 should use as large a trace as possible to provide low In the example shown in Figure 32, the serial clock is taken from impedance paths and reduce the effects of glitches on the power the ESSI so the SCK0 pin must be set as an output (SCKD = 1). supply line. Fast switching signals such as clocks should be The V pin of the AD7904/AD7914/AD7924 takes the same DRIVE shielded with digital ground to avoid radiating noise to other supply voltage as the DSP563xx. This allows the ADC to operate sections of the board, and clock signals should never be run at a higher voltage than the serial interface, that is, the DSP563xx, near the analog inputs. Avoid crossover of digital and analog if necessary. signals. Traces on opposite sides of the board should run at DSP563xx* AD7904/ right angles to each other to reduce the effects of feedthrough AD7914/ through the board. A microstrip technique is by far the best, but AD7924* is not always possible with a double-sided board. In this SCLK SCK technique, the component side of the board is dedicated to DOUT SRD ground planes while signals are placed on the solder side. CS STD Good decoupling is also important. All analog supplies should DIN SC2 be decoupled with 10 μF tantalum capacitors in parallel with V DRIVE 0.1 μF capacitors to AGND. To achieve the best performance from these decoupling components, place them as close as V DD possible to the device, ideally right up against the device. The *ADDITIONAL PINS REMOVED FOR CLARITY. 0.1 μF capacitors should have low effective series resistance Figure 32. Interfacing to the DSP563xx (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. B | Page 28 of 32 03087-032 AD7904/AD7914/AD7924 evaluation board, as well as with many other Analog Devices, EVALUATING AD7904/AD7914/AD7924 Inc., evaluation boards ending in the CB designator, to PERFORMANCE demonstrate and evaluate the ac and dc performance of the The recommended layout for the AD7904/AD7914/AD7924 AD7904/AD7914/AD7924. is outlined in the evaluation board for the AD7904/AD7914/ The software allows the user to perform ac (fast Fourier AD7924. The evaluation board package includes a fully assembled transform) and dc (histogram of codes) tests on the AD7904/ and tested evaluation board, documentation, and software for AD7914/AD7924. The software and documentation are on a controlling the board from a PC via the evaluation board controller CD shipped with the evaluation board. (EVAL-CONTROL-BRD2). The evaluation board controller can be used in conjunction with the AD7904/AD7914/AD7924 Rev. B | Page 29 of 32 AD7904/AD7914/AD7924 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0° 0.65 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1, 2 3 Model Notes Temperature Range Linearity Error (LSB) Package Option Package Description AD7904BRU −40°C to +85°C ±0.2 RU-16 16-Lead TSSOP AD7904BRU-REEL −40°C to +85°C ±0.2 RU-16 16-Lead TSSOP AD7904BRUZ −40°C to +85°C ±0.2 RU-16 16-Lead TSSOP AD7904BRUZ-REEL −40°C to +85°C ±0.2 RU-16 16-Lead TSSOP AD7904BRUZ-REEL7 −40°C to +85°C ±0.2 RU-16 16-Lead TSSOP AD7904WYRUZ-REEL7 −40°C to +125°C ±0.2 RU-16 16-Lead TSSOP AD7914BRU-REEL −40°C to +85°C ±0.5 RU-16 16-Lead TSSOP AD7914BRUZ −40°C to +85°C ±0.5 RU-16 16-Lead TSSOP AD7914BRUZ-REEL7 −40°C to +85°C ±0.5 RU-16 16-Lead TSSOP AD7914WYRUZ-REEL7 −40°C to +125°C ±0.5 RU-16 16-Lead TSSOP AD7924BRU −40°C to +85°C ±1 RU-16 16-Lead TSSOP AD7924BRU-REEL7 −40°C to +85°C ±1 RU-16 16-Lead TSSOP AD7924BRUZ −40°C to +85°C ±1 RU-16 16-Lead TSSOP AD7924BRUZ-REEL −40°C to +85°C ±1 RU-16 16-Lead TSSOP AD7924BRUZ-REEL7 −40°C to +85°C ±1 RU-16 16-Lead TSSOP AD7924WYRUZ-REEL7 −40°C to +125°C ±1 RU-16 16-Lead TSSOP 4 EVAL-AD79x4CBZ Evaluation Board 5 EVAL-CONTROL-BRD2 Controller Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 Linearity error refers to integral linearity error. 4 This board can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. The board comes with one chip each of the AD7904, AD7914, and AD7924. 5 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, you need to order the specific ADC evaluation board, for example, the EVAL-AD79x4CBZ, the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Technical Note for more information. AUTOMOTIVE PRODUCTS The AD7904W/AD7914W/AD7924W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. B | Page 30 of 32 AD7904/AD7914/AD7924 NOTES Rev. B | Page 31 of 32 AD7904/AD7914/AD7924 NOTES ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03087-0-7/11(B) Rev. B | Page 32 of 32