ANALOG DEVICES AD7911

2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs AD7911/AD7921 FUNCTIONAL BLOCK DIAGRAM FEATURES V DD Fast throughput rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V Low power: V IN0 10-/12-BIT 4 mW typ at 250 kSPS with 3 V supplies SUCCESSIVE MUX T/H APPROXIMATION V 13.5 mW typ at 250 kSPS with 5 V supplies IN1 ADC Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management SCLK No pipeline delays High speed serial interface: CS AD7911/AD7921 CONTROL LOGIC SPI®/QSPI™/MICROWIRE™/DSP compatible DOUT Standby mode: 1 μA maximum DIN 8-lead TSOT package 8-lead MSOP package GND APPLICATIONS Figure 1. Battery-powered systems: Personal digital assistants The AD7911/AD7921 use advanced design techniques to Medical instruments achieve very low power dissipation at high throughput rates. Mobile communications Instrumentation and control systems The reference for the part is taken internally from V , thereby DD Data acquisition systems allowing the widest dynamic input range to the ADC. The High speed modems analog input range for the part, therefore, is 0 to VDD. The Optical sensors conversion rate is determined by the SCLK signal. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. The AD7911/AD7921 are 10-bit and 12-bit, high speed, low 2. Low power consumption. power, 2-channel successive approximation ADCs, respectively. 3. Flexible power/serial clock speed management. The parts operate from a single 2.35 V to 5.25 V power supply The conversion rate is determined by the serial clock; and feature throughput rates of up to 250 kSPS. The parts conversion time is reduced when the serial clock speed is contain a low noise, wide bandwidth track-and-hold amplifier, increased. The parts also feature a power-down mode to which can handle input frequencies in excess of 6 MHz. The maximize power efficiency at lower throughput rates. conversion process and data acquisition are controlled using CS Average power consumption is reduced when the power- and the serial clock, allowing the devices to interface with down mode is used while not converting. Current microprocessors or DSPs. The input signal is sampled on the consumption is 1 μA maximum and 50 nA typically when falling edge of CS, and the conversion is also initiated at this in power-down mode. point. There are no pipeline delays associated with the part. 4. Reference derived from the power supply. 5. No pipeline delay. The channel to be converted is selected through the DIN pin, The parts feature a standard successive approximation CS and the mode of operation is controlled by . The serial data CS ADC with accurate control of the sampling instant via a stream from the DOUT pin has a channel identifier bit, which input and once-off conversion control. provides information about the converted channel. 1 Protected by U.S. Patent Number 6,681,332. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 ©2004–2011 Analog Devices, Inc. All rights reserved. 04350-0-001 AD7911/AD7921 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Input ............................................................................... 16 AD7911 Specifications................................................................. 3 Digital Inputs .............................................................................. 17 AD7921 Specifications................................................................. 5 DIN Input.................................................................................... 17 Timing Specifications .................................................................. 7 DOUT Output ............................................................................ 17 Timing Diagrams.......................................................................... 7 Modes of Operation ....................................................................... 18 Timing Examples.......................................................................... 8 Normal Mode.............................................................................. 18 Absolute Maximum Ratings............................................................ 9 Power-Down Mode.................................................................... 18 ESD Caution.................................................................................. 9 Power-Up Time .......................................................................... 19 Pin Configurations and Function Descriptions ......................... 10 Power vs. Throughput Rate....................................................... 20 Terminology .................................................................................... 11 Serial Interface ................................................................................ 21 Typical Performance Characteristics ........................................... 13 Microprocessor Interfacing....................................................... 22 Circuit Information........................................................................ 15 Application Hints ........................................................................... 24 Converter Operation.................................................................. 15 Grounding and Layout .............................................................. 24 ADC Transfer Function............................................................. 15 Outline Dimensions ....................................................................... 25 Typical Connection Diagram ................................................... 16 Ordering Guide .......................................................................... 25 REVISION HISTORY 5/11—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 4/04—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7911/AD7921 SPECIFICATIONS AD7911 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. V = 2.35 V to 5.25 V, f = 5 MHz, f = 250 kSPS; T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 1. 1 Parameter A Grade Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave 2 Signal-to- Noise and Distortion (SINAD) 61 dB min 2 Total Harmonic Distortion (THD) −71 dB max 2 Peak Harmonic or Spurious Noise (SFDR) −72 dB max 2 Intermodulation Distortion (IMD) Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −83 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ 2 Channel-to-Channel Isolation −90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 2 Integral Nonlinearity ±0.5 LSB max 2 Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 2 Offset Error ±0.5 LSB max 2, 3 Offset Error Match ±0.3 LSB max 2 Gain Error ±0.5 LSB max 2, 3 Gain Error Match ±0.3 LSB max 2 Total Unadjusted Error (TUE) ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±0.3 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 (V ) V min 2.35 V ≤ V ≤ 2.7 V INH DD DD 2 V min 2.7 V < V ≤ 5.25 V DD Input Low Voltage, VINL 0.3 V max VDD = 2.35 V 0.2 (VDD) V max 2.35 V < VDD ≤ 2.7 V 0.8 V max 2.7 V < VDD ≤ 5.25 V Input Current, IIN, SCLK Pin ±0.3 μA max VIN = 0 V or VDD Input Current, I , CS Pin IN ±0.3 μA max Input Current, I , DIN Pin ±0.3 μA max IN Input Capacitance, CIN 5 pF max LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, V = 2.35 V to 5.25 V OH DD SOURCE DD Output Low Voltage, VOL 0.2 V max ISINK = 200 μA Floating-State Leakage Current ±0.3 μA max 3 Floating-State Output Capacitance 5 pF max Output Coding Straight (natural) binary See notes at end of table. Rev. A | Page 3 of 28 AD7911/AD7921 1 Parameter A Grade Unit Test Conditions/Comments CONVERSION RATE Conversion Time 2.8 μs max 14 SCLK cycles with SCLK at 5 MHz 2 Track-and-Hold Acquisition Time 290 ns max Throughput Rate 250 kSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 3 mA typ V = 4.75 V to 5.25 V, SCLK on or off DD 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Full Power-Down Mode (Static) 1 μA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.38 mA typ V = 5 V, f = 5 MHz, f = 25 kSPS DD SCLK SAMPLE 0.2 mA typ V = 3 V, f = 5 MHz, f = 25 kSPS DD SCLK SAMPLE 4 Power Dissipation Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 250 kSPS 6 mW max VDD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 μW max V = 5 V DD 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. Rev. A | Page 4 of 28 AD7911/AD7921 AD7921 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter A Grade Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave 2 Signal-to-Noise and Distortion (SINAD) 70 dB min 72 dB typ 2 Signal-to-Noise Ratio (SNR) 71 dB min 72.5 dB typ 2 Total Harmonic Distortion (THD) −81 dB typ 2 Peak Harmonic or Spurious Noise (SFDR) −84 dB typ 2 Intermodulation Distortion (IMD) Second-Order Terms −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Term −86 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ 2 Channel-to-Channel Isolation −90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 2 Integral Nonlinearity ±1.5 LSB max 2 Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 2 Offset Error ±1.5 LSB max ±0.5 LSB typ 2, 3 Offset Error Match ±0.5 LSB max 2 Gain Error ± 2 LSB max ±0.3 LSB typ 2, 3 Gain Error Match ±1 LSB max 2 Total Unadjusted Error (TUE) ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±0.3 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 (VDD) V min 2.35 V ≤ VDD ≤ 2.7 V 2 V min 2.7 V < VDD ≤ 5.25 V Input Low Voltage, VINL 0.3 V max VDD = 2.35 V 0.2 (V ) V max 2.35 V < V ≤ 2.7 V DD DD 0.8 V max 2.7 V < V ≤ 5.25 V DD Input Current, IIN, SCLK Pin ±0.3 μA max VIN = 0 V or VDD CS ±0.3 μA max Input Current, IIN, Pin Input Current, IIN, DIN Pin ±0.3 μA max 3 Input Capacitance, C 5 pF max IN LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±0.3 μA max 3 Floating-State Output Capacitance 5 pF max Output Coding Straight (natural) binary See notes at end of table. Rev. A | Page 5 of 28 AD7911/AD7921 1 Parameter A Grade Unit Test Conditions/Comments CONVERSION RATE Conversion Time 3.2 μs max 16 SCLK cycles with SCLK at 5 MHz 2 Track-and-Hold Acquisition Time 290 ns max Throughput Rate 250 kSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.35/5.25 V min/max I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 3 mA typ V = 4.75 V to 5.25 V, SCLK on or off DD 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Full Power-Down Mode (Static) 1 μA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.4 mA typ V = 5 V, f = 5 MHz, f = 25 kSPS DD SCLK SAMPLE 0.22 mA typ V = 3 V, f = 5 MHz, f = 25 kSPS DD SCLK SAMPLE 4 Power Dissipation Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 250 kSPS 6 mW max VDD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 μW max V = 5 V DD 3 μW max V = 3 V DD 1 Operational from V = 2 V, with V = 1.9 V minimum and V = 0.1 V maximum. DD IH IL 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. Rev. A | Page 6 of 28 AD7911/AD7921 TIMING SPECIFICATIONS Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at T , T Unit Description MIN MAX 1 2 fSCLK 10 kHz min 5 MHz max t 16 × t AD7921 CONVERT SCLK 14 × t AD7911 SCLK t 30 ns min Minimum quiet time required between bus relinquish and start of next conversion QUIET t 15 ns min Minimum CS pulse width 1 t 10 ns min CS to SCLK setup time 2 3 t 30 ns max Delay from CS until DOUT three-state is disabled 3 3 t 45 ns max DOUT access time after SCLK falling edge 4 t 0.4 t ns min SCLK low pulse width 5 SCLK t6 0.4 tSCLK ns min SCLK high pulse width 4 t7 10 ns min SCLK to DOUT valid hold time t8 5 ns min DIN setup time prior to SCLK falling edge t 6 ns min DIN hold time after SCLK falling edge 9 5 t 30 ns max SCLK falling edge to DOUT three-state 10 10 ns min SCLK falling edge to DOUT three-state 6 tPOWER-UP 1 μs max Power-up time from full power-down 1 Mark/space ratio for SCLK input is 40/60 to 60/40. 2 Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V or V voltage. IH IL 4 Measured with a 50 pF load capacitor. 5 T is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated 10 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See the Power-Up Time section. TIMING DIAGRAMS t 7 200μAI OL SCLK TO OUTPUT 1.6V PIN C L V IH 50pF DOUT V IL 200μAI OH Figure 2. Load Circuit for Digital Output Timing Specifications Figure 4. Hold Time after SCLK Falling Edge t t 4 10 SCLK SCLK V IH 1.6V DOUT DOUT V IL Figure 3. Access Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State Rev. A | Page 7 of 28 04350-0-002 04350-0-003 04350-0-005 04350-0-004 AD7911/AD7921 Timing Example 2 TIMING EXAMPLES The AD7921 can also operate with slower clock frequencies. As Figure 6 and Figure 7 show some of the timing parameters from shown in Figure 7, when fSCLK = 2 MHz and the throughput rate the Timing Specifications section. is 100 KSPS, the cycle time is Timing Example 1 As shown in Figure 7, when f = 5 MHz and the throughput is t2 + 12.5(1/fSCLK) + tACQ = 10 μs SCLK 250 kSPS, the cycle time is With t = 10 ns minimum, then t is 3.74 μs, which satisfies 2 ACQ the requirement of 290 ns for t . t2 + 12.5(1/fSCLK) + tACQ = 4 μs ACQ In Figure 7, t is comprised of 2.5(1/f ) + t + t , where With t2 = 10 ns minimum, then tACQ is 1.49 μs, which satisfies ACQ SCLK 10 QUIET the requirement of 290 ns for tACQ. t10 = 30 ns maximum. This allows a value of 2.46 μs for tQUIET, satisfying the minimum requirement of 30 ns. In Figure 7, t is comprised of 2.5(1/f ) + t + t , where ACQ SCLK 10 QUIET t = 30 ns maximum. This allows a value of 960 ns for t , In this example, as with other slower clock values, the signal 10 QUIET satisfying the minimum requirement of 30 ns. might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum t between QUIET conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7. t 1 CS t CONVERT t 2 t B 6 SCLK 12 34 5 13 14 15 16 t t 5 7 t 10 t t 3 4 t QUIET Z ZERO CHN X DB11 DB10 DB2 DB1 DB0 DOUT THREE-STATE THREE-STATE t t 8 9 DIN X X CHN X X X X X X Figure 6. AD7921 Serial Interface Timing Diagram CS t CONVERT t 2 BC SCLK 12 3 4 5 13 14 15 16 t 10 t QUIET 12.5(1/f ) t SCLK ACQUISITION 1/THROUGHPUT Figure 7. Serial Interface Timing Example Rev. A | Page 8 of 28 04350-0-007 04350-0-006 AD7911/AD7921 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only and functional operation of the device at these or Analog Input Voltage to GND −0.3 V to V + 0.3 V DD any other conditions above those indicated in the operational Digital Input Voltage to GND −0.3 V to +7 V section of this specification is not implied. Exposure to absolute Digital Output Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect 1 Input Current to Any Pin except Supplies ±10 mA device reliability. Operating Temperature Range Commercial (A Grade) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSOT Package θJA Thermal Impedance 207°C/W MSOP Package θ Thermal Impedance 205.9°C/W JA θJC Thermal Impedance 43.74°C/W Lead Temperature Soldering Reflow (10 s to 30 s) 235 (0/+5)°C ESD 2 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 9 of 28 AD7911/AD7921 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 8-LEAD TSOT 8-LEAD MSOP DIN 1 8 V DOUT 1 8 V IN1 DD AD7911/ AD7911/ SCLK 2 7 V CS 2 7 GND IN0 AD7921 AD7921 CS 3 6 GND SCLK 3 6 V IN0 TOP VIEW TOP VIEW DOUT 4 5 V DIN 4 5 V (Not to Scale) (Not to Scale) DD IN1 Figure 8. 8-Lead TSOT Pin Configuration Figure 9. 8-Lead MSOP Pin Configuration Table 5. Pin Function Descriptions TSOT MSOP Pin No. Pin No. Mnemonic Function 1 4 DIN Data In. Logic input. The channel to be converted is provided on this input and is clocked into an internal register on the falling edge of SCLK. 2 3 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7911/AD7921’s conversion process. 3 2 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7911/AD7921 and framing the serial data transfer. 4 1 DOUT Data Out. Logic output. The conversion result from the AD7911/AD7921 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK signal. For the AD7921, the data stream consists of two leading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 12 bits of conversion data, with MSB first. For the AD7911, the data stream consists of two leading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 10 bits of conversion data, with MSB first and two trailing zeros. 5 8 V Power Supply Input. The V range for the AD7911/AD7921 is from 2.35 V to 5.25 V. DD DD 6 7 GND Analog Ground. Ground reference point for all circuitry on the AD7911/AD7921. All analog input signals should be referred to this GND voltage. 7, 8 6, 5 V , V Analog Inputs. These two single-ended analog input channels are multiplexed into the on-chip track- IN0 IN1 and-hold amplifier. The analog input channel to be converted is selected by writing to the third MSB on the DIN pin. The input range is 0 to V . DD Rev. A | Page 10 of 28 04350-0-008 04350-0-034 AD7911/AD7921 TERMINOLOGY Integral Nonlinearity Signal-to-Noise and Distortion Ratio (SINAD) The maximum deviation from a straight line passing through The measured ratio of signal-to-noise and distortion at the the endpoints of the ADC transfer function. For the AD7911/ output of the A/D converter. The signal is the rms value of the AD7921, the endpoints of the transfer function are zero scale, a sine wave, and noise is the rms sum of all nonfundamental point 1 LSB below the first code transition, and full scale, a signals up to half the sampling frequency (fs/2), including point 1 LSB above the last code transition. harmonics but excluding dc. Differential Nonlinearity Signal-to-Noise Ratio (SNR) The difference between the measured and the ideal 1 LSB The measured ratio of signal to noise at the output to the A/D change between any two adjacent codes in the ADC. converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist Offset Error bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by √2, and the rms value for the The deviation of the first code transition (00…000) to quantization noise is q/√12. The ratio is dependent on the (00…001) from the ideal, that is, AGND + 1 LSB. number of quantization levels in the digitization process; the Offset Error Match more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as The difference in offset error between any two channels. SNR= 6.02 N+ 1.76 dB Gain Error Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit The deviation of the last code transition (111…110) to converter, SNR is 62 dB. (111…111) from the ideal, that is, VREF − 1 LSB after the offset error has been adjusted out. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur Gain Error Match due to integral and differential nonlinearities, internal ac noise sources, and so on. The difference in gain error between any two channels. Total Harmonic Distortion (THD) Total Unadjusted Error A comprehensive specification that includes gain error, linearity The ratio of the rms sum of harmonics to the fundamental, error, and offset error. which is defined as 2 2 2 2 2 Channel-to-Channel Isolation V +V +V +V +V 2 3 4 5 6 THD( dB)= 20 log V A measure of the level of crosstalk between channels. It is 1 measured by applying a full-scale sine wave signal of 20 kHz to where: 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a V1 is the rms amplitude of the fundamental. 10 kHz signal. The figure is given worst case across both V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 channels for the AD7911/AD7921. through the sixth harmonics. Track-and-Hold Acquisition Time Peak Harmonic or Spurious Noise The time required for the output of the track-and-hold The ratio of the rms value of the next largest component in the amplifier to reach its final value within ±1 LSB after the end of ADC output spectrum (up to fs/2 and excluding dc) to the rms conversion. The track-and-hold amplifier returns to track mode value of the fundamental. Normally, the value of this specifica- at the end of conversion. See the Serial Interface section for tion is determined by the largest harmonic in the spectrum, but more details. for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Rev. A | Page 11 of 28 AD7911/AD7921 Intermodulation Distortion The AD7911/AD7921 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the With inputs consisting of sine waves at two frequencies, fa and Specifications section). In this case, the second-order terms are fb, any active device with nonlinearities creates distortion usually distanced in frequency from the original sine waves, products at sum and difference frequencies of mfa ± nfb, where while the third-order terms are usually at a frequency close to m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms the input frequencies. As a result, the second-order and third- are those for which neither m nor n is equal to zero. For order terms are specified separately. The calculation of the example, the second-order terms include (fa + fb) and (fa − fb), intermodulation distortion is as in the THD specification, while the third-order terms include (2fa + fb), (2fa − fb), (fa + where it is defined as the ratio of the rms sum of the individual 2fb), and (fa − 2fb). distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Rev. A | Page 12 of 28 AD7911/AD7921 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7921 Figure 14 and Figure 15 show INL and DNL performance for and AD7911, respectively, at a 250 kSPS sample rate and the AD7921. 100 kHz input frequency. Figure 16 shows a graph of the total harmonic distortion versus Figure 12 shows the SINAD ratio performance versus the input the analog input frequency for different source impedances frequency for various supply voltages while sampling at when using a supply voltage of 3.6 V and a sampling rate of 250 kSPS with a SCLK frequency of 5 MHz for the AD7921. 250 kSPS. See the Analog Input section. Figure 13 shows the SNR ratio performance versus the input Figure 17 shows a graph of the total harmonic distortion versus frequency for various supply voltages while sampling at the analog input frequency for various supply voltages while 250 kSPS with an SCLK frequency of 5 MHz for the AD7921. sampling at 250 kSPS with an SCLK frequency of 5 MHz. Figure 18 shows the shutdown current versus the voltage supply for different operating temperatures. 5 –70.5 8192 POINT FFT V = 2.7V DD F = 250kSPS –71.0 SAMP –15 V = 5.25V F = 100kHz DD IN V = 4.75V DD SNR = 73.13dB –71.5 SINAD = 72.73dB –35 THD = –83.30dB SFDR = –86.15dB –72.0 –55 V = 2.35V DD –72.5 –75 V = 3.6V DD –73.0 –95 –73.5 V = 2.7V DD –115 –74.0 0 20 40 60 80 100 120 10 100 1k FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. AD7921 Dynamic Performance at 250 kSPS Figure 12. AD7921 SINAD vs. Input Frequency at 250 kSPS 5 –72.0 8192 POINT FFT 8192 POINT FFT V = 2.7V V = 2.7V DD DD –72.2 F = 250kSPS F = 250kSPS SAMP SAMP –15 F = 100kHz F = 100kHz IN V = 2.35V IN DD SNR = 61.75dB SNR = 73.13dB –72.4 SINAD = 61.74dB SINAD = 72.73dB –35 THD = –86.24dB THD = –83.30dB –72.6 SFDR = –84.46dB V = 5.25V SFDR = –86.15dB DD V = 4.75V DD –55 –72.8 –73.0 –75 –73.2 V = 3.6V DD –95 –73.4 V = 2.7V DD –115 –73.6 0 20 40 60 80 100 120 10 100 1k FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. AD7911 Dynamic Performance at 250 kSPS Figure 13. AD7921 SNR vs. Input Frequency at 250 kSPS Rev. A | Page 13 of 28 SNR (dB) SNR (dB) 04350-0-010 04350-0-009 SNR (dB) SINAD (dB) 04350-0-012 04350-0-011 AD7911/AD7921 1.0 –74 V = 2.7V DD V = 5.25V V = 4.75V DD DD 0.8 F = 250kSPS SAMP –76 TEMPERATURE = 25°C 0.6 –78 0.4 0.2 –80 V = 2.7V DD 0 –82 –0.2 V = 2.35V DD –0.4 –84 –0.6 –86 –0.8 V = 3.6V DD –1.0 –88 0 512 1024 1536 2048 2560 3072 3584 4096 10 100 1k CODE FREQUENCY (kHz) Figure 14. AD7921 INL Performance Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages 1.0 180 V = 2.7V DD F = 250kSPS 0.8 SAMP 160 TEMPERATURE = 25°C 0.6 140 TEMPERATURE = +85°C 0.4 120 0.2 100 0 80 –0.2 60 –0.4 40 –0.6 TEMPERATURE = +25°C 20 –0.8 TEMPERATURE = –40°C –1.0 0 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CODE SUPPLY VOLTAGE (V) Figure 15. AD7921 DNL Performance Figure 18. Shutdown Current vs. Supply Voltage –25 V = 3.6V DD –35 R = 1kΩ IN –45 –55 R = 500Ω IN R = 100Ω IN –65 R = 50Ω IN –75 –85 R = 0Ω R = 10Ω IN IN –95 10 100 1k FREQUENCY (kHz) Figure 16. THD vs. Analog Input Frequency for Various Source Impedances Rev. A | Page 14 of 28 DNL ERROR (LSB) INL ERROR (LSB) THD (dB) 04350-0-015 04350-0-014 04350-0-013 SHUTDOWN CURRENT (nA) THD (dB) 04350-0-017 04350-0-016 AD7911/AD7921 CIRCUIT INFORMATION The AD7911/AD7921 are fast, 2-channel, 10-/12-bit, single When the ADC starts a conversion (see Figure 20), SW2 opens supply, analog-to-digital converters (ADCs), respectively. The and SW1 moves to Position B, causing the comparator to parts can be operated from a 2.35 V to 5.25 V supply. When become unbalanced. The control logic and the charge operated from either a 5 V supply or a 3 V supply, the redistribution DAC are used to add and subtract fixed amounts AD7911/AD7921 are capable of throughput rates of 250 kSPS of charge from the sampling capacitor to bring the comparator when provided with a 5 MHz clock. back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic The AD7911/AD7921 provide the user with an on-chip track- generates the ADC output code. Figure 21 shows the ADC and-hold, an ADC, and a serial interface, all housed in a tiny 8- transfer function. lead TSOT package or an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative CHARGE solutions. The serial clock input accesses data from the parts, REDISTRIBUTION DAC controls the transfer of data written to the ADC, and provides SAMPLING the clock source for the successive approximation ADC. The CAPACITOR A V IN0 analog input range is 0 to V . An external reference is not DD CONTROL SW2 LOGIC SW1 V CONVERSION required for the ADC, and neither is there a reference on-chip. IN1 B PHASE The reference for the AD7911/AD7921 is derived from the COMPARATOR V /2 DD power supply and, therefore, gives the widest dynamic input AGND range. Figure 20. ADC Conversion Phase The AD7911/AD7921 feature a power-down option that allows power saving between conversions. The power-down feature is ADC TRANSFER FUNCTION implemented across the standard serial interface as described in The output coding of the AD7911/AD7921 is straight binary. the Modes of Operation section. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is CONVERTER OPERATION V /4096 for the AD7921 and V /1024 for the AD7911. The DD DD The AD7911/AD7921 are 10-/12-bit successive approximation ideal transfer characteristic for the AD7911/AD7921 is shown ADCs based around a charge redistribution DAC. Figure 19 and in Figure 21. Figure 20 show simplified schematics of the ADC. Figure 19 shows the ADC during its acquisition phase. SW2 is closed and 111...111 SW1 is in Position A, the comparator is held in a balanced 111...110 condition, and the sampling capacitor acquires the signal on the selected VIN channel. 111...000 011...111 CHARGE 1LSB = V /4096 (AD7921) DD REDISTRIBUTION 1LSB = V /1024 (AD7911) DD DAC 000...010 000...001 SAMPLING 000...000 CAPACITOR A 1LSB +V – 1LSB 0V DD V IN0 CONTROL ANALOG INPUT SW2 SW1 LOGIC V ACQUISITION IN1 B PHASE COMPARATOR V /2 DD Figure 21. AD7911/AD7921 Transfer Characteristic AGND Figure 19. ADC Acquisition Phase Rev. A | Page 15 of 28 04350-0-018 ADC CODE 04350-0-020 04350-0-019 AD7911/AD7921 TYPICAL CONNECTION DIAGRAM Table 6 provides some typical performance data with various references used as a V source and a 50 kHz input tone under DD Figure 22 shows a typical connection diagram for the AD7911/ the same setup conditions. AD7921. VREF is taken internally from VDD and as such VDD should be well decoupled. This provides an analog input range Table 6. AD7921 Performance for Various Voltage of 0 V to V . The conversion result is output in a 16-bit word DD References IC with two leading zeros, followed by the channel identifier bit Reference Tied to VDD AD7921 SNR Performance (dB) that identifies the channel converted, followed by an invalid bit AD780 at 3 V −73 that matches up to the channel converted, followed by the MSB REF193 −72.42 of the 12-bit or 10-bit result. For the AD7911, the 10-bit result is ADR433 −72.9 followed by two trailing zeros. See the Serial Interface section. AD780 at 2.5 V −72.86 REF192 −72.27 Alternatively, because the supply current required by the ADR421 −72.75 AD7911/AD7921 is so low, a precision reference can be used as the supply source to the AD7911/AD7921. A REF19x voltage ANALOG INPUT reference (REF195 for 5 V or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This Figure 23 shows an equivalent circuit of the analog input configuration is especially useful, if the power supply is quite structure of the AD7911/AD7921. The two diodes, D1 and D2, noisy or if the system supply voltages are at some value other provide ESD protection for the analog input. Care must be than 5 V or 3 V (for example, 15 V). The REF19x outputs a taken to ensure that the analog input signal never exceeds the steady voltage to the AD7911/AD7921. If the low dropout supply rails by more than 300 mV, because this would cause REF193 is used, the current it needs to supply to the AD7911/ these diodes to become forward biased and start conducting AD7921 is typically 1.5 mA. When the ADC is converting at a current into the substrate. The maximum current these diodes rate of 250 kSPS, the REF193 needs to supply a maximum of can conduct without causing irreversible damage to the part is 2 mA to the AD7911/AD7921. The load regulation of the 10 mA. REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which V DD results in an error of 20 ppm (60 μV) for the 2 mA drawn from C2 it. This corresponds to a 0.082 LSB error for the AD7921 with D1 20pF R1 V = 3 V from the REF193 and a 0.061 LSB error for the DD V IN C1 AD7911. D2 6pF For applications where power consumption is a concern, the CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power perform- Figure 23. Equivalent Analog Input Circuit ance. See the Modes of Operation section. The capacitor C1 in Figure 23 is typically about 6 pF and can 3V 5V primarily be attributed to pin capacitance. The resistor R1 is a REF193 SUPPLY 1.5mA 1μF lumped component made up of the on resistance of a track- 0.1μF 10μF 0.1μF TANT and-hold switch and also includes the on resistance of the input 680nF multiplexer. This resistor is typically about 100 Ω. The capacitor V DD C2 is the ADC sampling capacitor and has a capacitance of 0V TO V V DD IN0 SCLK AD7911/ INPUT 20 pF typically. CS AD7921 μC/μP V IN1 DIN For ac applications, removing high frequency components from DOUT GND the analog input signal is recommended using a band-pass filter on the relevant analog input pin. In applications where SERIAL INTERFACE harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Figure 22. REF193 as Power Supply to AD7911/AD7921 Large source impedances can significantly affect the ac performance of the ADC. This might necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Rev. A | Page 16 of 28 04350-0-021 04350-0-022 AD7911/AD7921 DIN INPUT Table 7 provides some typical performance data with various op amps used as the input buffer, and a 50 kHz input tone The channel to be converted on in the next conversion is under the same setup conditions. selected by writing to the DIN pin. Data on the DIN pin is loaded into the AD7911/AD7921 on the falling edge of SCLK. Table 7. AD7921 Performance for Various Input Buffers The data is transferred into the part on the DIN pin at the same Op Amp in the Input AD7921 SNR Performance (dB) time that the conversion result is read from the part. Buffer 50 kHz Input , VDD = 3.6 V Single op amps Only the third bit of the DIN word is used; the rest are ignored AD8038 −72.79 by the ADC. The third MSB is the channel identifier bit, which AD8510 −72.35 identifies the channel to be converted on in the next conversion, AD8021 −72.2 VIN0 (CHN = 0) or VIN1 (CHN = 1). Dual op amps MSB LSB AD712 −72.68 X X CHN X DON'T CARE AD8022 −72.88 Figure 24. AD7911/AD7921 DIN Word When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum DOUT OUTPUT source impedance depends on the amount of total harmonic The conversion result from the AD7911/AD7921 is provided on distortion (THD) that can be tolerated. The THD increases as this output as a serial data stream. The bits are clocked out on the source impedance increases and performance degrades (see the SCLK falling edge at the same time that the conversion is Figure 16). taking place. DIGITAL INPUTS The serial data stream for the AD7921 consists of two leading The digital inputs applied to the AD7911/AD7921 are not zeros followed by the bit that identifies the channel converted, limited by the maximum ratings that limit the analog input. an invalid bit that matches up to the channel identifier bit, and Instead, the digital inputs applied can go to 7 V and are not the 12-bit conversion result with MSB provided first. restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7911/AD7921 are operated with a VDD of 3 V, For the AD7911, the serial data stream consists of two leading then 5 V logic levels could be used on the digital inputs. How- zeros followed by the bit that identifies the channel converted, ever, it is important to note that the data output on DOUT still an invalid bit that matches up to the channel identifier bit, and has 3 V logic levels when V = 3 V. Another advantage of DD the 10-bit conversion result with MSB provided first, followed SCLK, DIN, and CS not being restricted by the V + 0.3 V by two trailing zeros. DD limit is that power supply sequencing issues are avoided. If CS, MSB LSB DIN, or SCLK are applied before VDD, then there is no risk of 00 CHN X CONVERSION RESULT 0 0 AD7911 latch-up as there would be on the analog inputs, if a signal AD7921 greater than 0.3 V were applied prior to VDD. 0 0 CHN X CONVERSION RESULT Figure 25. AD7911/AD7921 DOUT Word Rev. A | Page 17 of 28 04350-0-023 04350-0-024 AD7911/AD7921 MODES OF OPERATION POWER-DOWN MODE The two modes of operation of the AD7911/AD7921 are normal mode and power-down mode. The mode of operation is Power-down mode is intended for use in applications where selected by controlling the logic state of the CS signal. The point slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of at which CS is pulled high after the conversion has been initi- conversions can be performed at a high throughput rate and ated determines whether the AD7911/AD7921 enter power- then the ADC is powered down for a relatively long duration CS down mode. Similarly, if already in power-down mode, can between these bursts of several conversions. When the control whether the device returns to normal operation or AD7911/AD7921 are in power-down mode, all analog circuitry remains in power-down mode. is powered down. Power-down mode is designed to provide flexible power To enter power-down mode, the conversion process must be management options and to optimize the ratio of power CS interrupted by bringing high any time after the second dissipation to throughput rate for different application falling edge of SCLK and before the 10th falling edge of SCLK, requirements. as shown in Figure 27. Once CS has been brought high in this NORMAL MODE window of SCLKs, then the part enters power-down mode, the Normal mode is intended for the fastest throughput rate conversion that was initiated by the falling edge of CS is performance. The user does not have to worry about any CS terminated, and DOUT goes back into three-state. If is power-up time, because the AD7911/AD7921 remain fully brought high before the second SCLK falling edge, then the part powered all the time. Figure 26 shows the operation of the remains in normal mode and does not power down. This helps AD7911/AD7921 in this mode. CS to avoid accidental power-down due to glitches on the line. CS The conversion is initiated on the falling edge of , as To exit this mode of operation and power the AD7911/AD7921 described in the Serial Interface section. To ensure that the part up again, a dummy conversion is performed. On the falling remains fully powered up at all times, CS must remain low until edge of CS, the device begins to power up and continues to at least 10 SCLK falling edges have elapsed after the falling edge power up as long as CS is held low until after the falling edge of of CS. If CS is brought high any time after the 10th SCLK falling the 10th SCLK. The device is fully powered up once 16 SCLKs edge but before the end of t , the part remains powered- CONVERT have elapsed and valid data results from the next conversion, as up, but the conversion is terminated and DOUT goes back into CS shown in Figure 28. If is brought high before the 10th falling three-state. For the AD7911/AD7921, a minimum of 14 and edge of SCLK, then the AD7911/AD7921 go back into power- 16 serial clock cycles, respectively, are needed to complete the down mode. This helps to avoid accidental power-up due to conversion and access the complete conversion result. glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. Therefore, although the device might begin to CS can idle high until the next conversion or can idle low until CS power up on the falling edge of , it powers down again on the CS returns high sometime prior to the next conversion CS rising edge of , as long as this occurs before the 10th SCLK CS (effectively idling low). Once a data transfer is complete falling edge. (DOUT has returned to three-state), another conversion can be CS initiated after the quiet time, tQUIET, has elapsed by bringing low again. AD7911/AD7921 CS 1 10 12 14 16 1 10 12 14 16 SCLK DIN CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION CONVERSION RESULT CONVERSION RESULT DOUT Figure 26. Normal Mode Operation Rev. A | Page 18 of 28 04350-0-025 AD7911/AD7921 CS 1210 16 SCLK THREE-STATE DIN INVALID DATA THREE-STATE DOUT INVALID DATA Figure 27. Entering Power- Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY THE PART GOES POWERED UP WITH V IN INTO TRACK FULLY ACQUIRED CS A 11 5 0 16 1 16 SCLK DIN CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION DOUT INVALID DATA CONVERSION RESULT Figure 28. Exiting Power-Down Mode with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At POWER-UP TIME this stage, the ADC would be fully powered up. In this case, CS The power-up time of the AD7911/AD7921 is 1 μs, which can be brought high after the 10th SCLK falling edge and means that with any frequency of SCLK up to 5 MHz, one brought low again after a time, t , to initiate the conversion. QUIET dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully When power supplies are first applied to the AD7911/AD7921, powered up and the input signal is acquired properly. The quiet the ADC can power up in either power-down mode or normal time, tQUIET, must still be allowed from the point at which the mode. Because of this, it is best to allow a dummy cycle to bus goes back into three-state after the dummy conversion to elapse to ensure that the part is fully powered up before CS the next falling edge of . When running at a 250 kSPS attempting a valid conversion. Likewise, if the user wants to throughput rate, the AD7911/AD7921 power up and acquire a keep the part in power-down mode while not in use and to signal within ±1 LSB in one dummy cycle. power up in power-down mode, then the dummy cycle can be used to ensure that the device is in power-down mode by When powering up from power-down mode with a dummy executing a cycle such as that shown in Figure 27. cycle, as in Figure 28, the track-and-hold that was in hold mode while the part was powered down returns to track mode on the Once supplies are applied to the AD7911/AD7921, the power- fifth SCLK falling edge that the part receives after the falling up time is the same as when powering up from the power-down CS edge of . This is shown as point A in Figure 28. At this point, mode. It takes the part approximately 1 μs to power up fully in the part starts to acquire the signal on the channel selected in normal mode. It is not necessary to wait 1 μs before executing a the current dummy conversion. dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to Although at any SCLK frequency one dummy cycle is sufficient the ADC. If the first valid conversion is then performed directly to power up the device and acquire VIN, it does not necessarily after the dummy conversion, care must be taken to ensure that mean that a full dummy cycle of 16 SCLKs must always elapse adequate acquisition time has been allowed. When the ADC to power up the device and acquire VIN fully. 1μs is sufficient to powers up initially after supplies are applied, the track-and-hold power up the device and acquire the input signal. For example, is in hold. It returns to track on the fifth SCLK falling edge that if a 5 MHz SCLK frequency was applied to the ADC, the cycle the part receives after the falling edge of CS. time would be 3.2 μs. In one dummy cycle, 3.2 μs, the part acquired fully. However, after 1 μs would be powered up and VIN Rev. A | Page 19 of 28 04350-0-026 04350-0-027 AD7911/AD7921 In the previous examples, the power dissipation when the part POWER VS. THROUGHPUT RATE is in power-down mode has not been taken into account, By using the power-down mode on the AD7911/AD7921 when because the shutdown current is so low that it does not have any not converting, the average power consumption of the ADC effect on the overall power dissipation value. Figure 29 shows decreases at lower throughput rates. Figure 29 shows how, as the the power consumption versus throughput rate when using the throughput rate is reduced, the device remains in its power- power-down mode between conversions with both 5 V and 3 V down state longer and the average power consumption over supplies. time drops accordingly. Power-down mode is intended for use with throughput rates of For example, if the AD7911/AD7921 are operating in a approximately 120 kSPS and under, because higher sampling continuous sampling mode with a throughput rate of 50 kSPS rates do not have a power saving in power-down mode. and a SCLK of 5 MHz (VDD = 5 V) and the devices are placed in 100 power-down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 20 mW (V = 5 V). If one dummy DD V = 5V, SCLK = 5MHz DD 10 cycle powers up the part between conversions (3.2 μs), and the remaining conversion time is another cycle (3.2 μs), then the AD7911/AD7921 dissipate 20 mW for 6.4 μs during each V = 3V, SCLK = 5MHz DD 1 conversion cycle. If the throughput rate is 50 kSPS and the cycle time is 20 μs, then the average power dissipated during each cycle is 0.1 (6.4/20) × (20 mW) = 6.4 mW If V = 3 V, SCLK= 5 MHz, and the device is again in power- DD 0.01 down mode between conversions, then the power dissipation 0 15 30 45 60 75 90 105 120 135 THROUGHPUT (kSPS) during normal operation is 6 mW. The AD7911/AD7921 now Figure 29. Power Consumption vs. Throughput Rate dissipate 6 mW for 6.4 μs during each conversion cycle. With a throughput rate of 50 kSPS, the average power dissipated during each cycle is (6.4/20) × (6 mW) = 1.92 mW Rev. A | Page 20 of 28 POWER (mW) 04350-0-035 AD7911/AD7921 SERIAL INTERFACE Figure 30 and Figure 31 show the detailed timing diagrams for If the rising edge of CS occurs before 14 SCLKs have elapsed, serial interfacing to the AD7921 and AD7911, respectively. The then the conversion is terminated and the DOUT line goes back serial clock provides the conversion clock and also controls the into three-state. If 16 SCLKs are considered in the cycle, DOUT transfer of information from the AD7911/AD7921 during returns to three-state on the 16th SCLK falling edge, as shown conversion. in Figure 31. CS The signal initiates the data transfer and conversion process. CS going low clocks out the first leading zero to be read in by CS The falling edge of puts the track-and-hold into hold mode, the microcontroller or DSP. The remaining data is then clocked takes the bus out of three-state, the analog input is sampled at out by subsequent SCLK falling edges beginning with the this point, and the conversion is initiated. second leading zero. Therefore, the first falling clock edge on the serial clock has the first leading zero provided and also For the AD7921, the conversion requires 16 SCLK cycles to clocks out the second leading zero. The final bit in the data complete. Once 13 SCLK falling edges have elapsed, the track- transfer is valid on the 16th falling edge, having been clocked and-hold goes back into track on the next SCLK rising edge, as out on the previous (15th) falling edge. shown in Figure 30 at Point B. On the 16th SCLK falling edge, the DOUT line goes back into three-state. If the rising edge of In applications with a slower SCLK, it is possible to read in data CS on each SCLK rising edge. In that case, the first falling edge of occurs before 16 SCLKs have elapsed, then the conversion is SCLK clocks out the second leading zero and it can be read in terminated and the DOUT line goes back into three-state. the first rising edge. However, the first leading zero that is Otherwise, DOUT returns to three-state on the 16th SCLK clocked out when CS goes low is missed, unless it is not read in falling edge, as shown in Figure 30. Sixteen serial clock cycles are required to perform the conversion process and to access the first falling edge. The 15th falling edge of SCLK clocks out data from the AD7921. the last bit and it can be read in the 15th rising SCLK edge. For the AD7911, the conversion requires 14 SCLK cycles to CS CS If goes low just after the SCLK falling edge has elapsed, complete. Once 13 SCLK falling edges have elapsed, the track- clocks out the first leading zero as before and it can be read in and-hold goes back into track on the next SCLK rising edge, as the SCLK rising edge. The next SCLK falling edge clocks out shown in Figure 31 at Point B. the second leading zero and it can be read in the following rising edge. t 1 CS t CONVERT t 2 t B 6 SCLK 12 34 5 13 14 15 16 t t 5 7 t 10 t t 3 4 t QUIET Z ZERO CHN X DB11 DB10 DB2 DB1 DB0 DOUT THREE-STATE THREE-STATE t t 8 9 DIN X X CHN X X X X X X Figure 30. AD7921 Serial Interface Timing Diagram t 1 CS t CONVERT t 2 t B 6 SCLK 12 34 5 13 14 15 16 t t 5 7 t 10 t t 3 4 t QUIET Z ZERO CHN X DB9 DB8 DB0 ZERO ZERO DOUT THREE-STATE THREE-STATE TWO TRAILING ZEROS t t 8 9 DIN X X CHN X X X X X X Figure 31. AD7911 Serial Interface Timing Diagram Rev. A | Page 21 of 28 04350-0-030 04350-0-029 AD7911/AD7921 MICROPROCESSOR INTERFACING AD7911/AD7921 to ADSP-218x The serial interface on the AD7911/AD7921 allows the parts to The ADSP-218x family of DSPs are interfaced directly to the be directly connected to a range of microprocessors. This AD7911/AD7921 without any glue logic required. The SPORT section explains how to interface the AD7911/AD7921 with control register should be set up as follows: some of the more common microcontroller and DSP serial interface protocols. TFSW = RFSW = 1, alternate framing AD7911/AD7921 to TMS320C541 Interface INVRFS = INVTFS = 1, active low frame signal The serial interface on the TMS320C541 uses a continuous DTYPE = 00, right-justify data serial clock and frame synchronization signals to synchronize ISCLK = 1, internal serial clock the data transfer operations with peripheral devices like the TFSR = RFSR = 1, frame every word CS IRFS = 0, set up RFS as an input AD7911/AD7921. The input allows easy interfacing between ITFS = 1, set up TFS as an output the TMS320C541 and the AD7911/AD7921 without any glue SLEN = 1111, 16 bits for the AD7921 logic required. The serial port of the TMS320C541 is set up to SLEN = 1101, 14 bits for the AD7911 operate in burst mode (FSM = 1 in the serial port control register, SPC) with the internal serial clock CLKX (MCM = 1 in To implement the power-down mode, SLEN should be set to the SPC register) and the internal frame signal (TXM = 1 in the 0111 to issue an 8-bit SCLK burst. The connection diagram is SPC register); therefore, both pins are configured as outputs. shown in Figure 33. The ADSP-218x has the TFS and RFS of the For the AD7921, the word length should be set to 16 bits (FO = SPORT tied together, with TFS set as an output and RFS set as 0 in the SPC register). This DSP allows frames with a word an input. The DSP operates in alternate framing mode and the length of 16 bits or 8 bits only. In the AD7911, therefore, where SPORT control register is set up as described previously. The 14 bits are required, the FO bit should be set up to 16 bits, and frame synchronization signal generated on the TFS is tied to CS 16 SCLKs are needed. For the AD7911, two trailing zeros are and, as with all signal processing applications, equidistant clocked out in the last two clock cycles. sampling is necessary. However, in this example, the timer The values in the SPC register are as follows: interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling might not be FO = 0 achieved. FSM = 1 MCM = 1 ADSP-218x* AD7911/ AD7921* TXM = 1 SCLK SCLK DR DOUT To implement the power-down mode on the AD7911/AD7921, the format bit, FO, can be set to 1, which sets the word length to DIN DT 8 bits. CS RFS TFS The connection diagram is shown in Figure 32. Note that, for signal processing applications, the frame synchronization signal *ADDITIONAL PINS OMITTED FOR CLARITY from the TMS320C541 must provide equidistant sampling. Figure 33. Interfacing to the ADSP-218x TMS320C541* AD7911/ The timer registers are loaded with a value that provides an AD7921* interrupt at the required sample interval. When an interrupt is SCLK CLKX CLKR received, a value is transmitted with TFS/DT (ADC control DR DOUT word). The TFS is used to control the RFS and, therefore, the DIN DX reading of data. The frequency of the serial clock is set in the CS FSX SCLKDIV register. When the instruction to transmit with TFS FSR is given, that is, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high *ADDITIONAL PINS OMITTED FOR CLARITY again before transmission starts. If the timer and SCLK values Figure 32. Interfacing to the TMS320C541 are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data might be transmitted, or it might wait until the next clock edge. Rev. A | Page 22 of 28 04350-0-031 04350-0-032 AD7911/AD7921 low and a conversion starts. Likewise, by means of the Bits For example, the ADSP-2189 has a master clock frequency of SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the 40 MHz. If the SCLKDIV register is loaded with the value of 3, frame sync signal) and SCK in the serial port are configured as then an SCLK of 5 MHz is obtained, and eight master clock outputs, and the MSB is shifted first. periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the The values are as follows: value 803 (803 + 1 = 804), then 100.5 SCLK occur between interrupts and subsequently between transmit instructions. This MOD = 0 situation results in nonequidistant sampling, because the SYN = 1 transmit instruction occurs on a SCLK edge. If the number of WL2, WL1, WL0 depend on the word length SCLKs between interrupts is a whole integer figure of N, then FSL1 = 0, FSL0 = 0 equidistant sampling is implemented by the DSP. FSP = 1, negative frame sync SCD2 = 1 AD7911/AD7921 to DSP563xx Interface SCKD = 1 The connection diagram in Figure 34 shows how the AD7911/ SHFD = 0 AD7921 can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The Note that, for signal processing applications, the frame SSI is operated in synchronous and normal mode (SYN = 1 and synchronization signal from the DSP563xx must provide MOD = 0 in the Control Register B, CRB) with internally equidistant sampling. generated word frame sync for both Tx and Rx (Bits FSL1 = 0 DSP563xx* AD7911/ and FSL0 = 0 in the CRB). Set the word length in the Control AD7921* Register A (CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and SCLK SCK WL0 = 0 for the AD7921. This DSP does not offer the option DOUT SRD for a 14-bit word length, so the AD7911 word length is set up to 16 bits like the AD7921. For the AD7911, the conversion DIN STD process uses 16 SCLK cycles, with the last two clock periods CS SC2 clocking out two trailing zeros to fill the 16-bit word. *ADDITIONAL PINS OMITTED FOR CLARITY To implement the power-down mode on the AD7911/AD7921, the word length can be changed to 8 bits by setting Bits Figure 34. Interfacing to the DSP563xx WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the CRB register can be set to 1, which means that the frame goes Rev. A | Page 23 of 28 04350-0-033 AD7911/AD7921 APPLICATION HINTS GROUNDING AND LAYOUT digital ground to avoid radiating noise to other sections of the The printed circuit board that houses the AD7911/AD7921 board, and clock signals should never be run near the analog should be designed such that the analog and digital sections are inputs. Avoid crossover of digital and analog signals. Traces on separated and confined to certain areas of the board. This opposite sides of the board should run at right angles to each facilitates the use of ground planes that can be separated easily. other to reduce the effects of feedthrough through the board. A A minimum etch technique is generally best for ground planes, microstrip technique is by far the best, but is not always possible because it gives the best shielding. Digital and analog ground with a double-sided board. In this technique, the component planes should be joined at only one place. If the AD7911/ side of the board is dedicated to ground planes, while signals are AD7921 is in a system where multiple devices require an placed on the solder side. AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be Good decoupling is also very important. The analog supply established as close as possible to the AD7911/AD7921. should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best performance from Avoid running digital lines under the device, because these these decoupling components, the user should endeavor to keep couple noise onto the die. The analog ground plane should be the distance between the decoupling capacitor and the VDD and allowed to run under the AD7911/AD7921 to avoid noise GND pins to a minimum with short track lengths connecting coupling. The power supply lines to the AD7911/AD7921 the respective pins. should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with Rev. A | Page 24 of 28 AD7911/AD7921 OUTLINE DIMENSIONS 3.20 2.90 BSC 3.00 2.80 8 7 6 5 8 5 5.15 1.60 BSC 2.80 BSC 3.20 4.90 13 2 4 3.00 4.65 1 2.80 4 PIN 1 INDICATOR 0.65 BSC PIN 1 IDENTIFIER 1.95 * 0.90 BSC 0.65 BSC 0.87 0.84 0.95 15° MAX * 0.85 1.10 MAX 1.00 MAX 0.20 0.08 0.75 0.60 0.80 8° 0.38 0.45 0.15 0.23 6° 0.10 MAX 0.55 4° 0.40 0.22 SEATING 0.30 0.05 0.09 0° 0.40 0.25 0° PLANE COPLANARITY 0.10 * COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 36. 8-Lead Thin Small Outline Transistor Package [TSOT] Figure 35. 8-Lead Mini Small Outline Package [MSOP] (UJ-8) (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters ORDERING GUIDE Temperature Linearity Package Package 1 2 Model Range Error (LSB) Description Option Branding AD7911ARMZ −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARMZ-REEL −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARM-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARMZ-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911AUJZ-R2 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 #C1J AD7911AUJZ-REEL7 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 #C1J AD7921ARMZ −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921ARMZ-REEL −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921ARMZ-REEL7 −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921AUJZ-R2 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 #C1K AD7921AUJZ-REEL7 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 #C1K 1 Z = RoHS Compliant Part. 2 Linearity error here refers to integral nonlinearity. Rev. A | Page 25 of 28 10-07-2009-B AD7911/AD7921 NOTES Rev. A | Page 26 of 28 AD7911/AD7921 NOTES Rev. A | Page 27 of 28 AD7911/AD7921 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04350–0–5/11(A) Rev. A | Page 28 of 28