ANALOG DEVICES AD7899

5 V Single Supply a 14-Bit 400 kSPS ADC AD7899 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast (2.2�s) 14-Bit ADC V V AVDD REF DRIVE 400 kSPS Throughput Rate 0.3�s Track/Hold Acquisition Time 6k� 2.5V STBY Single Supply Operation REFERENCE AD7899 Selection of Input Ranges: �10 V, �5 V and �2.5 V + 0 V to 2.5 V and 0 V to 5 V – RD High-Speed Parallel Interface which Also Allows Interfacing to 3 V Processors TRACK/HOLD DB13 Low Power, 80 mW Typ V INA SIGNAL OUTPUT 14-BIT Power-Saving Mode, 20�W Typ SCALING LATCH ADC V INB DB0 Overvoltage Protection on Analog Inputs Power-Down Mode via STBY Pin CS CONVERSION INT/EXT INT BUSY/EOC CONTROL CLOCK CLOCK SELECT LOGIC CONVST CLKIN GND OPGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7899 is a fast, low-power, 14-bit A/D converter that 1. The AD7899 features a fast (2.2 µs) ADC allowing through- operates from a single 5 V supply. The part contains a 2.2 µs put rates of up to 400 kSPS. successive-approximation ADC, a track/hold amplifier, 2.5 V 2. The AD7899 operates from a single 5 V supply and con- reference, on-chip clock oscillator, signal conditioning circuitry, sumes only 80 mW typ making it ideal for low power and and a high-speed parallel interface. The part accepts analog input portable applications. ranges of ±10 V, ±5 V, ±2.5 V, 0 V to 2.5 V, and 0 V to 5 V. 3. The part offers a high-speed parallel interface. The interface Overvoltage protection on the analog input for the part allows can operate in 3 V and 5 V mode allowing for easy connec- the input voltage to be exceeded without damaging the parts. tion to 3 V or 5 V microprocessors, microcontrollers, and Speed of conversion can be controlled either by an internally digital signal processors. trimmed clock oscillator or by an external clock. 4. The part is offered in three versions with different analog A conversion start signal (CONVST) places the track/hold into input ranges. The AD7899-1 offers the standard industrial hold mode and initiates conversion. The BUSY/EOC signal ranges of ±10 V and ±5 V; the AD7899-2 offers a unipolar indicates the end of the conversion. range of 0 V to 2.5 or 0 V to 5 V, and the AD7899-3 has an Data is read from the part via a 14-bit parallel data bus using the input range of ±2.5 V. standard CS and RD signals. Maximum throughput for the AD7899 is 400 kSPS. The AD7899 is available in a 28-lead SOIC and SSOP packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 (V = 5 V � 5%, AGND = DGND = 0 V, V = Internal. Clock = Internal, all specifications DD REF T to T and valid for V = 3 V � 5% and 5 V � 5% unless otherwise noted.) AD7899–SPECIFICATIONS MIN MAX DRIVE ABS 1 1 1 Parameter Version Version Version Unit Test Conditions/Comments SAMPLE AND HOLD –0.1 dB Full Power Bandwidth 500 500 500 kHz typ –3 dB Full Power Bandwidth 4.5 4.5 4.5 MHz typ Aperture Delay 20 20 20 ns max Aperture Jitter 25 25 25 ps typ 2 DYNAMIC PERFORMANCE f = 100 kHz, f = 400 kSPS IN S AD7899-1 Signal to (Noise + Distortion) 3 Ratio @ 25�C 78 78 78 dB min T to T 78 78 77 dB min MIN MAX 3 Total Harmonic Distortion –84 –84 –82 dB max 3 Peak Harmonic or Spurious Noise –86 –86 –85 dB max AD7899-2 Signal to (Noise + Distortion) 3 Ratio @ 25�C 78 dB min T to T 77 dB min MIN MAX 3 Total Harmonic Distortion –82 dB max 3 Peak Harmonic or Spurious Noise –82 dB max AD7899-3 Signal to (Noise + Distortion) 3 Ratio @ 25�C 78 78 dB min T to T 77 77 dB min MIN MAX 3 Total Harmonic Distortion –84 –84 dB max 3 Peak Harmonic or Spurious Noise –86 –86 dB max 3 Intermodulation Distortion fa = 49 kHz, fb = 50 kHz 2nd Order Terms –89 –89 –89 dB typ 3rd Order Terms –89 –89 –89 dB typ DC ACCURACY Resolution 14 14 14 Bits 3 Relative Accuracy (INL) ± 2 ±1.5 ±2 LSB max 3 Differential Nonlinearity (DNL) ± 1 ± 1 ±1 LSB max No Missing Codes Guaranteed AD7899-1 Input Voltage Range ±5, ±10 ±5, ±10 Volts Input Current 0.8, 0.8 0.8, 0.8 mA max V = –5 V and –10 V Respectively IN 3 Positive Gain Error ±10 ± 8 ±12 LSB max 3 Negative Gain Error ±10 ± 8 ±12 LSB max Bipolar Zero Error ±12 ± 8 ±12 LSB max AD7899-2 Input Voltage Range 0 to 2.5 Volts 0 to 5 Input Current 0.4, 800 µA max V = 2.5 V, V = 5 V IN IN 3 Positive Gain Error ±14 LSB max 3 Offset Error ±10 LSB max AD7899-3 Input Voltage Range ±2.5 ±2.5 Volts Input Current 0.8 0.8 mA max V = –2.5 V IN 3 Positive Gain Error ±14 ±12 LSB max 3 Negative Gain Error ±14 ±12 LSB max Bipolar Zero Error ±14 ±12 LSB max REFERENCE INPUT/OUTPUT V IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V /V 2.5 V ± 5% REF MIN MAX 4 V IN Input Capacitance 10 10 10 pF max REF V OUT Output Voltage 2.5 2.5 2.5 V nom REF V OUT Error @ 25�C ±10 ±10 ±10 mV max REF V OUT Error T to T ±20 ±20 ±25 mV max REF MIN MAX V OUT Temperature Coefficient 25 25 25 ppm/�C typ REF V OUT Output Impedance 6 6 6 kΩ typ See Reference Section REF –2– REV. A AD7899 ABS 1 1 1 Parameter Version Version Version Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, V V /2 + 0.4 V /2 + 0.4 V /2 + 0.4 V min V = 5 V ± 5% INH DRIVE DRIVE DRIVE DD Input Low Voltage, V V /2 – 0.4 V /2 – 0.4 V /2 – 0.4 V max V = 5 V ± 5% INL DRIVE DRIVE DRIVE DD Input Current, I ±10 ±10 ±10 µA max IN 4 Input Capacitance, C 10 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V – 0.4 V – 0.4 V – 0.4 V min I = 400 µA OH DRIVE DRIVE DRIVE SOURCE Output Low Voltage, V 0.4 0.4 0.4 V max I = 1.6 mA OL SINK DB13–DB0 High Impedance Leakage Current ±10 ±10 ±10 µA max 4 Capacitance 10 10 10 pF max Output Coding AD7899-1, AD7899-3 Two’s Complement AD7899-2 Straight (Natural) Binary CONVERSION RATE Conversion Time 2.2 2.2 2.2 µs max 2, 3 Track/Hold Acquisition Time 0.3 0.3 0.3 µs max Throughput Time 400 400 400 kSPS max POWER REQUIREMENTS V 5 5 5 V nom DD I DD Normal Mode 25 25 25 mA max Typically 16 mA Standby Mode 20 20 20 µA max (5 µA typ) Logic Inputs = 0 V or V DD Power Dissipation Normal Mode 125 125 125 mW max Typically 80 mW, V = 5 V DD Standby Mode 100 100 125 µW max NOTES 1 Temperature Ranges are as follows : A, B Versions: –40�C to +85�C. S Version: –55°C to +125°C. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Sample tested @ 25°C to ensure compliance. Specifications subject to change without notice. REV. A –3– AD7899 1, 2 (V = 5 V � 5%, AGND = DGND = 0 V, V = Internal, Clock = Internal; All specifications T TIMING CHARACTERISTICS DD REF MIN to T and valid for V = 3 V � 5% and 5 V � 5% unless otherwise noted.) MAX DRIVE A, B and S Parameter Versions Unit Test Conditions/Comments t 2.2 µs max Conversion Time, Internal Clock CONV 2.46 µs max CLKIN = 6.5 MHz t 0.3 µs max Acquisition Time ACQ t 120 ns min EOC Pulsewidth EOC 180 ns max 5 t – External V 2 µs max STBY Rising Edge to CONVST Rising Edge WAKE-UP REF (See Standby Mode Operation) t 35 ns min CONVST Pulsewidth 1 t 70 ns min CONVST Rising Edge to BUSY Rising Edge 2 Read Operation t 0 ns min CS to RD Setup Time 3 t 0 ns min CS to RD Hold Time 4 t 35 ns min Read Pulsewidth 5 3 t 35 ns max Data Access Time after Falling Edge of RD, V = 5 V 6 DRIVE 40 ns max Data Access Time after Falling Edge of RD, V = 3 V DRIVE 4 t 5 ns min Bus Relinquish Time after Rising Edge of RD 7 30 ns max t 0 ns min BUSY Falling Edge to RD Delay 8 External Clock t 0 ns min CLKIN to CONVST Rising Edge Setup Time 9 t 20 ns min CLKIN to CONVST Rising Edge Hold Time 10 t 100 ns min CONVST Rising Edge to CLK Falling Edge 11 NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V ) and timed from a voltage level of V /2. DRIVE DRIVE 2 See Figures 5, 6, 7, and 8. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5 Refer to the Standby Mode Operation section. Specifications subject to change without notice. 1.6mA TO OUTPUT 1.6V PIN 50pF 400�A Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. A AD7899 ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW (T = 25°C unless otherwise noted) A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W JA Lead Temperature, Soldering V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . 215°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . 220°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . V + 0.3 V DRIVE DD SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW Analog Input Voltage to AGND θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W JA AD7899-1 (±10 V Range) . . . . . . . . . . . . . . . . . . . . ±18 V Lead Temperature, Soldering AD7899-1 (±5 V Range) . . . . . . . . . . . . . . . –9 V to +18 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . 215°C AD7899-2 . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +18 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C AD7899-3 . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +18 V Reference Input Voltage to AGND . . . –0.3 V to V + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- DD nent damage to the device. This is a stress rating only; functional operation of the Digital Input Voltage to DGND . . . . . –0.3 V to V + 0.3 V DD device at these or any other conditions above those listed in the operational Digital Output Voltage to DGND . . . . –0.3 V to V + 0.3 V DD sections of this specification is not implied. Exposure to absolute maximum rating Operating Temperature Range conditions for extended periods may affect device reliability. Commercial (A, B Version) . . . . . . . . . . . –40°C to +85°C Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7899 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Relative Temperature Package Package Model Input Ranges Accuracy Range Description Option AD7899AR-1 ±5V, ±10 V ±2 LSB –40�C to +85�C Small Outline R-28 AD7899BR-1 ±5V, ±10 V ±1.5 LSB –40�C to +85�C Small Outline R-28 AD7899SR-1 ±5V, ±10 V ±2 LSB –55�C to +125�C Small Outline R-28 AD7899AR-2 0 V to 5 V, 0 V to 2.5 V ±2 LSB –40�C to +85�C Small Outline R-28 AD7899AR-3 ±2.5 V ±2 LSB –40�C to +85�C Small Outline R-28 AD7899BR-3 ±2.5 V ±1.5 LSB –40�C to +85�C Small Outline R-28 AD7899ARS-1 ±5V, ±10 V ±2 LSB –40�C to +85�C Shrink Small Outline RS-28 AD7899ARS-2 0 V to 5 V, 0 V to 2.5 V ±2 LSB –40�C to +85�C Shrink Small Outline RS-28 AD7899ARS-3 ±2.5 V ±2 LSB –40�C to +85�C Shrink Small Outline RS-28 REV. A –5– AD7899 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1V Reference Input/Output. This pin is provides access to the internal reference (2.5 V ± 20 mV) and REF also allows the internal reference to be overdriven by an external reference source (2.5 V ± 5%). A 0.1 µF decoupling capacitor should be connected between this pin and GND. 2, 6 GND Ground Pin. This pin should be connected to the system’s analog groundplane. 3, 4 V , V Analog Inputs. See Analog Input Section. INB INA 5V Positive Supply Voltage, 5.0 V ± 5%. DD 7–13 DB13–DB7 Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs. 14 OPGND Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/EOC. It should be connected to the system’s analog ground plane. 15 V This pin provides the positive supply voltage for the digital inputs and outputs. It is normally tied to V DRIVE DD but may also be powered by a 3 V ± 10% supply which allows the inputs and outputs to be interfaced to 3 V processors and DSPs. V should be decoupled with a 0.1 µF capacitor to GND. DRIVE 16–22 DB6–DB0 Data Bit 6 to Data Bit 0. Three-state Outputs. 23 BUSY/EOC BUSY/EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion has finished. The function of the BUSY/EOC is determined by the state of CONVST at the end of con- version. See the Timing and Control Section. 24 RD Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs. 25 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 26 CONVST Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode and starts conversion. 27 CLKIN Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the conversion rate of the AD7899. If the CLKIN input is high on the rising edge of CONVST an externally applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of CONVST the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required. 28 STBY Standby Mode Input. Logic input which is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. PIN CONFIGURATION SOIC/SSOP V 1 28 REF STBY 2 27 CLKIN GND 3 26 V CONVST INB 4 25 V CS INA V 5 24 RD DD 6 23 GND BUSY/EOC AD7899 DB13 7 22 DB0 TOP VIEW (Not to Scale) DB12 8 21 DB1 DB11 9 20 DB2 DB10 10 19 DB3 DB9 11 18 DB4 DB8 12 17 DB5 DB7 13 16 DB6 14 15 V OPGND DRIVE –6– REV. A AD7899 TERMINOLOGY and third order terms are specified separately. The calculation Signal to (Noise + Distortion) Ratio of the intermodulation distortion is as per the THD speci- This is the measured ratio of signal to (noise + distortion) at the fication where it is the ratio of the rms sum of the individual output of the A/D converter. The signal is the rms amplitude of distortion products to the rms amplitude of the fundamental the fundamental. Noise is the rms sum of all nonfundamental expressed in dBs. signals up to half the sampling frequency (f /2), excluding dc. S Differential Nonlinearity The ratio is dependent upon the number of quantization levels This is the difference between the measured and the ideal in the digitization process; the more levels, the smaller the quan- 1 LSB change between any two adjacent codes in the ADC. tization noise. The theoretical signal to (noise + distortion) ratio Positive Gain Error (AD7899-1, AD7899-3) for an ideal N-bit converter with a sine wave input is given by: This is the deviation of the last code transition (01 . . . 110 to Signal to (Noise + Distortion) = (6.02N + 1.76) dB 01 . . . 111) from the ideal 4 × V – 3/2 LSB (AD7899 at REF Thus for a 14-bit converter, this is 86.04 dB. ±10 V), 2 × V – 3/2 LSB (AD7899 at ± 5 V range) or V REF REF – 3/2 LSB (AD7899 at ±2.5 V range) after the Bipolar Offset Total Harmonic Distortion Error has been adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7899 it is defined Positive Gain Error (AD7899-2) This is the deviation of the last code transition (11 . . . 110 to 2 2 2 2 2 VVV ++ +V+V 2 3 4 5 6 11 . . . 111) from the ideal 2 × V – 3/2 LSB (AD7899 at REF THD (dB) = 20 log as: ±10 V), 2 × V – 3/2 LSB (AD7899 at 0 V to 5 V range) or V REF 1 V – 3/2 LSB (AD7899 at 0 V to 2.5 V range) after the Uni- REF where V is the rms amplitude of the fundamental and V , V , 1 2 3 polar Offset Error has been adjusted out. V , and V are the rms amplitudes of the second through the 4 5 Unipolar Offset Error (AD7899-2) fifth harmonics. This is the deviation of the first code transition (00 . . . 00 to Peak Harmonic or Spurious Noise 00 . . . 01) from the ideal AGND +1/2 LSB Peak harmonic or spurious noise is defined as the ratio of the Bipolar Zero Error (AD7899-1, AD7899-2) rms value of the next largest component in the ADC output This is the deviation of the midscale transition (all 0s to all 1s) spectrum (up to f /2 and excluding dc) to the rms value of the S from the ideal AGND – 1/2 LSB. fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts Negative Gain Error (AD7899-1, AD7899-3) where the harmonics are buried in the noise floor, it will be a This is the deviation of the first code transition (10 . . . 000 to noise peak. 10 . . . 001) from the ideal –4 × V + 1/2 LSB (AD7899 at REF ±10 V), –2 × V + 1/2 LSB (AD7899 at ±5 V range) or –V REF REF Intermodulation Distortion + 1/2 LSB (AD7899 at ±2.5 V range) after Bipolar Zero Error With inputs consisting of sine waves at two frequencies, fa and has been adjusted out. fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where Track/Hold Acquisition Time m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which Track/Hold acquisition time is the time required for the output neither m nor n are equal to zero. For example, the second order of the track/hold amplifier to reach its final value, within ±1/2 LSB, terms include (fa + fb) and (fa – fb), while the third order terms after the end of conversion (the point at which the track/hold include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected The AD7899 is tested using two input frequencies. In this case, the V input of the AD7899. It means that the user must wait INA/VINB second and third order terms are of different significance. The for the duration of the track/hold acquisition time after the end second order terms are usually distanced in frequency from the of conversion or after a step input change to V /V before INA INB original sine waves while the third order terms are usually at a starting another conversion, to ensure that the part operates to frequency close to the input frequencies. As a result, the second specification. REV. A –7– AD7899 CONVERTER DETAILS external CONVST signal and the track/hold actually going into The AD7899 is a high-speed, low-power, 14-bit A/D converter hold) is typically 15 ns and, more importantly, is well matched that operates from a single 5 V supply. The part contains a from device to device. It allows multiple AD7899s to sample 2.2 µs successive-approximation ADC, track/hold amplifier, an more than one channel simultaneously. At the end of a conversion, internal 2.5 V reference and a high-speed parallel interface. The the part returns to its tracking mode. The acquisition time of part accepts an analog input range of ±10 V or ±5 V (AD7899-1), the track/hold amplifier begins at this point. 0 V to 2.5 V or 0 V to 5 V (AD7899-2) and ±2.5 V (AD7899-3). Reference Section Overvoltage protection on the analog inputs for the part allows The AD7899 contains a single reference pin, labelled V , REF the input voltage to go to ±18 V (AD7899-1 with ±10 V input which either provides access to the part’s own 2.5 V reference or range), –9 V to +18 V (AD7899-1 with ±5 V input range), –1 V allows an external 2.5 V reference to be connected to provide to +18 V (AD7899-2) and –4 V to +18 V (AD7899-3) without the reference source for the part. The part is specified with a causing damage. 2.5 V reference voltage. A conversion is initiated on the AD7899 by pulsing the CONVST To use the internal reference as the reference source for the input. On the rising edge of CONVST, the on-chip track/hold is AD7899, simply connect a 0.1 µF capacitor from the V pin REF placed into hold and the conversion is started. The BUSY/EOC to AGND. The voltage that appears at this pin is internally output signal is triggered high on the rising edge of CONVST buffered before being applied to the ADC. If this reference is and will remain high for the duration of the conversion sequence. required for use external to the AD7899, it should be buffered, The conversion clock for the part is generated internally using a as the part has a FET switch in series with the reference output laser-trimmed clock oscillator circuit. There is also the option of resulting in a source impedance for this output of 6 kΩ nominal. using an external clock. An external noncontinuous clock is applied The tolerance on the internal reference is ±10 mV at 25°C with to the CLKIN pin. If, on the rising edge of CONVST, this input a typical temperature coefficient of 25 ppm/°C and a maximum is high, the external clock will be used. The external clock should error over temperature of ±20 mV. not start until 100 ns after the rising edge of CONVST. The If the application requires a reference with a tighter tolerance or optimum throughput is obtained by using the internally gener- the AD7899 needs to be used with a system reference, the user ated clock—see Using an External Clock. The BUSY/EOC signal has the option of connecting an external reference to this V REF indicates the end of the conversion, and at this time the Track and pin. The external reference will effectively overdrive the internal Hold returns to tracking mode. The conversion results can be reference and thus provide the reference source for the ADC. read at the end of the conversion (indicated by BUSY/EOC The reference input is buffered before being applied to the ADC going low) via a 14-bit parallel data bus with standard CS and RD with the maximum input current of ±100 µA. Suitable reference signals—see Timing and Control. sources for the AD7899 include the AD680, AD780, REF192, Conversion time for the AD7899 is 2.2 µs and the track/hold and REF43 precision 2.5 V references. acquisition time is 0.3 µs. To obtain optimum performance from Analog Input Section the part, the read operation should not occur during a conversion The AD7899 is offered as three part types, the AD7899-1 where or during the 150 ns prior to the next CONVST rising edge. the input can be configured for ±10 V or a ±5 V input voltage This allows the part to operate at throughput rates up to 400 kHz range, the AD7899-2 where the input can be configured for 0 V and achieve data sheet specifications. to 5 V or a 0 V to 2.5 V input voltage range and the AD7899-3 which handles input voltage range ±2.5 V. The amount of current CIRCUIT DESCRIPTION flowing into the analog input will depend on the analog input Track/Hold Section range and the analog input voltage. The maximum current flows The track/hold amplifier on the AD7899 allows the ADCs to when negative full-scale is applied. accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater AD7899-1 than the Nyquist rate of the ADC even when the ADC is oper- Figure 2 shows the analog input section of the AD7899-1. The ated at its maximum throughput rate of 400 kSPS (i.e., the input can be configured for ±5 V or ±10 V operation on the track/hold can handle input frequencies in excess of 200 kHz). AD7899-1. For ±5 V operation, the V and V inputs are INA INB tied together and the input voltage is applied to both. For ±10 V The track/hold amplifier’s acquire input signals to 14-bit operation, the V input is tied to AGND and the input voltage INB accuracy in less than 300 ns The operation of the track/hold is is applied to the V input. The V and V inputs are sym- INA INA INB essentially transparent to the user. The track/hold amplifier metrical and fully interchangeable. samples the input channel on the rising edge of CONVST. The aperture time for the track/hold (i.e., the delay time between the –8– REV. A AD7899 AD7899-2 AD7899-1 Figure 3 shows the analog input section of the AD7899-2. Each 2.5V input can be configured for 0 V to 5 V operation or 0 V to 2.5 V REFERENCE operation. For 0 V to 5 V operation, the V input is tied to INB GND and the input voltage is applied to the V input. For INA 6k� 0 V to 2.5 V operation, the V and V inputs are tied together INA INB TO ADC and the input voltage is applied to both. The V and V INA INB REFERENCE V REF CIRCUITRY inputs are symmetrical and fully interchangeable. R1 For the AD7899-2, R1 = 4 kΩ and R2 = 4 kΩ. Once again, the R2 TO INTERNAL designed code transitions occur on successive integer LSB values. V INA COMPARATOR Output coding is straight (natural) binary with 1 LSB = FSR/ TRACK/HOLD 16384 = 2.5 V/16384 = 0.153 mV, and 5 V/16384 = 0.305 mV, R3 for the 0 to 2.5 V and the 0 to 5 V options respectively. Table V INB II shows the ideal input and output transfer function for the R4 AD7899-2. GND AD7899-2 Figure 2. AD7899-1 Analog Input Structure 2.5V REFERENCE For the AD7899-1, R1 = 4 kΩ, R2 = 16 kΩ, R3 = 16 kΩ and R4 = 8 kΩ. The resistor input stage is followed by the high 6k� input impedance stage of the track/hold amplifier. TO ADC The designed code transitions take place midway between suc- REFERENCE V REF CIRCUITRY cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. For the ±5 V range, 1 LSB = 10 V/16384 = 610.4 µV. For the ±10 V R1 TO INTERNAL V INA COMPARATOR range, 1 LSB = 20 V/16384 = 1.22 mV. Output coding is TRACK/HOLD two’s complement binary with 1 LSB = FSR/16384. The ideal input/output transfer function for the AD7899-1 is shown in R2 V INB Table I. Table I. Ideal Input/Output Code Table for the AD7899-1 Figure 3. AD7899-2 Analog Input Structure Digital Output 1 Analog Input Code Transition Table II. Ideal Input/Output Code Table for the AD7899-2 2 +FSR/2 – 3/2 LSB 011 . . . 110 to 011 . . . 111 +FSR/2 – 5/2 LSB 011 . . . 101 to 011 . . . 110 Digital Output 1 +FSR/2 – 7/2 LSB 011 . . . 100 to 011 . . . 101 Analog Input Code Transition 2 +FSR – 3/2 LSB 111 . . . 110 to 111 . . . 111 GND + 3/2 LSB 000 . . . 001 to 000 . . . 010 +FSR – 5/2 LSB 111 . . . 101 to 111 . . . 110 GND + 1/2 LSB 000 . . . 000 to 000 . . . 001 +FSR – 7/2 LSB 111 . . . 100 to 111 . . . 101 GND – 1/2 LSB 111 . . . 111 to 000 . . . 000 GND – 3/2 LSB 111 . . . 110 to 111 . . . 111 GND + 5/2 LSB 000 . . . 010 to 000 . . . 011 GND + 3/2 LSB 000 . . . 001 to 000 . . . 010 –FSR/2 + 5/2 LSB 100 . . . 010 to 100 . . . 011 GND + 1/2 LSB 000 . . . 000 to 000 . . . 001 –FSR/2 + 3/2 LSB 100 . . . 001 to 100 . . . 010 –FSR/2 + 1/2 LSB 100 . . . 000 to 100 . . . 001 NOTES 1 FSR is Full-Scale Range and is 0 to 2.5 V and 0 to 5 V for AD7899-2 with V REF NOTES = 2.5 V. 1 FSR is full-scale range and is 20 V for the ±10 V range and 10 V for the ±5 V 2 1 LSB = FSR/16384 and is 0.153 mV (0 to 2.5 V) and 0.305 mV (0 to 5 V) for range, with V = 2.5 V. REF AD7899-2 with V = 2.5 V. 2 REF 1 LSB = FSR/16384 = 1.22 mV (±10 V – AD7899-1) and 610.4 µV (±5 V – AD7899-1) with V = 2.5 V. REF REV. A –9– AD7899 AD7899-3 TIMING AND CONTROL Figure 4 shows the analog input section of the AD7899-3. The Starting a Conversion analog input range is ±2.5 V on the V input. The V input The conversion is initiated by applying a rising edge to the INA INB can be left unconnected but if it is connected to a potential then CONVST signal. This places the track/hold into hold mode and that potential must be GND. starts the conversion. The status of the conversion is indicated by the dual function signal BUSY/EOC. The AD7899 can operate in two conversion modes, EOC (End Of Conversion) mode and AD7899-3 BUSY mode. The operating mode is determined by the state of 2.5V CONVST at the end of the conversion. REFERENCE Selecting a Conversion Clock 6k� The AD7899 has an internal laser trimmed oscillator which can be used to control the conversion process. Alternatively an external TO ADC REFERENCE clock source can be used to control the conversion process. The V REF CIRCUITRY highest external clock frequency allowed is 6.5 MHz. This means R1 a conversion time of 2.46 µs compared to 2.2 µs using the inter- R2 TO INTERNAL V nal clock. However in some instances it may be useful to use an INA COMPARATOR external clock when high throughput rates are not required. For TRACK/HOLD example two or more AD7899s may be synchronized by using the same external clock for all devices. In this way there is no V INB latency between output logic signals due to differences in the frequency of the internal clock oscillators. On the rising edge of CONVST the AD7899 will examine the Figure 4. AD7899-3 Analog Input Structure status of the CLKIN pin. If this pin is low it will use the internal laser trimmed oscillator as the conversion clock. If the CLKIN pin For the AD7899-3, R1 = 4 kΩ and R2 = 4 kΩ. The resistor is high the AD7899 will wait for an external clock to be supplied input stage is followed by the high input impedance stage of the to this pin which will then be used as the conversion clock. The track/hold amplifier. first falling edge of the external clock should not happen for at The designed code transitions take place midway between suc- least 100 ns after the rising edge of CONVST to ensure correct cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs operation. Figure 5 shows how the BUSY/EOC output is synchro- etc.) LSB size is given by the formula, 1 LSB = FSR/16384. nized to the CLKIN signal. Each conversion requires 16 clocks. Output coding is two’s complement binary with 1 LSB = FSR/ The result of the conversion is transferred to the output data 16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer register on the falling edge of the 15th clock cycle. When the function for the AD7899-3 is shown in Table III. internal clock is selected the status of the CLKIN pin is free to change during conversion but the CLKIN setup and hold times Table III. Ideal Input/Output Code Table for the AD7899-3 must be observed in order to ensure that the correct conversion clock is used. The CLKIN pin can also be tied low permanently if Digital Output l the internal conversion clock is to be used. Analog Input Code Transition 2 +FSR/2 – 3/2 LSB 011 . . . 110 to 011 . . . 111 t 9 1 2 3 4 5 6 7 8 9 10 111213 14 1516 +FSR/2 – 5/2 LSB 011 . . . 101 to 011 . . . 110 +FSR/2 – 7/2 LSB 011 . . . 100 to 011 . . . 101 CLKIN t 11 GND + 3/2 LSB 000 . . . 001 to 000 . . . 010 GND + 1/2 LSB 000 . . . 000 to 000 . . . 001 CONVST GND – 1/2 LSB 111 . . . 111 to 000 . . . 000 GND – 3/2 LSB 111 . . . 110 to 111 . . . 111 BUSY/EOC –FSR/2 + 5/2 LSB 100 . . . 010 to 100 . . . 011 –FSR/2 + 3/2 LSB 100 . . . 001 to 100 . . . 010 –FSR/2 + 1/2 LSB 100 . . . 000 to 100 . . . 001 RD NOTES CS 1 FSR is full-scale range is 5 V, with V = 2.5 V REF 2 1 LSB = FSR/16384 = 610.4 µV (±2.5 V – AD7899-3) with V = 2.5 V. REF Figure 5. Using an External Clock –10– REV. A AD7899 t 10 t 9 CLKIN t t 1 ACQ t CONVST EOC QUIET TIME t t 2 8 BUSY/EOC t CONV t 5 RD t t 3 4 CS THREE-STATE THREE-STATE DATA t t 6 7 Figure 6. Conversion Sequence Timing Diagram (EOC Mode) t 10 t 9 CLKIN t t 1 ACQ CONVST t 8 QUIET BUSY/EOC TIME t CONV t 5 RD t t 3 4 CS THREE-STATE THREE-STATE DATA t t 6 7 Figure 7. Conversion Sequence Timing Diagram (BUSY Mode) EOC Mode Continuous Conversion Mode The CONVST signal is normally high. Pulsing the CONVST low When the AD7899 is used with an external clock, connecting will initiate a conversion on its rising edge. The state of the the CLKIN and CONVST signals together will cause the AD7899 CONVST signal is checked at the end of conversion. Since the to continuously perform conversions. As each conversion com- CONVST will be high when this happens the AD7899 BUSY/ pletes the BUSY/EOC pin will pulse low for one clock period EOC pin will take on its EOC function and bring the BUSY/EOC (EOC function) indicating that the conversion result is available. line low for one clock period before returning high again. In this Figure 8 shows the timing and control sequence of the AD7899 mode the EOC can be tied to the RD and CS signals to allow in Continuous Conversion Mode. automatic reading of the conversion result if required. The timing Reading Data from the AD7899 diagram for operation in EOC mode is shown in Figure 6. Data is read from the part via a 14-bit parallel data bus with BUSY Mode standard CS and RD signals. The CS and RD inputs are inter- The CONVST signal is normally low. Pulsing the CONVST nally gated to enable the conversion result onto the data bus. high will initiate a conversion on its rising edge. The state of the The data lines DB0 to DB13 leave their high impedance state CONVST signal is checked at the end of conversion. Since the when both CS and RD are logic low. Therefore CS may be CONVST will be low when this happens the AD7899 BUSY/ permanently tied logic low and the RD signal used to access the EOC pin will take on its BUSY function will bring BUSY/EOC conversion result if required. Figures 6 and 7 show a timing low, indicating that the conversion is complete. BUSY/EOC will specification called “Quiet Time.” This is the amount of time remain low until the next rising edge of CONVST where BUSY/ which should be left after a read operation and before the next EOC returns high. The timing diagram for operation in BUSY conversion is initiated. The quiet time depends heavily on data mode is shown in Figure 7. bus capacitance but a figure of 50 ns to 100 ns is typical, with a worst case figure of 150 ns. REV. A –11– AD7899 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CONVST/ CLKIN EOC START OF NEW CONVERSION CONVERSION (INPUT SAMPLED) COMPLETE Figure 8. Continuous Conversion Mode Standby Mode Operation Signal-to-Noise Ratio (SNR) The AD7899 has a Standby Mode whereby the device can be SNR is the measured signal-to-noise ratio at the output of the placed in a low current consumption mode (5 µA typ). The ADC. The signal is the rms magnitude of the fundamental. AD7899 is placed in Standby by bringing the logic input STBY Noise is the rms sum of all the nonfundamental signals up to low. The AD7899 can be powered again up for normal opera- half the sampling frequency (f /2) excluding dc. SNR is dependent S tion by bringing STBY logic high. The output data buffers are upon the number of quantization levels used in the digitization still operational while the AD7899 is in Standby. This means process; the more levels, the smaller the quantization noise. The the user can still continue to access the conversion results while theoretical signal to noise ratio for a sine wave input is given by the AD7899 is in standby. This feature can be used to reduce SNR = (6.02N + 1.76) dB (1) the average power consumption in a system using low throughput where N is the number of bits. rates. To reduce the average power consumption, the AD7899 can be placed in standby at the end of each conversion sequence Thus for an ideal 14-bit converter, SNR = 86.04 dB. and taken out of standby again prior to the start of the next Figure 9 shows a histogram plot for 8192 conversions of a dc conversion sequence. The time it takes the AD7899 to come out input using the AD7899 with 5 V supply. The analog input was of standby is called the “wake up” time. This wake-up time will set at the center of a code transition. It can be seen that most of limit the maximum throughput rate at which the AD7899 can the codes appear in one output bin, indicating very good noise be operated when powering down between conversions. When performance from the ADC. the AD7899 is used with the internal reference, the reference capacitor will begin to discharge during standby. The voltage 7000 remaining on the capacitor at wake-up time will depend upon the standby time and hence affect the wake-up time. The mini- 6000 mum wake-up time is typically 2 µs. The maximum wake-up time will be when the AD7899 has been in standby long enough 5000 for the reference capacitor to fully discharge. The wake-up time in this case will typically be 15 ms. The AD7899 will wake up in 4000 approximately 1 µs when using an external reference, regardless 3000 of sleep time. When operating the AD7899 in a Standby mode between con- 2000 versions, the power savings can be significant. For example, with a throughput rate of 10 kSPS and an external reference, the 1000 AD7899 will be powered up for 4.2 µs out of every 100 µs (2 µs for wake-up time and 2.2 µs for conversion time). Therefore, the 0 average power consumption drops to 80 mW × 4.2% or approxi- Figure 9. Histogram of 8192 Conversions of a DC Input mately 3.36 mW. The output spectrum from the ADC is evaluated by applying a AD7899 DYNAMIC SPECIFICATIONS sine wave signal of very low distortion to the analog input. A The AD7899 is specified and 100% tested for dynamic perfor- Fast Fourier Transform (FFT) plot is generated from which the mance specifications as well as traditional dc specifications such SNR data can be obtained. Figure 10 shows a typical 4096 point as Integral and Differential Nonlinearity. These ac specifications FFT plot of the AD7899 with an input signal of 100 kHz and a are required for the signal processing applications such as phased sampling frequency of 400 kHz. The SNR obtained from this array sonar, adaptive filters, and spectrum analysis. These appli- graph is 80.5 dB. It should be noted that the harmonics are cations require information on the ADC’s effect on the spectral taken into account when calculating the SNR. content of the input signal. Hence, the parameters for which the AD7899 is specified include SNR, harmonic distortion, inter- modulation distortion, and peak harmonics. These terms are discussed in more detail in the following sections. –12– REV. A AD7899 second and third order terms are specified separately. The cal- 0 culation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the indi- –20 vidual distortion products to the rms amplitude of the fundamental f = 400kHz s f = 100kHz –40 IN expressed in dBs. In this case, the input consists of two, equal SNR = 80.5dB amplitude, low distortion sine waves. Figure 12 shows a typical –60 IMD plot for the AD7899. –80 0 –100 –20 –120 –40 –140 –60 0 50000 100000 150000 200000 FREQUENCY – Hz –80 Figure 10. FFT Plot –100 Effective Number of Bits The formula given in Equation 1 relates the SNR to the number –120 of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number –140 of bits (N). 0 50000 100000 150000 200000 FREQUENCY – Hz SNR − 1.76 Figure 12. IMD Plot N = (2) 6.02 AC Linearity Plots The effective number of bits for a device can be calculated directly The plots in Figure 13 show typical DNL and INL for the from its measured SNR. Figure 11 shows a typical plot of effec- AD7899. tive number of bits versus frequency for an AD7899. 1.00 14 13 –55�C 12 0.50 11 +25�C 10 9 8 +125�C 0 7 6 5 –0.50 4 3 2 1 –1.00 0 2000 0 4000 6000 8000 10000 12000 14000 16000 0 100 1000 10000 ADC – Code INPUT FREQUENCY – kHz 1.00 Figure 11. Effective Numbers of Bits vs. Frequency Intermodulation Distortion 0.50 With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for 0 which neither m nor n are equal to zero. For example, the sec- ond order terms include (fa + fb) and (fa – fb) while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). –0.50 The AD7899 is tested using two input frequencies. In this case the second and third order terms are of different significance. The second order terms are usually distanced in frequency from –1.00 0 2000 4000 6000 8000 10000 12000 14000 16000 the original sine waves while the third order terms are usually at ADC – Code a frequency close to the input frequencies. As a result, the Figure 13. Typical DNL and INL Plots REV. A –13– dB ENOB INL – LSB DNL – LSB dB AD7899 MICROPROCESSOR INTERFACING AD7899–TMS320C5x Interface The high-speed parallel interface of the AD7899 allows easy Figure 15 shows an interface between the AD7899 and the interfacing to most DSPs and microprocessors. The AD7899 TMS320C5x. As with the previous interfaces, conversion can be interface of the AD7899 consists of the data lines (DB0 to DB13), initiated from the TMS320C5x or from an external source and CS, RD, and BUSY/EOC. the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7899 derived from the DS AD7899–ADSP-21xx Interface signal and a decode of the address bus. This maps the AD7899 Figure 14 shows an interface between the AD7899 and the into external data memory. The RD signal from the TMS320 is ADSP-21xx. The CONVST signal can be generated by the used to enable the ADC data onto the data bus. The AD7899 has ADSP-21xx or from some other external source. Figure 14 shows a fast parallel bus so there are no wait state requirements. The the CS being generated by a combination of the DMS signal and following instruction is used to read the conversion results from the address bus of the ADSP-21xx. In this way the AD7899 is the AD7899: mapped into the data memory space of the ADSP-21xx. IN D,ADC The AD7899 BUSY/EOC line provides an interrupt to the ADSP-21xx when the conversion is complete. The conversion where D is Data Memory address and ADC is the AD7899 result can then be read from the AD7899 using a read operation. address. The AD7899 is read using the following instruction MR0 = DM(ADC) TMS320C5x where MR0 is the ADSP-21xx MR0 register and ADC is the A0–A13 ADDRESS AD7899 address. DECODE DS CS ADSP-21xx RD RD V IN A0–A13 ADDRESS DECODE DMS DB0–DB13 D0–D13 AD7899 CS RD RD V IN INTn BUSY/EOC CONVST PA0 DB0–DB13 D8–D21 AD7899 Figure 15. AD7899–TMS320C5x Interface BUSY/EOC IRQn CONVST DT1/F0 Figure 14. AD7899–ADSP-21xx Interface –14– REV. A AD7899 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 14 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) � 45� 0.0926 (2.35) 0.0098 (0.25) 8� 0.0118 (0.30) 0.0500 0.0192 (0.49) SEATING 0� 0.0500 (1.27) 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0040 (0.10) 0.0157 (0.40) BSC 0.0091 (0.23) 28-Lead Shrink Small Outline (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.07 (1.79) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) 0.002 (0.050) PLANE BSC 0.005 (0.127) AD7899–Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edit to Timing page heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to Converter Details section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edit to Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REV. A –15– 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) –16– C01365–0–6/01(A) PRINTED IN U.S.A.