ANALOG DEVICES AD7895

5 V, 12-Bit, Serial 3.8 ms a ADC in 8-Pin Package AD7895 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast 12-Bit ADC with 3.8 ms Conversion Time REF IN V 8-Pin Mini-DlP and SOIC DD Single 5 V Supply Operation AD7895 High Speed, Easy-to-Use, Serial Interface On-Chip Track/Hold Amplifier Selection of Input Ranges TRACK/HOLD 610 V for AD7895-10 62.5 V for AD7895-3 SIGNAL V IN SCALING* 0 V to +2.5 V for AD7895-2 12-BIT ADC High Input Impedance Low Power: 20 mW max 14-Bit Pin Compatible Upgrade (AD7894) OUTPUT CONVST REGISTER GND BUSY SCLK SDATA *AD7895-10, AD7895-3 GENERAL DESCRIPTION The AD7895 is a fast 12-bit ADC that operates from a single +5 V supply and is housed in a small 8-pin mini-DIP and 8-pin SOIC. The part contains a 3.8 μs successive approximation A/D PRODUCT HIGHLIGHTS converter, an on-chip track/hold amplifier, an on-chip clock and 1. Fast, 12-Bit ADC in 8-Pin Package a high speed serial interface. The AD7895 contains a 3.8 μs ADC, a track/hold amplifier, control logic and a high speed serial interface, all in an 8-pin Output data from the AD7895 is provided via a high speed, package. This offers considerable space saving over alterna- serial interface port. This two-wire serial interface has a serial tive solutions. clock input and a serial data output with the external serial clock accessing the serial data from the part. 2. Low Power, Single Supply Operation The AD7895 operates from a single +5 V supply and In addition to the traditional dc accuracy specifications such as consumes only 20 mW. The automatic power-down mode, linearity and full-scale and offset errors, the AD7895 is specified where the part goes into power-down once conversion is for dynamic performance parameters, including harmonic complete and “wakes up” before the next conversion cycle, distortion and signal-to-noise ratio. makes the AD7895 ideal for battery-powered or portable The part accepts an analog input range of ±10 V (AD7895-10), applications. ±2.5 V (AD7895-3), 0 V to 2.5 V (AD7895-2) and operates 3. High Speed Serial Interface from a single +5 V supply, consuming only 20 mW max. The part provides high speed serial data and serial clock lines The AD7895 features a high sampling rate mode and, for low allowing for an easy, two-wire serial interface arrangement. power applications, a proprietary automatic power-down mode where the part automatically goes into power down once conversion is complete and “wakes up” before the next conver- sion cycle. The part is available in a small, 8-pin, 0.3" wide, plastic dual-in- line package (mini-DIP) and in an 8-pin, small outline IC (SOIC). REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1996 (V = +5 V, GND = 0 V, REF IN = +2.5 V. DD AD7895–SPECIFICATIONS All specifications T to T unless otherwise noted) MIN MAX l Parameter A Versions B Versions Units Test Conditions/Comments 2 DYNAMIC PERFORMANCE 3 Signal to (Noise + Distortion) Ratio @ +25°C 70 70 dB min f = 50 kHz Sine Wave, f = 200 kHz IN SAMPLE T to T 70 70 dB min MIN MAX 3 Total Harmonic Distortion (THD) –78 –78 dB max f = 50 kHz Sine Wave, f = 200 kHz, IN SAMPLE Typically –87 dB 3 Peak Harmonic or Spurious Noise –89 –89 dB typ f = 50 kHz Sine Wave, f = 200 kHz IN SAMPLE 3 Intermodulation Distortion (IMD) fa = 9 kHz, fb = 9.5 kHz, f = 200 kHz SAMPLE 2nd Order Terms –87 –87 dB typ 3rd Order Terms –87 –87 dB typ DC ACCURACY Resolution 12 12 Bits Minimum Resolution for which No Missing Codes are Guaranteed 12 12 Bits 3 Relative Accuracy ±1 ±1 LSB max Typically 0.4 LSB 3 Differential Nonlinearity ±1 ±1 LSB max 3 Positive Full-Scale Error ±3 ±2 LSB max AD7895-2 Unipolar Offset Error ±3 ±2 LSB max AD7895-10, AD7895-3 Only 3 Negative Full-Scale Error ±3 ±2 LSB max Bipolar Zero Error ±4 ±3 LSB max ANALOG INPUT AD7895-10 Input Voltage Range ±10 ±10 Volts Input Resistance 24 24 kΩ min AD7895-3 Input Voltage Range ±2.5 ±2.5 Volts Input Resistance 9 9 kΩ min AD7895-2 Input Voltage Range 0 to +2.5 0 to +2.5 Volts Input Current 500 500 nA max REFERENCE INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Current 1 1 μA max 3 Input Capacitance 10 10 pF max LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min V = 5 V ± 5% INH DD Input Low Voltage, V 0.8 0.8 V max V = 5 V ± 5% INL DD Input Current, I ±10 ±10 μA max V = 0 V to V IN IN DD 4 Input Capacitance, C 10 10 pF ax IN LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 V min I = 200 μA OH SOURCE Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK Output Coding AD7895-10, AD7895-3 2s Complement AD7895-2 Straight (Natural) Binary CONVERSION RATE Conversion Time Mode 1 Operation 3.8 3.8 μs max 5 Mode 2 Operation 9.8 9.8 μs max 3 Track/Hold Acquisition Time 0.5 0.5 μs max POWER REQUIREMENTS V +5 +5 V nom ±5% for Specified Performance DD I 4 4 mA max Digital Inputs @ V , V = 5 V ± 5% DD DD DD Power Dissipation 20 20 mW max Typically 16 mW Power-Down Mode I @ +25°C55 μA max Digital Inputs @ GND, V = 5 V ± 5% DD DD T to T 10 10 μA max Digital Inputs @ GND, V = 5 V ± 5% MIN MAX DD Power Dissipation @ +25°C25 25 μW max NOTES 1 Temperature ranges are as follows: A, B Versions: –40°C to +85°C. 2 Applies to Mode 1 operation. See section on “Operating Modes.” 3 See Terminology. 4 Sample tested @ +25°C to ensure compliance. 5 This 9.8 μs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulse width the conversion time is effectively the “wake-up” time plus conversion time hence 9.8 μs. This can be seen from Figure 3. Note that if the CONVST pulse width is greater than 6 μs then the effective conversion time will increase beyond 9.8 μs. Specifications subject to change without notice. REV. 0 –2– AD7895 1, 2 (V = +5 V, GND = 0 V, REF IN = +2.5 V) TIMING CHARACTERISTICS DD Parameter A, B Versions Units Test Conditions/Comments t 40 ns min CONVST Pulse Width 1 2 t 35 ns min SCLK High Pulse Width 2 2 t 35 ns min SCLK Low Pulse Width 3 3 t 60 ns max Data Access Time after Falling Edge of SCLK, V = 5 V ± 5% 4 DD t 10 ns min Data Hold Time after Falling Edge of SCLK 5 4 t 50 ns max Bus Relinquish Time after Falling Edge of SCLK 6 NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.4 V. 2 The SCLK maximum frequency is 15 MHz. Care must be taken when interfacing to account for the data access time, t , and the setup time required for the user's 4 processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See “Serial Interface” section for more information. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time 6 of the part and, as such, is independent of external bus loading capacitances. *Stresses above those listed under “Absolute Maximum Ratings” may cause ABSOLUTE MAXIMUM RATINGS* permanent damage to the device. This is a stress rating only and functional (T = +25°C unless otherwise noted) A operation of the device at these or any other conditions above those listed in the V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V operational sections of this specification is not implied. Exposure to absolute DD maximum rating conditions for extended periods may affect device reliability. Analog Input Voltage to GND AD7895-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V AD7895-2, AD7895-3 . . . . . . . . . . . . . . . . . . . –5 V, +10 V Reference Input Voltage to GND . . . . –0.3 V to V + 0.3 V DD 2.0mA Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V DD Digital Output Voltage to GND . . . . . –0.3 V to V + 0.3 V DD TO OUTPUT +1.6V Operating Temperature Range PIN Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C 50pF Storage Temperature Range . . . . . . . . . . . –65°C to +150°C 2.0mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W JA Figure 1. Load Circuit for Access Time and Bus Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +260°C Relinquish Time SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C ORDERING GUIDE Model Temperature Range Linearity Error (LSB) SNR (dB) Package Option* AD7895AN-2 –40°C to +85°C ±1 LSB 70 dB N-8 AD7895AR-2 –40°C to +85°C ±1 LSB 70 dB SO-8 AD7895BR-2 –40°C to +85°C ±1 LSB 70 dB SO-8 AD7895AN-10 –40°C to +85°C ±1 LSB 70 dB N-8 AD7895AR-10 –40°C to +85°C ±1 LSB 70 dB SO-8 AD7895BR-10 –40°C to +85°C ±1 LSB 70 dB SO-8 AD7895AN-3 –40°C to +125°C ±1 LSB 70 dB N-8 AD7895AR-3 –40°C to +85°C ±1 LSB 70 dB SO-8 *N = Plastic DIP, SO = SOIC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7895 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– AD7895 PIN FUNCTION DESCRIPTION Pin Pin No. Mnemonic Description 1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the refer- ence voltage for the AD7895’s conversion process. The REF IN input is buffered on chip. The nominal ref- erence voltage for correct operation of the AD7895 is +2.5 V. 2V Analog Input Channel. The analog input range is ±10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to IN +2.5 V (AD7895-2). 3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC. 4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7895. A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of the serial data transmission. 5 SDATA Serial Data Output. Serial data from the AD7895 is provided at this output. The serial data is clocked out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is possible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 4). Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data. On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and then is disabled (three-stated). Output data coding is 2s complement for the AD7895-10, AD7895-3 and straight binary for the AD7895-2. 6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the falling edge of CONVST and will return low when the conversion is complete. 7 CONVST Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold mode, and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power- down mode. In this case, the rising edge of CONVST “wakes up” the part. 8V Positive supply voltage, +5 V ± 5%. DD PIN CONFIGURATION DIP and SOIC REF IN 1 8 V DD AD7895 V 2 7 CONVST IN TOP VIEW GND 3 (Not to Scale) 6 BUSY SCLK 4 5 SDATA REV. 0 –4– AD7895 Relative Accuracy TERMINOLOGY Relative accuracy or endpoint nonlinearity is the maximum Signal to (Noise + Distortion) Ratio deviation from a straight line passing through the endpoints of This is the measured ratio of signal to (noise + distortion) at the the ADC transfer function. output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental Differential Nonlinearity signals up to half the sampling frequency (f /2), excluding dc. S This is the difference between the measured and the ideal 1 LSB The ratio is dependent upon the number of quantization levels change between any two adjacent codes in the ADC. in the digitization process; the more levels, the smaller the Positive Full-Scale Error (AD7895-10) quantization noise. The theoretical signal to (noise + distortion) This is the deviation of the last code transition (01 . . . 110 to ratio for an ideal N-bit converter with a sine wave input is given 01 . . . 111) from the ideal (4 × VREF – 1 LSB) after the by: Bipolar Zero Error has been adjusted out. Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Positive Full-Scale Error (AD7895-3) Thus for a 12-bit converter, this is 74 dB. This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal ( VREF – 1 LSB) after the Total Harmonic Distortion Bipolar Zero Error has been adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7895, it is defined as: Positive Full-Scale Error (AD7895-2) This is the deviation of the last code transition (11 . . . 110 to 2 2 2 2 2 V +V +V +V +V 11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar 2 3 4 5 6 THD (dB) = 20 log V Offset Error has been adjusted out. 1 Bipolar Zero Error (AD7895-10, AD7895-3) where V is the rms amplitude of the fundamental, and V , V , 1 2 3 This is the deviation of the midscale transition (all 0s to all 1s) V , V and V are the rms amplitudes of the second through the 4 5 6 from the ideal 0 V (GND). sixth harmonics. Unipolar Offset Error (AD7895-2) Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000 to Peak harmonic or spurious noise is defined as the ratio of the 00 . . . 001) from the ideal 1 LSB. rms value of the next largest component in the ADC output spectrum (up to f /2 and excluding dc) to the rms value of the S Negative Full-Scale Error (AD7895-10) fundamental. Normally, the value of this specification is This is the deviation of the first code transition (10 . . . 000 to determined by the largest harmonic in the spectrum, but for 10 . . . 001) from the ideal (–4 × VREF + 1 LSB) after Bipolar parts where the harmonics are buried in the noise floor, it will Zero Error has been adjusted out. be a noise peak. Negative Full-Scale Error (AD7895-3) Intermodulation Distortion This is the deviation of the first code transition (10 . . . 000 to With inputs consisting of sine waves at two frequencies, fa and 10 . . . 001) from the ideal (–VREF + 1 LSB) after Bipolar Zero fb, any active device with nonlinearities will create distortion Error has been adjusted out. products at sum and difference frequencies of mfa ± nfb where Track/Hold Acquisition Time m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which Track/Hold acquisition time is the time required for the output neither m or n are equal to zero. For example, the second order of the track/hold amplifier to reach its final value, within terms include (fa + fb) and (fa – fb), while the third order terms ±1/2 LSB, after the end of conversion (the point at which the include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). track/hold returns to track mode). It also applies to situations The AD7895 is tested using the CCIF standard where two where there is a step input change on the input voltage applied input frequencies near the top end of the input bandwidth are to the V input of the AD7895. This means that the user must IN used. In this case, the second and third order terms are of wait for the duration of the track/hold acquisition time after the different significance. The second order terms are usually end of conversion or after a step input change to V before IN distanced in frequency from the original sine waves, while the starting another conversion to ensure that the part operates to third order terms are usually at a frequency close to the input specification. frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. REV. 0 –5– AD7895 CONVERTER DETAILS ance stage of the track/hold amplifier. For the AD7895-10, The AD7895 is a fast, 12-bit single supply A/D converter. It R1 = 30 kΩ, R2 = 7.5 kΩ and R3 = 10 kΩ. For the AD7895-3, provides the user with signal scaling, track/hold, A/D converter R1 = R2 = 6.5 kΩ and R3 is open circuit. and serial interface logic functions on a single chip. The A/D For the AD7895-10 and AD7895-3, the designed code transi- converter section of the AD7895 consists of a conventional tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs, successive-approximation converter based around an R-2R 3 LSBs . . .). Output coding is 2s complement binary with 1 LSB ladder structure. The signal scaling on the AD7895-10 and = FS/4096. The ideal input/output transfer function for the AD7895-3 allows the part to handle ±10 V and ±2.5 V input AD7895-10 and AD7895-3 is shown in Table I. signals, respectively, while operating from a single +5 V supply. The AD7895-2 accepts an analog input range of 0 V to +2.5 V. Table I. Ideal Input/Output Code Table for the AD7895-10/-3 The part requires an external +2.5 V reference. The reference Digital Output input to the part is buffered on-chip. The AD7895 has two l operating modes, the high sampling mode and the auto sleep Analog Input Code Transition mode, where the part automatically goes into sleep after the end of 2 +FSR/2 – 1 LSB 011 . . . 110 to 011 . . . 111 conversion. These modes are discussed in more detail in the +FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110 “Timing and Control” section. +FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101 A major advantage of the AD7895 is that it provides all of the above functions in an 8-pin package, either 8-pin mini-DIP or GND + 1 LSB 000 . . . 000 to 000 . . . 001 SOIC. This offers the user considerable spacing saving advantages GND 111 . . . 111 to 000 . . . 000 over alternative solutions. The AD7895 consumes only 20 mW GND – 1 LSB 111 . . . 110 to 111 . . . 111 maximum, making it ideal for battery-powered applications. –FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 Conversion is initiated on the AD7895 by pulsing the CONVST –FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 input. On the falling edge of CONVST, the on-chip track/hold –FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 goes from track to hold mode, and the conversion sequence is started. The conversion clock for the part is generated internally NOTES 1 FSR is full-scale range = 20 V (AD7895-10) and = 5 V (AD7895-3) using a laser-trimmed clock oscillator circuit. Conversion time with REF IN = +2.5 V. for the AD7895 is 3.8 μs in the high sampling mode (9.8 μs for 2 1 LSB = FSR/4096 = 4.883 mV (AD7895-10) and 1.22 mV (AD7895-3) the auto sleep mode), and the track/hold acquisition time is with REF IN = +2.5 V. 0.3 μs. To obtain optimum performance from the part, the read The analog input section for the AD7895-2 contains no biasing operation should not occur during the conversion or during resistors, and the V pin drives the input to the track/hold IN 300 ns prior to the next conversion. This allows the part to amplifier directly. The analog input range is 0 V to +2.5 V into operate at throughput rates up to 192 kHz and achieve data sheet a high impedance stage with an input current of less than specifications. 500 nA. This input is benign with no dynamic charging cur- rents. Once again, the designed code transitions occur on succes- CIRCUIT DESCRIPTION sive integer LSB values. Output coding is straight (natural) binary Analog Input Section with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table II shows The AD7895 is offered as three part types: the AD7895-10, the ideal input/output transfer function for the AD7895-2. which handles a ±10 V input voltage range; the AD7895-3, which handles input voltage range ±2.5 V; and the AD7895-2, Table II. Ideal Input/Output Code Table for AD7895-2 which handles a 0 V to +2.5 V input voltage range. Digital Output 1 Analog Input Code Transition REF IN 2 +FSR – 1 LSB 111 . . . 110 to 111 . . . 111 TO ADC +FSR – 2 LSB 111 . . . 101 to 111 . . . 110 REFERENCE CIRCUITRY +FSR – 3 LSB 111 . . . 100 to 111 . . . 101 R2 R1 TO INTERNAL GND + 3 LSB 000 . . . 010 to 000 . . . 011 V IN COMPARATOR GND + 2 LSB 000 . . . 001 to 000 . . . 010 TRACK/ R3 HOLD GND + 1 LSB 000 . . . 000 to 000 . . . 001 AGND NOTES 1 AD7895-10/AD7895-3 FSR is full-scale range and is 2.5 V for AD7895-2 with VREF = +2.5 V. 2 1 LSB = FSR/4096 and is 0.61 mV for AD7895-2 with VREF = +2.5 V. Track/Hold Section Figure 2. AD7895-10/AD7895-3 Analog Input Structure The track/hold amplifier on the analog input of the AD7895 Figure 2 shows the analog input section for the AD7895-10 and allows the ADC to accurately convert an input sine wave of full- scale amplitude to 12-bit accuracy. The input bandwidth of the AD7895-3. The analog input range of the AD7895-10 is ±10 V into an input resistance of typically 33 kΩ. The analog input track/hold is greater than the Nyquist rate of the ADC even range of the AD7895-3 is ±2.5 V into an input resistance of when the ADC is operated at its maximum throughput rate of 192 kHz (i.e., the track/hold can handle input frequencies in typically 12 kΩ. This input is benign with no dynamic charging currents, as the resistor stage is followed by a high input imped- excess of 100 kHz). REV. 0 –6– AD7895 The track/hold amplifier acquires an input signal to 12-bit stated. If there are more serial clock pulses after the sixteenth accuracy in less than 0.3 μs. The operation of the track/hold is clock, the shift register will be moved on past its reset state. essentially transparent to the user. With the high sampling However, the shift register will be reset again on the falling edge operating mode, the track/hold amplifier goes from its tracking of the CONVST signal to ensure that the part returns to a mode to its hold mode at the start of conversion (i.e. the falling known state every conversion cycle. As a result, a read opera- edge of CONVST). The aperture time for the track/hold (i.e. tion from the output register should not straddle across the the delay time between the external CONVST signal and the falling edge of CONVST as the output shift register will be reset track/hold actually going into hold) is typically 15 ns. At the in the middle of the read operation, and the data read back into end of conversion (on the falling edge of BUSY), the part returns the microprocessor will appear invalid. to its tracking mode. The acquisition time of the track/hold amplifier begins at this point. For the auto shut down mode, the OPERATING MODES rising edge of CONVST wakes up the part and the track, and Mode 1 Operation (High Sampling Performance) hold amplifier goes from its tracking mode to its hold mode 6 μs The timing diagram in Figure 3 is for optimum performance in after the rising edge of CONVST (provided that the CONVST operating Mode 1 where the falling edge of CONVST starts high time is less than 6 μs). Once again, the part returns to its conversion and puts the Track/Hold amplifier into its hold tracking mode at the end of conversion when the BUSY signal mode. This falling edge of CONVST also causes the BUSY goes low. signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, Reference Input which is 3.8 μs max after the falling edge of CONVST, and new The reference input to the AD7895 is buffered on-chip with a data from this conversion is available in the output register of maximum reference input current of 1 μA. The part is specified the AD7895. A read operation accesses this data. This read with a +2.5 V reference input voltage. Errors in the reference operation consists of 16 clock cycles, and the length of this read source will result in gain errors in the AD7895’s transfer operation will depend on the serial clock frequency. For the function and will add to the specified full-scale errors on the fastest throughput rate (with a serial clock of 15 MHz, 5 V part. Suitable reference sources for the AD7895 include the operation) the read operation will take 1.1 μs. The read opera- AD780 and AD680 precision +2.5 V references. tion must be complete at least 300 ns before the falling edge of Timing and Control Section the next CONVST, and this gives a total time of 5.2 μs for the Figure 3 shows the timing and control sequence required to full throughput time (equivalent to 192 kHz). This mode of obtain optimum performance from the AD7895. In the se- operation should be used for high sampling applications. quence shown, conversion is initiated on the falling edge of Mode 2 Operation (Auto Sleep After Conversion) CONVST, and new data from this conversion is available in The timing diagram in Figure 4 is for optimum performance in the output register of the AD7895 3.8 μs later. Once the read operating mode 2 where the part automatically goes into sleep operation has taken place, a further 300 ns should be allowed mode once BUSY goes low after conversion and “wakes-up” before the next falling edge of CONVST to optimize the settling before the next conversion takes place. This is achieved by keep- of the track/hold amplifier before the next conversion is initi- ing CONVST low at the end of conversion, whereas it was high ated. With the serial clock frequency at its maximum of at the end of conversion for Mode 1 Operation. The rising edge 15 MHz, the achievable throughput rate for the part is 3.8 μs of CONVST “wakes up” the part. This wake-up time is 6 μs at (conversion time) plus 1.1 μs (read time) plus 0.3 μs (acquisi- which point the Track/Hold amplifier goes into its hold mode, tion time). This results in a minimum throughput time of 8.2 μs provided the CONVST has gone low. The conversion takes (equivalent to a throughput rate of 192 kHz). A serial clock of 3.8 μs after this giving a total of 9.8 μs from the rising edge of less than 15 MHz can be used, but this will in turn mean that CONVST to the conversion being complete, which is indi- the throughput time will increase. cated by the BUSY going low. Note that since the wake-up time The read operation consists of sixteen serial clock pulses to the from the rising edge of CONVST is 6 μs, when the CONVST output shift register of the AD7895. After sixteen serial clock pulse width is greater than 6 μs, the conversion will take more pulses, the shift register is reset, and the SDATA line is three- t t = 40ns MIN 1 1 CONVST BUSY 300ns MIN SCLK t = 3.8µs CONVERT CONVERSION READ OPERATION CONVERSION IS SERIAL READ OUTPUT ENDS SHOULD END 300ns INITIATED AND OPERATION SERIAL 3.8µs LATER PRIOR TO NEXT TRACK/HOLD GOES INTO SHIFT FALLING EDGE OF HOLD REGISTER CONVST IS RESET Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance REV. 0 –7– AD7895 than the 9.8 μs shown in diagram from the rising edge of valid on the first falling edge of SCLK even though the data CONVST. This is because the Track/Hold amplifier goes into access time is specified at 60 ns for the other bits. The reason its hold mode on the falling edge of CONVST, and the conver- that the first bit will be clocked out faster than the other bits is sion will not be complete for a further 3.8 μs. In this case, the due to the internal architecture of the part. Sixteen clock pulses BUSY will be the best indicator for when the conversion is must be provided to the part to access to full conversion result. complete. Even though the part is in sleep mode, data can still The AD7895 provides four leading zeros, followed by the 12-bit be read from the part. The read operation consists of 16 clock conversion result starting with the MSB (DB11). The last data cycles as in Mode 1 Operation. For the fastest serial clock of bit to be clocked out on the penultimate falling clock edge is the 15 MHz, the read operation will take 1.1 μs and this must be LSB (DB0). On the sixteenth falling edge of SCLK, the LSB complete at least 300 ns before the falling edge of the next (DB0) will be valid for a specified time to allow the bit to be CONVST to allow the Track/Hold amplifier to have enough read on the falling edge of the SCLK, then the SDATA line is time to settle. This mode is very useful when the part is convert- disabled (three-stated). After this last bit has been clocked ing at a slow rate as the power consumption will be significantly out, the SCLK input should return low and remain low until the reduced from that of Mode 1 Operation. next serial data read operation. If there are extra clock pulses after the sixteenth clock, the AD7895 will start over again with Serial Interface outputting data from its output register, and the data bus will no The serial interface to the AD7895 consists of just three wires: a longer be three-stated even when the clock stops. Provided the serial clock input (SCLK), the serial data output (SDATA) and serial clock has stopped before the next falling edge of CONVST, a conversion status output (BUSY). This allows for an easy-to- the AD7895 will continue to operate correctly with the output use interface to most microcontrollers, DSP processors and shift shift register being reset on the falling edge of CONVST. registers. However, the SCLK line must be low when CONVST goes low in Figure 5 shows the timing diagram for the read operation to the order to reset the output shift register correctly. AD7895. The serial clock input (SCLK) provides the clock The serial clock input does not have to be continuous during the source for the serial interface. Serial data is clocked out from the serial read operation. The sixteen bits of data (four leading SDATA line on the falling edge of this clock and is valid on zeros and 12 bit conversion result) can be read from the AD7895 both the rising and falling edges of SCLK. The advantage of in a number of bytes. having the data valid on both the rising and falling edges of the SCLK is that it gives the user greater flexibility in interfacing to The AD7895 counts the serial clock edges to know which bit the part and allows a wider range of microprocessor and micro- from the output register should be placed on the SDATA controller interfaces to be accommodated. This also explains the output. To ensure that the part does not lose synchronization, two timing figures, t and t that are quoted on the diagram. the serial clock counter is reset on the falling edge of the 4 5, The time t specifies how long after the falling edge of the CONVST input, provided the SCLK line is low. The user 4 SCLK that the next data bit becomes valid, whereas the time t should ensure that the SCLK line remains low until the end of 5 specifies how long after the falling edge of the SCLK that the the conversion. When the conversion is complete, BUSY goes current data bit is valid for. The first leading zero is clocked out low, the output register will be loaded with the new conversion on the first rising edge of SCLK. Note that the first zero will be result and can be read from with sixteen clock cycles of SCLK. t = 6µs 1 WAKE-UP t 1 TIME CONVST BUSY 300ns MIN SCLK t = 9.8µs CONVERT PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED ENDS OPERATION SHOULD END 300ns SERIAL UP TRACK/HOLD 9.8µs LATER PRIOR TO NEXT SHIFT GOES INTO FALLING EDGE OF REGISTER HOLD IS RESET CONVST Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated t = t = 35ns MIN, t = 60ns MAX, t = 10ns MIN, t = 50ns MAX @ 5V, A, B, VERSIONS 2 3 4 5 6 t 2 SCLK (I/P) 1 2 3 4 5 6 15 16 t t t 3 5 6 t 4 3-STATE 4 LEADING ZEROS 3-STATE DOUT (O/P) DB11 DB10 DB0 Figure 5. Data Read Operation REV. 0 –8– AD7895 MICROPROCESSOR/MICROCONTROLLER INTERFACE AD7895–68HC11/L11 Interface The AD7895 provides a three-wire serial interface that can be An interface circuit between the AD7895 and the 68HC11/L11 used for connection to the serial ports of DSP processors and microcontroller is shown in Figure 7. For the interface shown, microcontrollers. Figures 6 through 9 show the AD7895 the 68L11 SPI port is used, and the 68L11 is configured in its interfaced to a number of different microcontrollers and DSP single-chip mode. The 68L11 is configured in the master mode processors. The AD7895 accepts an external serial clock, and with its CPOL bit set to a logic zero and its CPHA bit set to a as a result, in all interfaces shown here, the processor/controller logic one. As with the previous interface, the diagram shows the is configured as the master, providing the serial clock with the simplest form of the interface where the AD7895 is the only part AD7895 configured as the slave in the system. connected to the serial port of the 68L11 and, therefore, no decoding of the serial read operations is required. AD7895–8051 Interface Figure 6 shows an interface between the AD7895 and the 8XL51 microcontroller. The 8XL51 is configured for its Mode 0 serial PC2 OR BUSY interface mode. The diagram shows the simplest form of the IRQ interface where the AD7895 is the only part connected to the AD7895 68HC11/L11 serial port of the 8XL51 and, therefore, no decoding of the serial read operations is required. SCK SCLK SDATA MISO P1.2 OR BUSY INT1 AD7895 8X51/L51 Figure 7. AD7895 to 68HC11/L11 Interface P3.0 SDATA Once again, to chip select the AD7895 in systems where more than one device is connected to the 68HC11’s serial port, a port SCLK bit configured as an output from one of the 68HC11’s parallel P3.1 ports can be used to gate on or off the serial clock to the AD7895. A simple AND function on this port bit and the serial Figure 6. AD7895 to 8X51/L51 Interface clock from the 68L11 will provide this function. The port bit should be high to select the AD7895 and low when it is not To chip select the AD7895 in systems where more than one selected. device is connected to the 8XL51’s serial port, a port bit configured as an output, from one of the 8XL51’s parallel ports The end of conversion is monitored by using the BUSY signal can be used to gate on or off the serial clock to the AD7895. A that is shown in the interface diagram of Figure 7. With the simple AND function on this port bit and the serial clock from BUSY line from the AD7895 connected to the Port PC0 of the the 8XL51 will provide this function. The port bit should be 68HC11/L11, the BUSY line can be polled by the 68HC11/L11. high to select the AD7895 and low when it is not selected. The BUSY line can be connected to the IRQ line of the 68HC11/L11 if an interrupt driven system is preferred. These The end of conversion is monitored by using the BUSY signal two options are shown in the diagram. that is shown in the interface diagram of Figure 6. The BUSY line from the AD7895 is connected to the Port P1.2 of the The serial clock rate from the 68HC11/L11 is limited to 8XL51 so the BUSY line can be polled by the 8XL51. The BUSY significantly less than the allowable input serial clock frequency line can be connected to the INT1 line of the 8XL51 if an with which the AD7895 can operate. As a result, the time to interrupt driven system is preferred. These two options are read data from the part will actually be longer than the conver- shown in the diagram. sion time of the part. This means that the AD7895 cannot run at its maximum throughput rate when used with the 68HC11/L11. Note also that the AD7895 outputs the MSB first during a read operation, while the 8XL51 expects the LSB first. Therefore, AD7895–ADSP-2103/5 Interface the data which is read into the serial buffer needs to be rear- An interface circuit between the AD7895 and the ADSP-2103/5 ranged before the correct data format from the AD7895 appears DSP processor is shown in Figure 8. In the interface shown, the in the accumulator. RFS1 output from the ADSP-2103/5s SPORT1 serial port is used to gate the serial clock (SCLK1) of the ADSP-2103/5 The serial clock rate from the 8XL51 is limited to significantly before it is applied to the SCLK input of the AD7895. The less than the allowable input serial clock frequency with which RFS1 output is configured for active high operation. The BUSY the AD7895 can operate. As a result, the time to read data line from the AD7895 is connected to the IRQ2 line of the from the part will actually be longer than the conversion time of ADSP-2103/5 so that at the end of conversion an interrupt is the part. This means that the AD7895 cannot run at its maximum generated telling the ADSP-2103/5 to initiate a read operation. throughput rate when used with the 8XL51. The interface ensures a noncontinuous clock for the AD7895’s serial clock input with only sixteen serial clock pulses provided and the serial clock line of the AD7895 remaining low between data transfers. The SDATA line from the AD7895 is connected to the DR1 line of the ADSP-2103/5’s serial port. REV. 0 –9– AD7895 Because the BUSY line from the AD7895 is connected to the BUSY IRQ2 MODA/IRQA input of the DSP56002/L002, an interrupt will be generated at the end of conversion. This ensures that the RFS1 AD7895 read operation will take place after conversion is finished. ADSP-2103/5 SCLK SCLK1 AD7895 PERFORMANCE Linearity DR1 SDATA The linearity of the AD7895 is determined by the on-chip 12-bit D/A converter. This is a segmented DAC that is laser Figure 8. AD7896 to ADSP-2103 /5 Interface trimmed for 12-bit integral linearity and differential linearity. Typical relative accuracy numbers for the part are ±1/4 LSB The timing relationship between the SCLK1 and RFS1 outputs while the typical DNL errors are ±1/2 LSB. of the ADSP-2103/5 are such that the delay between the rising edge of the SCLK1 and the rising edge of an active high RFS1 Noise is up to 30 ns. There is also a requirement that data must be In an A/D converter, noise exhibits itself as code uncertainty in set up 10 ns prior to the falling edge of the SCLK1 to be read dc applications and as the noise floor (in an FFT, for example) correctly by the ADSP-2103/5. The data access time for the in ac applications. In a sampling A/D converter like the AD7895, AD7895 is 60 ns (5 V (A, B versions)) from the rising edge of all information about the analog input appears in the baseband its SCLK input. Assuming a 10 ns propagation delay through from dc to 1/2 the sampling frequency. The input bandwidth of the external AND gate, the high time of the SCLK1 output of the track/hold exceeds the Nyquist bandwidth and, therefore, an the ADSP-2105 must be ≥ (30 + 60 +10 +10) ns, i.e., ≥ 110 ns. antialiasing filter should be used to remove unwanted signals above This means that the serial clock frequency with which the f /2 in the input signal in applications where such signals exist. S interface of Figure 8 can work is limited to 4.5 MHz. However, Figure 10 shows a histogram plot for 8192 conversions of a dc there is an alternative method that allows for the ADSP-2105 input using the AD7895. The analog input was set at the center SCLK1 to run at 5 MHz (the max serial clock frequency of the of a code transition. It can be seen that almost all the codes SCLK1 output). The arrangement occurs when the first leading appear in the one output bin, indicating very good noise zero of the data stream from the AD7895 cannot be guaranteed performance from the ADC. to be clocked into the ADSP-2105 due to the combined delay of the RFS signal and the data access time of the AD7895. In most 9000 cases, this is acceptable because there will still be three leading 8000 zeros followed by the 12 data bits. For the ADSP-2103, the 7000 SCLK1 frequency will need to be limited to < 4 MHz to account for the 100 ns data access time of the AD7895. 6000 Another alternative scheme is to configure the ADSP-2103/5 so 5000 that it accepts an external noncontinuous serial clock. In this 4000 case, an external noncontinuous serial clock is provided that drives the serial clock inputs of both the ADSP-2103/5 and the 3000 AD7895. In this scheme, the serial clock frequency is limited to 2000 15 MHz by the AD7895. 1000 AD7895–DSP56002/L002 Interface Figure 9 shows an interface circuit between the AD7895 and the 0 957 958 959 960 961 962 DSP56002/L002 DSP processor. The DSP56002/L002 is configured for normal mode asynchronous operation with gated Figure 10. Histogram of 8192 Conversions of a DC Input clock. It is also set up for a 16-bit word with SCK as gated clock output. In this mode, the DSP56002/L002 provides In this case where the output data read for the device occurs sixteen serial clock pulses to the AD7895 in a serial read during conversion, this has the effect of injecting noise onto the operation. Because the DSP56002/L002 assumes valid data on die while bit decisions are being made, and this increases the the first falling edge of SCK, the interface is simply two-wire as noise generated by the AD7895. A histogram plot for 8192 shown in Figure 9. conversions of the same dc input would show a larger spread of codes with the rms noise for the AD7895 increasing. This effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. It is possible MODA / IRQA BUSY to achieve the same level of performance when reading during DSP56002/L002 AD7895 conversion as when reading after conversion, depending on the SCK SCLK relationship of the serial clock edges to the bit trial points. SDATA SDR Figure 9. AD7895 to DSP56002/L002 Interface REV. 0 –10– AD7895 12.0 Dynamic Performance (Mode 1 Only) 11.8 With a combined conversion and acquisition time of 4.1 μs, the AD7895 is ideal for wide bandwidth signal processing applica- 11.6 tions. These applications require information on the ADC’s 11.4 effect on the spectral content of the input signal. Signal to 11.2 (Noise + Distortion), Total Harmonic Distortion, Peak Har- 11.0 monic or Spurious Noise, and Intermodulation Distortion are all specified. Figure 11 shows a typical FFT plot of a 10 kHz, 10.8 0 V to +5 V input after being digitized by the AD7895 operating 10.6 at a 198.656 kHz sampling rate. The Signal to (Noise + Distor- 10.4 tion) Ratio is 73.04 dB, and the Total Harmonic Distortion is 10.2 –84.91 dB. 10.0 The formula for Signal to (Noise + Distortion) Ratio (see 0 200 400 600 800 1000 Terminology section) is related to the resolution or number of FREQUENCY – kHz bits in the converter. Rewriting the formula, below, gives a measure of performance expressed in effective number of bits (N): Figure 12. Effective Number of Bits vs. Frequency N = (SNR 1.76)/6.02 Power Considerations In the automatic power-down mode, then, the part may be where SNR is Signal to (Noise + Distortion) Ratio. operated at a sample rate that is considerably less than –0 100 kHz. In this case, the power consumption will be reduced F = 198656 SAMPLE –10 and will depend on the sample rate. Figure 13 shows a graph F = 10kHz IN –20 SNR = –73.04dB of the power consumption versus sampling rates from 100 Hz to THD = –84.91dB –30 90 kHz in the automatic power-down mode. The conditions –40 are 5 V supply 25°C, serial clock frequency of 8.33 MHz, and –50 the data was read after conversion. –60 11 –70 10 –80 9 –90 8 –100 7 –110 6 –120 0 10k 30k 50k 70k 90k 9.9k 5 4 Figure 11. AD7896 FFT Plot Effective Number of Bits 3 The effective number of bits for a device can be calculated from 2 its measured Signal to (Noise + Distortion) Ratio. Figure 12 1 shows a typical plot of effective number of bits versus frequency 0 for the AD7895 from dc to f /2. The sampling frequency SAMPLING 0.1 10 20 30 40 50 60 70 80 90 is 198.656 kHz. The plot shows that the AD7895 converts an FREQUENCY – kHz input sine wave of 10 kHz to an effective numbers of bits of 11.84, which equates to a Signal to (Noise + Distortion) level of Figure 13. Power vs. Sample Rate in Auto Power-Down 73.04 dB. Mode REV. 0 –11– ENOB POWER – mW AD7895 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 14 0.325 (8.25) 0.300 (7.62) PIN 1 0.060 (1.52) 0.015 (0.38) 0.195 (4.95) 0.210 (5.33) 0.115 (2.93) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 85 0.2440 (6.20) 0.1574 (4.00) 0.2284 (5.80) 0.1497 (3.80) 1 4 0.102 (2.59) PIN 1 0.0196 (0.50) x 45° 0.094 (2.39) 0.0099 (0.25) 0.0098 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° 0.0500 (1.27) SEATING 0.0098 (0.25) (1.27) 0.0138 (0.35) 0.0160 (0.41) PLANE BSC 0.0075 (0.19) –12– REV. 0 PRINTED IN U.S.A. C2209–12–10/96