ANALOG DEVICES AD7892

2 LC MOS Single Supply, a 12-Bit 600 kSPS ADC AD7892 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast 12-Bit ADC with 1.47�s Conversion Time REF OUT/REF IN V DD 600 kSPS Throughput Rate (AD7892-3) 500 kSPS Throughput Rate (AD7892-1, AD7892-2) 2k� +2.5V MODE Single Supply Operation AD7892 REFERENCE On-Chip Track/Hold Amplifier Selection of Input Ranges: DB0 �10 V or �5 V for AD7892-1 DB2 0 V to +2.5 V for AD7892-2 DB3/RFS 12-BIT DB4/SCLK �2.5 V for AD7892-3 ADC DB5/SDATA V High Speed Serial and Parallel Interface IN1 SIGNAL DB10/LOW SCALING V Low Power, 60 mW typ IN2 DB11/LOW Overvoltage Protection on Analog Inputs (AD7892-1 TRACK/HOLD and AD7892-3) CLOCK CONTROL LOGIC CS RD EOC CONVST AGND DGND STANDBY GENERAL DESCRIPTION The AD7892 is fabricated in Analog Devices’ Linear Compat- 2 The AD7892 is a high speed, low power, 12-bit A/D converter ible CMOS (LC MOS) process, a mixed technology process that operates from a single +5 V supply. The part contains a that combines precision bipolar circuits with low power CMOS 1.47 µs successive approximation ADC, an on-chip track/hold logic. It is available in a 24-lead, 0.3" wide, plastic or hermetic amplifier, an internal +2.5 V reference and on-chip versatile DIP or in a 24-lead SOIC. interface structures that allow both serial and parallel connec- tion to a microprocessor. The part accepts an analog input range PRODUCT HIGHLIGHTS of ±10 V or ±5 V (AD7892-1), 0 V to +2.5 V (AD7892-2) and 1. The AD7892-3 features a conversion time of 1.47µs and a ±2.5 V (AD7892-3). Overvoltage protection on the analog inputs track/hold acquisition time of 200 ns. This allows a through- for the AD7892-1 and AD7892-3 allows the input voltage to go put rate for the part up to 600 kSPS. The AD7892-1 and to ±17 V or ±7 V respectively without damaging the ports. AD7892-2 operate with throughput rates of 500 kSPS. The AD7892 offers a choice of two data output formats: a 2. The AD7892 operates from a single +5 V supply and con- single, parallel, 12-bit word or serial data. Fast bus access times sumes 60 mW typ making it ideal for low power and portable and standard control inputs ensure easy parallel interface to applications. microprocessors and digital signal processors. A high speed 3. The part offers a high speed, flexible interface arrangement serial interface allows direct connection to the serial ports of with parallel and serial interfaces for easy connection to microcontrollers and digital signal processors. microprocessors, microcontrollers and digital signal In addition to the traditional dc accuracy specifications such as processors. linearity, full-scale and offset errors, the part is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 (V = +5 V � 5%, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T to T DD MIN MAX AD7892–SPECIFICATIONS unless otherwise noted.) 1 2 Parameter A Versions B Versions S Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE AD7892-1, AD7892-2 f = 100 kHz. f = 500 kSPS IN SAMPLE 3 Signal to (Noise + Distortion) Ratio 70 70 70 dB min 3 Total Harmonic Distortion –78 –78 –78 dB max typ –84 dB 3 Peak Harmonic or Spurious Noise –79 –79 –79 dB max 3 Intermodulation Distortion fa = 49 kHz, fb = 50 kHz 2nd Order Terms –78 –78 –78 dB max typ –84 dB 3rd Order Terms –78 –78 –78 dB max typ –84 dB AD7892-3 f = 100 kHz. f = 600 kSPS IN SAMPLE 3 Signal to (Noise + Distortion) Ratio 70 70 dB min 3 Total Harmonic Distortion –78 –78 dB max 3 Peak Harmonic or Spurious Noise –79 –79 dB max 3 Intermodulation Distortion fa = 49 kHz, fb = 50 kHz 2nd Order Terms –78 –78 dB max 3rd Order Terms –78 –78 dB max DC ACCURACY Resolution 12 12 12 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 12 12 12 Bits 3 Relative Accuracy ±1.5 ±1 ±1 LSB max 3 Differential Nonlinearity ±1 ±1 ±1 LSB max AD7892-1 3 Positive Full-Scale Error ±4 ±4 ±5 LSB max 3 Negative Full-Scale Error ±4 ±4 ±5 LSB max 3 Bipolar Zero Error ±3 ±2 ±3 LSB max AD7892-3 3 Positive Full-Scale Error ±4 ±4 LSB max 3 Negative Full-Scale Error ±4 ±4 LSB max 3 Bipolar Zero Error ±4 ±3 LSB max AD7892-2 3 Positive Full-Scale Error ±5 ±5 ±5 LSB max 3 Unipolar Offset Error ±4 ±3 ±4 LSB max ANALOG INPUT AD7892-1 Input Voltage Range ±10 ±10 ±10 Volts Input Applied to V with V Grounded IN1 IN2 Input Voltage Range ±5 ±5 ±5 Volts Input Applied to V and V IN1 IN2 Input Resistance 8 8 8 kΩ min Input Applied to V with V Grounded IN1 IN2 AD7892-2 Input Voltage Range on V 0 to +2.5 0 to +2.5 0 to +2.5 Volts Input Applied to V IN1 IN1 Input Current 10 10 50 nA max Input Voltage Range on V ±50 ±50 ±50 mV max IN2 AD7892-3 Input Voltage Range on V ±2.5 ±2.5 Volts Input Applied to V IN1 IN1 Input Resistance 2 2 kΩ min REFERENCE OUTPUT/INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Impedance 1.6 1.6 1.6 kΩ min Resistor Connected to Internal Reference Node 4 Input Capacitance 10 10 10 pF max REF OUT Output Voltage 2.5 2.5 2.5 V nom REF OUT Error @ +25°C ±10 ±10 ±10 mV max T to T ±20 ±20 ±25 mV max MIN MAX REF OUT Temperature Coefficient 25 25 25 ppm/°C typ REF OUT Output Impedance 5.5 5.5 5.5 kΩ nom LOGIC INPUTS Input High Voltage, V 2.4 2.4 2.4 V min V = 5 V ± 5% INH DD Input Low Voltage, V 0.8 0.8 0.8 V max V = 5 V ± 5% INL DD Input Current, I ±10 ±10 ±10 µA max V = 0 V to V IN IN DD 4 Input Capacitance, C 10 10 10 pF max IN –2– REV. C AD7892 1 2 Parameter A Versions B Versions S Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 4.0 V min I = 200 µA OH SOURCE Output Low Voltage, V 0.4 0.4 0.4 V max I = 1.6 mA OL SINK DB11–DB0 Floating-State Leakage Current ±10 ±10 ±10 µA max 4 Floating-State Capacitance 15 15 15 pF max Output Coding AD7892-1 and AD7892-3 Two’s Complement AD7892-2 Straight (Natural) Binary CONVERSION RATE Conversion Time 1.47 1.47 µs max AD7892-3 3 Track/Hold Acquisition Time 0.2 0.2 µs max AD7892-3 Conversion Time 1.6 1.6 1.68 µs max AD7892-1 and AD7892-2 3 Track/Hold Acquisition Time 0.4 0.4 0.32 µs max AD7892-1 and AD7892-2 POWER REQUIREMENTS V +5 +5 +5 V nom ±5% for Specified Performance DD 5 I DD Normal Operation 18 18 19 mA max 6 Standby Mode AD7892-2 250 250 µA typ AD7892-3, AD7892-1 80 80 100 µA max typ 15 µA 5 Power Dissipation Normal Operation 90 90 95 mW max V = +5 V. Typically 60 mW DD 6 Standby Mode AD7892-2 1.25 1.25 mW typ AD7892-3, AD7892-1 400 400 500 µW max V = +5 V. Typically 75 µW DD NOTES 1 Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C. 2 S Version available on AD7892-1 and AD7892-2 only. 3 See Terminology. 4 Sample tested @ +25°C to ensure compliance. 5 These normal mode and standby mode currents are achieved with resistors (in the range 10 kΩ to 100 kΩ) to either DGND or V on Pins 8, 9, 16 and 17. DD 6 A conversion should not be initiated on the part within 30 µs of exiting standby mode. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C (T = +25°C unless otherwise noted) Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W JA V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW Analog Input Voltage to AGND θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA AD7892-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C AD7892-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V DD SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW AD7892-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA Reference Input Voltage to AGND . . . –0.3 V to V + 0.3 V DD Lead Temperature, Soldering Digital Input Voltage to DGND . . . . . –0.3 V to V + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Digital Output Voltage to DGND . . . . –0.3 V to V + 0.3 V DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Operating Temperature Range *Stresses above those listed under Absolute Maximum Ratings may cause perma- Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C nent damage to the device. This is a stress rating only; functional operation of the Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C device at these or any other conditions above those listed in the operational Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REV. C –3– AD7892 1, 2 TIMING CHARACTERISTICS (V = +5 V � 5%, AGND = DGND = 0 V, REF IN = +2.5 V) DD A, B S Parameter Versions Version Unit Test Conditions/Comments t 1.47 µs max Conversion Time for AD7892-3 CONV 1.6 1.68 µs max Conversion Time for AD7892-1, AD7892-2 t 200 ns min Acquisition Time for AD7892-3 ACQ 400 320 ns min Acquisition Time for AD7892-1, AD7892-2 Parallel Interface 35 45 ns min CONVST Pulsewidth t 1 t 60 60 ns min EOC Pulsewidth 2 t 0 0 ns min EOC Falling Edge to CS Falling Edge Setup Time 3 t 0 0 ns min CS to RD Setup Time 4 t 35 45 ns min Read Pulsewidth 5 3 t 35 40 ns max Data Access Time After Falling Edge of RD 6 4 t 5 5 ns min Bus Relinquish Time After Rising Edge of RD 7 30 40 ns max t 0 0 ns min CS to RD Hold Time 8 t 200 200 ns min RD to CONVST Setup Time 9 Serial Interface t 30 35 ns min RFS Low to SCLK Falling Edge Setup Time 10 3 t 25 30 ns max RFS Low to Data Valid Delay 11 t 25 25 ns min SCLK High Pulsewidth 12 t 25 25 ns min SCLK Low Pulsewidth 13 3 t 5 5 ns min SCLK Rising Edge to Data Valid Hold Time 14 3 t 25 30 ns max SCLK Rising Edge to Data Valid Delay 15 t 20 30 ns min RFS to SCLK Falling Edge Hold Time 16 4 t 0 0 ns min Bus Relinquish Time after Rising Edge of RFS 17 30 30 ns max 4 t 0 0 ns min Bus Relinquish Time after Rising Edge of SCLK 17A 30 30 ns max NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figures 2 and 3. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5 Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min. Specifications subject to change without notice. 1.6mA TO +1.6V OUTPUT PIN 50pF 200�A Figure 1. Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7892 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. C AD7892 ORDERING GUIDE Input Sample Relative Temperature Package 1 Model Range Rate Accuracy Range Option AD7892AN-1 ±5 V or ±10 V 500 kSPS –40°C to +85°C N-24 AD7892BN-1 ±5 V or ±10 V 500 kSPS ±1 LSB –40°C to +85°C N-24 AD7892AR-1 ±5 V or ±10 V 500 kSPS –40°C to +85°C R-24 AD7892BR-1 ±5 V or ±10 V 500 kSPS ±1 LSB –40°C to +85°C R-24 AD7892SQ-1 ±5 V or ±10 V 500 kSPS ±1 LSB –55°C to +125°CQ-24 AD7892AN-2 0 V to +2.5 V 500 kSPS –40°C to +85°C N-24 AD7892BN-2 0 V to +2.5 V 500 kSPS ±1 LSB –40°C to +85°C N-24 AD7892AR-2 0 V to +2.5 V 500 kSPS –40°C to +85°C R-24 AD7892BR-2 0 V to +2.5 V 500 kSPS ±1 LSB –40°C to +85°C R-24 AD7892AN-3 ±2.5 V 600 kSPS –40°C to +85°C N-24 AD7892BN-3 ±2.5 V 600 kSPS ±1 LSB –40°C to +85°C N-24 AD7892AR-3 ±2.5 V 600 kSPS –40°C to +85°C R-24 AD7892BR-3 ±2.5 V 600 kSPS ±1 LSB –40°C to +85°C R-24 2 EVAL-AD7892-2CB Evaluation Board 2 EVAL-AD7892-3CB Evaluation Board 3 EVAL-CONTROL BOARD Controller Board NOTES 1 N = Plastic DIP; Q = Cerdip; R = SOIC. 2 These boards can be used as stand-alone evaluation boards or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators. REV. C –5– AD7892 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1V Positive Supply Voltage, +5 V ± 5%. DD 2 STANDBY Standby Input. Logic Input. With this input at a logic high, the part is in its normal operating mode; with this input at a logic low, the part is placed in its standby or power-down mode, which reduces power consumption to 5 mW typical. 3V Analog Input 2. For the AD7892-1, this input either connects to AGND or to V to determine IN2 IN1 the analog input voltage range. With V connected to AGND on the AD7892-1, the analog input IN2 range at the V input is ±10 V. With V connected to V on the AD7892-1, the analog input IN1 IN2 IN1 range to the part is ±5V. For the AD7892-2 and AD7892-3, this input can be left unconnected but must not be connected to a potential other than AGND. 4V Analog Input 1. The analog input voltage to be converted by the AD7892 is applied to this input. IN1 For the AD7892-1, the input voltage range is either ±5 V or ±10 V depending on where the V IN2 input is connected. For the AD7892-2, the voltage range on the V input is 0 V to +2.5 V with IN1 respect to the voltage appearing at the V input. For the AD7892-3, the voltage range on the V IN2 IN1 input is ±2.5 V. 5 REF OUT/REF IN Voltage Reference Output/Input. The part can be used with either its own internal reference or with an external reference source. The on-chip +2.5 V reference is provided at this pin. When using this internal reference as the reference source for the part, REF OUT should be decoupled to AGND with a 0.1 µF disc ceramic capacitor. The output impedance of this reference source is typically 5.5 kΩ. When using an external reference source as the reference voltage for the part, the reference source should be connected to this pin. This overdrives the internal reference and provides the reference source for the part. The REF IN input is buffered on-chip but must be able to sink or source current through the resistor to the output of the on-chip reference. The nominal reference voltage for correct operation of the AD7892 is +2.5 V. 6 AGND Analog Ground. Ground reference for track/hold, comparator and DAC. 7 MODE Mode. Control input which determines the interface mode for the AD7892. With this pin at a logic low, the device is in its serial interface mode; with this pin at a logic high, the device is in its parallel interface mode. 8 DB11/LOW Data Bit 11/Test Pin. When the device is in its parallel mode, this pin is Data Bit 11 (MSB), a three-state TTL-compatible output. When the device is in its serial mode, this is used as a test pin which must be tied to a logic low for correct operation of the AD7892. 9 DB10/LOW Data Bit 10/Test Pin. When the device is in its parallel mode, this pin is Data Bit 10, a three-state TTL-compatible output. When the device is in its serial mode, this is used as a test pin which must be tied to a logic low for correct operation of the AD7892. 10 DB9 Data Bit 9. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 11 DB8 Data Bit 8. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 12 DB7 Data Bit 7. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 13 DB6 Data Bit 6. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 14 DGND Digital Ground. Ground reference for digital circuitry. 15 DB5/SDATA Data Bit 5/Serial Data. When the device is in its parallel mode, this pin is Data Bit 5, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the serial data output line. Sixteen bits of serial data are provided with four leading zeros preceding the 12 bits of valid data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. –6– REV. C AD7892 Pin No. Mnemonic Description 16 DB4/SCLK Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin, SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial data from the AD7892. Serial data is clocked out from the output shift register on the rising edges of SCLK after RFS goes low. 17 DB3/RFS Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the receive frame synchronization input with RFS provided externally to obtain serial data from the AD7892. 18 DB2 Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 19 DB1 Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the device is in its serial mode. 20 DB0 Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left unconnected when the device is in its serial mode. 21 RD Read. Active low logic input which is used in conjunction with CS low to enable the data outputs. 22 CS Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs. 23 EOC End-of-Conversion. Active low logic output indicating converter status. The end of conversion is signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns. 24 CONVST Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion. PIN CONFIGURATION DIP and SOIC V 1 24 CONVST DD STANDBY 2 23 EOC V 3 22 CS IN2 V 4 21 RD IN1 REF OUT/REF IN 5 20 DB0 (LSB) AD7892 AGND 6 19 DB1 TOP VIEW MODE 7 18 DB2 (Not to Scale) DB11/LOW817 DB3/RFS DB4/SCLK DB10/LOW916 DB9 10 15 DB5/SDATA DB8 11 11 14 DGND DB7 12 13 DB6 REV. C –7– AD7892 TERMINOLOGY Relative Accuracy Signal to (Noise + Distortion) Ratio Relative accuracy or endpoint nonlinearity is the maximum This is the measured ratio of signal to (noise + distortion) at the deviation from a straight line passing through the endpoints of output of the A/D converter. The signal is the rms amplitude of the ADC transfer function. the fundamental. Noise is the rms sum of all nonfundamental Differential Nonlinearity signals up to half the sampling frequency (f /2), excluding dc. S This is the difference between the measured and the ideal The ratio is dependent upon the number of quantization levels 1 LSB change between any two adjacent codes in the ADC. in the digitization process; the more levels, the smaller the quan- Positive Full-Scale Error (AD7892-1) tization noise. The theoretical signal to (noise + distortion) This is the deviation of the last code transition (01 . . . 110 to ratio for an ideal N-bit converter with a sine wave input is given 01 . . . 111) from the ideal 4 × REF IN – 3/2 LSB (±10 V range) by: or 2 × REF IN – 3/2 LSB (±5 V range) after the bipolar zero Signal to (Noise + Distortion) = (6.02 N + 1.76) dB error has been adjusted out. Thus for a 12-bit converter, this is 74 dB. Positive Full-Scale Error (AD7892-2) Total Harmonic Distortion This is the deviation of the last code transition (11 . . . 110 to Total harmonic distortion (THD) is the ratio of the rms sum of 11 . . . 111) from the ideal (REF IN – 3/2 LSB) after the unipo- harmonics to the fundamental. For the AD7892, it is defined lar offset error has been adjusted out. as: Positive Full-Scale Error (AD7892-3) This is the deviation of the last code transition (01 . . . 110 to 2 2 2 2 2 V +V +V +V +V 01 . . . 111) from the ideal (REF IN – 3/2 LSB) after the bipolar 2 3 4 5 6 THD (dB)= 20 log zero error has been adjusted out. V 1 Bipolar Zero Error (AD7892-1, AD7892-3) where V is the rms amplitude of the fundamental and V , V , 1 2 3 This is the deviation of the midscale transition (all 1s to all 0s) V , V and V are the rms amplitudes of the second through the 4 5 6 from the ideal (AGND – 1/2 LSB). sixth harmonics. Unipolar Offset Error (AD7892-2) Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000 to Peak harmonic or spurious noise is defined as the ratio of the 00 . . . 001) from the ideal (AGND + 1/2 LSB). rms value of the next largest component in the ADC output Negative Full-Scale Error (AD7892-1) spectrum (up to f /2 and excluding dc) to the rms value of the S This is the deviation of the first code transition (10 . . . 000 to fundamental. Normally, the value of this specification is deter- 10 . . . 001) from the ideal –4 × REF IN + 1/2 LSB (±10 V mined by the largest harmonic in the spectrum, but for parts range) or –2 × REF IN + 1/2 LSB (±5 V range) after bipolar where the harmonics are buried in the noise floor, it will be a zero error has been adjusted out. noise peak. Negative Full-Scale Error (AD7892-3) Intermodulation Distortion This is the deviation of the first code transition (10 . . . 000 to With inputs consisting of sine waves at two frequencies, fa and 10 . . . 001) from the ideal – REF IN + 1/2 LSB after bipolar fb, any active device with nonlinearities will create distortion zero error has been adjusted out. products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for Track/Hold Acquisition Time which neither m nor n are equal to zero. For example, the sec- Track/Hold acquisition time is the time required for the output ond order terms include (fa + fb) and (fa – fb), while the third of the track/hold amplifier to reach its final value, within ±1/2 LSB, order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and after the end of conversion (the point at which the track/hold (fa – 2fb). returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the V IN The AD7892 is tested using two input frequencies away from input of the AD7892. It means that the user must wait for the the bottom end of the input bandwidth. In this case, the second duration of the track/hold acquisition time after the end of con- and third order terms are of different significance. The second version or after a step input change to V before starting another IN order terms are usually distanced in frequency from the original conversion, to ensure that the part operates to specification. sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. –8– REV. C AD7892 CIRCUIT DESCRIPTION specified with a +2.5 V reference voltage. Errors in the refer- The AD7892 is a fast, 12-bit single supply A/D converter. It ence source will result in gain errors in the AD7892’s transfer provides the user with signal scaling, track/hold, reference, A/D function and will add to the specified full-scale errors on the converter and versatile interface logic functions on a single chip. part. On the AD7892-1 and AD7892-3, it will also result in an offset error injected in the attenuator stage. The signal scaling on the AD7892-1 allows the part to handle either ±5 V or ±10 V input signals while operating from a single The AD7892 contains an on-chip +2.5 V reference. To use this +5 V supply. The AD7892-2 handles a 0 V to +2.5 V analog reference as the reference source for the AD7892, simply con- input range, while signal scaling on the AD7892-3 allows it to nect a 0.1 µF disc ceramic capacitor from the REF OUT/ handle ±2.5 V input signals when operating from a single supply. REF IN pin to AGND. The voltage that appears at this pin is The part requires a +2.5 V reference which can be provided from internally buffered before being applied to the ADC. If this the part’s own internal reference or from an external reference reference is required for use external to the AD7892, it should source. be buffered as the part has a FET switch in series with the refer- Conversion is initiated on the AD7892 by pulsing the CONVST ence output resulting in a source impedance for this output of input. On the rising edge of CONVST, the track/hold goes 5.5 kΩ nominal. The tolerance on the internal reference is ±10 mV at 25°C with a typical temperature coefficient of from track mode to hold mode and the conversion sequence is started. At the end of conversion (falling edge of EOC), the 25 ppm/°C and a maximum error over temperature of ±25 mV. track/hold returns to tracking mode and the acquisition time If the application requires a reference with a tighter tolerance or begins. Conversion time for the part is 1.47 µs (AD7892-3) and the AD7892 needs to be used with a system reference, then the the track/hold acquisition time is 200 ns (AD7892-3). This allows user has the option of connecting an external reference to this the AD7892-3 to operate at throughput rates up to 600 kSPS. REF OUT/REF IN pin. The external reference will effectively The AD7892-1 and AD7892-2 are specified with a 1.6µs con- overdrive the internal reference and thus provide the reference version and 400 ns acquisition time allowing a throughput rate source for the ADC. The reference input is buffered before of 500 kSPS. being applied to the ADC with the maximum input current is Track/Hold Section ±100 µA. Suitable reference sources for the AD7892 include the The track/hold amplifier on the AD7892 allows the ADC to AD680, AD780 and REF43 precision +2.5 V references. accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater INTERFACING The part provides two interface options, a 12-bit parallel inter- than the Nyquist rate of the ADC even when the ADC is oper- ated at its maximum throughput rate of 600 kHz (i.e., the track/ face and a three-wire serial interface. The required interface hold can handle input frequencies in excess of 300 kHz). mode is selected via the MODE pin. The two interface modes are discussed in the following sections. The track/hold amplifier acquires an input signal to 12-bit accu- racy in less than 200 ns. The operation of the track/hold is Parallel Interface Mode essentially transparent to the user. The track/hold amplifier The parallel interface mode is selected by tying the MODE goes from its tracking mode to its hold mode on the rising edge input to a logic high. Figure 2 shows a timing diagram illustrat- of CONVST. The aperture time for the track/hold (i.e., the ing the operational sequence of the AD7892. The on-chip delay time between the external CONVST signal and the track/ track/hold goes into hold mode, and conversion is initiated on hold actually going into hold) is typically 15 ns. At the end of the rising edge of the CONVST signal. When conversion is complete, the end of conversion line (EOC) pulses low to indi- conversion, the part returns to its tracking mode. The acquisi- tion time of the track/hold amplifier begins at this point. cate that new data is available in the AD7892’s output register. This EOC line can be used to drive an edge-triggered interrupt Reference Section of a microprocessor. The falling edge of the RD signal should The AD7892 contains a single reference pin, labelled REF OUT/ occur 200 ns prior to the next rising edge of CONVST. CS and REF IN, which either provides access to the part’s own +2.5 V RD going low accesses the 12-bit conversion result. In systems reference or to which an external +2.5 V reference can be con- where the part is interfaced to a gate array or ASIC, this EOC nected to provide the reference source for the part. The part is CONVST (I) t ACQ t 1 t 2 EOC (O) t CONV t 9 t 3 CS (I) t 4 t 8 t 5 RD (I) t 7 t 6 THREE-STATE THREE-STATE VALID DB0–DB11 (O) DATA NOTE: I = INPUT; O = OUTPUT Figure 2. Parallel Mode Timing Diagram REV. C –9– AD7892 pulse can be applied to the CS and RD inputs to latch data out CONVST. For the AD7892-1 and AD7892-2, a serial read of the AD7892 and into the gate array or ASIC. This eliminates should also be avoided within 400 ns of the rising edge of the logic required in the gate array or ASIC to recognize the end CONVST. This limits the maximum achievable throughput of conversion and generate the read signal for the AD7892. To rate in serial mode (assuming 20 MHz serial clock) to 400 kSPS obtain optimum performance from the AD7892, it is not recom- for the AD7892-3 and 357 kSPS for the AD7892-1 and mended to tie CS and RD permanently low as this keeps the AD7892-2. three-state active during conversion. Analog Input Section Serial Interface Mode The AD7892 is offered as three part types allowing for four The AD7892 is configured for serial mode interfacing by tying different analog input voltage ranges. The AD7892-1 handles the MODE input low. It provides for a three-wire, serial link either ±5 V or ±10 V input voltage ranges. The AD7892-2 between the AD7892 and industry-standard microprocessors, handles a 0 V to +2.5 V input voltage range while the AD7892-3 microcontrollers and digital signal processors. SCLK and RFS handles an input range of ±2.5 V. of the AD7892 are inputs, and the AD7892’s serial interface is AD7892-1 designed for direct interface to systems that provide a serial Figure 4 shows the analog input section for the AD7892-1. The clock input that is synchronized to the serial data output includ- analog input range is pin-strappable (using V ) for either ±5V IN2 ing microcontrollers such as the 80C51, 87C51, 68HC11 and or ±10 V on the V input. With V connected to AGND, the IN1 IN2 68HC05 and most digital signal processors. input range on V is ±10 V, and the input resistance on V is IN1 IN1 Figure 3 shows the timing diagram for reading from the AD7892 15 kΩ nominal. With V connected to V , the input range on IN2 IN1 in the serial interface mode. RFS goes low to access data from V is ±5 V, and the input resistance on V is 8 kΩ nominal. IN1 IN1 the AD7892. The serial clock input does not have to be con- As a result, the V and V inputs should be driven from a IN1 IN2 tinuous. The serial data can be accessed in a number of bytes. low impedance source. The resistor attenuator stage is followed However, RFS must remain low for the duration of the data by the high input impedance stage of the track/hold amplifier. transfer operation. Sixteen bits of data are transmitted with four This resistor attenuator stage allows the input voltage to go to leading zeros followed by the 12-bit conversion result starting ±17 V without damaging the AD7892-1. with the MSB. Serial data is clocked out of the device on the rising edge of SCLK. Old data is guaranteed to be valid for 5 ns +2.5 after this edge. This is useful for high speed serial clocks where REFERENCE 2k� the access time of the part would not allow sufficient set-up time REF OUT/ for the data to be accepted on the falling edge of the clock. In REF IN this case, care must be taken that RFS does not go just prior to a rising edge of SCLK. For slower serial clocks data is valid on TO ADC REFERENCE the falling edge of SCLK. At the end of the read operation, the 3.25k� CIRCUITRY SDATA line is three-stated by a rising edge on either the SCLK 13k� TO HIGH or RFS inputs, whichever occurs first. Serial data cannot be V IN1 IMPEDANCE read during conversion to avoid feedthrough problems from the 13k� SHA INPUT 6.5k� V IN2 serial clock to the conversion process. For optimum perfor- mance of the AD7892-3, a serial read should also be avoided within 200 ns of the rising edge of CONVST to avoid feedthrough AGND into the track/hold during its acquisition time. The serial read should, therefore, occur between the end of conversion (EOC Figure 4. AD7892-1 Analog Input Structure falling edge) and 200 ns prior to the next rising edge of RFS (I) t 10 t 12 t 16 SCLK (I) t t 17 13 t t 14 t 11 17A t 15 FOUR LEADING ZEROS DB11 DB10 DB0 SDATA (O) THREE- NOTE: STATE I = INPUT; O = OUTPUT Figure 3. Serial Mode Timing Diagram –10– REV. C AD7892 The designed code transitions occur midway between successive AD7892-3 integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs). Output Figure 5 shows the analog input section for the AD7892-3. The coding is two’s complement binary with 1 LSB = FSR/4096 = analog input range is ±2.5 V on the V input. The V input IN1 IN2 20 V/4096 = 4.88 mV for the ±10 V range and 1 LSB = FSR/ can be left unconnected but if it is connected to a potential then 4096 = 10 V/4096 = 2.44 mV for the ±5 V range. The ideal that potential must be AGND. The input resistance on the V IN1 input/output transfer function for the AD7892-1 is shown in is 1.8 kΩ nominal. As a result, the V input should be driven IN1 Table I. from a low impedance source. The resistor attenuator stage is followed by the high input impedance stage of the track/hold AD7892-2 amplifier. This resistor attenuator stage allows the input voltage The analog input section for the AD7892-2 contains no biasing to go to ±7 V without damaging the AD7892-3. resistors. The analog input looks directly into the track/hold input stage. The analog input range on the V input is 0 V to The designed code transitions occur midway between succes- IN1 +2.5 V. The V input can be left unconnected but if it is sive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs). IN2 connected to a potential then that potential must be AGND. Output coding is two’s complement binary with 1 LSB = FSR/ The V input connects directly to the input sampling capacitor 4096 = 5 V/4096 = 1.22 mV with REF IN = +2.5 V. The ideal IN1 of the AD7892-2’s track/hold. The value of this input sampling input/output transfer function for the AD7892-3 is shown in capacitor is nominally 10 pF. Table III. Once again, the designed code transitions occur midway be- tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, +2.5 5/2 LSBs). Output coding is straight (natural) binary with REFERENCE 2k� 1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/ REF OUT/ REF IN output transfer function for the AD7892-2 is shown in Table II. TO ADC Table I. Ideal Input/Output Code Table for the AD7892-1 REFERENCE 3.25k� CIRCUITRY Digital Output 3.25k� TO HIGH Analog Input Code Transition V IN1 IMPEDANCE 1, 2 3 SHA INPUT +FSR/2 – 3/2 LSB (9.99268 or 4.99634) 011 . . . 110 to 011 . . . 111 V * IN2 +FSR/2 – 5/2 LSBs (9.98779 or 4.99390) 011 . . . 101 to 011 . . . 110 +FSR/2 – 7/2 LSBs (9.98291 or 4.99146) 011 . . . 100 to 011 . . . 101 AGND AGND + 3/2 LSB (0.00732 or 0.00366) 000 . . . 001 to 000 . . . 010 AGND + 1/2 LSB (0.00244 or 0.00122) 000 . . . 000 to 000 . . . 001 * UNCONNECTED INTERNALLY ON THE AD7892-3 AGND – 1/2 LSB (–0.00244 or –0.00122) 111 . . . 111 to 000 . . . 000 AGND – 3/2 LSB (–0.00732 or –0.00366) 111 . . . 110 to 111 . . . 111 Figure 5. AD7892-3 Analog Input Structure –FSR/2 + 5/2 LSB (–9.98779 or –4.99390) 100 . . . 010 to 100 . . . 011 –FSR/2 + 3/2 LSB (–9.99268 or –4.99634) 100 . . . 001 to 100 . . . 010 Table III. Ideal Input/Output Code Table for the AD7892-3 –FSR/2 + 1/2 LSB (–9.99756 or –4.99878) 100 . . . 000 to 100 . . . 001 Digital Output NOTES 1 Analog Input Code Transition FSR is full-scale range and REF IN = +2.5 V, is 20 V for the ±10 V range and 10 V for the ±5 V range. 1, 2 +FSR/2 – 3/2 LSB (2.49817) 011 . . . 110 to 011 . . . 111 2 1 LSB = FSR/4096 = 4.88 mV (±10 V range) and 2.44 mV (±5 V range) with REF +FSR/2 – 5/2 LSBs (2.49695) 011 . . . 110 to 011 . . . 110 IN = +2.5 V. 3 +FSR/2 – 7/2 LSBs (2.49573) 011 . . . 110 to 011 . . . 101 ± 10 V range or ±5 V range. AGND + 3/2 LSB (0.00183) 000 . . . 001 to 000 . . . 010 AGND + 1/2 LSB (0.00061) 000 . . . 000 to 000 . . . 001 AGND – 1/2 LSB (–0.00061) 111 . . . 111 to 000 . . . 000 Table II. Ideal Input/Output Code Table for the AD7892-2 AGND – 3/2 LSB (–0.00183) 111 . . . 110 to 111 . . . 111 Digital Output –FSR/2 + 5/2 LSB (–2.49695) 100 . . . 010 to 100 . . . 011 Analog Input Code Transition –FSR/2 + 3/2 LSB (–2.49817) 100 . . . 001 to 100 . . . 010 1, 2 –FSR/2 + 1/2 LSB (–2.49939) 100 . . . 000 to 100 . . . 001 +FSR – 3/2 LSB (2.499084 V) 111 . . . 110 to 111 . . . 111 +FSR – 5/2 LSBs (2.498474 V) 111 . . . 110 to 111 . . . 110 NOTES 1 FSR is full-scale range and is 5 V with REF IN = +2.5 V. +FSR – 7/2 LSBs (2.497864 V) 111 . . . 100 to 111 . . . 101 2 1 LSB = FSR/4096 = 1.22 mV with REF IN = +2.5 V. AGND + 5/2 LSB (0.001526 V) 000 . . . 010 to 010 . . . 011 AGND + 3/2 LSB (0.00916 V) 000 . . . 001 to 001 . . . 010 AGND + 1/2 LSB (0.000305 V) 000 . . . 000 to 000 . . . 001 NOTES 1 FSR is full-scale range and is 2.5 V with REF IN = +2.5 V. 2 1 LSB = FSR/4096 = 0.61 mV with REF IN = +2.5 V. REV. C –11– AD7892 MICROPROCESSOR INTERFACING EOC Pulse Provides CS and RD The AD7892 features both high speed parallel and serial inter- Figure 8 shows a parallel interface between the AD7892 and a faces, allowing considerable flexibility in interfacing to micro- gate array or ASIC. CONVST starts conversion and at the end processor systems. To obtain optimum performance from the of conversion the falling edge of the EOC output provides the part, data should not be read during conversion and this limits CS and RD pulse to latch data out of the AD7892 and into the the achievable throughput rate in serial mode to 400 kSPS for gate array/ASIC. This scheme allows for the fastest possible the AD7892-3. throughput rate with the part as no time is lost in interrupt service routines and as soon as data is available from the part it Figures 6, 7 and 9 show some typical interface circuits between is transferred out of it. the AD7892 and popular DSP processors. Figure 8 shows an interface between the part and a gate array or ASIC where data is clocked into the ASIC by the AD7892 itself at the end of TIMER conversion. In all cases, the CONVST signal is generated from an external timer to ensure equidistant sampling. AD7892 AD7892 to ADSP-2101 Interface GATE Figure 6 shows a parallel interface between the AD7892 and the ARRAY/ASIC CONVST ADSP-2101 DSP processor. CONVST starts conversion and at the end of conversion the falling edge of the EOC output pro- EOC ENABLE vides an interrupt request to the ADSP-2101. RD CS TIMER DMA13–DMA0 ADDRESS BUS DB11–DB0 DATA BUS DB11–DB0 ADSP-2101 ADDRESS DECODE LOGIC AD7892 DMS EN Figure 8. AD7892 to Gate Array/ASIC Interface CONVST AD7892 to DSP56000 Interface CS Figure 9 shows a serial interface between the AD7892 and the DSP56000 DSP processor. CONVST starts conversion and at IRQn EOC the end of conversion the falling edge of the EOC output pro- RD RD vides an interrupt request to the DSP56000. DATA BUS DMD15–DMD0 DB11–DB0 TIMER AD7892 DSP56000 Figure 6. AD7892 to ADSP-2101 CONVST AD7892 to TMS320C25 Interface IRQA EOC Figure 7 shows a parallel interface between the AD7892 and the SCLK SCK TMS320C25 DSP processor. CONVST starts conversion and SRD SDATA at the end of conversion the falling edge of the EOC output RFS provides an interrupt request to the TMS320C25. SC1 TIMER Figure 9. AD7892 to DSP56000 Interface A15–A0 ADDRESS BUS TMS320C25 ADDRESS DECODE CS LOGIC IS EN CONVST READY G2 AD7892 MSC STRB RD R/W EOC INT D15–D0 DATA BUS DB11–DB0 Figure 7. AD7892 to TMS320C25 Interface –12– REV. C AD7892 Grounding and Layout Good decoupling is important when using high resolution ADCs. The AD7892 has a single supply voltage pin, V , which sup- All analog supplies should be decoupled with 10µF tantalum in DD plies both the analog and digital circuitry on the part. For opti- parallel with 0.1µF capacitors to AGND. To achieve the best mum performance from the part, it is recommended that this from these decoupling components, they have to be placed as +5 V is taken from the +5 V analog supply in the system. The close as possible to the device, ideally right up against the device. analog and digital grounds to the AD7892 are independent and All logic chips should be decoupled with 0.1 µF disc ceramic separately pinned out to minimize coupling between the analog capacitors to DGND. It is recommended that the system’s supply is used to supply the V for the AD7892. This and digital sections of the device. The part exhibits good immu- AV DD DD nity to noise on the supplies but care must still be taken with supply should have the recommended analog supply decoupling regard to grounding and layout especially when using switching capacitors between the V pin of the AD7892 and AGND and DD mode supplies. the recommended digital supply decoupling capacitor between the V pin of the AD7892 and DGND. DD The printed circuit board which houses the AD7892 should be designed such that the analog and digital sections are separated Evaluating the AD7892 Performance and confined to certain areas of the board. This facilitates the The recommended layout for the AD7892 is outlined in the use of ground planes which can be separated easily. A minimum evaluation board for the AD7892. The evaluation board package etch technique is generally best for ground planes as it gives the includes a fully assembled and tested evaluation board, docu- best shielding. Digital and analog ground planes should only be mentation and software for controlling the board from a PC joined in one place. If the AD7892 is the only device requiring using the EVAL-CONTROL BOARD. The EVAL-CONTROL an AGND to DGND connection, then the ground planes BOARD can be used in conjunction with the AD7892 evalua- should be connected at the AGND and DGND pins of the tion board, as well as many other Analog Devices evaluation AD7892. If the AD7892 is in a system where multiple devices boards ending in the CB designator. Using the EVAL-CONTROL require AGND to DGND connections, the connection should BOARD with the AD7892 evaluation board allows the user to still be made at one point only, a star ground point which evaluate the ac and dc performance of the AD7892 on a PC. should be established as close as possible to the AD7892. The software provided with the evaluation board allows the user Avoid running digital lines under the device as these will couple to perform ac (Fast Fourier Transform) and dc (histogram of noise onto the die. The analog ground plane should be allowed codes) tests on the AD7892. The evaluation board can also to run under the AD7892 to avoid noise coupling. The power be used in a stand-alone fashion without the EVAL-CONTROL supply lines to the AD7892 should use as large a trace as pos- BOARD but in this case, the user has to write their own software sible to provide low impedance paths and reduce the effects of to evaluate the part. There are two versions of the evaluation glitches on the power supply line. Fast switching signals like board available, one for the AD7892-2 and one for the AD7892-3. clocks should be shielded with digital ground to avoid radiating To order the AD7892-2 evaluation board, the order number is noise to other sections of the board and clock signals should EVAL-AD7892-2CB and to order the AD7892-3 evaluation never be run near the analog inputs. Avoid crossover of digital board, the order number is EVAL-AD7892-3CB. and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. REV. C –13– AD7892 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-24) 1.228 (31.19) 1.226 (31.14) 24 13 0.260 ± 0.001 (6.61 ± 0.03) 112 0.32 (8.128) 0.30 (7.62) PIN 1 0.130 (3.30) 0.128 (3.25) 0.011 (0.28) 0.07 (1.78) SEATING 0.02 (0.5) 0.11 (2.79) 0.009 (0.23) 15� PLANE 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) 0 Cerdip (Q-24) 0.005 (0.13) MIN 0.098 (2.49) MAX 24 13 0.310 (7.87) 0.220 (5.59) 1 12 0.320 (8.13) PIN 1 0.290 (7.37) 1.280 (32.51) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 0.200 (5.08) (3.81) MIN 0.125 (3.18) 0.015 (0.38) 0.023 (0.58) 0.100 (2.54) 0.070 (1.78) SEATING 15° 0.008 (0.20) PLANE BSC 0.014 (0.36) 0.030 (0.76) 0° SOIC (R-24) 0.614 (15.6) 0.598 (15.2) 24 13 1 12 0.1043 (2.65) PIN 1 0.0291 (0.74) � 45� 0.0926 (2.35) 0.0098 (0.25) 8� 0.050 (1.27) 0.050 0.019 (0.49) 0.012 (0.30) 0� 0.015 (0.40) SEATING (1.27) 0.014 (0.35) 0.013 (0.32) 0.004 (0.10) PLANE 0.009 (0.23) BSC –14– REV. C 0.299 (7.60) 0.291(7.40) 0.419 (10.65) 0.394 (10.00) PRINTED IN U.S.A. C1933c–2.5–6/00 (rev. C) 01359