ANALOG DEVICES AD7889

Low Voltage Controller for Touch Screens AD7879/AD7889 FEATURES FUNCTIONAL BLOCK DIAGRAM V /REF CC 4-wire touch screen interface 1.6 V to 3.6 V operation X– Y– X+ Y+ Median and averaging filter to reduce noise Automatic conversion sequencer and timer X+ X– User-programmable conversion parameters REF– REF– REF+ Auxiliary analog input/battery monitor (0.5 V to 5 V) Y+ 1 optional GPIO Y– Interrupt outputs (INT, PENIRQ) 12-BIT RESULT GND Touch-pressure measurement SAR ADC REGISTERS TEMPERATURE Wake-up on touch function SENSOR Shutdown mode: 6 μA maximum AD7879/ 12-ball, 1.6 mm × 2 mm WLCSP AD7879-1/ CONTROL REGISTERS AD7889/ 16-lead, 4 mm × 4 mm LFCSP AD7889-1 APPLICATIONS Personal digital assistants SEQUENCER SERIAL PORT AND TIMER Smart handheld devices TO RESULT Touch screen monitors REGISTERS Point-of-sale terminals CS/ DIN/ DOUT/ SCL Medical devices ADD0 ADD1 SDA Cell phones Figure 1. GENERAL DESCRIPTION The AD7879/AD7889 are 12-bit successive approximation The AD7879/AD7889 have a programmable pin that can operate analog-to-digital converters (SAR ADCs) with a synchronous as an auxiliary input to the ADC, as a battery monitor, or as a serial interface and low on-resistance switches for driving 4-wire GPIO. In addition, a programmable interrupt output can operate resistive touch screens. The AD7879/AD7889 work with a very in three modes: as a general-purpose interrupt to signal when low power supply—a single 1.6 V to 3.6 V supply—and feature new data is available (DAV), as an interrupt to indicate when throughput rates of 105 kSPS. The devices include a shutdown INT limits are exceeded ( ), or as a pen-down interrupt when the mode that reduces current consumption to less than 6 μA. PENIRQ screen is touched ( ). The AD7879/AD7889 offer temp- erature measurement and touch-pressure measurement. To reduce the effects of noise from LCDs and other sources, the AD7879/AD7889 contain a preprocessing block. The prepro- The AD7879 is available in a 12-ball, 1.6 mm × 2 mm WLCSP cessing function consists of a median filter and an averaging and in a 16-lead, 4 mm × 4 mm LFCSP. The AD7889 is available filter. The combination of these two filters provides a more robust in a backside-coated version of the WLCSP. Both parts support 2 solution, discarding the spurious noise in the signal and keeping an SPI interface (AD7879/AD7889) or an I C interface only the data of interest. The size of both filters is programmable. (AD7879-1/AD7889-1). Other user-programmable conversion controls include variable acquisition time and first conversion delay; up to 16 averages can be taken per conversion. The AD7879/AD7889 can run in slave mode or standalone (master) mode, using an automatic conversion sequencer and timer. Rev. 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AUX/VBAT/GPIO 6-TO-1 MUX FILTERING PENIRQ/INT/DAV 07667-001 AD7879/AD7889 TABLE OF CONTENTS Features .............................................................................................. 1 Auxiliary Input ........................................................................... 18 Applications ....................................................................................... 1 Battery Input ............................................................................... 18 Functional Block Diagram .............................................................. 1 Limit Comparison ...................................................................... 18 General Description ......................................................................... 1 GPIO ............................................................................................ 18 Revision History ............................................................................... 2 Conversion Timing ........................................................................ 20 Specifications ..................................................................................... 3 Register Map ................................................................................... 21 SPI Timing Specifications (AD7879/AD7889)......................... 4 Detailed Register Descriptions ..................................................... 22 2 I C Timing Specifications (AD7879-1/AD7889-1).................. 5 Control Registers ............................................................................ 26 Absolute Maximum Ratings ............................................................ 6 Control Register 1 ...................................................................... 26 Thermal Resistance ...................................................................... 6 Control Register 2 ...................................................................... 28 ESD Caution .................................................................................. 6 Control Register 3 ...................................................................... 29 Pin Configurations and Function Descriptions ........................... 7 Interrupts ..................................................................................... 30 Typical Performance Characteristics ............................................. 9 Synchronizing the AD7879/AD7889 to the Host CPU ........ 31 Terminology .................................................................................... 12 Serial Interface ................................................................................ 32 Theory of Operation ...................................................................... 13 SPI Interface ................................................................................ 32 2 Touch Screen Principles ............................................................ 13 I C-Compatible Interface .......................................................... 34 Measuring Touch Screen Inputs ............................................... 14 Grounding and Layout .................................................................. 37 Touch-Pressure Measurement .................................................. 15 Lead Frame Chip Scale Packages ............................................. 37 Temperature Measurement ....................................................... 15 WLCSP Assembly Considerations ........................................... 37 Median and Averaging Filters ....................................................... 17 Outline Dimensions ....................................................................... 38 AUX/VBAT/GPIO Pin ................................................................... 18 Ordering Guide .......................................................................... 39 REVISION HISTORY 11/10—Rev. B to Rev. C Changes to GPIO Interrupt Enable (Bit 12, Control Register 3, Changes to Table 2 ............................................................................ 3 Address 0x03) Section ................................................................... 19 Added Conversion Timing Section .............................................. 20 Changes to Table 13 ....................................................................... 22 Added Figure 34 .............................................................................. 29 Changes to ADC Channel (Control Register 1, Bits[14:12]) Section .............................................................................................. 26 1/10—Rev. A to Rev. B Changes to Power Management (Control Register 2, Updated Outline Dimensions ....................................................... 37 Bits[15:14]) Section ........................................................................ 27 Changes to Ordering Guide .......................................................... 38 Changes to DAV—Data Available Interrupt Section ................. 29 INT Changes to —Out-of-Limit Interrupt Section .................... 29 3/09—Rev. 0 to Rev. A Changes to Writing Data Section ................................................. 31 Added AD7889 and Backside-Coated WLCSP ......... Throughout Changes to Reading Data Section and Figure 40 ....................... 32 Change to Battery Monitor, Input Voltage Range Parameter ..... 3 Changes to Figure 41 ...................................................................... 33 Changes to Table 4 ............................................................................ 6 2 Changes to Writing Data over the I C Bus Section .................... 34 Added Thermal Resistance Section and Table 5; Changes to Figure 44 ...................................................................... 35 Renumbered Sequentially ................................................................ 6 Updated Outline Dimensions ....................................................... 37 Changes to Pin Configurations and Function Descriptions Changes to Ordering Guide. ......................................................... 38 Section ................................................................................................ 7 Added Table 7 .................................................................................... 8 10/08—Revision 0: Initial Version Changes to First Method Section ................................................. 15 Changes to Median and Averaging Filters Section .................... 17 Rev. C | Page 2 of 40 AD7879/AD7889 SPECIFICATIONS VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DC ACCURACY Resolution 12 Bits No Missing Codes 11 12 Bits 1 Integral Nonlinearity (INL) ±3 LSB LSB size = 390 µV. 1 Differential Nonlinearity (DNL) LSB size = 390 µV. Negative DNL −0.99 LSB Positive DNL 2 LSB 1, 2 Offset Error ±2 ±6 LSB 1, 2 Gain Error ±4 LSB 3 Noise 70 µV rms 3 Power Supply Rejection 60 dB Internal Clock Frequency 2 MHz Internal Clock Accuracy 1.8 2.2 MHz SWITCH DRIVERS 1 On Resistance Y+, X+ 6 Ω Y−, X− 5 Ω ANALOG INPUTS Input Voltage Range 0 V V CC DC Leakage Current ±0.1 µA Input Capacitance 30 pF Accuracy 0.3 % TEMPERATURE MEASUREMENT Temperature Range −40 +85 °C Resolution 0.3 °C 2 Accuracy ±2 °C Calibrated at 25°C. BATTERY MONITOR Input Voltage Range 0.5 5 V 3 Input Impedance 16 kΩ Accuracy 2 5 % Uncalibrated accuracy. LOGIC INPUTS (DIN, SCL, CS, SDA, GPIO) Input High Voltage, V 0.7 × V V INH CC Input Low Voltage, V 0.3 × V V INL CC Input Current, IIN 0.01 µA VIN = 0 V or VCC. 3 Input Capacitance, CIN 10 pF LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA, INT) Output High Voltage, VOH VCC − 0.2 V Output Low Voltage, VOL 0.4 V Floating-State Leakage Current ±0.1 µA 2 Floating-State Output Capacitance 5 pF 3 CONVERSION RATE Conversion Time 9.5 µs Including 2 µs of acquisition time, MAV filter off. 2 µs of additional time is required if MAV filter is on. Throughput Rate 105 kSPS Rev. C | Page 3 of 40 AD7879/AD7889 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VCC 1.6 2.6 3.6 V Specified performance. ICC Digital inputs = 0 V or VCC. Converting Mode 480 650 µA ADC on, PM = 10. Static 406 µA ADC and temperature sensor are off; the reference and oscillator are on; PM = 01 or 11. Shutdown Mode 0.5 6 µA PM = 00. 1 See the Terminology section. 2 Guaranteed by characterization; not production tested. 3 Sample tested at 25°C to ensure compliance. SPI TIMING SPECIFICATIONS (AD7879/AD7889) V = 1.6 V to 3.6 V, T = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are CC A specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.4 V. R F CC Table 2. 1 Parameter Limit Unit Description f 5 MHz max SCL t 5 ns min CS falling edge to first SCL falling edge 1 t2 20 ns min SCL high pulse width t3 20 ns min SCL low pulse width t4 15 ns min DIN setup time t 15 ns min DIN hold time 5 t 20 ns max DOUT access time after SCL falling edge 6 t7 16 ns max CS rising edge to DOUT high impedance t8 15 ns min SCL rising edge to CS high 1 Guaranteed by design; not production tested. CS t 1 t t 2 8 t 3 1 2 3 15 16 1 2 15 16 SCL t 4 t 5 LSB MSB DIN t 6 t 7 DOUT MSB LSB Figure 2. Detailed SPI Timing Diagram Rev. C | Page 4 of 40 07667-002 AD7879/AD7889 2 I C TIMING SPECIFICATIONS (AD7879-1/AD7889-1) VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are timed from a voltage level of 1.4 V. Table 3. 1 Parameter Limit Unit Description fSCL 400 kHz max t1 0.6 µs min Start condition hold time, tHD; STA t2 1.3 µs min Clock low period, tLOW t 0.6 µs min Clock high period, t 3 HIGH t 100 ns min Data setup time, t 4 SU; DAT t5 300 ns min Data hold time, tHD; DAT t6 0.6 µs min Stop condition setup time, tSU; STO t7 0.6 µs min Start condition setup time, tSU; STA t 1.3 µs min Bus-free time between stop and start conditions, t 8 BUF t 300 ns max Clock/data rise time R t 300 ns max Clock/data fall time F 1 Guaranteed by design; not production tested. t t R F t t 1 2 SCL t 3 t t 1 7 t 6 t 5 t 4 SDA t 8 STOP START START STOP 2 Figure 3. Detailed I C Timing Diagram Rev. C | Page 5 of 40 07667-003 AD7879/AD7889 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Table 4. soldered in a circuit board for surface-mount packages. Parameter Rating V to GND −0.3 V to +3.6 V CC Table 5. Thermal Resistance Analog Input Voltage to GND −0.3 V to V + 0.3 V CC 1 Package Type θ Unit JA AUX/VBAT to GND −0.3 V to +5 V 12-Ball WLCSP 75 °C/W Digital Input Voltage to GND −0.3 V to VCC + 0.3 V 16-Lead LFCSP 30.4 °C/W Digital Output Voltage to GND −0.3 V to VCC + 0.3 V 1 4-layer board. 1 Input Current to Any Pin Except Supplies 10 mA ESD Rating (X+, Y+, X−, Y−) 200µA I OL Air Discharge Human Body Model 15 kV Contact Human Body Model 10 kV ESD Rating (All Other Pins) TO OUTPUT 1.4V PIN Human Body Discharge 4 kV C L 50pF Field-Induced Charged Device Model 1 kV Machine Model 0.2 kV 200µA I OH Operating Temperature Range −40°C to +85°C Figure 4. Circuit Used for Digital Timing Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Power Dissipation ESD CAUTION WLCSP (4-Layer Board) 866 mW LFCSP (4-Layer Board) 2.138 W IR Reflow Peak Temperature 260°C (±0.5°C) Lead Temperature (Soldering 10 sec) 300°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 6 of 40 07667-004 AD7879/AD7889 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 BALL A1 INDICATOR INDICATOR 1 2 3 1 2 3 AUX/ AUX/ VBAT/ VBAT/ V /REF V /REF CC X+ CC X+ GPIO GPIO A A PENIRQ/ PENIRQ/ Y+ Y+ INT/DAV CS INT/DAV ADD0 B B DOUT DIN X– SDA ADD1 X– C C SCL GND Y– SCL GND Y– D D TOP VIEW TOP VIEW (BALL SIDE DOWN) (BALL SIDE DOWN) Not to Scale Not to Scale Figure 5. AD7879/AD7889 WLCSP Pin Configuration Figure 6. AD7879-1/AD7889-1 WLCSP Pin Configuration Table 6. Pin Function Descriptions, WLCSP Ball No. AD7879/ AD7879-1/ AD7889 AD7889-1 Mnemonic Description 1A 1A AUX/VBAT/GPIO This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure- ment input to the ADC (VBAT), or as a general-purpose digital input/output (GPIO). 1B 1B PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure- ment exceeds the preprogrammed limits (INT), or when new data is available in the registers (DAV). Active low, internal 50 kΩ pull-up resistor. 1C N/A DOUT SPI Serial Data Output for the AD7879/AD7889. 2 N/A 1C SDA I C Serial Data Input and Output for the AD7879-1/AD7889-1. 1D 1D SCL Serial Interface Clock Input. 2A 2A V /REF Power Supply Input and ADC Reference. CC 2B N/A CS Chip Select for the SPI Serial Interface on the AD7879/AD7889. Active low. 2 N/A 2B ADD0 I C Address Bit 0 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine an address for the AD7879-1/AD7889-1 (see Table 25). 2C N/A DIN SPI Serial Data Input to the AD7879/AD7889. 2 N/A 2C ADD1 I C Address Bit 1 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine an address for the AD7879-1/AD7889-1 (see Table 25). 2D 2D GND Ground. Ground reference point for all circuitry on the AD7879/AD7889. All analog input signals and any external reference signal should be referred to this voltage. 3A 3A X+ Touch Screen Input Channel. 3B 3B Y+ Touch Screen Input Channel. 3C 3C X− Touch Screen Input Channel. 3D 3D Y− Touch Screen Input Channel. Rev. C | Page 7 of 40 07667-005 07667-006 AD7879/AD7889 PIN 1 PIN 1 INDICATOR 12 PENIRQ/INT/DAV INDICATOR 12 PENIRQ/INT/DAV Y+ 1 Y+ 1 NC 2 AD7879 11 NC NC 2 AD7879-1 11 NC TOP VIEW TOP VIEW NC 3 10 NC NC 3 10 NC (Not to Scale) (Not to Scale) X– 4 9 DOUT X– 4 9 SDA NOTES NOTES 1. NC = NO CONNECT 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. AD7879 LFCSP Pin Configuration Figure 8. AD7879-1 LFCSP Pin Configuration Table 7. Pin Function Descriptions, LFCSP Pin No. AD7879 AD7879-1 Mnemonic Description 1 1 Y+ Touch Screen Input Channel. 2, 3, 10, 11 2, 3, 10, 11 NC No Connect. 4 4 X− Touch Screen Input Channel. 5 5 Y− Touch Screen Input Channel. 6 N/A DIN SPI Serial Data Input to the AD7879. 2 N/A 6 ADD1 I C Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1 (see Table 25). 7 7 GND Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and any external reference signal should be referred to this voltage. 8 8 SCL Serial Interface Clock Input. 9 N/A DOUT SPI Serial Data Output for the AD7879. 2 N/A 9 SDA I C Serial Data Input and Output for the AD7879-1. 12 12 PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure- ment exceeds the preprogrammed limits (INT), or when new data is available in the registers (DAV). Active low, internal 50 kΩ pull-up resistor. 13 13 AUX/VBAT/GPIO This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure- ment input to the ADC (VBAT), or as a general-purpose digital input/output (GPIO). 14 N/A CS Chip Select for the SPI Serial Interface on the AD7879. Active low. 2 N/A 14 ADD0 I C Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1 (see Table 25). 15 15 VCC/REF Power Supply Input and ADC Reference. 16 16 X+ Touch Screen Input Channel. EP Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. Rev. C | Page 8 of 40 07667-007 07667-008 Y– 5 16 X+ V /REF DIN 6 15 CC GND 7 14 CS 13 AUX/VBAT/GPIO SCL 8 Y– 5 16 X+ V /REF ADD1 6 15 CC GND 7 14 ADD0 SCL 8 13 AUX/VBAT/GPIO AD7879/AD7889 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 2.6 V, fSCL = 2 MHz, unless otherwise noted. 475 1.0 470 0.8 465 0.6 460 0.4 455 0.2 2.6V 450 0 3.6V 445 –0.2 440 –0.4 1.6V 435 –0.6 430 –0.8 425 –1.0 –40 –25 –10 10 25 40 55 70 85 –40 –25 –10 10 25 40 55 70 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Supply Current vs. Temperature Figure 12. Change in ADC Gain vs. Temperature 700 1.0 0.8 600 0.6 500 0.4 1.6V 0.2 400 2.6V 0 300 –0.2 3.6V –0.4 200 –0.6 100 –0.8 0 –1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 –40 –25 –10 10 25 40 55 70 85 V (V) TEMPERATURE (°C) CC Figure 10. Supply Current vs. VCC Figure 13. Change in ADC Offset vs. Temperature 4.0 2.0 3.5 1.5 1.0 3.0 0.5 2.5 0 2.0 –0.5 1.5 –1.0 1.0 –1.5 0.5 0 –2.0 –40 –25 –10 10 25 50 75 100 0 512 1024 1536 2048 2560 3072 3584 4096 TEMPERATURE (°C) CODE Figure 11. Full Power-Down IDD vs. Temperature Figure 14. ADC INL Rev. C | Page 9 of 40 CURRENT (µA) CURRENT (µA) CURRENT (µA) 07667-012 07667-010 07667-009 INL (LSB) OFFSET VARIATION (LSB) GAIN ERROR VARIATION (LSB) 07667-013 07667-011 07667-014 AD7879/AD7889 1.0 6.0 0.8 5.5 0.6 0.4 5.0 0.2 0 4.5 –0.2 4.0 –0.4 X+ TO V CC –0.6 Y+ TO V CC 3.5 X– TO GND –0.8 Y– TO GND –1.0 3.0 1 501 1001 1501 2001 2501 3001 3501 4001 –40 –25 –10 10 25 40 55 70 85 CODE TEMPERATURE (°C) Figure 15. ADC DNL Figure 17. Switch On Resistance vs. Temperature (X+, Y+: Pin to VCC; X−, Y−: Pin to GND) 7 2370 2369 6 2368 5 2367 2366 4 2365 3 2364 X+ TO V CC Y+ TO V CC 2363 2 X– TO GND Y– TO GND 2362 1 2361 0 2360 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 –40 –25 –15 –5 5 15 25 35 45 55 65 75 85 V (V) TEMPERATURE (°C) CC Figure 16. Switch On Resistance vs. V Figure 18. ADC Code vs. Temperature (Fixed Analog Input) CC (X+, Y+: Pin to V ; X−, Y−: Pin to GND) CC Rev. C | Page 10 of 40 DNL (LSB) R (Ω) ON 07667-016 07667-015 ADC CODE (Decimal) R (Ω) ON 07667-017 07667-018 AD7879/AD7889 1400 MEAN: –1.98893 SD: 0.475534 250 1200 1000 200 800 150 600 100 400 50 200 0 0 –4 –3 –2 –1 0 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 ERROR (%) V (V) CC Figure 19. Temperature Code vs. V for 25°C Figure 21. Typical Uncalibrated Accuracy for the Battery Channel (25°C) CC 0 SNR = 61.58dB THD = 72.34dB –20 –40 –60 –80 –100 –120 –140 –160 FREQUENCY (Hz) Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling Rate and 1 kHz Input Frequency Rev. C | Page 11 of 40 INPUT TONE AMPLITUDE (dB) TEMPERATURE (Code) 0 1603 3206 4809 6412 8015 9618 11221 12824 14427 16030 17633 19236 20839 22442 24045 25648 27251 28854 30457 32060 33663 35266 36869 07667-020 07667-019 NUMBER OF UNITS 07667-021 AD7879/AD7889 TERMINOLOGY Gain Error Differential Nonlinearity (DNL) Gain error is the deviation of the last code transition DNL is the difference between the measured and the ideal (111 … 110 to 111 … 111) from the ideal (VREF − 1 LSB) 1 LSB change between any two adjacent codes in the ADC. after the offset error has been calibrated out. Integral Nonlinearity (INL) Offset Error INL is the maximum deviation from a straight line passing Offset error is the deviation of the first code transition through the endpoints of the ADC transfer function. The (00 … 000 to 00 … 001) from the ideal (AGND + 1 LSB). endpoints of the transfer function are zero scale at 1 LSB below the first code transition and full scale at 1 LSB above the last On Resistance code transition. On resistance is a measure of the ohmic resistance between the drain and the source of the switch drivers. Rev. C | Page 12 of 40 AD7879/AD7889 THEORY OF OPERATION PLASTIC FILM WITH The AD7879/AD7889 are a complete 12-bit data acquisition TRANSPARENT, RESISTIVE COATING ON BOTTOM SIDE system for digitizing positional inputs from a 4-wire resistive CONDUCTIVE ELECTRODE Y+ ON BOTTOM SIDE touch screen. To support this function, data acquisition on the AD7879/AD7889 is highly programmable to ensure accurate and noise-free results from the touch screen. The core of the AD7879/AD7889 is a high speed, low power, 12-bit analog-to-digital converter (ADC) with an input multi- plexer, on-chip track-and-hold, and on-chip clock. Conversion X– results are stored in on-chip result registers. The results from Y– the auxiliary input or the battery input can be compared with high and low limits stored in limit registers to generate an out- X+ INT of-limit interrupt ( ). The AD7879/AD7889 also contain low resistance analog CONDUCTIVE ELECTRODE PLASTIC FILM WITH ON TOP SIDE TRANSPARENT, RESISTIVE switches to switch the X and Y excitation voltages to the touch COATING ON TOP SIDE screen and to the on-chip temperature sensor. The high speed LCD SCREEN SPI serial bus provides control of the devices, as well as com- Figure 22. Basic Construction of a Touch Screen munication with the devices. The AD7879-1/AD7889-1 are The Y layer has conductive electrodes running along the top 2 available with an I C interface. and bottom edges, allowing the application of an excitation Operating from a single supply from 1.6 V to 3.6 V, the AD7879/ voltage down the Y layer from top to bottom. AD7889 offer a throughput rate of 105 kHz. The device is avail- Provided that the layers are of uniform resistivity, the voltage able in a 1.6 mm × 2 mm, 12-ball wafer level chip scale package at any point between the two electrodes is proportional to the (WLCSP) and in a 4 mm × 4 mm, 16-lead lead frame chip scale horizontal position for the X layer and the vertical position for package (LFCSP). the Y layer. The AD7879/AD7889 have an on-chip sequencer that schedules When the screen is touched, the two layers make contact. If a sequence of preprogrammed conversions. The conversion only the X layer is excited, the voltage at the point of contact sequence starts automatically when the screen is touched or and, therefore, the horizontal position, can be sensed at one of at preset intervals, using the on-board timer. the Y layer electrodes. Similarly, if only the Y layer is excited, To ensure that the AD7879/AD7889 work well with different the voltage and, therefore, the vertical position, can be sensed touch screens, the user can select the acquisition time. A at one of the X layer electrodes. By switching alternately programmable delay ensures that the voltage on the touch between X and Y excitation and measuring the voltages, the screen settles before a measurement is taken. X and Y coordinates of the contact point can be determined. To help reduce noise in the system, the ADC takes up to 16 In addition to measuring the X and Y coordinates, it is also conversion results from each channel and writes the average of possible to estimate the touch pressure by measuring the the results to the register. To further improve the performance contact resistance between the X and Y layers. The AD7879/ of the AD7879/AD7889, the median filter can also be used if AD7889 are designed to facilitate this measurement. there is noise present in the system. TOUCH SCREEN PRINCIPLES A 4-wire touch screen consists of two flexible, transparent, resistive-coated layers that are normally separated by a small air gap (see Figure 22). The X layer has conductive electrodes running down the left and right edges, allowing the application of an excitation voltage across the X layer from left to right. Rev. C | Page 13 of 40 07667-022 AD7879/AD7889 Figure 23 shows an equivalent circuit of the analog input structure The voltage seen at the input to the ADC in Figure 24 is of the AD7879/AD7889, showing the touch screen switches, the R Y− V = V × (1) main analog multiplexer, the ADC, and the dual 3-to-1 multi- IN CC R YTOTAL plexer that selects the reference source for the ADC. The advantage of the single-ended method is that the touch V CC screen excitation voltage is switched off when the signal is acquired. Because a screen can draw over 1 mA, this is a significant consideration for a battery-powered system. X+ X– The disadvantage of the single-ended method is that voltage Y+ drops across the switches can introduce errors. Touch screens Y– can have a total end-to-end resistance ranging from 200 Ω to X– Y– GND X+ Y+ V CC INPUT 900 Ω. By taking the lowest screen resistance of 200 Ω and a MUX DUAL 3-TO-1 MUX typical switch resistance of 14 Ω, the user can reduce the apparen t AUX/VBAT/GPIO REF– REF+ excitation voltage to 200/228 × 100 = 87% of its actual value. In TEMPERATURE 12-BIT SUCCESSIVE IN+ SENSOR addition, the voltage drop across the low-side switch adds to the APPROXIMATION ADC WITH TRACK-AND-HOLD ADC input voltage. This introduces an offset into the input voltage; thus, it can never reach 0. Ratiometric Method Figure 23. Analog Input Structure The ratiometric method illustrated in Figure 25 shows the The AD7879/AD7889 can be set up to automatically convert negative input of the ADC reference connected to Y− and the either specific input channels or a sequence of channels. The positive input connected to Y+. Thus, the screen excitation results of the ADC conversions are stored in the result registers. voltage provides the reference for the ADC. The input of the ADC is connected to X+ to determine the Y position. When measuring the ancillary analog inputs (AUX, TEMP, or V CC VBAT), the ADC uses a VCC reference and the measurement is referred to GND. Y+ MEASURING TOUCH SCREEN INPUTS When measuring the touch screen inputs, it is possible to use REF+ INPUT X+ (VIA MUX) VCC as a reference or instead to use the touch screen excitation ADC voltage as the reference and to perform a ratiometric, differential TOUCH REF– SCREEN measurement. The differential method is the default method Y– DFR and is selected by clearing the SER/ bit (Bit 9 in Control Register 2) to 0. The single-ended method is selected by setting GND this bit to 1. Figure 25. Ratiometric Conversion of Touch Screen Inputs Single-Ended Method For greater accuracy, the ratiometric method has two significant Figure 24 illustrates the single-ended method for the Y position. advantages. One is that the reference to the ADC is provided For the X position, the excitation voltage is applied to X+ and from the actual voltage across the screen; therefore, any voltage X− and the voltage is measured at Y+. dropped across the switches has no effect. The other advantage V CC is that because the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. Y+ However, it must not change after the signal has been acquired. V REF The disadvantage of the ratiometric method is that the screen REF+ INPUT must be powered up at all times because it provides the reference X+ (VIA MUX) ADC voltage for the ADC. TOUCH REF– SCREEN Y– GND Figure 24. Single-Ended Conversion of Touch Screen Inputs Rev. C | Page 14 of 40 07667-024 07667-023 07667-025 AD7879/AD7889 Second Method TOUCH-PRESSURE MEASUREMENT The second method requires the user to know the resistance of The pressure applied to the touch screen by a pen or finger can the X-plate and Y-plate tablets. Three touch screen conversions also be measured with the AD7879/AD7889 using some simple are required: a measurement of the X position (XPOSITION), the calculations. The contact resistance between the X and Y plates Y position (YPOSITION), and the Z1 position. is measured, providing a good indication of the size of the depressed area and, therefore, the applied pressure. The area of The following equation also calculates the touch resistance the spot that is touched is proportional to the size of the object (R ): TOUCH touching it. The size of this resistance (RTOUCH) can be calculated R = R × (X /4096) × [(4096/Z1) − 1] − TOUCH XPLATE POSITION using two different methods. R × [1 − (Y /4096)] (3) YPLATE POSITION First Method The first method requires the user to know the total resistance TEMPERATURE MEASUREMENT of the X-plate tablet (R ). Three touch screen conversions are X A temperature measurement option called the single-conversion required: measurement of the X position, X (Y+ input); POSITION method is available on the AD7879/AD7889. The conversion measurement of the X+ input with the excitation voltage applied method requires only a single measurement on ADC Channel to Y+ and X− (Z1 measurement); and measurement of the Y− 001. The results are stored in the temperature conversion result input with the excitation voltage applied to Y+ and X− (Z2 register (Address 0x0D). The AD7879/AD7889 do not provide measurement). These three measurements are illustrated in an explicit output of the temperature reading; the system must Figure 26. perform some external calculations. This method is based on The AD7879/AD7889 have two special ADC channel settings an on-chip diode measurement. that configure the X and Y switches for the Z1 and Z2 measure- The acquisition time is fixed at 16 ms for temperature ments and store the results in the Z1 and Z2 result registers. The measurement. Z1 measurement is selected by setting the CHNL ADD[2:0] bits Conversion Method to 101 in Control Register 1 (Address 0x01); the result is stored The conversion method makes use of the fact that the tempera- in the X+ (Z1) result register (Address 0x0A). The Z2 measurement ture coefficient of a silicon diode is approximately −2.1 mV/°C. is selected by setting the CHNL ADD[2:0] bits to 100 in Control However, this small change is superimposed on the diode forward Register 1 (Address 0x01); the result is stored in the Y− (Z2) voltage, which can have a wide tolerance. Therefore, it is necessary result register (Address 0x0B). to calibrate by measuring the diode voltage at a known temperature The touch resistance (R ) can then be calculated using the TOUCH to provide a baseline from which the change in forward voltage following equation: with temperature can be measured. This method provides a RTOUCH = (RXPLATE) × (XPOSITION/4096) × [(Z2/Z1) − 1] (2) resolution of approximately 0.3°C and a predicted accuracy of ±2°C. MEASURE X POSITION The temperature limit comparison is performed on the result X+ Y+ TOUCH in the temperature conversion result register (Address 0x0D), RESISTANCE which is the measurement of the diode forward voltage. The values programmed into the high and low limits should be X– Y– referenced to the calibrated diode forward voltage to make MEASURE accurate limit comparisons. Z1 POSITION Y+ X+ TOUCH RESISTANCE Y– X– Y+ X+ TOUCH RESISTANCE Y– X– MEASURE Z2 POSITION Figure 26. Three Measurements Required for Touch Pressure Rev. C | Page 15 of 40 07667-026 AD7879/AD7889 Temperature Calculations Example If an explicit temperature reading in degrees Celsius is required, Using VCC = 2.5 V as reference, calculate for the single-measurement method as follows: −3 Degrees per LSB = (2.5/4096)/−2.1 × 10 = −0.291 1. Calculate the scale factor of the ADC in degrees per LSB. The ADC output is 983 decimal at 25°C, equivalent to a diode forward voltage of 0.6 V. Degrees per LSB = ADC LSB size/−2.1 mV = (V /4096)/−2.1 mV CC The ADC output at T is 880. AMB 2. Save the ADC output, D , at the calibration temperature, CAL ∆T = (880 − 983) × −0.291 = 30°C T . CAL TAMB = 25 + 30 = 55°C 3. Take the ADC reading, DAMB, at the temperature to be measured, TAMB. 4. Calculate the difference in degrees between TCAL and TAMB by ∆T = (DAMB − DCAL) × degrees per LSB 5. Add ∆T to TCAL. Rev. C | Page 16 of 40 AD7879/AD7889 MEDIAN AND AVERAGING FILTERS As explained in the Touch Screen Principles section, touch When both filter values are 00, only one measurement is screens are composed of two resistive layers, normally placed transferred to the register map. over an LCD screen. Because these layers are in close proximity The number specified with the MED1 and MED0 settings must to the LCD screen, noise can be coupled from the screen onto be greater than or equal to the number specified with the AVG1 these resistive layers, causing errors in the touch screen and AVG0 settings. If both settings specify the same number, positional measurements. the median filter is switched off. The AD7879/AD7889 contain a filtering block to process the Table 10. Median Averaging Filters (MAVF) Settings data and discard the spurious noise before sending the infor- Setting Function mation to the host. The purpose of this block is not only the M = A Median filter is disabled; output is the average of suppression of noise; the on-chip filtering also greatly reduces A converted results the host processing loading. M > A Output is the average of the middle A values from The processing function consists of two filters that are applied the array of M measurements to the converted results: the median filter and the averaging filter. M < A Not possible because the median filter size is always larger than the averaging window size The median filter suppresses the isolated out-of-range noise and sets the number of measurements to be taken. These measurements Example are arranged in a temporary array, where the first value is the smallest measurement and the last value is the largest measure- In this example, MED1, MED0 = 11 and AVG1, AVG0 = 10; ment. Bit 6 and Bit 5 in Control Register 2 (MED1, MED0) set the median filter has a window size of 16. This means that 16 the window of the median filter and, therefore, the number of measurements are taken and arranged in descending order in a measurements taken. temporary array. The averaging window size in this example is 8. The output is Table 8. Median Filter Size the average of the middle eight values of the 16 measurements MED1 MED0 Number of Measurements taken with the median filter. 0 0 Median filter disabled 0 1 4 1 0 8 12-BIT SAR MEDIAN AVERAGING 1 1 16 ADC FILTER FILTER CONVERTED 16 MEASUREMENTS AVERAGE OF The averaging filter size determines the number of values to RESULTS ARRANGED MIDDLE 8 VALUES average. Bit 8 and Bit 7 in Control Register 2 (AVG1, AVG0) 6 1 1 2 2 2 set the average to 2, 4, 8, or 16 samples. Only the final averaged 13 3 3 4 4 4 result is written into the result register. 16 5 5 5 6 6 15 7 7 Table 9. Averaging Filter Size 10 8 8 M = 16 A = 8 9 9 9 AVG1 AVG0 Filter Size 3 10 10 11 11 11 0 0 Average of 2 middle samples 8 12 12 1 13 13 0 1 Average of 4 middle samples 12 14 14 14 15 15 1 0 Average of 8 middle samples 7 16 16 1 1 Average of 16 samples Figure 27. Median and Averaging Filter Example It takes approximately 2 μs to sort the data in the rank filter (t in Figure 34); t adds to the update rate of the AD7879. SORT SORT Rev. C | Page 17 of 40 07667-027 AD7879/AD7889 AUX/VBAT/GPIO PIN The AUX/VBAT/GPIO pin on the AD7879/AD7889 can be LIMIT COMPARISON programmed as an auxiliary input to the ADC, as a battery The AUX measurement and the battery measurement can monitoring input, or as a general-purpose digital input/output. be compared with high and low limits stored on chip. An To select the auxiliary measurement, set the ADC channel INT out-of-limit result generates an alarm output at the pin address to 011 (Bits[14:12] in Control Register 1, Address 0x01). (PENIRQ/INT/DAV) when the INT function is enabled. The To select a battery measurement, set the ADC channel address high limit for both channels is stored in the AUX/VBAT high to 010. To select the GPIO function, set Bit 13 in Control limit register (Address 0x04), and the low limit is stored in the Register 2 (Address 0x02) to 1. AUX/VBAT low limit register (Address 0x05). AUXILIARY INPUT After a measurement from either AUX or VBAT is taken, it The AD7879/AD7889 have an auxiliary analog input, AUX. is compared with the high and low limits. The out-of-limit When the auxiliary input function is selected, the signal on the comparison sets a status bit in Control Register 3. Separate AUX pin (AUX/VBAT/GPIO) is connected directly to the ADC status bits for the high limit and the low limit indicate which input. This channel has a full-scale input range from 0 V to VCC. limit was exceeded. The interrupt sources can be masked by The ADC channel address for AUX is 011 (Bits[14:12] in clearing the corresponding enable bit in Control Register 3. Control Register 1, Address 0x01), and the result is stored in GPIO the AUX/VBAT result register (Address 0x0C). The AD7879/AD7889 have one general-purpose logic input/ BATTERY INPUT output pin, GPIO (AUX/VBAT/GPIO). To enable GPIO, set Bit The AD7879/AD7889 can monitor battery voltages from 0.5 V 13 in Control Register 2 to 1. If this bit is set to 0, the to 5 V when the BAT measurement is selected. Figure 28 shows AUX/VBAT function is active on the pin. If the GPIO is not a block diagram of a battery voltage monitored through the VBAT enabled, the other GPIO configuration bits have no effect. pin. The voltage to the V pin (V /REF) of the AD7879/AD7889 CC CC The GPIO data bit is Bit 12 in Control Register 2. is maintained at the desired supply voltage via the dc-to-dc Direction (Bit 11, Control Register 2, Address 0x02) converter, and the input to the converter is monitored. This voltage on VBAT is divided by 4 internally, so that a 5 V battery Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO). voltage is presented to the ADC as 1.25 V. To conserve power, When GPIO DIR = 0, the pin is an output. Setting or clearing the divider circuit is on only during the sampling of a voltage on the GPIO data bit (Bit 12 in Control Register 2) outputs a value VBAT. Note that the possible maximum input is 5 V. on the GPIO pin. The ADC channel address for VBAT is 010 (Bits[14:12] in When GPIO DIR = 1, the pin is an input. An input value on the Control Register 1, Address 0x01), and the result is stored in GPIO pin sets or clears the GPIO data bit (Bit 12 in Control the AUX/VBAT result register (Address 0x0C). Register 2). GPIO data register bits are read-only when GPIO DIR = 1. DC-TO-DC CONVERTER Polarity (Bit 10, Control Register 2, Address 0x02) BATTERY 0.5V TO 5V V CC When GPIO POL = 0, the GPIO pin is active low. When GPIO VBAT SW POL = 1, the GPIO pin is active high. How this bit affects the 0.125V TO 1.25V 12kΩ GPIO operation also depends on the GPIO DIR bit. ADC If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets 4kΩ the corresponding GPIO data register bit to 1. A 0 at the input pin clears the corresponding GPIO data bit to 0. If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data Figure 28. Block Diagram of Battery Measurement Circuit register bit puts a 1 on the corresponding GPIO output pin. A 0 The maximum battery voltage that the AD7879/AD7889 can in the GPIO data register bit puts a 0 on the GPIO output pin. measure changes when a different reference voltage is used. The If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets maximum voltage that is measurable is V × 4 because this CC the corresponding GPIO data bit to 0. A 0 at the input pin clears voltage gives a full-scale output from the ADC. The battery the corresponding GPIO data bit to 1. voltage can be calculated using the following formula: If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data VBAT (V) = [(Register Value) × VCC × 4]/4095 register bit puts a 0 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 1 on the GPIO output pin. Rev. C | Page 18 of 40 07667-028 AD7879/AD7889 GPIO Interrupt Enable (Bit 12, Control Register 3, INT is asserted if the GPIO data register bit is set when the Address 0x03) INT GPIO is configured as an input, provided that is enabled. INT The GPIO pin can operate as an interrupt source to trigger the is triggered only when the GPIO is configured as an input, INT that is, when GPIO DIR = 1. output. This is controlled by Bit 12 in Control Register 3. If the GPIO ALERT interrupt enable bit is set to 0, the GPIO can INT is cleared only when the GPIO signal or the GPIO enable INT INT trigger . If this bit is set to 1, the GPIO cannot trigger . bit changes. Rev. C | Page 19 of 40 AD7879/AD7889 CONVERSION TIMING Conversion timing or update rate is the rate at which the Conversion time per channel depends on the number of AD7879 provides converted values from the ADC so that the samples to be converted. The number of samples is pro- XY positions in the touch screen can be updated. In other grammed using the following median filter settings: words, the update rate is the timing required to give valid TCHANNEL = TMEASURE × MED measurements in the sequencer. T _ =9.5 μs (ACQ = 2 μs, MED = 0) CHANNEL MIN Figure 29 shows conversion timing for a conversion sequence. T _ = 376 μs (ACQ = 16 μs, MED = 16) CHANNEL MAX VBAT/AUX X+ Y+ Z1 Z2 TEMP Update Rate = [FCD + (T × MED)] × N + FCD + TMR F F F F F MEASURE T T T T T T C MEASURE C MEASURE C MEASURE C MEASURE MEASURE MEASURE C D D D D D where: N = number of channels to be measured (1 to 6). × M × M × M × M × M × M Figure 29. Conversion Timing Sequence MED = median filter setting (1, 4, 8, 16). FCD is required before each touch screen measurement (X+, TMR = timer setting (0 μs to 9.4 ms). Y+, Z1, and Z2). This time is required to allow the screen inputs The total update rate depends on the median filter settings and to settle before converting. If the sequence does not contain any the number of channels in the conversion sequence. The timer screen channel (VBAT, AUX, or TEMP), only one FCD is added setting (TMR) allows the user more flexibility to program the at start of the sequence. At the end of the sequence, there is update rate. always another FCD. For example, if T is the time required to perform one measurement in MEASURE ACQ = 4 us the conversion sequence. MED = 8 T = [ACQ (2 μs, 4 μs, 8 μs, 16 μs) + T (7.5 μs) + T MEASURE CONV SORT (2 μs)] N = 2 where: FCD = 1.024 ms ACQ is the acquisition time which is programmable in Control TMR = 620 μs Register 1. For temperature measurements, ACQ is fixed at 16 μs. T = 4 + 7.5 + 2 = 13.5 μs MEASURE T (typical ADC conversion time) is specified at 7.5 μs. CONV T is the time needed to sort the new sample within the SORT TCHANNEL = (13.5 × 8) = 108 μs median filter array. The T value is approximately 2 μs. If a SORT Then median filter is not used (MED =0), the T value is 0. SORT Update rate = [1024 + 108] × 2 + 1024 + 620 = 3.9 ms TMEASURE_MIN = 9.5 μs (ACQ = 2 μs, no median filter) Rev. C | Page 20 of 40 07667-046 AD7879/AD7889 REGISTER MAP Table 11. Register Table 1 Address Register Name Description Default Value Type 0x00 Unused Unused 0x0000 R/W 0x01 Control Register 1 Pen interrupt enable, channel selection for manual conversion, 0x0000 R/W ADC mode, acquisition time, and conversion timer 0x02 Control Register 2 ADC power management, GPIO control, pen interrupt mode, 0x4040 R/W averaging, median filter, software reset, and FCD 0x03 Control Register 3 Status of high/low limit comparisons for TEMP and AUX/VBAT, 0x0000 R/W and enable bits to allow them to become interrupts; channel selection for slave/master mode 0x04 AUX/VBAT high limit AUX/VBAT high limit for comparison 0x0000 R/W 0x05 AUX/VBAT low limit AUX/VBAT low limit for comparison 0x0000 R/W 0x06 TEMP high limit TEMP high limit for comparison 0x0000 R/W 0x07 TEMP low limit TEMP low limit for comparison 0x0000 R/W 0x08 X+ X+ measurement for Y position 0x0000 R 0x09 Y+ Y+ measurement for X position 0x0000 R 0x0A X+ (Z1) X+ measurement for touch-pressure calculation (Z1) 0x0000 R 0x0B Y− (Z2) Y− measurement for touch-pressure calculation (Z2) 0x0000 R 0x0C AUX/VBAT AUX/VBAT voltage measurement 0x0000 R 0x0D TEMP Temperature conversion measurement 0x0000 R 0x0E Revision and device ID Revision and device ID 0x0379 R (AD7879-1/AD7889-1) 0x037A R (AD7879/AD7889) 1 Do not write to addresses outside the register map. Rev. C | Page 21 of 40 AD7879/AD7889 DETAILED REGISTER DESCRIPTIONS All addresses and default values are expressed in hexadecimal. Table 12. Control Register 1 Default Address Bit Name Data Bit Description Value 0x01 Disable PENIRQ 15 Pen interrupt enable. 0x0000 0 = PENIRQ is enabled. 1 = PENIRQ is disabled and INT is enabled. CHNL ADD[2:0] [14:12] ADC channel address for manual conversion (ADC mode = 01). 111 = X+ input (Y position). 110 = Y+ input (X position). 101 = X+ (Z1) input for touch-pressure calculation. 100 = Y− (Z2) input (used for touch-pressure measurement). 1 011 = AUX input. 1 010 = VBAT input. 001 = temperature measurement. 000 = not applicable. ADC MODE[1:0] [11:10] ADC mode. 00 = no conversion. 2 01 = single conversion. 2 10 = conversion sequence (slave mode). 11 = conversion sequence (master mode). ACQ[1:0] [9:8] ADC acquisition time. 00 = 4 clock periods (2 µs). 01 = 8 clock periods (4 µs). 10 = 16 clock periods (8 µs). 11 = 32 clock periods (16 µs). Note that the acquisition time does not apply to the temperature sensor channels; the temperature channel has a constant settling time of 16 μs. TMR[7:0] [7:0] Conversion interval timer. Starts at 550 µs (00000001) and continues to 9.440 ms (11111111) in steps of 35 µs (see Table 18). Note that, in slave mode, the conversion interval timer starts to count as soon as the conversion sequence is finished; in master mode, it starts to count again only if the screen remains touched. If the screen is released, the timer stops counting and, on the next screen touch, a conversion starts immediately. 1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected in Control Register 3 and GPIO is disabled, AUX is ignored and VBAT is measured. 2 Note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (Address 0x01) Bits[7:0] = 0x00 at the end of the conversion sequence. Rev. C | Page 22 of 40 AD7879/AD7889 Table 13. Control Register 2 Default Address Bit Name Data Bit Description Value 0x02 PM[1:0] [15:14] ADC power management. 0x4040 00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered down. 01 = analog blocks to be powered down depend on the ADC mode. If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are powered down and must wake up when the user touches the screen. If ADC mode is slave mode, the ADC and temperature sensor are powered down when not being used. They wake up automatically when required. The oscillator and bias are powered up because they are needed to measure time. This also applies to the single-conversion mode. 10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode. 11 = same as 01. GPIO EN 13 GPIO enable. 0 = AUX/VBAT channel active. 1 = GPIO enabled on AUX/VBAT/GPIO pin. GPIO DAT 12 GPIO data bit. GPIO DIR 11 GPIO direction. 0 = output. 1 = input. GPIO POL 10 GPIO polarity. 0 = GPIO pin is active low. 1 = GPIO pin is active high. SER/DFR 9 Selects normal (single-ended) or ratiometric (differential) conversion. 0 = ratiometric (differential). 1 = normal (single-ended). AVG[1:0] [8:7] ADC averaging. 00 = 2 middle values averaged (one measurement when median filter is disabled). 01 = 4 middle values averaged. 10 = 8 middle values averaged. 11 = 16 values averaged. MED[1:0] [6:5] Median filter size. 00 = median filter disabled. 01 = 4 measurements. 10 = 8 measurements. 11 = 16 measurements. SW/RST 4 Software reset; digital logic is reset when this bit is set. 1 FCD[3:0] [3:0] ADC first conversion delay. Starts at 128 µs (default) and continues to 4.096 ms in steps of 128 µs (see Table 22). 1 This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the ADC to power up. Rev. C | Page 23 of 40 AD7879/AD7889 Table 14. Control Register 3 Default Address Bit Name Data Bit Description Value 0x03 TEMP MASK 15 TEMP mask bit. 0x0000 0 = temperature measurement is allowed to cause interrupt. 1 = temperature measurement is not allowed to cause interrupt. AUX/VBAT MASK 14 AUX/VBAT mask bit. 0 = AUX/VBAT measurement is allowed to cause interrupt. 1 = AUX/VBAT measurement is not allowed to cause interrupt. INT MODE 13 DAV/INT mode select. 0 = enable DAV mode. 1 = enable INT mode. Note that this bit overrides any mask bits associated with individual channels. GPIO ALERT 12 GPIO interrupt enable. 0 = GPIO can cause an alert on the INT output. 1 = mask GPIO from causing an alert on the INT output. AUX/VBAT LOW 11 1 = AUX/VBAT below low limit. AUX/VBAT HIGH 10 1 = AUX/VBAT above high limit. TEMP LOW 9 1 = TEMP below low limit. TEMP HIGH 8 1 = TEMP above high limit. X+ 7 1 = include measurement of Y position (X+ input). Y+ 6 1 = include measurement of X position (Y+ input). Z1 5 1 = include Z1 touch-pressure measurement (X+ input). Z2 4 1 = include measurement of Z2 touch-pressure measurement (Y− input). 1 AUX 3 1 = include measurement of AUX channel. 1 VBAT 2 1 = include measurement of battery monitor (VBAT). TEMP 1 1 = include temperature measurement. Not used 0 Unused. 1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected and GPIO is disabled, AUX is ignored and VBAT is measured. Table 15. Limit Registers Default Address Register Name Data Bit Description Value 0x04 AUX/VBAT high limit [15:0] User-programmable AUX/VBAT high limit register 0x0000 0x05 AUX/VBAT low limit [15:0] User-programmable AUX/VBAT low limit register 0x0000 0x06 TEMP high limit [15:0] User-programmable TEMP high limit register 0x0000 0x07 TEMP low limit [15:0] User-programmable TEMP low limit register 0x0000 Rev. C | Page 24 of 40 AD7879/AD7889 Table 16. Measurement Result Registers (Read Only) Address Register Name Data Bits Description Default Value 0x08 X+ [15:0] Measured X+ input with Y excitation (Y position) 0x0000 0x09 Y+ [15:0] Measured Y+ input with X excitation (X position) 0x0000 0x0A X+ (Z1) [15:0] Measured X+ input with X − and Y+ excitation (touch -pressure calculation Z1) 0x0000 0x0B Y− (Z2) [15:0] Measured Y − input with X− and Y+ excitation (touch-pressure calculation Z2) 0x0000 0x0C AUX/VBAT [15:0] AUX/VBAT voltage measurement 0x0000 0x0D TEMP [15:0] Temperature conversion measurement 0x0000 Table 17. Revision and Device ID Register (Read Only) Address Data Bits Description Default Value 0x0E [15:12] Unused 0x0379 (AD7879-1/AD7889-1) 0x037A (AD7879/AD7889) [11:8] Revision and device ID bits [7:0] Device ID Rev. C | Page 25 of 40 AD7879/AD7889 CONTROL REGISTERS 15 0 DISABLE CHNL CHNL CHNL ADC ADC ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 PENIRQ ADD2 ADD1 ADD0 MODE1 MODE0 Figure 30. Control Register 1 CONTROL REGISTER 1 ADC Mode (Control Register 1, Bits[11:10]) Control Register 1 (Address 0x01) contains the ADC channel The mode bits select the operating mode of the ADC. The address and the ADC mode bits. It sets the acquisition time and AD7879/AD7889 have three operating modes. These modes are the timer. It also contains a bit to disable the pen interrupt. selected by writing to the mode bits in Control Register 1. If the Control Register 1 should always be the last register programmed mode bits are set to 00, no conversion is performed. prior to starting conversions. Its power-on default value is 0x0000. Table 20. Mode Selection To change any parameter after conversion has begun, the part ADC ADC must first be put into ADC Mode 00. Make the changes, and MODE1 MODE0 Function then reprogram Control Register 1, ensuring that it is always 0 0 Do not convert (default) the last register programmed before conversions begin. 0 1 Single-channel conversion; the device is Timer (Control Register 1, Bits[7:0]) in slave mode 1 0 Sequence 0; the device is in slave mode The TMR bits in Control Register 1 set the conversion interval 1 1 Sequence 1; the device is in master mode timer, which enables the ADC to perform a conversion sequence at regular intervals from 550 µs (00000001) up to 9.440 ms If the mode bits are set to 01, a single conversion is performed (11111111) in increments of 35 µs (see Table 18). The default on the channel selected by writing to the channel bits of Control value of these bits is 00000000, which enables the ADC to Register 1 (Bits[14:12]). At the end of the conversion, if the TMR perform one conversion only. bits in Control Register 1 are set to 00000000, the mode bits revert to 00 and the ADC returns to no convert mode until a In slave mode, the timer starts as soon as the conversion sequence new conversion is initiated by the host. Setting the TMR bits to is finished. In master mode, the timer starts at the end of a conver- a value other than 00000000 causes the conversion to be repeated. sion sequence only if the screen remains touched. If the touch is released at any stage, the timer stops. The next time that the The AD7879/AD7889 can also be programmed to automatically screen is touched, a conversion sequence begins immediately. convert a sequence of selected channels. The two modes for this type of conversion are slave mode and master mode. Table 18. Timer Selection For slave mode operation, the channels to be digitized are selected TMR[7:0] Conversion Interval 00000000 Convert one time only (default) by setting the corresponding bits in Control Register 3. Conversion 00000001 Every 550 µs is initiated by writing 10 to the mode bits of Control Register 1. The ADC then digitizes the selected channels and stores the 00000010 Every 585 µs results in the corresponding result registers. At the end of the 00000011 Every 620 µs conversion, if the TMR bits in Control Register 1 are set to … … 00000000, the mode bits revert to 00 and the ADC returns to no 11111101 Every 9.370 ms convert mode until a new conversion is initiated by the host. 11111110 Every 9.405 ms Setting the TMR bits to a value other than 00000000 causes the 11111111 Every 9.440 ms conversion sequence to be repeated. Acquisition Time (Control Register 1, Bits[9:8]) For master mode operation, the channels to be digitized are The ACQ bits in Control Register 1 allow the selection of acquisi- written to Control Register 3. Master mode is then selected by tion times for the ADC of 2 µs (default), 4 µs, 8 µs, or 16 µs. The writing 11 to the mode bits in Control Register 1. In this mode, user can program the ADC with an acquisition time suitable for the wake-up on touch feature is active; therefore, conversion the type of signal being sampled. For example, signals with large does not begin immediately. The AD7879/AD7889 wait until RC time constants can require longer acquisition times. the screen is touched before beginning the sequence of conver- Table 19. Acquisition Time Selection sions. The ADC then digitizes the selected channels, and the results are written to the result registers. Before beginning ACQ1 ACQ0 Acquisition Time another sequence of conversions, the AD7879/AD7889 wait for 0 0 4 clock periods (2 µs) the screen to be touched again or for a timer event if the screen 0 1 8 clock periods (4 µs) remains touched. 1 0 16 clock periods (8 µs) 1 1 32 clock periods (16 µs) Rev. C | Page 26 of 40 07667-029 AD7879/AD7889 ADC Channel (Control Register 1, Bits[14:12]) For both single-channel and sequential conversion, a normal DFR conversion (single-ended) is selected by setting the SER/ The ADC channel address is selected by Bits[14:12] of Control bit in Control Register 2 (Bit 9). Ratiometric (differential) Register 1 (CHNL ADD2 to CHNL ADD0). A complete list of conversion is selected by clearing the SER/DFR bit. channel addresses is given in Table 21. PENIRQ Enable (Control Register 1, Bit 15) For single-channel conversion, the channel address is selected by writing the appropriate code to the CHNL ADD2 to CHNL The AD7879/AD7889 have a dual function output that performs ADD0 bits in Control Register 1. PENIRQ INT as or depending on the pen interrupt enable bit For sequential channel conversion, the channels to be converted (Bit 15 of Control Register 1). When this bit is set to 0, the pin are selected by setting the bits corresponding to the channel functions as a pen interrupt and goes low whenever the screen number in Control Register 3 for slave and master mode is touched. When the pen interrupt enable bit is set to 1, the pen sequencing. interrupt request is disabled and the pin functions as an interrupt when a measurement exceeds a preprogrammed limit (INT). Table 21. Codes for Selecting Input Channel and Normal or Ratiometric Conversion SER/DFR Channel CHNL ADD[2:0] Analog Input X Switches Y Switches REF+ REF− 0 0 111 X+ (Y position) Off On Y+ Y− 1 0 110 Y+ (X position) On Off X+ X− 2 0 101 X+ (Z1 touch pressure) X+ off, X− on Y+ on, Y− off Y+ X− 3 0 100 Y− (Z2 touch pressure) X+ off, X− on Y+ on, Y− off Y+ X− 4 0 011 AUX Off Off V GND CC 5 0 010 VBAT Off Off VCC GND 6 0 001 TEMP Off Off VCC GND 0 000 Invalid address 7 1 111 X+ (Y position) Off On V GND CC 8 1 110 Y+ (X position) On Off V GND CC 9 1 101 X+ (Z1 touch pressure) Off Off VCC GND 12 1 100 Y− (Z2 touch pressure) Off Off VCC GND 13 1 011 AUX Off Off VCC GND 14 1 010 VBAT Off Off V GND CC 15 1 001 TEMP Off Off V GND CC 1 000 Invalid address Rev. C | Page 27 of 40 AD7879/AD7889 15 0 GPIO GPIO GPIO GPIO SER/ SW/ PM1 PM0 AVG1 AVG0 MED1 MED0 FCD3 FCD2 FCD1 FCD0 EN DAT DIR POL DFR RST Figure 31. Control Register 2 CONTROL REGISTER 2 Power Management (Control Register 2, Bits[15:14]) Control Register 2 (Address 0x02) contains the ADC power The power management (PM) bits in Control Register 2 allow DFR management bits, the GPIO settings, the SER/ bit (to the power management features of the ADC to be programmed choose the single-ended or differential method of touch screen (see Table 23). If the PM bits are set to 00, the ADC is in full measurement), the averaging and median filter settings, a bit shutdown. This setting overrides any setting of the mode bits in that allows resetting of the part, and the first conversion delay Control Register 1. Power management overrides the ADC modes. bits. Its power-on default value is 0x4040. See the Detailed Table 23. Power Management Selection Register Descriptions section for more information about the PM1 PM0 Function control registers. 0 0 Full shutdown; ADC, oscillator, bias, and temp- For information about the averaging and median filter settings, erature sensor are turned off. The only way to see the Median and Averaging Filters section. For information exit this mode is to write to the part over the about the GPIO settings, see the GPIO section. serial interface and change the PM bits. This setting overrides any other setting on the First Conversion Delay (Control Register 2, Bits[3:0]) part, including the ADC mode bits. The first conversion delay (FCD) bits in Control Register 2 0 1 The analog blocks to be powered down depend on the ADC mode setting. In master program a delay from 128 µs (default) up to 4.096 ms before mode, the ADC, bias, temperature sensor, and the first conversion to allow the ADC time to power up. This oscillator are powered down and must wake delay also occurs before conversion of the X and Y coordinate up when the user touches the screen. In slave channels to allow extra time for screen settling, and after the mode, the ADC and temperature sensor are last conversion in a sequence to precharge PENIRQ. powered down when not being used. They wake up automatically when required. The Table 22. First Conversion Delay Selection oscillator and bias are powered up because they are needed to measure time. This setting FCD[3:0] Delay also applies to the single-conversion mode. 0000 128 µs 1 0 The ADC, bias, and oscillator are powered up 0001 256 µs continuously, irrespective of ADC mode. 0010 384 µs 1 1 Same as 01. 0011 512 µs 0100 640 µs 0101 768 µs 0110 896 µs 0111 1.024 ms 1000 1.152 ms 1001 1.280 ms 1010 1.536 ms 1011 1.792 ms 1100 2.048 ms 1101 2.560 ms 1110 3.584 ms 1111 4.096 ms Rev. C | Page 28 of 40 07667-030 AD7879/AD7889 15 0 AUX/ AUX/ AUX/ TEMP INT GPIO TEMP TEMP NOT VBAT VBAT VBAT X+ Y+ Z1 Z2 AUX VBAT TEMP MASK MODE ALERT LOW HIGH USED MASK LOW HIGH Figure 32. Control Register 3 CONTROL REGISTER 3 START OF Control Register 3 (Address 0x03) includes the interrupt CONVERSION SET CHANNEL register (Bits[15:8]) and the sequencer bits (Bits[7:0]). SEQUENCE Sequencer (Control Register 3, Bits[7:0]) YES FCD REQ’D? The sequencer bits control which channels are converted during a conversion sequence in both slave mode and master mode. NO FCD To include a measurement in a sequence, the relevant bit must WAIT FOR be set in the sequence. Setting Bit 7 includes a measurement on ACQUISITION ACQ the X+ channel (Y position). Setting Bit 6 includes a measure- ment on the Y+ channel (X position), and so on (see Table 14). CONVERT DATA Figure 32 illustrates the correspondence between the bits in YES Control Register 3 and the various measurements. Bit 0 is RANK NEW YES MAV FILTER not used. DATA ENABLED (WAIT t ) SORT ? NO 00 IDLE ADC MODE? MEDIAN NO # OF SAMPLES 1 TAKEN? 01 10 11 MASTER MODE SINGLE SLAVE MODE CONVERSION TRANSFER DATA AVERAGE DATA TO REGISTERS WAIT FOR CONVERSION FIRST TOUCH SEQUENCE YES SET ALERT AND OUT-OF- CONVERSION INTERRUPT LIMIT? SEQUENCE TIMER = 00? NO NO NO END OF NO SCREEN SEQUENCE TOUCHED? START TIMER ? YES YES 1 MEDIAN # MEANS MEDIAN WAIT FOR TIMER FCD YES FILTER SIZE. TIMER = 00? Figure 34. Conversion Sequence NO START TIMER WAIT FOR TIMER SCREEN NO TOUCHED? YES Figure 33. Conversion Modes Rev. C | Page 29 of 40 YES 07667-032 07667-031 07667-033 AD7879/AD7889 PENIRQ INTERRUPTS —Pen Interrupt The AD7879/AD7889 have a dual function interrupt output, The pen interrupt request output (PENIRQ) goes low whenever INT, as well as a pen-down interrupt, PENIRQ. The INT output the screen is touched and the PENIRQ enable bit is set to 0 DAV can be configured as a data available interrupt ( ), as an (Control Register 1, Bit 15). When PENIRQ enable is set to 1, INT out-of-limit interrupt ( ), or as a GPIO interrupt. the pen interrupt request output is disabled. DAV The pen interrupt equivalent output circuitry is shown in —Data Available Interrupt Figure 36. This digital logic output has an internal 50 kΩ pull- The behavior of the interrupt output is controlled by Bit 13 in up resistor, so it does not need an external pull-up. The Control Register 3. In default mode (Bit 13 = 0), INT operates PENIRQ PENIRQ output idles high, and the circuitry is always as a data available interrupt (DAV). When the AD7879/AD7889 enabled in master mode (ADC mode = 11), except during finish a conversion or a conversion sequence, the interrupt is conversions. asserted to let the host know that new ADC data is available in V CC Y+ the result registers. V CC 50kΩ DAV While the ADC is idle or is converting, is high. When the PENIRQ X+ ADC has finished converting and new data has been written to X– the result registers, DAV goes low. Reading the result registers TOUCH SCREEN PENIRQ resets DAV to a high condition. DAV is also reset if a new con- ENABLE version is started by the AD7879/AD7889 because the timer Y– expired. The host should read the result registers only when DAV DAV is low. To ensure correct operation of the mode PENIRQ Figure 36. Output Equivalent Circuit when using the SPI interface, it is necessary to write 0x0000 PENIRQ When the screen is touched, goes low. This generates to Register 0x81 after a set of register reads. This clears the an interrupt request to the host. When the screen touch ends, internal data read signal. PENIRQ immediately goes high if the ADC is idle. If the ADC PENIRQ is converting, goes high when the ADC becomes idle. DAV The PENIRQ operation for these two conditions is shown in t CONV AD7879/ Figure 37. AD7889 SETUP ADC NEW DATA HOST READS IDLE STATUS BY HOST CONVERTING AVAILABLE RESULTS IDLE NOT NOT SCREEN TOUCHED TOUCHED TOUCHED Figure 35. Operation of DAV Output PENIRQ When the on-board timer is programmed to perform automatic DETECTS PENIRQ TOUCH conversions, limited time is available to the host to read the PENIRQ DETECTS RELEASE result registers before another sequence of conversions begins. ADC ADC IDLE The DAV signal is reset high when the timer expires, and the STATUS host should not access the result registers while DAV is high. RELEASE NOT NOT NOT DETECTED SCREEN TOUCHED TOUCHED TOUCHED INT —Out-of-Limit Interrupt PENIRQ INT The pin operates as an alarm or interrupt output when DETECTS PENIRQ TOUCH PENIRQ Bit 13 in Control Register 3 (Address 0x03) is set to 1. The DETECTS RELEASE output goes low if any one of the interrupt sources is asserted. ADC ADC ADC IDLE ADC IDLE STATUS CONVERTING The results of high and low limit comparisons on the AUX, VBAT, and TEMP channels are interrupt sources. An out-of- Figure 37. PENIRQ Operation for ADC Idle and ADC Converting limit comparison sets a status bit in the interrupt register. A separate status bit for the high limit and the low limit on each channel indicates which limit was exceeded. The interrupt sources can be masked by setting the corresponding enable bit in this register to 1. There is one enable bit per channel. Rev. C | Page 30 of 40 07667-034 07667-035 07667-036 AD7879/AD7889 INT DAV SYNCHRONIZING THE AD7879/AD7889 TO THE and enable or using Bit 15 in Control Register 1 and Bit 13 in Control Register 3. The host can then enter sleep mode HOST CPU to conserve power. The wake-up on touch feature of the The two methods for synchronizing the AD7879/AD7889 to its AD7879/AD7889 is active in this mode; therefore, when the host CPU are slave mode (in which the mode bits are set to 01 screen is touched, the programmed sequence of conversions or 10) and master mode (in which the mode bits set to 11). automatically begins. When the INT or DAV signal is asserted, In master mode (ADC mode bits = 11), PENIRQ can be used the host reads the new data available in the AD7879/AD7889 as an interrupt to the host. When PENIRQ goes low to indicate result registers and returns to sleep mode. This method can that the screen has been touched, the host is awakened. The significantly reduce the load on the host. host can then program the AD7879/AD7889 to convert in any PENIRQ Figure 38 shows how the circuit is enabled. The wake-up mode and read the results after the conversions are completed. PENIRQ on touch circuit and the circuit are enabled only in master INT DAV In master mode, or can also be used as an interrupt to mode (ADC mode = 11). In slave mode, the PENIRQ/INT/DAV the host. The host should first define a conversion sequence in pin can output only INT or DAV signals. Control Register 3, initialize the AD7879/AD7889 in Mode 11, YES YES ADC MODE = 11? MASTER MODE ENABLE ENABLE PENIRQ TOUCH SCREEN TOUCHED TO THE DIGITAL CORE WAKE-UP DETECTION ON TOUCH CIRCUIT TOUCH SCREEN TOUCHED DAV 0 PENIRQ/INT/DAV PIN (END OF CONVERSION SEQUENCE) 0 INT/DAV/GPIO ALERT INT 1 (GPIO ALERT/OUT OF LIMITS) 1 CONTROL REGISTER 1 BIT 15 CONTROL REGISTER 3 BIT 13 Figure 38. Master Mode Operation Rev. C | Page 31 of 40 07667-037 AD7879/AD7889 SERIAL INTERFACE The AD7879 and AD7879-1 (and the AD7889 and AD7889-1) Bits[15:11] of the command word must be set to 11100 to differ only in the serial interface provided on the part. The successfully begin a bus transaction. AD7879 and the AD7889 are available with a serial peripheral Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates interface (SPI). The AD7879-1 and the AD7889-1 are available a write. 2 with an I C-compatible interface. It is recommended that Bits[9:0] contain the target register address. When reading or addresses outside the register map not be written to. writing to more than one register, this address indicates the SPI INTERFACE address of the first register to be written to or read from. The AD7879/AD7889 have a 4-wire SPI. The SPI has a data Writing Data input pin (DIN) for inputting data to the device, a data output Data is written to the AD7879/AD7889 in 16-bit words. The pin (DOUT) for reading data back from the device, and a data first word written to the device is the command word, with the clock pin (SCL) for clocking data into and out of the device. A read/write bit set to 0. The master then supplies the 16-bit input CS CS chip select pin ( ) enables or disables the serial interface. is data-word on the DIN line. The AD7879/AD7889 clock the required for correct operation of the SPI interface. Data is data into the register addressed in the command word. If there clocked out of the AD7879/AD7889 on the falling edge of SCL, is more than one word of data to be clocked in, the AD7879/ and data is clocked into the device on the rising edge of SCL. AD7889 automatically increment the address pointer and clock SPI Command Word the next data-word into the following register. All data transactions on the SPI bus begin with the master The AD7879/AD7889 continue to clock in data on the DIN line taking CS from high to low and sending out the command CS until the master ends the write transition by pulling high or word. This indicates to the AD7879/AD7889 whether the until the address pointer reaches its maximum value. The AD7879/ transaction is a read or a write and gives the address of the AD7889 address pointer does not wrap. When the address register from which to begin the data transfer. The bit map in pointer reaches its maximum value, any data provided by the Table 24 shows the SPI command word. master on the DIN line is ignored by the AD7879/AD7889. Table 24. SPI Command Word MSB LSB 15 14 13 12 11 10 [9:0] 1 1 1 0 0 R/W Register address 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS 16-BIT DATA CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW DIN D15 D14 D13 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t t t 1 3 8 CS NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE COMMAND WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SINGLE WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) Figure 39. Single Register Write, SPI Timing Rev. C | Page 32 of 40 07667-038 AD7879/AD7889 16-BIT COMMAND WORD DATA FOR STARTING DATA FOR NEXT ENABLE WORD R/W STARTING REGISTER ADDRESS REGISTER ADDRESS REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW DIN D15 D14 D1 D0 D15 D14 D1 D0 D15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) Figure 40. Sequential Register Write, SPI Timing 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW DIN X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t t t 1 3 8 CS t t 6 7 DOUT D15 D14 D13 D2 D1 D0 XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX 16-BIT READBACK DATA NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN. 4. X DENOTES DON’T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) Figure 41. Single Register Readback, SPI Timing The AD7879/AD7889 continue to clock out data on the DOUT Reading Data line provided that the master continues to supply the clock signal A read transaction begins when the master writes the command on SCL. The read transaction ends when the master takes CS high. word to the AD7879/AD7889 with the read/write bit set to 1. The If the AD7879/AD7889 address pointer reaches its maximum master then supplies 16 clock pulses per data-word to be read, value, the AD7879/AD7889 repeatedly clock out data from the and the AD7879/AD7889 clock out data from the addressed addressed register. The address pointer does not wrap. register on the DOUT line. The first data-word is clocked out on the first falling edge of SCL following the command word, as shown in Figure 41. Rev. C | Page 33 of 40 07667-040 07667-039 AD7879/AD7889 16-BIT COMMAND WORD ENABLE WORD R/W STARTING REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW DIN X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS DOUT XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D1 D0 D15 D14 D1 D0 D15 READBACK DATA FOR READBACK DATA FOR NEXT REGISTER ADDRESS STARTING REGISTER ADDRESS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE DOUT PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON’T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) Figure 42. Sequential Register Readback, SPI Timing 2 All slave peripherals connected to the serial bus respond to the I C-COMPATIBLE INTERFACE start condition and shift in the next eight bits, consisting of a The AD7879-1/AD7889-1 support the industry standard 2-wire W 7-bit address (MSB first) plus a R/ bit that determines the 2 I C serial interface protocol. The two wires associated with the direction of the data transfer. The peripheral whose address 2 I C timing are the SCL and SDA inputs. SDA is an I/O pin that corresponds to the transmitted address responds by pulling the allows both register write and register readback operations. The data line low during the ninth clock pulse. This is known as the 2 AD7879-1/AD7889-1 are always slave devices on the I C serial acknowledge bit. All other devices on the bus then remain idle interface bus. while the selected device waits for data to be read from or written The devices have a 7-bit device address, Address 0101 1XX. The W to it. If the R/ bit is a 0, the master writes to the slave device. lower two bits are set by tying the ADD0 and ADD1 pins high or W If the R/ bit is a 1, the master reads from the slave device. low. The AD7879-1/AD7889-1 respond when the master device Data is sent over the serial bus in a sequence of nine clock sends its device address over the bus. The AD7879-1/AD7889-1 pulses (eight bits of data followed by an acknowledge bit from cannot initiate data transfers on the bus. the slave device). Transitions on the data line must occur during 2 Table 25. I C Device Addresses for the AD7879-1/AD7889-1 the low period of the clock signal and remain stable during the 2 high period because a low-to-high transition when the clock ADD1 ADD0 I C Address is high can be interpreted as a stop signal. The number of data 0 0 0101 100 bytes transmitted over the serial bus in a single read or write 0 1 0101 101 operation is limited only by what the master and slave devices 1 0 0101 110 can handle. 1 1 0101 111 When all data bytes are read or written, a stop condition is Data Transfer established. A stop condition is defined by a low-to-high 2 Data is transferred over the I C serial interface in 8-bit bytes. transition on SDA while SCL remains high. If the AD7879-1/ The master initiates a data transfer by establishing a start AD7889-1 encounter a stop condition, they return to the idle condition, defined as a high-to-low transition on the serial data condition. line, SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. Rev. C | Page 34 of 40 07667-041 AD7879/AD7889 START AD7879-1/AD7889-1 DEVICE ADDRESS REGISTER ADDRESS[A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A7 A6 A1 A0 A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCL 1 2 3 4 5 6 7 8 9 10 11 16 17 t 2 STOP START AD7879-1/AD7889-1 REGISTER DATA[D15:D8] REGISTER DATA[D7:D0] t DEVICE ADDRESS 8 DEV DEV DEV ACK D15 D14 D9 D8 ACK D7 D1 D0 ACK D6 A6 A5 A4 t t t t 6 7 4 5 1 2 3 18 19 20 25 26 27 28 29 34 35 36 37 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE Xs ARE DON'T CARE BITS. 4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 2 Figure 43. Example of I C Timing for Single Register Write Operation 2 Writing Data over the I C Bus All registers on the AD7879-1/AD7889-1 have 16 bits. Two 2 consecutive 8-bit data bytes are combined and written to the The process of writing to the AD7879-1/AD7889-1 over the I C 16-bit registers. To avoid errors, all writes to the device must bus is shown in Figure 43 and Figure 45. The device address is contain an even number of data bytes. W sent over the bus followed by the R/ bit set to 0. This is followed by one byte of data that contains the 8-bit address of the internal To end the transaction, the master generates a stop condition on data register to be written. The bit map in Table 26 shows the SDA, or it generates a repeat start condition if the master is to register address byte. maintain control of the bus. 2 Reading Data over the I C Bus 2 Table 26. I C Register Address Byte To read from the AD7879-1/AD7889-1, the address pointer MSB LSB register must first be set to the address of the required internal 7 6 5 4 3 2 1 0 register. The master performs a write transaction and writes to Register Address the AD7879-1/AD7889-1 to set the address pointer. The master Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 then outputs a repeat start condition to keep control of the bus The third data byte contains the eight MSBs of the data to be or, if this is not possible, the master ends the write transaction written to the internal register. The fourth data byte contains with a stop condition. A read transaction is initiated, with the the eight LSBs of data to be written to the internal register. R/W bit set to 1. The AD7879-1/AD7889-1 address pointer register automatically The AD7879-1/AD7889-1 supply the upper eight bits of data increments after each write. This allows the master to sequentially from the addressed register in the first readback byte, followed write to all registers on the AD7879-1/AD7889-1 in the same by the lower eight bits in the next byte. This is shown in Figure 44 write transaction. However, the address pointer register does and Figure 45. not wrap after the last address. Because the address pointer automatically increments after each Any data written to the AD7879-1/AD7889-1 after the address read, the AD7879-1/AD7889-1 continue to output readback data pointer has reached its maximum value is discarded. until the master puts a no acknowledge and a stop condition on the bus. If the address pointer reaches its maximum value and the master continues to read from the part, the AD7879-1/ AD7889-1 repeatedly send data from the last register addressed. Rev. C | Page 35 of 40 07667-042 AD7879/AD7889 START AD7879-1/AD7889-1 REGISTER ADDRESS[A7:A0] DEVICE ADDRESS SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A7 A6 A1 A0 ACK A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCL 1 2 3 4 5 6 7 8 9 10 11 16 17 18 t 2 P AD7879-1/AD7889-1 AD7879-1/AD7889-1 REGISTER DATA[D7:D0] SR DEVICE ADDRESS t DEVICE ADDRESS 8 DEV DEV DEV DEV DEV DEV DEV D7 D6 D1 D0 ACK ACK R/W A6 A5 A1 A0 A6 A5 A4 USING t t t REPEATED t 7 4 5 6 START 25 26 27 28 29 35 36 37 1 2 3 19 20 21 30 AD7879-1/AD7889-1 REGISTER DATA[D7:D0] P P S DEVICE ADDRESS DEV DEV DEV DEV D7 D1 D0 D6 ACK R/W ACK A6 A5 A1 A0 SEPARATE READ AND t t 4 5 WRITE TRANSACTIONS 25 26 27 28 29 30 35 36 37 19 20 21 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE TWO LSB Xs ARE DON'T CARE BITS. 5. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. THE R/W BIT IS SET TO 1 TO INDICATE A READBACK OPERATION. 2 Figure 44. Example of I C Timing for Single Register Readback Operation WRITE 7-BIT DEVICE REGISTER ADDR WRITE DATA WRITE DATA WRITE DATA WRITE DATA . . . S W P ADDRESS [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (USING REPEATED START) 7-BIT DEVICE REGISTER ADDR 7-BIT DEVICE READ DATA READ DATA READ DATA READ DATA . . . S W R P ADDRESS [7:0] ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS) 7-BIT DEVICE REGISTER ADDR 7-BIT DEVICE READ DATA READ DATA READ DATA READ DATA S P S R . . . P W ADDRESS [7:0] ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] OUTPUT FROM MASTER S = START BIT W = WRITE BIT P = STOP BIT ACK = ACKNOWLEDGE BIT OUTPUT FROM SR = REPEATED START BIT ACK = NO ACKNOWLEDGE BIT AD7879-1/AD7889-1 R = READ BIT 2 Figure 45. Example of Sequential I C Write and Readback Operation Rev. C | Page 36 of 40 ACK ACK ACK ACK ACK ACK SR ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK 07667-043 07667-044 AD7879/AD7889 GROUNDING AND LAYOUT of at least 0.25 mm between the thermal pad and the inner For detailed information on grounding and layout considerations edges of the land pattern on the PCB. Thermal vias can be used for the AD7879/AD7889, refer to the AN-577 Application Note, on the PCB thermal pad to improve the thermal performance of Layout and Grounding Recommendations for Touch Screen the package. If vias are used, incorporate them into the thermal Digitizers. pad at a 1.2 mm pitch grid. The via diameter should be between LEAD FRAME CHIP SCALE PACKAGES 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. of copper to plug the via. The lands on the lead frame chip scale package (CP-16-10) are rectangular. The printed circuit board (PCB) pad for these lands Connect the PCB thermal pad to GND. should be 0.1 mm longer than the package land length and WLCSP ASSEMBLY CONSIDERATIONS 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. For detailed information on the WLCSP PCB assembly and reliability, see the AN-617 Application Note, MicroCSP™ Wafer The bottom of the lead frame chip scale package has a central Level Chip Scale Package. thermal pad. The thermal pad on the PCB should be at least as large as this exposed pad. To avoid shorting, provide a clearance VOLTAGE REGULATOR 0.1µF 0.1µF TO 10µF MAIN (OPTIONAL) BATTERY 16 15 14 13 HOST CS 1 12 Y+ INT PENIRQ/INT/DAV 11 2 SCLK NC NC AD7879/ MISO 10 3 NC AD7889 NC MOSI 9 4 X– DOUT TOUCH SCREEN 5 6 7 8 NC = NO CONNECT Figure 46. Typical Application Circuit Rev. C | Page 37 of 40 SPI INTERFACE 07667-045 Y– X+ V /REF DIN CC GND CS AUX/ SCL VBAT/ GPIO AD7879/AD7889 OUTLINE DIMENSIONS 0.65 0.59 1.67 0.53 0.17 1.61 0.15 1.55 SEATING 0.13 3 2 1 PLANE A BALL 1 IDENTIFIER 2.07 0.36 B 1.50 2.01 REF 0.32 1.95 0.28 C D 0.50 REF TOP VIEW BOTTOM VIEW 0.10 MAX 0.37 (BALL SIDE DOWN) (BALL SIDE UP) COPLANARITY 0.35 0.28 0.33 0.24 0.20 Figure 47. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-1) Dimensions shown in millimeters 0.650 0.595 1.555 0.540 1.505 0.040 MAX 1.455 SEATING 0.020 MIN 3 2 1 PLANE A BALL 1 IDENTIFIER 2.055 B 0.340 1.50 2.005 REF 0.320 1.955 0.300 C D 0.50 REF TOP VIEW BOTTOM VIEW 0.10 MAX 0.380 (BALL SIDE DOWN) (BALL SIDE UP) COPLANARITY 0.355 1.00 0.270 0.330 REF 0.240 0.210 Figure 48. 12-Ball, Backside-Coated Wafer Level Chip Scale Package [WLCSP] (CB-12-5) Dimensions shown in millimeters 4.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC 2.50 INDICATOR TOP EXPOSED 3.75 2.35 SQ VIEW PAD BSC SQ (BOTTOM VIEW) 2.20 0.50 9 0.40 4 8 5 0.30 0.25 MIN 0.80 MAX 12° MAX 1.95 BSC 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM THE EXPOSED PAD, REFER TO 0.85 THE PIN CONFIGURATION AND 0.35 FUNCTION DESCRIPTIONS 0.20 REF 0.80 0.30 COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm, Very Thin Quad (CP-16-10) Dimensions shown in millimeters Rev. C | Page 38 of 40 082008-A 120808-A 010410-A AD7879/AD7889 ORDERING GUIDE Temperature Serial Interface Package 1 Model Range Description Package Description Option Branding AD7879ACBZ-RL −40°C to +85°C SPI Interface 12-Ball WLCSP CB-12-1 T2Y AD7879ACBZ-500R7 −40°C to +85°C SPI Interface 12-Ball WLCSP CB-12-1 T2Y AD7879ACPZ-RL −40°C to +85°C SPI Interface 16-Lead LFCSP_VQ CP-16-10 AD7879ACPZ-500R7 −40°C to +85°C SPI Interface 16-Lead LFCSP_VQ CP-16-10 2 AD7879-1ACBZ-RL −40°C to +85°C I C Interface 12-Ball WLCSP CB-12-1 T0Q 2 AD7879-1ACBZ-500R7 −40°C to +85°C I C Interface 12-Ball WLCSP CB-12-1 T0Q 2 AD7879-1ACPZ-RL −40°C to +85°C I C Interface 16-Lead LFCSP_VQ CP-16-10 2 AD7879-1ACPZ-500R7 −40°C to +85°C I C Interface 16-Lead LFCSP_VQ CP-16-10 AD7889ACBZ-RL −40°C to +85°C SPI Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3R AD7889ACBZ-500R7 −40°C to +85°C SPI Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3R 2 AD7889-1ACBZ-RL −40°C to +85°C I C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q 2 AD7889-1ACBZ-RL7 −40°C to +85°C I C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q 2 AD7889-1ACBZ-500R7 −40°C to +85°C I C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q EVAL-AD7879EBZ SPI Interface Evaluation Board 2 EVAL-AD7879-1EBZ I C Interface Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 39 of 40 AD7879/AD7889 NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07667-0-11/10(C) Rev. C | Page 40 of 40