ANALOG DEVICES AD7888

2.7 V to 5.25 V, Micropower, 8-Channel, a 125 kSPS, 12-Bit ADC in 16-Lead TSSOP AD7888 FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for V of 2.7 V to 5.25 V DD Flexible Power/Throughput Rate Management AD7888 AIN1 Shutdown Mode: 1 �A Max I/P T/H Eight Single-Ended Inputs MUX V DD AIN8 Serial Interface: SPI™/QSPI™/MICROWIRE™/DSP Compatible 2.5V COMP 16-Lead Narrow SOIC and TSSOP Packages REF APPLICATIONS REF IN/REF OUT BUF Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) CHARGE Instrumentation and Control Systems REDISTRIBUTION DAC High-Speed Modems SAR + ADC CONTROL LOGIC AGND AGND GENERAL DESCRIPTION SPORT The AD7888 is a high speed, low power, 12-bit ADC that oper- ates from a single 2.7 V to 5.25 V power supply. The AD7888 is capable of a 125 kSPS throughput rate. The input track-and- CS DIN DOUT SCLK hold acquires a signal in 500 ns and features a single-ended sampling scheme. The AD7888 contains eight single-ended analog inputs, AIN1 through AIN8. The analog input on each PRODUCT HIGHLIGHTS of these channels is from 0 to V . The part is capable of con- REF 1. Smallest 12-bit 8-channel ADC; 16-lead TSSOP is the same verting full power signals up to 2.5 MHz. area as an 8-lead SOIC and less than half the height. The AD7888 features an on-chip 2.5 V reference that can be 2. Lowest Power 12-bit 8-channel ADC. used as the reference source for the A/D converter. The REF 3. Flexible power management options including automatic IN/REF OUT pin allows the user access to this reference. Alter- power-down after conversion. natively, this pin can be overdriven to provide an external refer- 4. Analog input range from 0 V to V (V ). ence voltage for the AD7888. The voltage range for this external REF DD reference is from 1.2 V to V . DD 5. Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP Compatible). CMOS construction ensures low power dissipation of typically 2 mW for normal operation and 3 µW in power-down mode. The part is available in a 16-lead narrow body small outline (SOIC) and a 16-lead thin shrink small outline (TSSOP) package. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 (V = 2.7 V to 5.25 V, REFIN/REFOUT = 2.5 V External/Internal Reference unless AD7888–SPECIFICATIONS DD otherwise noted; f = 2 MHz (V = 2.7 V to 5.25 V); T = T to T , unless otherwise noted.) SCLK DD A MIN MAX 1 1 Parameter A Version B Version Unit Test Condition/Comment DYNAMIC PERFORMANCE 2, 3 Signal to Noise + Distortion Ratio (SNR) 71 71 dB typ f = 10 kHz Sine Wave, f = 125 kSPS IN SAMPLE 2 Total Harmonic Distortion (THD) –80 –80 dB typ f = 10 kHz Sine Wave, f = 125 kSPS IN SAMPLE 2 Peak Harmonic or Spurious Noise –80 –80 dB typ f = 10 kHz Sine Wave, f = 125 kSPS IN SAMPLE 2 Intermodulation Distortion (IMD) Second Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 125 kSPS SAMPLE Third Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 125 kSPS SAMPLE 2 Channel-to-Channel Isolation –80 –80 dB typ f = 25 kHz IN Full Power Bandwidth 2.5 2.5 MHz typ @ 3 dB DC ACCURACY Any Channel Resolution 12 12 Bits 2 Integral Nonlinearity ±2 ±1 LSB max 2 Differential Nonlinearity ±2 –1/+1.5 LSB max Guaranteed No Missed Codes to 11 Bits (A Grade) Guaranteed No Missed Codes to 12 Bits (B Grade) Offset Error ±6 ±6 LSB max V = 4.75 V to 5.25 V (Typically ±3 LSB) DD ±4.5 ±4.5 LSB max V = 2.7 V to 3.6 V (Typically ±2 LSB) DD 2 Offset Error Match 2 2 LSB typ 2 Gain Error ±2 ±2 LSB max Typically 30 LSB with Internal Reference 2 Gain Error Match 3 3 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V Volts REF REF Leakage Current ±1 ±1 µA max Input Capacitance 38 38 pF typ When in Track 4 4 pF typ When in Hold REFERENCE INPUT/OUTPUT REFIN Input Voltage Range 2.5/V 2.5/V V min/max Functional from 1.2 V DD DD Input Impedance 5 5 kΩ typ Very High Impedance If Internal Reference Disabled REFOUT Output Voltage 2.45/2.55 2.45/2.55 V min/max REFOUT Tempco ±50 ±50 ppm/°C typ LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min V = 4.75 V to 5.25 V INH DD 2.1 2.1 V min V = 2.7 V to 3.6 V DD Input Low Voltage, V 0.8 0.8 V max V = 2.7 V to 5.25 V INL DD Input Current, I ±10 ±10 µA max Typically 10 nA, V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V I = 200 µA OH SOURCE V – 0.5 V – 0.5 V min V = 2.7 V to 5.25 V DD DD DD Output Low Voltage, V 0.4 0.4 V max I = 200 µA OL SINK Floating-State Leakage Current ±10 ±10 µA max 5 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Throughput Time 16 16 SCLK Cycles Conversion Time + Acquisition Time. 125 kSPS with 2 MHz Clock 2 Track/Hold Acquisition Time 1.5 1.5 SCLK Cycles Conversion Time 14.5 14.5 SCLK Cycles 7.25 µs (2 MHz Clock) REV. C –2– AD7888 1 1 Parameter A Version B Version Unit Test Condition/Comment POWER REQUIREMENTS V 2.7/5.25 2.7/5.25 V min/max DD I DD 5 Normal Mode (Static) 700 700 µA max Normal Mode (Operational) 700 700 µA typ f = 125 kSPS SAMPLE Using Standby Mode 450 450 µA typ f = 50 kSPS SAMPLE Using Shutdown Mode 80 80 µA typ f = 10 kSPS SAMPLE 12 12 µA typ f = 1 kSPS SAMPLE 6 Standby Mode µA max V = 2.7 V to 5.25 V DD 6 Shutdown Mode 22 µA max V = 4.75 V to 5.25 V (0.5 µA typ) DD 11 µA max V = 2.7 V to 3.6 V DD Normal-Mode Power Dissipation 3.5 3.5 mW max V = 5 V DD 2.1 2.1 mW max V = 3 V DD Shutdown Power Dissipation 10 10 µW max V = 5 V DD 33 µW max V = 3 V DD Standby Power Dissipation 1 1 mW max V = 5 V DD 600 600 µW max V = 3 V DD NOTES 1 Temperature ranges as follows: A Version: –40°C to +105°C; B Version: –40°C to +105°C. 2 See Terminology. 3 SNR calculation includes distortion and noise components. 4 Sample tested @ 25°C to ensure compliance. 5 All digital inputs @ GND except CS @ V . No load on the digital outputs. Analog inputs @ GND. DD 6 SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ V . No load on the digital outputs. Analog inputs @ GND. DD Specifications subject to change without notice. 1 ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Analog Input Voltage to AGND . . . . . –0.3 V to V + 0.3 V DD Digital Input Voltage to AGND . . . . . . –0.3 V to V + 0.3 V DD Digital Output Voltage to AGND . . . . –0.3 V to V + 0.3 V DD REFIN/REFOUT to AGND . . . . . . . . –0.3 V to V + 0.3 V DD 2 Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA Operating Temperature Range Commercial (A Version) . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C (B Version) . . . . . . . . . . . . . . . . . . . . . . °C to +105°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C SOIC, TSSOP Package, Power Dissipation . . . . . . . . 450 mW θ Thermal Impedance . . . . . . . . . . . . 124.9°C/W (SOIC) JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP) θ Thermal Impedance . . . . . . . . . . . . . 42.9°C/W (SOIC) JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7888 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– AD7888 1 TIMING SPECIFICATIONS (T = T to T , unless otherwise noted) A MIN MAX Limit at T , T MIN MAX (A, B Versions) Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description 2 f 2 2 MHz max SCLK t 14.5 t 14.5 t CONVERT SCLK SCLK t 1.5 t 1.5 t Throughput Time = t + t = 16 t ACQ SCLK SCLK CONVERT ACQ SCLK t 10 10 ns min CS to SCLK Setup Time 1 3 t 30 60 ns max Delay from CS until DOUT 3-State Disabled 2 3 t 75 100 ns max Data Access Time after SCLK Falling Edge 3 t 20 20 ns min Data Setup Time Prior to SCLK Rising Edge 4 t 20 20 ns min Data Valid to SCLK Hold Time 5 t 0.4 t 0.4 t ns min SCLK High Pulsewidth 6 SCLK SCLK t 0.4 t 0.4 t ns min SCLK Low Pulsewidth 7 SCLK SCLK 4 t 80 80 ns max CS Rising Edge to DOUT High Impedance 8 t 55 µs typ Power-Up Time from Shutdown 9 NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V = 5 V ± 10% and time for an output to DD cross 0.4 V or 2.0 V with V = 3 V ± 10%. DD 4 t is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated 8 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 8 time of the part and is independent of the bus loading. Specifications subject to change without notice. I 200�A OL TO 1.6V OUTPUT PIN C L 50pF 200�A I OH Figure 1. Load Circuit for Digital Output Timing Specifications REV. C –4– AD7888 PIN CONFIGURATIONS SOIC AND TSSOP CS 1 16 SCLK REF IN/REF OUT 2 15 DOUT V 3 14 DIN DD AD7888 4 13 AGND AGND TOP VIEW 5 12 AIN8 AIN1 (Not to Scale) AIN2 6 11 AIN7 AIN3 7 10 AIN6 AIN4 8 9 AIN5 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7888 and also frames the serial data transfer. 2 REF IN/REF OUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external reference is from 1.2 V to V . DD 3V Power Supply Input. The V range for the AD7888 is from 2.7 V to 5.25 V. DD DD 4, 13 AGND Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and any external reference signals should be referred to this AGND voltage. Both of these pins should connect to the AGND plane of a system. 5–12 AIN1–AIN8 Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0 through ADD2 bits of the Control Register. The input range for all input channels is 0 to V . Any REF unused input channels should be connected to AGND to avoid noise pickup. 14 DIN Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input and is clocked into the register on the rising edge of SCLK (see Control Register section). 15 DOUT Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. 16 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial data to the Control Register. This clock input is also used as the clock source for the AD7888’s conversion process. REV. C –5– AD7888 TERMINOLOGY Peak Harmonic or Spurious Noise Integral Nonlinearity Peak harmonic or spurious noise is defined as the ratio of the This is the maximum deviation from a straight line passing rms value of the next largest component in the ADC output through the endpoints of the ADC transfer function. The end- spectrum (up to f /2 and excluding dc) to the rms value of the S points of the transfer function are zero scale, a point 1/2 LSB fundamental. Normally, the value of this specification is deter- below the first code transition, and full scale, a point 1/2 LSB mined by the largest harmonic in the spectrum, but for ADCs above the last code transition. where the harmonics are buried in the noise floor, it will be a noise peak. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB Intermodulation Distortion change between any two adjacent codes in the ADC. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion Offset Error products at sum and difference frequencies of mfa ± nfb where This is the deviation of the first code transition (00 . . . 000) to m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are (00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB. those for which neither m nor n is equal to zero. For example, Offset Error Match the second order terms include (fa + fb) and (fa – fb), while the This is the difference in offset error between any two channels. third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Gain Error This is the deviation of the last code transition (111 . . . 110) to The AD7888 is tested using the CCIF standard where two (111 . . . 111) from the ideal (i.e., V – 1.5 LSB) after the REF input frequencies near the top end of the input bandwidth are offset error has been adjusted out. used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order Gain Error Match terms are usually at a frequency close to the input frequencies. This is the difference in gain error between any two channels. As a result, the second and third order terms are specified sepa- Track/Hold Acquisition Time rately. The calculation of the intermodulation distortion is as The track/hold amplifier returns into track mode at the end of per the THD specification where it is the ratio of the rms sum of conversion. Track/Hold acquisition time is the time required for the individual distortion products to the rms amplitude of the the output of the track/hold amplifier to reach its final value, sum of the fundamentals expressed in dBs. within ±1/2 LSB, after the end of conversion. Channel-to-Channel Isolation Signal to (Noise + Distortion) Ratio Channel-to-channel isolation is a measure of the level of crosstalk This is the measured ratio of signal to (noise + distortion) at the between channels. It is measured by applying a full-scale 25 kHz output of the A/D converter. The signal is the rms amplitude of sine wave signal to all nonselected input channels and determin- the fundamental. Noise is the sum of all nonfundamental sig- ing how much that signal is attenuated in the selected channel. nals up to half the sampling frequency (f /2), excluding dc. The S The figure given is the worst case across all four or eight chan- ratio is dependent on the number of quantization levels in the nels for the AD7888. digitization process; the more levels, the smaller the quantiza- PSR (Power Supply Rejection) tion noise. The theoretical signal to (noise + distortion) ratio for Variations in power supply will affect the full-scale transition, an ideal N-bit converter with a sine wave input is given by: but not the converter’s linearity. Power supply rejection is the Signal to (Noise + Distortion) = (6.02 N + 1.76) dB maximum change in the full-scale transition point due to a Thus for a 12-bit converter, this is 74 dB. change in power-supply voltage from the nominal value. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7888, it is defined as: 2 2 2 2 2 VVV ++ ++ VV 2 3 4 5 6 THD(dB)= log V 1 where V is the rms amplitude of the fundamental and V , V , 1 2 3 V , V and V are the rms amplitudes of the second through the 4 5 6 sixth harmonics. REV. C –6– AD7888 CONTROL REGISTER The Control Register on the AD7888 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7888 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer. Only the information provided on the first 8 rising clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The default contents of the Control Register on power-up is all zeros. Table I. Control Register Bit Function Description MSB DO ONTCZ2 ERA1 DDA0 DDAF DDR1 E P0 M PM Bit Mnemonic Comment 7 DONTC Don’t Care. The value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if the bit is 0 or 1. 6 ZERO A zero must be written to this bit to ensure correct operation of the AD7888. 5 ADD2 These three address bits are loaded at the end of the present conversion sequence and select which analog input 4 ADD1 channel is converted for the next conversion. The selected input channel is decoded as shown in Table II. 3 ADD0 2 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is disabled. To obtain best performance from the AD7888, the internal reference should be disabled when using an externally applied reference source. (See On-Chip Reference section.) 1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7888 as shown in Table III. PERFORMANCE CURVES Figure 3 shows a typical plot for the SNR vs. frequency for a Figure 2 shows a typical FFT plot for the AD7888 at 100 kHz 5 V supply and with a 5 V external reference. sample rate and 10 kHz input frequency. 73.0 4096 POINT FFT –10 V = 5V SAMPLING DD 100kSPS 5V EXT REFERENCE f = 10kHz IN 72.5 SNR = 70dB –30 –50 72.0 –70 71.5 –90 –110 71.0 0 12.21 24.41 36.62 48.83 0 10.89 21.14 31.59 42.14 FREQUENCY – kHz INPUT FREQUENCY – kHz Figure 2. Dynamic Performance Figure 3. SNR vs. Input Frequency REV. C –7– dB SNR – dB AD7888 Figure 4 shows the typical power supply rejection ratio vs. CHARGE REDISTRIBUTION frequency for the part. The power supply rejection ratio is defined DAC as the ratio of the power in the ADC output at frequency f SAMPLING to the power of a full-scale sine wave applied to the ADC of CAPACITOR A AIN frequency fs: CONTROL SW1 B LOGIC ACQUISITION PSRR (dB) = 10 log (Pf/Pfs) AGND PHASE SW2 COMPARATOR Pf = Power at frequency f in ADC output, Pfs = power at fre- quency fs in ADC full scale input. Here a 100 mV peak-to-peak (REF IN/REF OUT)/2 sine wave is coupled onto the V supply. Both the 2.7 V and DD Figure 5. ADC Acquisition Phase 5.5 V supply performances are shown. When the ADC starts a conversion, (see Figure 6), SW2 will open –75 and SW1 will move to Position B causing the comparator to V = 5.5V/2.7V DD become unbalanced. The control logic and the charge redistribu- –77 100mV p-p SINE WAVE ON V DD tion DAC are used to add and subtract fixed amounts of charge REF = 2.488V EXT REFERENCE IN –79 from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the –81 conversion is complete. The control logic generates the ADC –83 output code. Figure 7 shows the ADC transfer function. –85 CHARGE –87 REDISTRIBUTION DAC –89 SAMPLING CAPACITOR A –91 VIN CONTROL SW1 LOGIC –93 B CONVERSION 2.65 12.85 23.15 33.65 43.85 54.35 64.15 PHASE SW2 AGND COMPARATOR INPUT FREQUENCY – kHz Figure 4. PSRR vs. Frequency (REF IN/REF OUT)/2 Figure 6. ADC Conversion Phase CIRCUIT INFORMATION The AD7888 is a fast, low power, 12-bit, single supply, 8-channel ADC TRANSFER FUNCTION A/D converter. The part can be operated from 3 V (2.7 V to The output coding of the AD7888 is straight binary. The 3.6 V) supply or from 5 V (4.75 V to 5.25 V) supply. When designed code transitions occur at successive integer LSB operated from either a 5 V supply or a 3 V supply, the AD7888 values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V / is capable of throughput rates of 125 kSPS when provided with REF 4096. The ideal transfer characteristic for the AD7888 is a 2 MHz clock. shown in Figure 7 below. The AD7888 provides the user with an 8-channel multiplexer, on-chip track/hold, A/D converter, reference and serial interface housed in a tiny 16-lead TSSOP package, which offers the user considerable space saving advantages over alternative solutions. 111...111 The serial clock input accesses data from the part and also 111...110 provides the clock source for the successive-approximation A/D converter. The analog input range is 0 to V (where REF 111...000 the externally-applied V can be between 1.2 V and V ). REF DD 1LSB = V /4096 REF 011...111 The 8-channel multiplexer is controlled by the part’s Control Register. This Control Register also allows the user to power-off the internal reference and to determine the Modes of Operation. 000...010 000...001 000...000 CONVERTER OPERATION +V – 1.5LSB 0.5LSB REF 0V The AD7888 is a successive-approximation analog-to-digital ANALOG INPUT converter based around a charge redistribution DAC. Figures 5 Figure 7. Transfer Characteristic and 6 show simplified schematics of the ADC. Figure 5 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on AIN. REV. C –8– PSRR – dB ADC CODE AD7888 TYPICAL CONNECTION DIAGRAM For ac applications, removing high frequency components from Figure 8 shows a typical connection diagram for the AD7888. the analog input signal is recommended by use of an RC low- Both AGND pins are connected to the analog ground plane of pass filter on the relevant analog input pin. In applications the system. V is connected to a well decoupled V pin to where harmonic distortion and signal to noise ratio are critical REF DD provide an analog input range of 0 V to V . The conversion the analog input should be driven from a low impedance source. DD result is output in a 16-bit word with four leading zeroes fol- Large source impedances will significantly affect the ac perfor- lowed by the MSB of the 12-bit result. For applications where mance of the ADC. This may necessitate the use of an input power consumption is of concern, the automatic power down at buffer amplifier. The choice of the op amp will be a function of the end of conversion should be used to improve power perfor- the particular application. mance. See Modes of Operation section of the data sheet. When no amplifier is used to drive the analog input the source impedance should be limited to low values. The maximum SUPPLY 2.7V source impedance will depend on the amount of total harmonic TO 5.25V 10�F 0.1�F distortion (THD) that can be tolerated. The THD will increase SERIAL INTERFACE as the source impedance increases and performance will degrade. V REF IN/ DD Figure 10 shows a graph of the total harmonic distortion versus REF OUT analog input signal frequency for different source impedances. AD7888 AIN1 SCLK 0V TO –65 AIN2 REF IN/ THD vs. FREQUENCY FOR DIFFERENT DOUT REF OUT SOURCE IMPEDANCES �C/�P INPUT AIN8 DIN V = 5V –70 DD 5V EXT REFERENCE CS AGND R = 1k�, C = 100pF IN IN AGND –75 R = 50�, C = 2.2nF IN IN Figure 8. Typical Connection Diagram –80 Analog Input Figure 9 shows an equivalent circuit of the analog input structure –85 of the AD7888. The two diodes D1 and D2 provide ESD pro- tection for the analog inputs. Care must be taken to ensure that R = 10�, C = 10nF IN IN the analog input signal never exceeds the supply rails by more –90 than 200 mV. This will cause these diodes to become forward- 0.15 10.89 21.14 31.59 42.14 49.86 INPUT FREQUENCY – kHz biased and start conducting current into the substrate. 20 mA is the maximum current these diodes can conduct without causing Figure 10. THD vs. Analog Input Frequency irreversible damage to the part. However, it is worth noting that Analog Input Selection a small amount of current (1 mA) being conducted into the On power-up, the default AIN selection is AIN1. When returning substrate due to an overvoltage on an unselected channel, can to normal operation from power-down, the AIN selected will be cause inaccurate conversions on a selected channel. The capaci- the same one that was selected prior to power-down being initi- tor C1 in Figure 9 is typically about 4 pF and can primarily be ated. Table II below shows the multiplexer address correspond- attributed to pin capacitance. The resistor R1 is a lumped com- ing to each analog input from AIN1 to AIN8 for the AD7888. ponent made up of the on resistance of a multiplexer and a switch. This resistor is typically about 100 Ω. The capacitor C2 is the Table II. Channel Configurations ADC sampling capacitor and has a capacitance of 20 pF typically. Note: The analog input capacitance seen when the track and ADD2 ADD1 ADD0 Analog Input Channel hold is in track mode is typically 38 pF, while in hold mode it is 0 0 0 AIN1 typically 4 pF. 0 0 1 AIN2 0 1 0 AIN3 V DD 0 1 1 AIN4 1 0 0 AIN5 D1 C2 1 0 1 AIN6 20pF R1 V 1 1 0 AIN7 IN C1 1 1 1 AIN8 D2 4pF CONVERSION PHASE – SWITCH OPEN On-Chip Reference TRACK PHASE – SWITCH CLOSED The AD7888 has an on-chip 2.5 V reference. This reference can Figure 9. Equivalent Analog Input Circuit be enabled or disabled by clearing or setting the REF bit in the Control Register, respectively. If the on-chip reference is to be used externally in a system, it must be buffered before it is applied elsewhere. If an external reference is applied to the device, the internal reference is automatically overdriven. However, in REV. C –9– THD – dB AD7888 order to obtain optimum performance from the device it is the only way to fully power it up again is to reprogram the advised to disable the internal reference by setting the REF bit power management bits to PM1 = PM0 = 0, i.e., normal in the Control Register when an external reference is applied. mode. In this case the device will power up on the 16th SCLK When the internal reference is disabled, SW1 in Figure 11 will rising edge after the CS falling edge as this is when the power open and the input impedance seen at the REF IN/REF OUT management bits become effective. pin is the input impedance of the reference buffer, which is in Power-Up Times the region of giga Ω. When the reference is enabled, the input The AD7888 has an approximate 1 µs power-up time when impedance seen at the pin is typically 5 kΩ. powering up from standby or when using an external reference. When V is first connected, the AD7888 will fully power up, DD REF IN/REF OUT i.e., it powers up in normal mode. If the part is put into shut- down, a subsequent power-up will take approximately 5 µs. The SW1 AD7888 wake-up time is very short in the autostandby mode so 5k� it is possible to wake up the part and carry out a valid conver- 2.5V sion in the same read/write operation. Figure 11. On-Chip Reference Circuitry POWER vs. THROUGHPUT RATE By operating the AD7888 in autoshutdown or autostandby Table III. Power Management Options mode the average power consumption of the AD7888 decreases at lower throughput rates. Figure 12 shows how as the through- PM1 PM0 Mode put rate is reduced, the device remains in its power-down state 00 Normal Operation. In this mode, the AD7888 longer and the average power consumption over time drops remains in full power mode regardless of the accordingly. status of any of the logic inputs. This mode For example, if the AD7888 were operated in a continuous allows the fastest possible throughput rate from sampling mode, with a throughput rate of 10 kSPS and a SCLK the AD7888. of 2 MHz (V = 5 V), and if PM1 = 1 and PM0 = 0, i.e., the DD 01 Full Shutdown. In this mode, the AD7888 is device is in autoshutdown mode and the on-chip reference is in full shutdown mode with all circuitry on the used, the power consumption is calculated as follows. The AD7888, including the on-chip reference, enter- power dissipation during normal operation is 3.5 mW (V = DD ing its power-down mode. The AD7888 retains 5 V). If the power-up time is 5 µs and the remaining conversion- the information in the control Register bits plus-acquisition time is 15.5 t , i.e., approximately 7.75 µs, SCLK while in full shutdown. The part remains in full (see Figure 14a), the AD7888 can be said to dissipate 3.5 mW shutdown until these bits are changed. for 12.75 µs during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissi- 10 Autoshutdown. In this mode, the AD7888 pated during each cycle is (12.75/100) × (3.5 mW) = 446.25 µW. automatically enters full shutdown mode at the If V = 3 V SCLK = 2 MHz, and the device is again in auto- DD end of each conversion. Wake-up time from full shutdown mode using the on-chip reference, the power dissipa- shutdown is 5 µs and the user should ensure that tion during normal operation is 2.1 mW. The AD7888 can now 5 µs have elapsed before attempting to perform be said to dissipate 2.1 mW for 12.75 µs during each conversion a valid conversion on the part in this mode. cycle. With a throughput rate of 10 kSPS, the average power 11 Autostandby. In this standby mode, portions dissipated during each cycle is (12.75/100) × (2.1 mW) = of the AD7888 are powered down but the on- 267.75 µW. Figure 12 shows the power vs. throughput rate for chip reference voltage remains powered up. The automatic shutdown with both 5 V and 3 V supplies. REF bit should be 0 to ensure the on-chip refer- ence is enabled. This mode is similar to auto- 10 shutdown but allows the part to power-up much faster. V = 5V DD SCLK = 2MHz 1 POWER-DOWN OPTIONS The AD7888 provides flexible power management to allow the user to achieve the best power performance for a given through- V = 3V DD put rate. SCLK = 2MHz The power management options are selected by programming 0.1 the power management bits (i.e., PM1 and PM0) in the control register. Table III summarizes the options available. When the power management bits are programmed for either of the auto power-down modes, the part will enter the power-down mode 0.01 0 10 20 30 40 50 on the 16th rising SCLK edge after the falling edge of CS. The THROUGHPUT – kSPS first falling SCLK edge after the CS falling edge will cause the part to power up again. When the AD7888 is in full shutdown, Figure 12. Power vs. Throughput REV. C –10– POWER – mW AD7888 THE PART REMAINS POWERED UP AT ALL TIMES AS PM1 AND PM0 = 0 CS 16 1 SCLK DOUT 4 LEADING ZEROES + CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS. PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE Figure 13. Normal-Mode Operation MODES OF OPERATION Full Shutdown (PM1 = 0, PM0 = 1) The AD7888 has a number of different modes of operation. In this mode, all internal circuitry on the AD7888, including the These are designed to provide flexible power management on-chip reference, is powered-down. The part retains the infor- options. These options can be chosen to optimize the power mation in the Control Register during full shutdown. The part dissipation/throughput rate ratio for differing application require- remains in full shutdown until the power management bits are ments. The modes of operation are controlled by the PM1 and changed. If the power management bits are changed to PM1 = 1 PM0 bits of the Control Register as outlined previously. and PM0 = 0, i.e., the autoshutdown mode, the part will remain in shutdown (now in autoshutdown) but will power up once a Normal Mode (PM1 = 0, PM0 = 0) conversion is initiated after that (see Power-Up Times section). This mode is intended for fastest throughput rate performance The part changes mode as soon as the control register has been as the user does not have to worry about any power-up times updated, so if the part is in full shutdown mode and the power with the AD7888 remaining fully powered all the time. Figure management bits are changed to PM1 = PM0 = 0, i.e., normal 13 shows the general diagram of the operation of the AD7888 in mode, then the part will power up on the 16th SCLK rising edge. this mode. Autoshutdown (PM1 = 1, PM0 = 0) The data presented to the AD7888 on the DIN line during the In this mode, the AD7888 automatically enters its power-down first eight clock cycles of the data transfer are loaded to the mode at the end of every conversion. Figure 14a shows the Control Register. The part will remain powered up at the end of general diagram of the operation of the AD7888 in this mode. the conversion as long as PM1 and PM0 were set to zero in the write during that conversion. To continue to operate in this When CS goes from high to low, all on-chip circuitry will start mode, the user must ensure that PM1 and PM0 are both loaded to power up on the next falling edge of SCLK. On the sixteenth with 0 on every data transfer. SCLK rising edge the part will power down again. It takes approximately 5 µs for the AD7888 internal circuitry to be fully The falling edge of CS initiates the sequence and the input powered up. As a result, a conversion (or sample-and-hold signal is sampled on the second rising edge of the SCLK input. acquisition) should not be initiated during this 5 µs. The input Sixteen serial clock cycles are required to complete the conver- signal is sampled on the second rising edge of SCLK following sion and access the conversion result. Once a data transfer is the CS falling edge. The user should ensure that 5 µs elapse complete (CS has returned high), another conversion can be between the first falling edge of SCLK after the falling edge of initiated immediately by bringing CS low again. THE PART ENTERS THE PART POWERS UP FROM SHUTDOWN AT THE END OF SHUTDOWN ON SCLK FALLING EDGE AS CONVERSION AS PM1 = 1 AND PM0 = 0 PM1 = 1 AND PM0 = 0 CS 16 16 1 2 1 SCLK t = 5�s 10 DOUT 4 LEADING ZEROES + CONVERSION RESULT 4 LEADING ZEROES + CONVERSION RESULT DATA IN DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE PM1 = 1 AND PM0 = 0 TO KEEP THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0 PART IN THIS MODE Figure 14a. Autoshutdown Operation REV. C –11– AD7888 THE PART ENTERS THE PART ENTERS SHUTDOWN AT THE END SHUTDOWN AT THE END OF OF CONVERSION AS THE PART BEGINS TO POWER- THE PART REMAINS POWERED CONVERSION AS PM1 = 1 PM1 = 1 AND PM0 = 0 UP FROM SHUTDOWN UP AS PM1 AND PM0 = 0 AND PM0 = 0 CS 8 16 8 1 8 16 1 116 SCLK 4 LEADING ZEROES 4 LEADING ZEROES 4 LEADING ZEROES DOUT + CONVERSION RESULT + CONVERSION RESULT + CONVERSION RESULT DIN DATA IN DATA IN DATA IN PM1 = 1 AND PM0 = 0 TO CONTROL REGISTER DATA IS LOADED ON PM1 AND PM0 = 0 TO PLACE PLACE THE PART BACK IN THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0 THE PART IN NORMAL MODE AUTOSHUTDOWN MODE Figure 14b. Autoshutdown Operation Autostandby (PM1 = 1, PM0 = 1) CS and the second rising edge of SCLK as shown in Figure 14a. In this mode, the AD7888 automatically enters a standby (or In microcontroller applications, this is readily achievable by sleep) mode at the end of every conversion. In this standby driving the CS input from one of the port lines and ensuring mode, all on-chip circuitry, apart from the on-chip reference, is that the serial data read (from the microcontrollers serial port) is powered down. This mode is similar to the autoshutdown but not initiated for 5 µs. In DSP applications, where the CS is in this case, the power-up time is much shorter as the on-chip generally derived from the serial frame synchronization line, it is reference remains powered up at all times. not possible to separate the first falling edge and second rising edge of SCLK after the CS falling edge by up to 5 µs. There- Figure 15 shows the general diagram of the operation of the fore, the user will need to write to the Control Register to exit AD7888 in this mode. On the first falling SCLK edge after CS this mode and (by writing PM1 = 0 and PM0 = 0) put the part goes low, the AD7888 comes out of standby. The AD7888 into normal mode. A second conversion will then need to be wake-up time is very short in this mode so it is possible to wake initiated when the part is powered up to obtain a conversion up the part and carry out a valid conversion in the same read/ result as shown in Figure 14b. write operation. The input signal is sampled on the second rising edge of SCLK following the CS falling edge. At the end of conversion (last rising edge of SCLK) the part automatically enters its standby mode. THE PART POWERS UP THE PART ENTERS FROM STANDBY ON SCLK STANDBY AT THE END OF FALLING EDGE AS PM1 = 1 CONVERSION AS AND PM0 = 1 PM1 = 1 AND PM0 = 1 CS 1 16 1 16 SCLK 4 LEADING ZEROES + CONVERSION RESULT 4 LEADING ZEROES + CONVERSION RESULT DOUT DATA IN DATA IN DIN CONTROL REGISTER DATA IS LOADED ON PM1 = 1 AND PM0 = 1 TO KEEP THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1 THE PART IN THIS MODE Figure 15. Autostandby Operation REV. C –12– AD7888 SERIAL INTERFACE Writing of information to the Control Register takes place on Figure 16 shows the detailed timing diagram for serial interfac- the first eight rising edges of SCLK in a data transfer. The Con- ing to the AD7888. The serial clock provides the conversion trol Register is always written to when a data transfer takes clock and also controls the transfer of information to and from place. The user must be careful to always set up the correct the AD7888 during conversion. information on the DIN line when reading data from the part. CS initiates the data transfer and conversion process. For the Sixteen serial clock cycles are required to perform the conver- autoshutdown mode, the first falling edge of SCLK after the sion process and to access data from the AD7888. In applica- falling edge of CS wakes up the part. In all cases, it gates the tions where the first serial clock edge, following CS going low, is serial clock to the AD7888 and puts the on-chip track/hold into a falling edge, this edge clocks out the first leading zero. Thus, track mode. The input signal is sampled on the second rising the first rising clock edge on the SCLK clock has the first lead- edge of the SCLK input after the falling edge of CS. Thus, the ing zero provided. In applications where the first serial clock first one and one-half clock cycles after the falling edge of CS is edge, following CS going low, is a rising edge, the first leading when the acquisition of the input signal takes place. This time is zero may not be set up in time for the processor to read it cor- denoted as the acquisition time (t ). In autoshutdown mode, rectly. However, subsequent bits are clocked out on the falling ACQ the acquisition time must allow for the wake-up time of 5 µs. The edge of SCLK so they are provided to the processor on the on-chip track/hold goes from track mode to hold mode on the following rising edge. Thus, the second leading zero is clocked second rising edge of SCLK and a conversion is also initiated on out on the falling edge subsequent to the first rising edge. The this edge. The conversion process takes a further fourteen and final bit in the data transfer is valid on the 16th rising edge, one-half SCLK cycles to complete. The rising edge of CS will having being clocked out on the previous falling edge. put the bus back into three-state. If CS is left low a new conver- NOTE: The mark space ratio for SCLK is specified for at least sion will be initiated. 40% high time (with corresponding 60% low time) or 40% low The input channel that is sampled is the one selected in the time (with corresponding 60% high time). As the SCLK frequency previous write to the Control Register. Thus, the user must is reduced, the mark space ratio may vary provided the conver- write ahead of the channel for conversion. In other words, the sion time never exceeds 50 µs—to avoid capacitive droop effects. user must write the channel address for the next conversion while the present conversion is in progress. t ACQ t CONVERT CS t t 1 6 15 23 46 16 15 SCLK t t t 7 8 2 t 3 THREE- THREE- 4 LEADING ZEROS STATE STATE DB11 DB10 DB9 DB0 DOUT t 4 t 5 DIN DONTC ZERO ADD2 ADD1 ADD0 REF PM1 PM0 Figure 16. Serial Interface Timing Diagram REV. C –13– AD7888 MICROPROCESSOR INTERFACING The Timer Registers, etc., are loaded with a value that will The serial interface on the AD7888 allows the part to be directly provide an interrupt at the required sample interval. When an connected to a range of many different microprocessors. This interrupt is received, a value is transmitted with TFS/DT (ADC section explains how to interface the AD7888 with some of the control word). The TFS is used to control the RFS and hence more common microcontroller and DSP serial interface protocols. the reading of data. The frequency of the serial clock is set in the SCLKDIV Register. When the instruction to transmit with AD7888 to TMS320C5x TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The serial interface on the TMS320C5x uses a continuous serial The DSP will wait until the SCLK has gone high, low and high clock and frame synchronization signals to synchronize the data before transmission will start. If the timer and SCLK values are transfer operations with peripheral devices like the AD7888. chosen such that the instruction to transmit occurs on or near The CS input allows easy interfacing with an inverter between the rising edge of SCLK, the data may be transmitted or it may the serial clock of the TMS320C5x and the AD7888 being the wait until the next clock edge. only glue logic required. The serial port of the TMS320C5x is set up to operate in burst mode with internal CLKX (TX serial For example, the ADSP-2111 has a master clock frequency of clock) and FSX (TX frame sync). The serial port control register 16 MHz. If the SCLKDIV Register is loaded with the value 3, a (SPC) must have the following setup: FO = 0, FSM = 1, MCM SCLK of 2 MHz is obtained, and eight master clock periods will = 1 and TXM = 1. The connection diagram is shown in Figure 17. elapse for every one SCLK period. If the timer registers are loaded with the value 803, then 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. The TMS320C5x* AD7888* situation will result in nonequidistant sampling as the transmit CLKX SCLK instruction is occurring on a SCLK edge. If the number of SCLKs CLKR between interrupts is not a figure of N.5, equidistant sampling DOUT DR will be implemented by the DSP. DIN DT FSX CS AD7888* ADSP-21xx* FSR SCLK SCLK DR DOUT *ADDITIONAL PINS OMITTED FOR CLARITY DIN DT Figure 17. Interfacing to the TMS320C5x RFS CS AD7888 to ADSP-21xx TFS The ADSP-21xx family of DSPs are interfaced to the AD7888 with an inverter between the serial clock of the ADSP-21xx *ADDITIONAL PINS OMITTED FOR CLARITY and the AD7888. This is the only glue logic required. The SPORT Figure 18. Interfacing to the ADSP-21xx control register should be set up as follows: AD7888 to DSP56xxx TFSW = RFSW = 1, Alternate Framing The connection diagram in Figure 19 shows how the AD7888 INVRFS = INVTFS = 1, Active Low Frame Signal can be connected to the SSI (Synchronous Serial Interface) of DTYPE = 00, Right Justify Data the DSP56xxx family of DSPs from Motorola. The SSI is oper- SLEN = 1111, 16-Bit Data Words ated in synchronous mode (SYN bit in CRB = 1) with internally ISCLK = 1, Internal Serial Clock generated 1-bit clock period frame sync for both TX and RX TFSR = RFSR = 1, Frame Every Word (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to IRFS = 0 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An inverter is ITFS = 1 also necessary between the SCLK from the DSP56xxx and the The connection diagram is shown in Figure 18. The ADSP- SCLK pin of the AD7888 as shown in Figure 19. 21xx has the TFS and RFS of the SPORT tied together with TFS set as an output and RFS set as in input. The DSP oper- ated in Alternate Framing Mode and the SPORT Control Reg- AD7888* DSP56xxx* ister is set up as described. The frame synchronization signal SCLK SCK generated on the TFS is tied to CS and, as with all signal pro- DOUT SRD cessing applications, equidistant sampling is necessary. How- DIN STD ever, in this example the timer interrupt is used to control the SC2 CS sampling rate of the ADC and, under certain conditions, equi- distant sampling may not be achieved. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. Interfacing to the DSP56xxx REV. C –14– AD7888 AD7888 to MC68HC11 APPLICATION HINTS The Serial Peripheral Interface (SPI) on the MC68HC11 is Grounding and Layout configured for Master Mode (MSTR = 1), Clock Polarity Bit The AD7888 has very good immunity to noise on the power (CPOL) = 1 and the Clock Phase Bit (CPHA) = 1. The SPI is supplies as can be seen by the PSRR vs. Frequency graph. configured by writing to the SPI Control Register (SPCR)—see However, care should still be taken with regard to grounding 68HC11 User Manual. The serial transfer will take place as two and layout. 8-bit operations. A connection diagram is shown in Figure 20. The printed circuit board that houses the AD7888 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of MC68HC11* AD7888* ground planes that can be easily separated. A minimum etch SCLK SCLK/PD4 technique is generally best for ground planes as it gives the best MISO/PD2 DOUT shielding. Digital and analog ground planes should be joined in DIN MOSI/PD3 only one place. Both AGND pins of the AD7888 should be sunk in the AGND plane. The AGND plane and DGND plane PA0 CS connection should be made at one point only, a star ground point that should be established as close as possible to an AGND *ADDITIONAL PINS OMITTED FOR CLARITY pin of the AD7888. Figure 20. Interfacing to the MC68HC11 Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed AD7888 to 8051 to run under the AD7888 to avoid noise coupling. The power It is possible to implement a serial interface using the data supply lines to the AD7888 should use as large a trace as pos- ports on the 8051. This allows a full duplex serial transfer to be sible to provide low impedance paths and reduce the effects of implemented. The technique involves “bit-banging” an I/O port glitches on the power supply line. Fast switching signals like (e.g., P1.0) to generate a serial clock and using two other I/O clocks should be shielded with digital ground to avoid radiating ports (e.g., P1.1 and P1.2) to shift data in and out—see noise to other sections of the board, and clock signals should Figure 21. never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should AD7888* 8051* run at right angles to each other. This will reduce the effects of P1.0 SCLK feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In P1.1 DOUT this technique, the component side of the board is dedicated to P1.2 DIN ground planes while signals are placed on the solder side. P1.3 CS Good decoupling is also important. All analog supplies should be decoupled with 10µF tantalum in parallel with 0.1µF capaci- *ADDITIONAL PINS OMITTED FOR CLARITY tors to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the Figure 21. Interfacing to the 8051 Using I/O Ports device, ideally right up against the device. AD7888 to PIC16C6x/7x Evaluating the AD7888 Performance The PIC16C6x Synchronous Serial Port (SSP) is configured The recommended layout for the AD7888 is outlined in the as an SPI Master with the Clock Polarity Bit = 1. This is done evaluation board for the AD7888. The evaluation board pack- by writing to the Synchronous Serial Port Control Register age includes a fully assembled and tested evaluation board, (SSPCON). See user PIC16/17 Microcontroller User Manual. documentation, and software for controlling the board from the Figure 22 shows the hardware connections needed to interface PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL to the PIC16/17. In this example I/O port RA1 is being used to BOARD can be used in conjunction with the AD7888 evalua- pulse CS. This microcontroller only transfers eight bits of data tion board, as well as many other Analog Devices evaluation during each serial transfer operation. Therefore, two consecutive boards ending in the CB designator, to demonstrate/evaluate read/write operations are needed. the ac and dc performance of the AD7888. The software allows the user to perform ac (fast Fourier trans- AD7888* PIC16C6x/7x* form) and dc (histogram of codes) tests on the AD7888. SCK/RC3 SCLK SDO/RC5 DOUT DIN SDI/RC4 CS RA1 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Interfacing to the PIC16C6x/17x REV. C –15– AD7888 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 16 9 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 8 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 23. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. C| Page 16 of 17 060606-A AD7888 ORDERING GUIDE Linearity Temperature Package 1 2 Model Notes Error (LSB) Range Package Description Option AD7888ARU ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARU-REEL ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARU-REEL7 ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARUZ ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARUZ-REEL ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARUZ-REEL7 ±2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7888ARZ ±2 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD7888ARZ-REEL ±2 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD7888ARZ-REEL7 ±2 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD7888BR-REEL ±1 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD7888BR-REEL7 ±1 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD7888BRZ ±1 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 3 EVAL-AD7888CB 1 Z = RoHS Compliant Part. 2 Linearity error here refers to integral linearity error. 3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. REVISION HISTORY 6/10—Rev. B to Rev. C Changes to Standby Mode Parameter, AD7888 Specifications Section ............................................................................................... 3 Changes to Operating Temperature Range, Commercial (B Version) Parameter, Absolute Maximum Ratings Section ..... 3 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 6/01—Rev. A to Rev. B Edit to DC Accuracy Section of Specifications ............................ 2 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01356-0-6/10(C) Rev. C | Page 17 of 17