ANALOG DEVICES AD7887

2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP AD7887 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for V of 2.7 V to 5.25 V DD AD7887 AIN0 Flexible power/throughput rate management I/P T/H MUX Shutdown mode: 1 μA max AIN1/ One or two single-ended inputs V REF 2.5V Serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible COMP REF 8-lead narrow SOIC and MSOP packages AIN1/V REF SOFTWARE V BUF DD CONTROL APPLICATIONS LATCH Battery-powered systems (personal digital assistants, GND CHARGE medical instruments, mobile communications) REDISTRIBUTION DAC Instrumentation and control systems High speed modems SAR + ADC CONTROL LOGIC SPORT DIN CS DOUT SCLK Figure 1. GENERAL DESCRIPTION The AD7887 is a high speed, low power, 12-bit analog-to-digital a result, the input voltage range on both the AIN0 and AIN1 converter (ADC) that operates from a single 2.7 V to 5.25 V inputs is 0 to VDD. power supply. The AD7887 is capable of 125 kSPS throughput CMOS construction ensures low power dissipation of typically rate. The input track-and-hold acquires a signal in 500 ns and 2 mW for normal operation and 3 μW in power-down mode. features a single-ended sampling scheme. The output coding for The part is available in an 8-lead, 0.15-inch-wide narrow body the AD7887 is straight binary, and the part is capable of SOIC and an 8-lead MSOP package. converting full power signals of up to 2.5 MHz. PRODUCT HIGHLIGHTS The AD7887 can be configured for either dual- or single-channel 1. Smallest 12-bit dual-/single-channel ADC; 8-lead MSOP operation via the on-chip control register. There is a default package. single-channel mode that allows the AD7887 to be operated as a read-only ADC. In single-channel operation, there is one 2. Lowest power 12-bit dual-/single-channel ADC. analog input (AIN0) and the AIN1/V pin assumes its V REF REF 3. Flexible power management options, including automatic function. This V pin allows the user access to the part’s REF power-down after conversion. internal 2.5 V reference, or the V pin can be overdriven by an REF 4. Read-only ADC capability. external reference to provide the reference voltage for the part. This external reference voltage has a range of 2.5 V to VDD. The 5. Analog input range from 0 V to VREF. analog input range on AIN0 is 0 to VREF. 6. Versatile serial input/output port (SPI/QSPI/MICROWIRE/ In dual-channel operation, the AIN1/VREF pin assumes its AIN1 DSP compatible). function, providing a second analog input channel. In this case, the reference voltage for the part is provided via the V pin. As DD Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06191-001 AD7887 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 11  Applications ....................................................................................... 1  Circuit Information .................................................................... 11  Functional Block Diagram .............................................................. 1  Converter Operation .................................................................. 11  General Description ......................................................................... 1  ADC Transfer Function ............................................................. 11  Product Highlights ........................................................................... 1  Typical Connection Diagram ................................................... 11  Revision History ............................................................................... 2  Analog Input ............................................................................... 12  Specif ica t ions ..................................................................................... 3  Power-Down Options ................................................................ 13  Timing Specifications .................................................................. 5  Power vs. Throughput Rate ....................................................... 13  Absolute Maximum Ratings ............................................................ 6  Modes of Operation ................................................................... 13  ESD Caution .................................................................................. 6  Serial Interface ............................................................................ 17  Pin Configurations and Function Descriptions ........................... 7  Microprocessor Interfacing ....................................................... 18  Typical Performance Characteristics ............................................. 8  Application Hints ....................................................................... 20  Terminology ...................................................................................... 9  Outline Dimensions ....................................................................... 21  Control Register .............................................................................. 10  Ordering Guide .......................................................................... 21  REVISION HISTORY 2/09—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 21 9/06—Rev. B to Rev. C Updated Format .................................................................. Universal Change to Absolute Maximum Ratings ......................................... 6 Additions to Pin Configurations .................................................... 7 Added Table 7 .................................................................................. 18 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 Rev. D | Page 2 of 24 AD7887 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VREF = 2.5 V, external/internal reference unless otherwise noted, fSCLK = 2 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 1 Parameter A Version B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2, 3 Signal to Noise + Distortion Ratio (SNR) 71 71 dB typ f = 10 kHz sine wave, f = 125 kSPS IN SAMPLE 2 Total Harmonic Distortion (THD) −80 −80 dB typ fIN = 10 kHz sine wave, fSAMPLE = 125 kSPS 2 Peak Harmonic or Spurious Noise –80 −80 dB typ fIN = 10 kHz sine wave, fSAMPLE = 125 kSPS 2 Intermodulation Distortion (IMD) Second-Order Terms −80 −80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 125 kSPS SAMPLE Third-Order Terms −80 −80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 125 kSPS SAMPLE 2 Channel-to-Channel Isolation −80 −80 dB typ f = 25 kHz IN Full-Power Bandwidth 2.5 2.5 MHz typ @ 3 dB DC ACCURACY Any channel Resolution 12 12 Bits 2 Integral Nonlinearity ±2 ±1 LSB max 2 Differential Nonlinearity ±2 ±1 LSB max Guaranteed no missing codes to 11 bits (A Grade) 2 Offset Error ±3 ±3 LSB max V = 5 V, dual-channel mode DD ±4 ±4 LSB max V = 3 V, dual-channel mode DD ±6 ±6 LSB typ Single-channel mode 2 Offset Error Match 0.5 0.5 LSB max 2 Gain Error ±2 ±2 LSB max Dual-channel mode ±1 ±1 LSB max Single-channel mode, external reference ±6 ±6 LSB typ Single-channel mode, internal reference 2 Gain Error Match 2 2 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V REF REF Leakage Current ±5 ±5 μA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REF Input Voltage Range 2.5/V 2.5/V V min/max Functional from 1.2 V IN DD DD Input Impedance 10 10 kΩ typ Very high impedance if internal reference disabled REFOUT Output Voltage 2.45/2.55 2.45/2.55 V min/max REFOUT Temperature Coefficient ±50 ±50 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min VDD = 4.75 V to 5.25 V 2.1 2.1 V min VDD = 2.7 V to 3.6 V Input Low Voltage, V 0.8 0.8 V max V = 2.7 V to 5.25 V INL DD Input Current, I ±1 ±1 μA max Typically 10 nA, V = 0 V or V IN IN DD 4 Input Capacitance, CIN 10 10 pF max LOGIC OUTPUTS Output High Voltage, V I = 200 μA OH SOURCE VDD − 0.5 VDD − 0.5 V min VDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 ±1 μA max 5 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary Rev. D | Page 3 of 24 AD7887 1 1 Parameter A Version B Version Unit Test Conditions/Comments CONVERSION RATE Throughput Time 16 16 SCLK cycles Conversion time plus acquisition time is 125 kSPS, with 2 MHz Clock 2 Track/Hold Acquisition Time 1.5 1.5 SCLK cycles Conversion Time 14.5 14.5 SCLK cycles 7.25 μs (2 MHz Clock) POWER REQUIREMENTS V +2.7/+5.25 +2.7/+5.25 V min/max DD I DD 5 Normal Mode (Mode 2) Static 700 700 μA max Operational (fSAMPLE = 125 kSPS) 850 850 μA typ Internal reference enabled 700 700 μA typ Internal reference disabled Using Standby Mode (Mode 4) 450 450 μA typ f = 50 kSPS SAMPLE Using Shutdown Mode (Modes 1, 3) 120 120 μA typ f = 10 kSPS SAMPLE 12 12 μA typ fSAMPLE = 1 kSPS 6 Standby Mode 210 210 μA max VDD = 2.7 V to 5.25 V 6 Shutdown Mode 1 1 μA max VDD = 2.7 V to 3.6 V 2 2 μA max V = 4.75 V to 5.25 V DD Normal Mode Power Dissipation 3.5 3.5 mW max V = 5 V DD 2.1 2.1 mW max VDD = 3 V Shutdown Power Dissipation 5 5 μW max VDD = 5 V 3 3 μW max VDD = 3 V Standby Power Dissipation 1.05 1.05 mW max VDD = 5 V 630 630 μW max V = 3 V DD 1 Temperature range for A and B versions is −40°C to +125°C. 2 See the Terminology section. 3 SNR calculation includes distortion and noise components. 4 Sample tested at +25°C to ensure compliance. 5 CS All digital inputs at GND except at VDD. No load on the digital outputs. Analog inputs at GND. 6 SCLK at GND when SCLK off. All digital inputs at GND except for CS at V . No load on the digital outputs. Analog inputs at GND. DD Rev. D | Page 4 of 24 AD7887 1 TIMING SPECIFICATIONS Table 2. Limit at TMIN, TMAX (A, B Versions) Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description 2 f 2 2 MHz max SCLK tCONVERT 14.5 × tSCLK 14.5 × tSCLK t 1.5 × t 1.5 × t Throughput time = t + t = 16 t ACQ SCLK SCLK CONVERT ACQ SCLK t1 10 10 ns min CS to SCLK setup time 3 t2 30 60 ns max Delay from CS until DOUT three-state disabled 3 t3 75 100 ns max Data access time after SCLK falling edge t 20 20 ns min Data setup time prior to SCLK rising edge 4 t 20 20 ns min Data valid to SCLK hold time 5 t 0.4 × t 0.4 × t ns min SCLK high pulse width 6 SCLK SCLK t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width 4 t8 80 80 ns max CS rising edge to DOUT high impedance t9 5 5 μs typ Power-up time from shutdown 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated 8 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 5 of 24 06191-002 AD7887 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND −0.3 V to +7 V DD rating only; functional operation of the device at these or any Analog Input Voltage to AGND −0.3 V to V + 0.3 V DD other conditions above those indicated in the operational Digital Input Voltage to AGND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Digital Output Voltage to AGND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect REFIN/REFOUT to AGND −0.3 V to VDD + 0.3 V device reliability. 1 Input Current to Any Pin Except Supplies ±10 mA ESD CAUTION Operating Temperature Range Commercial Temperature Range A, B Versions −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature +150°C SOIC or MSOP Package Power Dissipation 450 mW θ Thermal Impedance 157°C/W (SOIC) JA 205.9°C/W (MSOP) θJC Thermal Impedance 56°C/W (SOIC) 43.74°C/W (MSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Pb-Free Temperature, Soldering Reflow 260(0)°C ESD 4 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. D | Page 6 of 24 AD7887 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CS 1 8 SCLK CS 1 8 SCLK AD7887 V 2 AD7887 7 DOUT V 2 7 DOUT DD DD TOP VIEW GND 3 6 DIN GND 3 6 DIN TOP VIEW (Not to Scale) (Not to Scale) AIN1/V 4 5 AIN0 AIN1/V 4 5 AIN0 REF REF Figure 3. SOIC_N Pin Configuration Figure 4. MSOP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode. 2 VDD Power Supply Input. The VDD range for the AD7887 is from 2.7 V to 5.25 V. When the AD7887 is configured for two-channel operation, this pin also provides the reference source for the part. 3 GND Ground Pin. This pin is the ground reference point for all circuitry on the AD7887. In systems with separate AGND and DGND planes, these planes should be tied together as close as possible to this GND pin. Where this is not possible, this GND pin should connect to the AGND plane. 4 AIN1/V Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/output. REF In this case, the user can either access the internal 2.5 V reference or overdrive the internal reference with the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.2 V to VDD. In two- channel mode, this pin provides the second analog input channel, AIN1. The input voltage range on AIN1 is 0 to V . DD 5 AIN0 Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to V . In dual- REF channel mode, it has an analog input range of 0 to VDD. 6 DIN Data In. Logic Input. Data to be written to the AD7887’s control register is provided on this input and clocked into the register on the rising edge of SCLK (see the Control Register section). The AD7887 can be operated as a single-channel, read-only ADC by tying the DIN line permanently to GND. 7 DOUT Data Out. Logic output. The conversion result from the AD7887 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. 8 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part and writing serial data to the control register. This clock input is also used as the clock source for the AD7887’s conversion process. Rev. D | Page 7 of 24 06191-003 06191-004 AD7887 TYPICAL PERFORMANCE CHARACTERISTICS 0 –75 4096 POINT FFT V = 5.5V/2.7V DD –77 SAMPLING 100mV p-p SINE WAVE ON V DD –10 125kSPS REF = 2.488V EXT REFERENCE IN f = 10kHz –79 IN SNR = 71dB –30 –81 –83 –50 –85 –87 –70 –89 –90 –91 –110 –93 2.65 12.85 23.15 33.65 43.85 54.35 64.15 INPUT FREQUENCY (kHz) Figure 5. Dynamic Performance Figure 7. PSRR vs. Frequency 73.0 V = 5V DD 5V EXT REFERENCE 72.5 72.0 71.5 71.0 0.15 10.89 21.14 31.59 42.14 INPUT FREQUENCY (kHz) Figure 6. SNR vs. Input Frequency Rev. D | Page 8 of 24 SNR (dB) 0 6.103516 12.20703 18.31055 24.41406 30.51758 36.62109 42.72461 48.82813 54.93164 61.03516 06191-005 06191-006 PSRR (dB) 06191-007 AD7887 TERMINOLOGY Peak Harmonic or Spurious Noise Integral Nonlinearity Peak harmonic or spurious noise is defined as the ratio of the This is the maximum deviation from a straight line passing rms value of the next largest component in the ADC output through the endpoints of the ADC transfer function. The end- spectrum (up to fS/2 and excluding dc) to the rms value of the points of the transfer function are zero scale, a point ½ LSB fundamental. Normally, the value of this specification is below the first code transition, and full scale, a point ½ LSB determined by the largest harmonic in the spectrum, but for above the last code transition. ADCs where the harmonics are buried in the noise floor, the Differential Nonlinearity largest harmonic could be a noise peak. This is the difference between the measured and the ideal 1 LSB Intermodulation Distortion change between any two adjacent codes in the ADC. With inputs consisting of sine waves at two frequencies, fa and fb, Offset Error any active device with nonlinearities creates distortion products This is the deviation of the first code transition (00 . . . 000) to at sum and difference frequencies of mfa ± nfb where m, n = 0, (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. 1, 2, 3, and so on. Intermodulation distortion terms are those for Offset Error Match which neither m nor n are equal to 0. For example, the second- This is the difference in offset error between any two channels. order terms include (fa + fb) and (fa − fb), and the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb). Gain Error This is the deviation of the last code transition (111 . . . 110) to The AD7887 is tested using the CCIF standard in which two (111 . . . 111) from the ideal (that is, VREF − 1.5 LSB) after the input frequencies near the top end of the input bandwidth are offset error has been adjusted out. used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order Gain Error Match terms are usually at a frequency close to the input frequencies. This is the difference in gain error between any two channels. As a result, the second- and third-order terms are specified Track/Hold Acquisition Time separately. The calculation of the intermodulation distortion is The track/hold amplifier returns to track mode at the end of as per the THD specification, where it is the ratio of the rms conversion. Track/hold acquisition time is the time required for sum of the individual distortion products to the rms amplitude the output of the track/hold amplifier to reach its final value, of the sum of the fundamentals expressed in decibels. within ±1/2 LSB, after the end of a conversion. Channel-to-Channel Isolation Signal to (Noise + Distortion) Ratio Channel-to-channel isolation is a measure of the level of This is the measured ratio of signal to (noise + distortion) at the crosstalk between channels. It is measured by applying a full- output of the ADC. The signal is the rms amplitude of the fun- scale 25 kHz sine wave signal to the nonselected input channel damental. Noise is the sum of all nonfundamental signals up to half and determining how much that signal is attenuated in the the sampling frequency (f /2), excluding dc. The ratio is dependent S selected channel. The figure given is the worst case across both on the number of quantization levels in the digitization process: the channels for the AD7887. more levels, the smaller the quantization noise. The theoretical Power Supply Rejection (PSR) signal to (noise + distortion) ratio for an ideal N-bit converter Variations in power supply affect the full-scale transition, but with a sine wave input is given by not the converter’s linearity. PSR is the maximum change in the Signal to (Noise + Distortion) = (6.02 N + 1.76) dB full-scale transition point due to a change in power supply voltage Thus for a 12-bit converter, this is 74 dB. from the nominal value. See Figure 7. Total Harmonic Distortion PSRR is defined as the ratio of the power in the ADC output at Total harmonic distortion (THD) is the ratio of the rms sum of frequency f to the power of a full-scale sine wave applied to the harmonics to the fundamental. For the AD7887, it is defined as ADC of frequency fS: 2 2 2 2 2 PSRR (dB) = 10 log(Pf/Pfs) V + V + V + V + V 2 3 4 5 6 THD(dB)= 20 log where Pf is the power at frequency f in ADC output and Pfs is V 1 the power at frequency f in ADC full-scale input. S where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Rev. D | Page 9 of 24 AD7887 CONTROL REGISTER The control register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer. Only the information provided on the first eight rising clock edges after CS falling edge is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 5. The contents of the control register on power up is all 0s. MSB DONTC ZERO REF SIN/DUAL CH ZERO PM1 PM0 Table 5. Control Register Bit Mnemonic Comment 7 DONTC Don’t Care. The value written to this bit of the control register is a don’t care, that is, it doesn’t matter if the bit is 0 or 1. 6 ZERO A zero must be written to this bit to ensure correct operation of the AD7887. 5 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is disabled. 4 SIN/DUAL Single/Dual Bit. This bit determines whether the AD7887 operates in single-channel or dual-channel mode. A 0 in this bit selects single-channel operation and the AIN1/VREF pin assumes its VREF function. A 1 in this bit selects dual-channel mode, with the reference voltage for the ADC internally connected to VDD and the AIN1/VREF pin assuming its AIN1 function as the second analog input channel. To obtain best performance from the AD7887, the internal reference should be disabled when operating in the dual-channel mode, that is, REF = 1. 3 CH Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel is converted for the next conversion. A 0 in this bit selects the AIN0 input, and a 1 in this bit selects the AIN1 input. In single- channel mode, this bit should always be 0. 2 ZERO A 0 must be written to this bit to ensure correct operation of the AD7887. 1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7887 as described in Table 6. Table 6. Power Management Options PM1 PM0 Mode 0 0 Mode 1. In this mode, the AD7887 enters shutdown if the CS input is 1 and is in full power mode when CS is 0. Thus the part comes out of shutdown on the falling edge of CS and enters shutdown on the rising edge of CS. 0 1 Mode 2. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic inputs. 1 0 Mode 3. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion, regardless of the state of CS. 1 1 Mode 4. In this standby mode, portions of the AD7887 are powered down but the on-chip reference voltage remains powered up. This mode is similar to Mode 3, but allows the part to power up much faster. The REF bit should be 0 to ensure that the on-chip reference is enabled. Rev. D | Page 10 of 24 AD7887 THEORY OF OPERATION CHARGE CIRCUIT INFORMATION REDISTRIBUTION DAC The AD7887 is a fast, low power, 12-bit, single-supply, single- SAMPLING channel/dual-channel ADC. The part can be operated from a CAPACITOR A V IN 3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply. CONTROL SW1 LOGIC B When operated from either a 5 V or 3 V supply, the AD7887 is CONVERSION SW2 PHASE COMPARATOR AGND capable of throughput rates of 125 kSPS when provided with a 2 MHz clock. (REF IN/REF OUT)/2 The AD7887 provides the user with an on-chip, track/hold Figure 9. ADC Conversion Phase analog-to-digital converter reference and a serial interface ADC TRANSFER FUNCTION housed in an 8-lead package. The serial clock input accesses data from the part and provides the clock source for the successive The output coding of the AD7887 is straight binary. The approximation ADC. The part can be configured for single- designed code transitions occur at successive integer LSB values channel or dual-channel operation. When configured as a (that is, 1 LSB, 2 LSB, and so on). The LSB size is V /4096. The REF single-channel part, the analog input range is 0 to VREF (where the ideal transfer characteristic for the AD7887 is shown in Figure 10. externally applied VREF can be between 1.2 V and VDD). When the AD7887 is configured for two input channels, the input range is determined by internal connections to be 0 to V . DD 111 ... 111 If single-channel operation is required, the AD7887 can be 111 ... 110 operated in a read-only mode by tying the DIN line permanently to GND. For applications where the user wants to change the 111 ... 000 mode of operation or wants to operate the AD7887 as a dual- 1LSB = V /4096 REF 011 ... 111 channel ADC, the DIN line can be used to clock data into the part’s control register. 000 ... 010 CONVERTER OPERATION 000 ... 001 000 ... 000 The AD7887 is a successive approximation ADC built around a +V – 1.5LSB 0.5LSB REF 0V ANALOG INPUT charge-redistribution DAC. Figure 8 and Figure 9 show simplified Figure 10. Transfer Characteristic schematics of the ADC. Figure 8 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the TYPICAL CONNECTION DIAGRAM comparator is held in a balanced condition, and the sampling Figure 11 shows a typical connection diagram for the AD7887. capacitor acquires the signal on AIN. The GND pin is connected to the analog ground plane of the CHARGE system. The part is in dual-channel mode so V is internally REF REDISTRIBUTION DAC connected to a well-decoupled VDD pin to provide an analog SAMPLING input range of 0 V to VDD. The conversion result is output in a CAPACITOR A AIN 16-bit word with four leading zeros followed by the MSB of the CONTROL SW1 LOGIC B 12-bit result. For applications where power consumption is of ACQUISITION SW2 concern, the automatic power-down at the end of conversion PHASE COMPARATOR AGND should be used to improve power performance. See the Modes (REF IN/REF OUT)/2 of Operation section. Figure 8. ADC Acquisition Phase SUPPLY 2.7V TO 5.25V 10µF 0.1µF When the ADC starts a conversion (see Figure 9), SW2 opens and SW1 moves to Position B, causing the comparator to become SERIAL INTERFACE V DD unbalanced. The control logic and the charge-redistribution DAC are used to add and subtract fixed amounts of charge from the AD7887 sampling capacitor to bring the comparator back into a balanced AIN1 SCLK 0V TO V DD µC/µP condition. When the comparator is rebalanced, the conversion INPUT DOUT AIN2 is complete. The control logic generates the ADC output code. DIN Figure 10 shows the ADC transfer function. CS GND Figure 11. Typical Connection Diagram Rev. D | Page 11 of 24 06191-008 ADC CODE 06191-010 06191-009 06191-011 AD7887 –65 ANALOG INPUT THD vs. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES Figure 12 shows an equivalent circuit of the analog input V = 5V –70 DD structure of the AD7887. The two diodes, D1 and D2, provide 5V EXT REFERENCE R = 1kΩ, C = 100pF ESD protection for the analog inputs. Care must be taken to IN IN ensure that the analog input signal never exceed the supply rails –75 R = 50Ω, C = 2.2nF by more than 200 mV. Exceeding this value causes the diodes IN IN to become forward biased and to start conducting into the –80 substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 20 mA. –85 However, it is worth noting that a small amount of current (1 mA) being conducted into the substrate due to an R = 10Ω, C = 10nF IN IN overvoltage on an unselected channel can cause inaccurate –90 0.15 10.89 21.14 31.59 42.14 49.86 conversions on a selected channel. Capacitor C1 in Figure 12 is INPUT FREQUENCY (kHz) typically about 4 pF and can primarily be attributed to pin Figure 13. THD vs. Analog Input Frequency capacitance. Resistor R1 is a lumped component made up of the On-Chip Reference on resistance of a multiplexer and a switch. This resistor is The AD7887 has an on-chip 2.5 V reference. This reference can typically about 100 Ω. Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 20 pF. be enabled or disabled by clearing or setting the REF bit in the control register, respectively. If the on-chip reference is to be used Note that the analog input capacitance seen when in track mode externally in a system, it must be buffered before it is applied is typically 38 pF, whereas in hold mode it is typically 4 pF. elsewhere. If an external reference is applied to the device, the V DD internal reference is automatically overdriven. However, it is advised to disable the internal reference by setting the REF bit D1 C2 20pF R1 in the control register when an external reference is applied in V IN order to obtain optimum performance from the device. When C1 D2 4pF the internal reference is disabled, SW1, shown in Figure 14, CONVERSION PHASE—SWITCH OPEN opens and the input impedance seen at the AIN1/VREF pin is the TRACK PHASE—SWITCH CLOSED input impedance of the reference buffer, which is in the region Figure 12. Equivalent Analog Input Circuit of gigaohms. When the internal reference is enabled, the input For ac applications, removing high frequency components from impedance seen at the pin is typically 10 kΩ. When the AD7887 the analog input signal is recommended by use of an RC is operated in two-channel mode, the reference is taken from low-pass filter on the relevant analog input pin. In applications V internally, not from the on-chip 2.5 V reference. DD where harmonic distortion and signal-to-noise ratio are critical, AIN1/V REF the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac SW1 performance of the ADC. This may necessitate the use of an 10kΩ 2.5V input buffer amplifier. The choice of op amp is a function of the particular application. Figure 14. On-Chip Reference Circuitry When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 13 shows a graph of the total harmonic distortion vs. the analog input signal frequency for different source impedances. Rev. D | Page 12 of 24 06191-012 THD (dB) 06191-014 06191-013 AD7887 power vs. throughput rate for automatic shutdown with both POWER-DOWN OPTIONS 5 V and 3 V supplies. The AD7887 provides flexible power management to allow 10 the user to achieve the best power performance for a given throughput rate. The power management options are selected by programming V = 5V DD the power management bits (that is, PM1 and PM0) in the SCLK = 2MHz 1 control register. Table 6 summarizes the available options. When the power management bits are programmed for either V = 3V of the auto power-down modes, the part enters power-down DD SCLK = 2MHz th mode on the 16 rising SCLK edge after the falling edge of CS. 0.1 The first falling SCLK edge after the CS falling edge causes the part to power up again. When the AD7887 is in Mode 1, that is, PM1 = PM0 = 0, the part enters shutdown on the rising edge of CS CS 0.01 and power up from shutdown on the falling edge of . If 0 10 20 30 40 50 CS is brought high during the conversion in this mode, the part THROUGHPUT RATE (kSPS) immediately enters shutdown. Figure 15. Power vs. Throughput Rate Power-Up Times MODES OF OPERATION The AD7887 has an approximate 1 μs power-up time when The AD7887 has several modes of operation that are designed powering up from standby or when using an external reference. to provide flexible power management options. These options When V is first connected the AD7887 powers up in Mode 1, DD can be chosen to optimize the power dissipation/throughput that is, PM1 = PM0 = 0. The part is put into shutdown on the rate ratio for differing application requirements. The modes of rising edge of CS in this mode. A subsequent power-up from operation are controlled by the PM1 and PM0 bits of the control shutdown takes approximately 5 μs. The AD7887 wake-up time register, as previously outlined in Table 6. For read-only operation is very short in the autostandby mode; therefore, it is possible to of the AD7887, the default mode of all 0s in the control register wake up the part and carry out a valid conversion in the same can be set up by tying the DIN line permanently low. read/write operation. Mode 1 (PM1 = 0, PM0 = 0) POWER VS. THROUGHPUT RATE This mode allows the user to control the powering down of the By operating the AD7887 in autoshutdown mode, autostandby part via the CS pin. Whenever CS is low, the AD7887 is fully mode, or Mode 1, the average power consumption of the CS powered up; whenever is high, the AD7887 is in full AD7887 decreases at lower throughput rates. Figure 15 shows CS shutdown. When goes from high to low, all on-chip circuitry how as the throughput rate is reduced, the device remains in its starts to power up. It takes approximately 5 μs for the AD7887 power-down state longer and the average power consumption internal circuitry to be fully powered up. As a result, a over time drops accordingly. conversion (or sample-and-hold acquisition) should not be For example, if the AD7887 is operated in a continuous sampling initiated during this 5 μs. mode with a throughput rate of 10 kSPS and a SCLK of 2 MHz Figure 16 shows a general diagram of the operation of the (VDD = 5 V), PM1 = 1 and PM0 = 0, that is, the device is in auto- AD7887 in this mode. The input signal is sampled on the shutdown mode, and the on-chip reference is used, the power CS second rising edge of SCLK following the falling edge. The consumption is calculated as follows: The power dissipation user should ensure that 5 μs elapses between the falling edge of during normal operation is 3.5 mW (V = 5 V). If the power-up DD CS and the second rising edge of SCLK. In microcontroller time is 5 μs and the remaining conversion plus acquisition time CS applications, this is readily achievable by driving the input is 15.5 tSCLK, that is, approximately 7.75 μs (see Figure 18), the from one of the port lines and ensuring that the serial data read AD7887 can be said to dissipate 3.5 mW for 12.75 μs during (from the microcontrollers serial port) is not initiated for 5 μs. each conversion cycle. If the throughput rate is 10 kSPS, the In DSP applications, where CS is generally derived from the cycle time is 100 μs and the average power dissipated during serial frame synchronization line, it is usually not possible to each cycle is (12.75/100) × (3.5 mW) = 446.25 μW. If V = 3 V, DD CS separate the falling edge and second SCLK rising edge by up SCLK = 2 MHz, and the device is in autoshutdown mode using the to 5 μs without affecting the speed of the rest of the serial clock. on-chip reference, the power dissipation during normal operation Therefore, the user must write to the control register to exit this is 2.1 mW. The AD7887 can now be said to dissipate 2.1 mW mode and (by writing PM1 = 0 and PM0 = 1) put the part into for 12.75 μs during each conversion cycle. With a throughput Mode 2, that is, normal mode. A second conversion needs to be rate of 10 kSPS, the average power dissipated during each cycle initiated when the part is powered up to get a conversion result. is (12.75/100) × (2.1 mW) = 267.75 μW. Figure 15 shows the The write operation that takes place in conjunction with this Rev. D | Page 13 of 24 POWER (mW) 06191-015 AD7887 second conversion can put the part back into Mode 1, and the SCLK between the first falling edge of and the second rising CS part goes into power-down mode when returns high. CS edge of SCLK after the falling edge, as shown in Figure 18. In microcontroller applications (or with a slow serial clock), this Mode 2 (PM1 = 0, PM0 = 1) is readily achievable by driving the CS input from one of the In this mode of operation, the AD7887 remains fully powered port lines and ensuring that the serial data read (from the up regardless of the status of the CS line. It is intended for fastest microcontroller’s serial port) is not initiated for 5 μs. However, throughput rate performance because the user does not have to for higher speed serial clocks, it will not be possible to have a worry about the 5 μs power-up time previously mentioned. 5 μs delay between powering up and the first rising edge of the Figure 17 shows the general diagram of the operation of the SCLK. Therefore, the user must write to the control register to AD7887 in this mode. exit this mode and (by writing PM1 = 0 and PM0 = 1) put the The data presented to the AD7887 on the DIN line during the part into Mode 2. A second conversion needs to be initiated first eight clock cycles of the data transfer are loaded to the when the part is powered up to get a conversion result, as control register. To continue to operate in this mode, the user shown in Figure 19. The write operation that takes place in must ensure that PM1 is loaded with 0 and PM0 is loaded with conjunction with this second conversion can put the part back 1 on every data transfer. into Mode 3, and the part goes into power-down mode when the conversion sequence ends. CS The falling edge of initiates the sequence, and the input signal is sampled on the second rising edge of the SCLK input. Mode 4 (PM1 = 1, PM0 = 1) Sixteen serial clock cycles are required to complete the conversion In this mode, the AD7887 automatically enters a standby (or and access the conversion result. Once a data transfer is complete sleep) mode at the end of every conversion. In this standby (that is, once CS returns high), another conversion can be initiated mode, all on-chip circuitry, apart from the on-chip reference, is immediately by bringing CS low again. powered down. This mode is similar to Mode 3, but, in this case, the power-up time is much shorter because the on-chip Mode 3 (PM1 = 1, PM0 = 0) reference remains powered up at all times. In this mode, the AD7887 automatically enters its full shutdown Figure 20 shows the general diagram of the operation of the mode at the end of every conversion. It is similar to Mode 1 AD7887 in this mode. On the first falling SCLK edge after CS except that the status of CS does not have any effect on the goes low, the AD7887 comes out of standby. The AD7887 wake- power-down status of the AD7887. up time is very short in this mode, so it is possible to wake up Figure 18 shows the general diagram of the operation of the the part and carry out a valid conversion in the same read/write CS AD7887 in this mode. On the first falling SCLK edge after operation. The input signal is sampled on the second rising goes low, all on-chip circuitry starts to power up. It takes CS edge of SCLK following the falling edge. At the end of approximately 5 μs for the AD7887 internal circuitry to be fully conversion (last rising edge of SCLK), the part automatically powered up. As a result, a conversion (or sample-and-hold enters its standby mode. acquisition) should not be initiated during this 5 μs. The input signal is sampled on the second rising edge of SCLK following the CS falling edge. The user should ensure that 5 μs elapses Rev. D | Page 14 of 24 AD7887 THE PART POWERS UP ON CS THE PART POWERS DOWN ON CS FALLING EDGE AS PM1 AND PM0 = 0 RISING EDGE AS PM1 AND PM0 = 0 CS 16 1 SCLK DOUT FOUR LEADING ZEROS + CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE Figure 16. Mode 1 Operation THE PART REMAINS POWERED UP AT ALL TIMES AS PM1 = 0 AND PM0 = 1 CS 16 1 SCLK DOUT FOUR LEADING ZEROS + CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE Figure 17. Mode 2 Operation Rev. D | Page 15 of 24 06191-017 06191-016 AD7887 THE PART ENTERS THE PART POWERS UP FROM SHUTDOWN AT THE END OF SHUTDOWN ON SCLK FALLING EDGE AS CONVERSION AS PM1 = 1 AND PM0 = 0 PM1 = 1 AND PM0 = 0 CS 16 16 1 2 1 SCLK t = 5µs 10 FOUR LEADING ZEROS + CONVERSION RESULT FOUR LEADING ZEROS + CONVERSION RESULT DOUT DATA IN DATA IN DIN CONTROL REGISTER DATA IS LOADED ON THE PM1 = 1 AND PM0 = 0 TO KEEP THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0 PART IN THIS MODE Figure 18. Mode 3 Operation (Microcontroller for Slow SCLKs) THE PART ENTERS THE PART ENTERS SHUTDOWN AT THE END SHUTDOWN AT THE END OF OF CONVERSION AS THE PART BEGINS TO POWER THE PART REMAINS POWERED UP CONVERSION AS PM1 = 1 PM1 = 1 AND PM0 = 0 UP FROM SHUTDOWN AS PM1 = 0 AND PM0 = 1 AND PM0 = 0 CS 8 16 8 1 1 1 16 8 16 SCLK FOUR LEADING ZEROS FOUR LEADING ZEROS FOUR LEADING ZEROS DOUT + CONVERSION RESULT + CONVERSION RESULT + CONVERSION RESULT DATA IN DIN DATA IN DATA IN CONTROL REGISTER DATA IS LOADED ON PM1 = 0 AND PM0 = 1 TO PLACE PM1 = 1 AND PM0 = 0 TO PLACE THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0 THE PART IN NORMAL MODE THE PART BACK IN MODE 3 Figure 19. Mode 3 Operation (Microcontroller for High Speed SCLKs) THE PART POWERS UP THE PART ENTERS FROM STANDBY ON SCLK STANDBY AT THE END OF FALLING EDGE AS PM1 = 1 CONVERSION AS AND PM0 = 1 PM1 = 1 AND PM0 = 1 CS 16 16 1 1 SCLK FOUR LEADING ZEROS + CONVERSION RESULT FOUR LEADING ZEROS + CONVERSION RESULT DOUT DIN DATA IN DATA IN CONTROL REGISTER DATA IS LOADED ON PM1 = 1 AND PM0 = 1 TO KEEP THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 1 THE PART IN THIS MODE Figure 20. Mode 4 Operation Rev. D | Page 16 of 24 06191-019 06191-018 06191-020 AD7887 the channel address for the next conversion while the present SERIAL INTERFACE conversion is in progress. Figure 21 shows the detailed timing diagrams for serial Writing of information to the control register takes place on the interfacing to the AD7887. The serial clock provides the conversion clock and also controls the transfer of information first eight rising edges of SCLK in a data transfer. The control to and from the AD7887 during conversion. register is always written to when a data transfer takes place. However, the AD7887 can be operated in a read-only mode by CS initiates the data transfer and conversion process. For some tying DIN low, thereby loading all 0s to the control register CS modes, the falling edge of wakes up the part. In all cases, it every time. When operating the AD7887 in write/read mode, gates the serial clock to the AD7887 and puts the on-chip the user must be careful to always set up the correct track/hold into track mode. The input signal is sampled on the information on the DIN line when reading data from the part. second rising edge of the SCLK input after the falling edge of Sixteen serial clock cycles are required to perform the con- CS. Thus, the first one and one-half clock cycles after the falling version process and to access data from the AD7887. In CS edge of are when the acquisition of the input signal takes applications where the first serial clock edge following CS going place. This time is denoted as the acquisition time (t ). In ACQ low is a falling edge, this edge clocks out the first leading zero. CS modes where the falling edge of wakes up the part, the Thus, the first rising clock edge on the SCLK clock has the first acquisition time must allow for the wake-up time of 5 μs. The leading zero provided. In applications where the first serial on-chip track/hold goes from track mode to hold mode on the CS clock edge following going low is a rising edge, the first second rising edge of SCLK, and a conversion is also initiated leading zero may not be set up in time for the processor to read on this edge. The conversion process takes an additional it correctly. However, subsequent bits are clocked out on the fourteen and one-half SCLK cycles to complete. The rising edge falling edge of SCLK so that they are provided to the processor CS CS of puts the bus back into three-state. If is left low, a new on the following rising edge. Thus, the second leading zero is conversion can be initiated. clocked out on the falling edge subsequent to the first rising In dual-channel operation, the input channel that is sampled is th edge. The final bit in the data transfer is valid on the 16 rising the one that was selected in the previous write to the control edge, having been clocked out on the previous falling edge. register. Thus, in dual-channel operation, the user must write t ACQ t CONVERT CS t t 1 6 16 1 23 4 5 6 15 SCLK t t t 2 7 t 8 3 THREE- THREE- STATE STATE FOUR LEADING ZEROS DOUT DB11 DB10 DB9 DB0 t 4 t 5 DONTC ZERO REF SIN/DUAL CH ZERO PM1 PM0 DIN Figure 21. Serial Interface Timing Diagram Rev. D | Page 17 of 24 06191-021 AD7887 this example however, the timer interrupt is used to control the MICROPROCESSOR INTERFACING sampling rate of the ADC and, under certain conditions, The serial interface on the AD7887 allows the part to be directly equidistant sampling cannot be achieved. connected to a range of many different microprocessors. This section explains how to interface the AD7887 with some of the The timer registers are loaded with a value that will provide an more common microcontroller and DSP serial interface interrupt at the required sample interval. When an interrupt is protocols. received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and hence the AD7887 to TMS320C5x reading of data. The frequency of the serial clock is set in the The serial interface on the TMS320C5x uses a continuous serial SCLKDIV register. When the instruction to transmit with TFS clock and frame synchronization signals to synchronize the data is given (that is, AX0 = TX0), the state of the SCLK is checked. transfer operations with peripheral devices like the AD7887. The DSP waits until the SCLK has gone high, low, and high CS The input allows easy interfacing with an inverter between again before a transmission starts. If the timer and SCLK values the serial clock of the TMS320C5x and the AD7887 being the are chosen such that the instruction to transmit occurs on or only glue logic required. The serial port of the TMS320C5x is near the rising edge of SCLK, the data may be transmitted or it set up to operate in burst mode with internal CLKX (Tx serial may wait until the next clock edge. clock) and FSX (Tx frame sync). The serial port control register For example, the ADSP-2111 has a master clock frequency of (SPC) must have the following setup: FO = 0, FSM = 1, 16 MHz. If the SCLKDIV register is loaded with the value 3, a MCM = 1, and TXM = 1. The connection diagram is shown in SCLK of 2 MHz is obtained and eight master clock periods will Figure 22. elapse for every one SCLK period. If the timer registers are 1 1 TMS320C5x loaded with the value 803, 100.5 SCLKs will occur between AD7887 CLKX SCLK interrupts and subsequently between transmit instructions. This CLKR situation results in nonequidistant sampling because the transmit instruction is occurring on an SCLK edge. If the DOUT DR number of SCLKs between interrupts is a whole integer number DIN DT of N, equidistant sampling will be implemented by the DSP. CS FSX FSR 1 1 ADSP-21xx AD7887 SCLK SCLK 1 ADDITIONAL PINS OMITTED FOR CLARITY. DR DOUT Figure 22. Interfacing to the TMS320C5x DT DIN AD7887 to ADSP-21xx CS RFS The ADSP-21xx family of DSPs are easily interfaced to the TFS AD7887 with an inverter between the serial clock of the ADSP- 1 ADDITIONAL PINS OMITTED FOR CLARITY. 21xx and the AD7887. This is the only glue logic required. The Figure 23. Interfacing to the ADSP-21xx SPORT control register should be set up as follows: AD7887 to DSP56xxx Table 7. SPORT0 Control Register Setup The connection diagram in Figure 24 shows how the AD7887 Setting Description can be connected to the SSI (synchronous serial interface) of TFSW = RFSW = 1 Alternative framing the DSP56xxx family of DSPs from Motorola. The SSI is INVRFS = INVTFS = 1 Active low frame signal operated in synchronous mode (SYN bit in CRB = 1) with an DTYPE = 00 Right justify data internally generated 1-bit clock period frame sync for both Tx SLEN = 1111 16-bit data-word and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word ISCLK = 1 Internal serial clock length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An TFSR = RFSR = 1 Frame every word inverter is also necessary between the SCLK from the DSP56xxx IRFS = 0 and the SCLK pin of the AD7887, as shown in Figure 24. ITFS = 1 1 1 DSP56xxx AD7887 The connection diagram is shown in Figure 23. The ADSP-21xx SCLK SCK has the TFS and RFS of the SPORT tied together, with TFS set DOUT SRD as an output and RFS set as an input. The DSP operates in DIN STD alternate framing mode, and the SPORT control register is set CS SC2 up as described in Table 7. The frame synchronization signal CS generated on the TFS is tied to and, as with all signal 1 ADDITIONAL PINS OMITTED FOR CLARITY. processing applications, equidistant sampling is necessary. In Figure 24. Interfacing to the DSP56xxx Rev. D | Page 18 of 24 06191-022 06191-024 06191-023 AD7887 AD7887 to MC68HC11 1 1 8051 AD7887 P1.0 SCLK The serial peripheral interface (SPI) on the MC68HC11 is P1.1 configured for master mode (MSTR = 1) when the clock DOUT polarity bit (CPOL) = 1 and the clock phase bit (CPHA) = 1. DIN P1.2 The SPI is configured by writing to the SPI Control Register P1.3 CS (SPCR)—see the M68HC11 reference manual from Freescale Semiconductor, Inc., for more information. The serial transfer 1 ADDITIONAL PINS OMITTED FOR CLARITY. takes place as two 8-bit operations. A connection diagram is Figure 26. Interfacing to the 8051 Using Input/Output Ports shown in Figure 25. AD7887 to PIC16C6x/PIC16C7x 1 1 MC68HC11 AD7887 The PIC16C6x synchronous serial port (SSP) is configured as an SCLK SCLK/PD4 SPI master with the clock polarity bit = 1. This is done by writing to MISO/PD2 DOUT the synchronous serial port control register (SSPCON). See the DIN MOSI/PD3 PIC16/PIC17 Microcontroller User Manual. Figure 27 shows the CS PA0 hardware connections needed to interface to the PIC16C6x/ PIC16C7x. In this example, input/output port RA1 is being used to 1 ADDITIONAL PINS OMITTED FOR CLARITY. CS pulse . This microcontroller only transfers eight bits of data Figure 25. Interfacing to the MC68HC11 during each serial transfer operation. Therefore, two consecutive read/write operations are needed. AD7887 to 8051 PIC16C6x/ It is possible to implement a serial interface using the data ports 1 AD7887 1 PIC16C7x on the 8051. This allows a full duplex serial transfer to be imple- SCLK SCK/RC3 mented. The technique involves bit-banging an input/output DOUT SDI/RC4 port (for example, P1.0) to generate a serial clock and using two DIN SDO/RC5 other input/output ports (for example, P1.1 and P1.2) to shift CS RA1 data in and out—see Figure 26. 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. Interfacing to the PIC16C6x/PIC16C7x Rev. D | Page 19 of 24 06191-025 06191-027 06191-026 AD7887 and analog signals. Traces on opposite sides of the board should APPLICATION HINTS run at right angles to each other. This reduces the effects of Grounding and Layout feedthrough through the board. A microstrip technique is by far The AD7887 has very good immunity to noise on the power the best approach, but it is not always possible with a double- supplies, as can be seen in Figure 7. However, care should still sided board. In this technique, the component side of the board be taken with regard to grounding and layout. is dedicated to ground planes, and signals are placed on the The printed circuit board that houses the AD7887 should be solder side. designed so that the analog and digital sections are separated Good decoupling is also important. All analog supplies should and confined to certain areas of the board. This facilitates the be decoupled with 10 μF tantalum in parallel with 0.1 μF use of ground planes that can be easily separated. A minimum capacitors to AGND. To achieve the best from these decoupling etch technique is generally best for ground planes because it components, they must be placed as close as possible to the results in the best shielding. Digital and analog ground planes device, ideally right up against the device. should be joined in only one place, as close as possible to the Evaluating the AD7887 Performance GND pin of the AD7887. If the AD7887 is in a system where multiple devices require AGND-to-DGND connections, the The recommended layout for the AD7887 is outlined in the connection should still be made at one point only, a star ground evaluation board for the AD7887. The evaluation board point, which should be established as close as possible to the package includes a fully assembled and tested evaluation board, AD7887. documentation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL Avoid running digital lines under the device because these will BOARD can be used in conjunction with the AD7887 couple noise onto the die. The analog ground plane should be evaluation board, as well as many other Analog Devices, Inc., allowed to run under the AD7887 to avoid noise coupling. The evaluation boards ending in the CB designator, to power supply lines to the AD7887 should use as large a trace as demonstrate/evaluate the ac and dc performance of the possible to provide low impedance paths and reduce the effects AD7887. of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating The software allows the user to perform ac (fast Fourier noise to other sections of the board, and clock signals should transform) and dc (histogram of codes) tests on the AD7887. never be run near the analog inputs. Avoid crossover of digital Rev. D | Page 20 of 24 AD7887 OUTLINE DIMENSIONS 3.20 5.00 (0.1968) 3.00 4.80 (0.1890) 2.80 85 8 5 5.15 6.20 (0.2440) 4.00 (0.1574) 3.20 4.90 1 5.80 (0.2284) 3.80 (0.1497) 4 3.00 4.65 2.80 1 4 1.27 (0.0500) 0.50 (0.0196) 45° PIN 1 BSC 1.75 (0.0688) 0.25 (0.0099) 0.65 BSC 1.35 (0.0532) 0.25 (0.0098) 8° 0.95 0.10 (0.0040) 0° 0.85 1.10 MAX COPLANARITY 0.51 (0.0201) 0.75 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) 0.80 SEATING 0.40 (0.0157) 8° 0.15 0.17 (0.0067) 0.38 0.60 PLANE 0.23 0° 0.00 0.22 0.40 0.08 SEATING COPLANARITY COMPLIANT TO JEDEC STANDARDS MS-012-AA PLANE 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COMPLIANT TO JEDEC STANDARDS MO-187-AA REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 8-Lead Standard Small Outline Package [SOIC_N] Figure 29. 8-Lead Mini Small Outline Package [MSOP] Narrow Body (RM-8) (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) ORDERING GUIDE Linearity 1 Model Error Temperature Package Description Package Option Branding AD7887AR ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD7887AR-REEL ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD7887AR-REEL7 ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887ARZ ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887ARZ-REEL ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887ARZ-REEL7 ±2 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD7887ARM ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A AD7887ARM-REEL ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A AD7887ARM-REEL7 ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A 2 AD7887ARMZ ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A# 2 AD7887ARMZ-REEL ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A# 2 AD7887ARMZ-REEL7 ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A# AD7887BR ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD7887BR-REEL ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD7887BR-REEL7 ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887BRZ ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887BRZ-REEL ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2 AD7887BRZ-REEL7 ±1 LSB −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2, 3 AD7887WARMZ ±2 LSB −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 C5A# 4 EVAL-AD7887CB Evaluation Board 5 EVAL-CONTROL BRD2 Controller Board 1 Linearity error here refers to integral linearity error. 2 Z = RoHS Compliant Part, # denotes lead-free product, may be top or bottom marked. 3 Qualified for automotive. 4 This can be used as a standalone evaluation board or can be used in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. Rev. D | Page 21 of 24 060506-A AD7887 NOTES Rev. D | Page 22 of 24 AD7887 NOTES Rev. D | Page 23 of 24 AD7887 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06191-0-2/09(D) Rev. D | Page 24 of 24