ANALOG DEVICES AD7880

2 LC MOS Single +5 V Supply, a Low Power, 12-Bit Sampling ADC AD7880 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-Bit Monolithic A/D Converter 66 kHz Throughput Rate V DD 12 ms Conversion Time 3 ms On-Chip Track/Hold Amplifier SAMPLING R V COMPARATOR LOW POWER MODE INA Low Power CONTROL + Power Save Mode: 2 mW typ R CIRCUIT V – INB Normal Operation: 25 mW typ 70 dB SNR V REF 12-BIT DAC Fast Data Access Time: 57 ns AGND Small 24-Lead SOIC and 0.3" DIP Packages CS SAR + APPLICATIONS CLKIN COUNTER CONTROL Battery Powered Portable Systems CONVST LOGIC Digital Signal Processing RD THREE BUSY Speech Recognition and Synthesis STATE AD7880 BUFFERS High Speed Modems Control and Instrumentation DB11 DB0 DGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7880 is a high speed, low power, 12-bit A/D converter 1. Fast Conversion Time. which operates from a single +5 V supply. It consists of a 3 μs 12 μs conversion time and 3 μs acquisition time allow for track/hold amplifier, a 12 μs successive-approximation ADC, large input signal bandwidth. This performance is ideally versatile interface logic and a multiple-input-range circuit. The suited for applications in areas such as telecommunications, part also includes a power save feature. audio, sonar and radar signal processing. An internal resistor network allows the part to accept both uni- 2. Low Power Consumption. polar and bipolar input signals while operating from a single 2 mW power consumption in the power-down mode makes +5 V supply. Fast bus access times and standard control inputs the part ideally suited for portable, hand held, battery pow- ensure easy interfacing to modern microprocessors and digital ered applications. signal processors. 3. Multiple Input Ranges. The AD7880 features a total throughput time of 15 μs and can The part features three user-determined input ranges, 0 V to convert full power signals up to 33 kHz with a sampling fre- +5 V, 0 V to 10 V and ±5 V. These unipolar and bipolar quency of 66 kHz. ranges are achieved with a 5 V only power supply. In addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the AD7880 is also fully specified for dynamic performance parameters including har- monic distortion and signal-to-noise ratio. The AD7880 is fabricated in Analog Devices’ Linear Compat- 2 ible CMOS (LC MOS) process, a mixed technology process that combines precision bipolar circuits with low power CMOS logic. The part is available in a 24-pin, 0.3 inch-wide, plastic or hermetic dual-in-line package (DIP) as well as a small 24-lead SOIC package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (V = +5 V 6 5%, V = V , AGND = DGND = O V, f = 2.5 MHz, MODE = V DD REF DD CLKIN DD AD7880–SPECIFICATIONS unless otherwise noted. All Specifications T to T unless otherwise noted.) MIN MAX 1 1 Parameter B Versions C Versions Units Test Conditions/Comments 2 DYNAMIC PERFORMANCE 3 Signal-to-Noise Ratio (SNR) 70 70 dB min Typically SNR Is 72 dB V = 1 kHz Sine Wave, f = 66 kHz IN SAMPLE Total Harmonic Distortion (THD) –80 –80 dB typ V = 1 kHz Sine Wave, f = 66 kHz IN SAMPLE Peak Harmonic or Spurious Noise –80 –80 dB typ V = 1 kHz, f = 66 kHz IN SAMPLE Intermodulation Distortion (IMD) = 66 kHz Second Order Terms –80 –80 dB typ fa = 0.983 kHz, fb = 1.05 kHz, f SAMPLE Third Order Terms –80 –80 dB typ fa = 0.983 kHz, fb = 1.05 kHz, f = 66 kHz SAMPLE DC ACCURACY Resolution 12 12 Bits All DC ACCURACY Specifications Apply for the Three Analog Input Ranges Integral Nonlinearity ±1 ±1 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic Full-Scale Error ±15 ±5 LSB max Bipolar Zero Error ±10 ±5 LSB max Unipolar Offset Error ±5 ±5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V Volts See Figure 5 REF REF 0 to 2 V 0 to 2 V Volts See Figure 6 REF REF ±V ±V Volts See Figure 7 REF REF Input Resistance 10 10 MΩ min 0 to V Range REF 5/12 5/12 kΩ min/max 8 kΩ typical: 0 to 2 V Range REF 5/12 5/12 kΩ min/max 8 kΩ typical: ±V Range REF REFERENCE INPUT V (For Specified Performance) 5 5 V ±5%: Normally V = V (See Reference Input Section) REF REF DD I 1.5 1.5 mA max REF Nominal Reference Range 2.5/V 2.5/V V min/max See Figure 3 for Degradation in Performance Down to 2.5 V DD DD LOGIC INPUTS CONVST, RD, CS, CLKIN Input High Voltage, V 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 V max INL Input Current, I ±10 ±10 μA max V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 pF max IN MODE INPUT Input High Voltage, V 4 4 V min INH Input Low Voltage, V 1 1 V max INL Input Current, I ±125 ±125 μA max V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS DB11–DB0, BUSY Output High Voltage, V 4.0 4.0 V min I = 400 μA OH SOURCE Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK DB11–DB0 Floating-State Leakage Current ±10 ±10 μA max 4 Floating-State Output Capacitance 10 10 pF max CONVERSION Conversion Time 12 12 μs max f = 2.5 MHz CLKIN Track/Hold Acquisition Time 3 3 μs max POWER REQUIREMENTS V +5 +5 V nom ±5% for Specified Performance DD I DD Normal Power Mode @ +25°C 7.5 7.5 mA max Typically 4 mA; MODE = V DD T to T 10 10 mA max Typically 5 mA; MODE = V MIN MAX DD Power Save Mode @ +25°C 750 750 μA max Logic Inputs @ 0 V or V ; MODE = 0 V DD T to T 1 1 mA max Logic Inputs @ 0 V or V ; MODE = 0 V MIN MAX DD Power Dissipation Normal Power Mode @ +25°C 37.5 37.5 mW max V = 5 V: Typically 20 mW; MODE = V DD DD T to T 50 50 mW max V = 5 V: Typically 25 mW; MODE = V MIN MAX DD DD Power Save Mode @ +25°C 3.75 3.75 mW max V = 5 V: Typically 2 mW; MODE = 0 V DD T to T 5 5 mW max V = 5 V: Typically 2.5 mW; MODE = 0 V MIN MAX DD NOTES 1 Temperature ranges are as follows: B/C Versions, –40°C to +85°C. 2 V = 0 to V IN REF 3 SNR calculation includes distortion and noise components. 4 Sample tested @ +25°C to ensure compliance. Specifications subject to change without notice. –2– REV. 0 AD7880 1 (V = +5 V 6 5%, V = V , AGND = DGND = 0 V) DD REF DD TIMING CHARACTERISTICS Limit at +258C Limit at T , T MIN MAX Parameter (All Versions) (All Versions) Units Conditions/Comments t 50 50 ns min CONVST Pulse Width 1 t 130 130 ns min CONVST to BUSY Falling Edge 2 t 0 0 ns min BUSY to CS Setup Time 3 t 0 0 ns min CS to RD Setup Time 4 t 0 0 ns min CS to RD Hold Time 5 t 60 75 ns min RD Pulse Width 6 2 t 57 70 ns max Data Access Time after RD 7 3 t 55 ns min Bus Relinquish Time after RD 8 50 50 ns max NOTES 1 Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 7 3 t is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo- 8 lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time of 8 the part and as such is independent of external bus loading capacitances. t 1 Table I. Truth Table TRACK/HOLD CONVST GOES INTO HOLD t 2 CS CONVST RD Function t CONVERT BUSY 1 1 X Not Selected 1 j 1 Start Conversion g t 3 0 1 0 Enable ADC Data 0 1 1 Data Bus Three Stated CS t 5 t 4 ABSOLUTE MAXIMUM RATINGS* t 6 RD V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD t 8 V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD t 7 AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD THREE-STATE DATA DB0 – DB11 VALID V , V to AGND (Figure 5) . . . . . . –0.3 V to V + 0.3 V INA INB DD V to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 V + 0.6 V INA DD V to AGND (Figure 7) . . . . . –V – 0.3 V to V + 0.3 V Figure 1. Timing Diagram INA DD DD V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V REF DD Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V + 0.3 V DD 1.6mA Digital Outputs to DGND . . . . . . . . . . –0.3 V to V + 0.3 V DD Operating Temperature Range TO OUTPUT Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C +2.1V PIN Storage Temperature Range . . . . . . . . . . . –65°C to +150°C 50pF Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW 200µA Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C *Stresses above those listed under “Absolute Maximum Ratings” may cause Figure 2. Load Circuit for Access and Relinquish Time permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7880 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– AD7880 ORDERING GUIDE PIN CONFIGURATION Bipolar V 24 V INA 1 DD Full-Scale Zero V Temperature Error Error Package 2 23 INB MODE Model Range (LSBs) (LSBs) Option* 3 22 DB11 AGND V REF 4 21 AD7880BN –40°C to +85°C ±15 ±10 N-24 DB10 AD7880BQ –40°C to +85°C ±15 ±10 Q-24 CS 5 20 DB9 AD7880CN –40°C to +85°C ±5 ±5 N-24 AD7880 CONVST 6 19 DB8 TOP VIEW AD7880CQ –40°C to +85°C ±5 ±5 Q-24 (Not to Scale) 7 RD DB7 AD7880BR –40°C to +85°C ±15 ±10 R-24 18 AD7880CR –40°C to +85°C ±5 ±5 R-24 BUSY 8 17 DB6 9 *N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit). DB5 CLKIN 16 10 DB4 DGND 15 DB3 DB0 11 14 12 DB1 13 DB2 PIN FUNCTION DESCRIPTION Pin Pin No. Mnemonic Function 1V Analog Input. INA 2V Analog Input. INB 3 AGND Analog Ground. 4V Voltage Reference Input. This is normally tied to V . REF DD 5 CS Chip Select. Active Low Logic input. The device is selected when this input is active. CONVST Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con- 6 version. This input is asynchronous to the CLKIN and is independent of CS and RD. RD Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs. 7 8 BUSY Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion. 9 CLKIN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/ space ratio of the clock can vary from 40/60 to 60/40. 10 DGND Digital Ground. 11 . . . 22 DB0–DB11 Three-State Data Outputs. These become active when CS and RD are brought low. 23 MODE MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During normal operation, the MODE input will be a logic high (MODE = V ). DD 24 V Power Supply. This is nominally +5 V. DD REV. 0 –4– AD7880 CIRCUIT INFORMATION R The AD7880 is a +5 V single supply 12-bit A/D converter. The V INA part requires no external components apart from a 2.5 MHz ex- + ternal clock and power supply decoupling capacitors. It contains R a 12-bit successive approximation ADC based on a fast-settling V INB – voltage-output DAC, a high speed comparator and SAR, as well as the necessary control logic. The charge balancing comparator used in the AD7880 provides the user with an inherent track- V DAC and-hold function. The ADC is specified to work with sampling rates up to 66 kHz. Figure 4. AD7880 Input Circuit CONVERTER DETAILS The AD7880 accommodates three separate input ranges, 0 to The AD7880 conversion cycle is initiated on the rising edge of V , 0 to 2 V and ±V . The input configurations corre- REF REF REF the CONVST pulse, as shown in the timing diagram of Figure sponding to these ranges are shown in Figures 5, 6 and 7. 1. The rising edge of the CONVST pulse places the track/hold With V = V and using a nominal V of +5 V, the input REF DD DD amplifier into “HOLD” mode. The conversion cycle then takes ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in between 26 and 28 clock periods. The maximum specified con- Table II. version time is 12 μs. This corresponds to a conversion cycle Table II. Analog Input Ranges time of 28 clock periods with a CLKIN frequency of 2.5 MHz and also includes internal propagation delays. During conver- Input Connections Analog Input Connection sion the BUSY output will remain low, and the output databus Range V V V Diagram REF INA INB drivers will be three-stated. When a conversion is completed, the BUSY output will go to a high level, and the result of the 0 V to +5 V V V V Figure 5 DD IN IN conversion can be read by bringing CS and RD low. 0 V to +10 V V V AGND Figure 6 DD IN The track/hold amplifier acquires a 12-bit input signal in 3 μs. ±5 V V V V Figure 7 DD IN REF The overall throughput time for the AD7880 is equal to the conversion time plus the track/hold acquisition time. For a SAMPLING 2.5 MHz input clock the throughput time is 15 μs. R COMPARATOR V = 0 TO V IN REF 0 TO V V REF INA + REFERENCE INPUT R For specified performance, it is recommended that the reference – V INB input be tied to V . The part, however, will operate with a ref- DD V erence down to 2.5 V though with reduced performance specifi- REF V REF 12-BIT DAC cations. Figure 3 shows a graph of signal-to-noise ratio (SNR) AGND versus V . REF V must not be allowed to go above V by more than REF DD 100 mV. Figure 5. 0 to V Unipolar Input Configuration REF 74 F = 51.2kHz SAMPLING S R 72 COMPARATOR F = 2.525kHz V = 0 TO 2V IN IN REF 0 TO V REF V T = 25 C INA A + R 70 – V INB 68 V REF V REF 12-BIT DAC AGND 66 64 Figure 6. 0 to 2 V Unipolar Input Configuration REF 62 SAMPLING R 60 COMPARATOR V = V ± 234 5 IN REF 0 TO V V REF INA V – Volts + REF R – Figure 3. SNR vs. V V REF INB V REF V REF 12-BIT DAC ANALOG INPUT AGND The AD7880 has two analog input pins, V and V . Figure INA INB 4 shows the input circuitry to the ADC sampling comparator. The on-board attenuator network, made up of equal resistors, allows for various input ranges. Figure 7. ±V Bipolar Input Configuration REF REV. 0 –5– SNR – dBs AD7880 The AD7880 has two unipolar input ranges, 0 V to 5 V and 0 V CLOCK INPUT to 10 V. Figure 5 shows the analog input for the 0 V to 5 V The AD7880 is specified to operate with a 2.5 MHz clock con- range. The designed code transitions occur midway between nected to the CLKIN input pin. This pin may be driven directly successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, by CMOS or TTL buffers. The mark/space ratio on the clock 5/2 LSBs . . . FS –3/2 LSBs). The output code is straight binary can vary from 40/60 to 60/40. As the clock frequency is slowed with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The same applies down, it can result in slightly degraded accuracy performance. for the 0 V to 10 V range, as shown in Figure 6, except that the This is due to leakage effects on the hold capacitor in the inter- LSB size is bigger. In this case 1 LSB = FS/4096 = 10 V/4096 = nal track-and-hold amplifier. Figure 10 is a typical plot of accu- 2.44 mV. The ideal input/output transfer characteristic for both racy versus clock frequency for the ADC. these unipolar ranges is shown in Figure 8. 2.5 OUTPUT CODE 2.0 111...111A A111...110 A 1.5 111...101 A 111...100A A1.0 A A 0.5A 000...011A FS 1LSB = 4096A000...010 0.0 A0.5 1.5 2.5 3.5 000...001 ACLOCK FREQUENCY – MHz 000...000 A 1LSB + 0V FS – 1LSB Figure 10. Normalized Linearity Error vs. Clock Frequency V INPUT VOLTAGE IN TRACK/HOLD AMPLIFIER Figure 8. AD7880 Unipolar Transfer Characteristic The charge balanced comparator used in the AD7880 for the Figure 7 shows the AD7880’s ±5 V bipolar analog input con- A/D conversion provides the user with an inherent track/hold figuration. Once again the designed code transitions occur mid- function. The track/hold amplifier acquires an input signal to way between successive integer LSB values. The output code is 12-bit accuracy in less than 3 μs. The overall throughput time is straight binary with 1 LSB = FS/4096 = 10 V/4096 = 2.44 mV. equal to the conversion time plus the track/hold amplifier acqui- The ideal bipolar input/output transfer characteristic is shown in sition time. For a 2.5 MHz input clock, the throughput time is Figure 9. 15 μs. OUTPUT The operation of the track/hold amplifier is essentially transpar- CODE ent to the user. The track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion, i.e., on the ris- ing edge of CONVST as shown in Figure 1. 111...111 A 111...110A OFFSET AND FULL-SCALE ADJUSTMENT A In most Digital Signal Processing (DSP) applications, offset and Afull-scale errors have little or no effect on system performance. AOffset error can always be eliminated in the analog domain by 100...101 – FS – 1LSBAac coupling. Full-scale error effect is linear and does not cause 2 100...000 problems as long as the input signal is within the full dynamicAA +1LSB + FS – 1LSB 011...111 range of the ADC. Some applications will require that the inputA2 signal range match the maximum possible dynamic range of the A ADC. In such applications, offset and full-scale error will have FS = 10VA 011...110 to be adjusted to zero. FS 1LSB =A 4096 000...001 The following sections describe suggested offset and full-scaleA 000...000 adjustment techniques which rely on adjusting the inherent off- A set of the op amp driving the input to the ADC as well as tweak- ing an additional external potentiometer as shown in Figure 11. 0V V INPUT VOLTAGE IN Figure 9. AD7880 Bipolar Transfer Characteristic REV. 0 –6– NORMALIZED LINEARITY ERROR AD7880 R1 Signal-to-Noise Ratio (SNR) 10 kΩ SNR is the measured signal-to-noise ratio at the output of the V 1 ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to R2 + half the sampling frequency (FS/2) excluding dc. SNR is depen- 500 Ω V INA – dent upon the number of quantization levels used in the digiti- R4 10 kΩ zation process; the more levels, the smaller the quantization R3 AD7880* noise. The theoretical signal to noise ratio for a sine wave input R5 10 kΩ is given by: 10 kΩ AGND SNR = (6.02 N + 1.76) dB (1) *ADDITIONAL PINS OMITTED FOR CLARITY where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB. Figure 11. Offset and Full-Scale Adjust Circuit The output spectrum from the ADC is evaluated by applying a Unipolar Adjustments sine wave signal of very low distortion to the V input which is IN In the case of the 0 V to 5 V unipolar input configuration, unipolar sampled at a 66 kHz sampling rate. A Fast Fourier Transform offset error must be adjusted before full-scale error. Adjustment is (FFT) plot is generated from which the SNR data can be ob- achieved by trimming the offset of the op amp driving the ana- tained. Figure 12 shows a typical 2048 point FFT plot of the log input of the AD7880. This is done by applying an input AD7880 with an input signal of 2.5 kHz and a sampling fre- voltage of 0.61 mV (1/2 LSB) to V in Figure 11 and adjusting 1 quency of 61 kHz. The SNR obtained from this graph is 73 dB. the op amp offset voltage until the ADC output code flickers It should be noted that the harmonics are taken into account between 0000 0000 0000 and 0000 0000 0001. For full-scale when calculating the SNR. adjustment, an input voltage of 4.9982 V (FS–3/2 LSBs) is applied to V and R2 is adjusted until the output code flickers 1 between 1111 1111 1110 and 1111 1111 1111. The same procedure is required for the 0 V to 10 V input con- figuration of Figure 6. An input voltage of 1.22 mV (1/2 LSB) is applied to V in Figure 11 and the op amp’s offset voltage is 1 adjusted until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. For full-scale adjustment, an input voltage of 9.9963 V (FS–3/2 LSBs) is applied to V and R2 is 1 adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. Bipolar Adjustments Bipolar zero and full-scale errors for the bipolar input configura- tion of Figure 7 are adjusted in a similar fashion to the unipolar case. Again, bipolar zero error must be adjusted before full-scale error. Bipolar zero error adjustment is achieved by trimming the offset of the op amp driving the analog input of the AD7880 while the input voltage is 1/2 LSB below ground. This is done by applying an input voltage of –1.22 mV (1/2 LSB) to V in 1 Figure 12. FFT Plot Figure 11 and adjusting the op amp offset voltage until the Effective Number of Bits ADC output code flickers between 0111 1111 1111 and 1000 The formula given in Equation 1 relates the SNR to the number 0000 0000. For full-scale adjustment, an input voltage of of bits. Rewriting the formula, as in Equation 2, it is possible to 4.9982 V (FS/2–3/2 LSBs) is applied to V and R2 is adjusted 1 get a measure of performance expressed in effective number of until the output code flickers between 1111 1111 1110 and bits (N). 1111 1111 1111. SNR − 1.76 N = DYNAMIC SPECIFICATIONS (2) 6.02 The AD7880 is specified and tested for dynamic performance The effective number of bits for a device can be calculated specifications as well as traditional dc specifications such as directly from its measured SNR. integral and differential nonlinearity. The ac specifications are required for signal processing applications such as speech recog- Figure 13 shows a plot of effective number of bits versus input nition, spectrum analysis and high speed modems. These appli- frequency for an AD7880 with a sampling frequency of 61 kHz. cations require information on the ADC’s effect on the spectral The effective number of bits typically remains better than 11.5 content of the input signal. Hence, the parameters for which the for frequencies up to 12 kHz. AD7880 is specified include SNR, harmonic distortion, inter- modulation distortion and peak harmonics. These terms are dis- cussed in more detail in the following sections. REV. 0 –7– AD7880 12 Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, 11.5 while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the inter- modulation distortion is as per the THD specification where it is 11 the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion, sine waves. Figure 14 shows a typical IMD plot for the 10.5 SAMPLE FREQUENCY = 61kHz AD7880. T = 25 C A 10 15 30.5 INPUT FREQUENCY – kHz Figure 13. Effective Number of Bits vs. Frequency Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD7880, THD is defined as: 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD = 20log (3) V 1 where V is the rms amplitude of the fundamental and V , V , 1 2 3 V , V and V are the rms amplitudes of the second through the 4 5 6 sixth harmonic. The THD is also derived from the FFT plot of the ADC output spectrum. Intermodulation Distortion Figure 14. IMD Plot With inputs consisting of sine waves at two frequencies, fa and Peak Harmonic or Spurious Noise fb, any active device with nonlinearities will create distortion Peak harmonic or spurious noise is defined as the ratio of the products at sum and difference frequencies of mfa ± nfb where rms value of the next largest component in the ADC output m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which spectrum (up to FS/2 and excluding dc) to the rms value of the neither m nor n are equal to zero. For example, the second or- fundamental. Normally, the value of this specification will be der terms include (fa + fb) and (fa – fb), while the third order determined by the largest harmonic in the spectrum, but for terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). parts where the harmonics are buried in the noise floor the peak will be a noise peak. REV. 0 –8– EFFECTIVE NUMBER OF BITS AD7880 MICROPROCESSOR INTERFACING TIMER The AD7880 high speed bus timing allows direct interfacing to PA2 real time digital signal processors, DSPs, as well as modern high ADDRESS BUS PA0 speed, 16-bit microprocessors. Suitable microprocessor inter- faces are shown in Figures 15 through 20. ADDR CONVST AD7880–ADSP-2100 Interface DECODE CS Figure 15 shows an interface between the AD7880 and the MEN EN ADSP-2100. Conversion is initiated using a timer to drive the CONVST input asynchronously to the microprocessor. This al- TMS32010 AD7880* lows very accurate control of the sampling instant. When con- version is complete, the AD7880 BUSY line goes high. An RD DEN inverter on this BUSY output drives the IRQ line low thus pro- INT BUSY viding an interrupt to the ADSP-2100 when conversion is com- pleted. The conversion result is then read from the AD7880 into DB11 A the ADSP-2100 with the following instruction: DB0 A MR0 = DM(ADC) D15 DATA BUS where MR0 is the ADSP-2100 MR0 Register and D0 where ADC is the AD7880 address. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 16. AD7880–TMS32010 Interface DMA13 TIMER AD7880–TMS320C25 Interface ADDRESS BUS DMA0 Figure 17 shows an interface between the AD7880 and the TMS320C25. As with the two previous interfaces, conversion is CONVST ADDR initiated with a timer, and the processor is interrupted when the CS DECODE conversion sequence is completed. The TMS320C25 does not DMS EN have a separate RD output to drive the AD7880 RD input di- rectly. This has to be generated from the processor STRB and AD7880* ADSP-2100 R/W outputs with the addition of some logic gates. The RD sig- (ADSP-2101/ nal is OR-gated with the MSC signal to provide the one WAIT ADSP-2102) state required in the read cycle for correct interface timing. DMRD (RD) RD Conversion results are read from the AD7880 using the follow- ing instruction: IRQn BUSY IN D,ADC DB11 A where D is Data Memory Address and DB0A where ADC is the AD7880 address. DMD15 DATA BUS TIMER DMD0 A15 * ADDITIONAL PINS OMITTED FOR CLARITY ADDRESS BUS A0 Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102) ADDR Interface CONVST DECODE CS AD7880-ADSP-2101/ADSP-2102 Interface IS EN The interface outlined in Figure 15 also forms the basis for an AD7880* TMS320C25 interface between the AD7880 and the ADSP-2101/ADSP-2102. INTn BUSY The READ line of the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the RD pulse width of the processor can be STRB RD programmed using the Data Memory Wait State Control Regis- R/W ter. The instruction used to read a conversion result is as out- READY lined for the ADSP-2100. DB11 AMSC AD7880-TMS32010 Interface DB0 AAn interface between the AD7880 and the TMS32010 is shown in Figure 16. Once again the conversion is initiated using an ex- D15 DATA BUS ternal timer and the TMS32010 is interrupted when conversion D0 *ADDITIONAL PINS OMITTED FOR CLARITY is completed. The following instruction is used to read the con- version result from the AD7880: Figure 17. AD7880–TMS320C25 Interface IN D,ADC Some applications may require that the conversion be initiated where D is Data Memory Address and by the microprocessor rather than an external timer. One option where ADC is the AD7880 address. is to decode the AD7880 CONVST from the address bus so that REV. 0 –9– AD7880 a write operation starts a conversion. Data is read at the end of the conversion sequence as before. Figure 19 shows an example ADDRESS BUS of initiating conversion using this method. A similar implemen- tation can be used for DSPs. Note that for all interfaces, a read ADDR 8086 operation should not be attempted during conversion. DECODE CS AD7880–MC68000 Interface AD7880* An interface between the AD7880 and the MC68000 is shown ALE LATCH in Figure 18. As before, conversion is initiated using an external CONVST timer. The AD7880 BUSY line can be used to interrupt the WR processor or, alternatively, software delays can ensure that con- RD RD version has been completed before a read to the AD7880 is at- tempted. Because of the nature of its interrupts, the 68000 DB11 requires additional logic (not shown in Figure 18) to allow it to DB0A be interrupted correctly. For further information on 68000 in- AD15 terrupts, consult the 68000 users manual. ADDRESS/DATA BUS AD0 The MC68000 AS and R/W outputs are used to generate a *ADDITIONAL PINS OMITTED FOR CLARITY separate RD input signal for the AD7880. CS is used to drive the 68000 DTACK input to allow the processor to execute a Figure 19. AD7880–8086 Interface normal read operation to the AD7880. The conversion results AD7880–6809 Interface are read using the following 68000 instruction: The AD7880 can also interface quite easily with 8-bit micro- MOVE.W ADC, D0 processors. The 12-bit parallel data output from the AD7880 where D0 is the 68000 D0 register can be read into the microprocessor as an 8+4 byte structure. Figure 20 shows an interface to the MC6809 8-bit microproces- where ADC is the AD7880 address sor. As in previous cases, conversion is initiated using an exter- nal timer. At the end of conversion, BUSY triggers a one-shot TIMER A15 ADDRESS BUS which drives the IRQ interrupt input of the microprocessor. A A0 double read is then performed to two unique addresses. The first read fetches the lower 8 bits (DB0–DB7) and loads the MC68000 ADDR CONVST 74HC374 latch with the upper 4 bits (DB8–DB11). The sec- DECODE CS ond read fetches these upper 4 bits. AS EN DTACK A15 AD7880* TIMER ADDRESS BUS A0 RD R/W ADDR CONVST DECODE DB11 MC6809ACS DB0 A AD7880* D15 R/W DATA BUS RD D0 E *ADDITIONAL PINS OMITTED FOR CLARITY ONE IRQ BUSY SHOT Figure 18. AD7880–MC68000 Interface CLK OE AD7880–8086 Interface DB11 D3A Q3 Figure 19 shows an interface between the AD7880 and the DB8 D0 ADB7 Q0 8086 microprocessor. Unlike the previous interface examples, 74HC374 DB0Athe microprocessor initiates conversion. This is achieved by gat- ing the 8086 WR signal with a decoded address output (differ- D7 ent to the AD7880 CS address). Conversion is initiated and the DATA BUS D0 result is read from the AD7880 using the following instruction: *ADDITIONAL PINS OMITTED FOR CLARITY MOV AX, ADC where AX is the 8086 accumulator and Figure 20. AD7880–6809 Interface where ADC is the AD7880 address REV. 0 –10– AD7880 APPLICATION HINTS LK2 AB Good printed circuit board (PCB) layout is as important as the V+ V DD circuit design itself in achieving high speed A/D performance.AA V+ The AD7880’s comparator is required to make bit decisions onA an LSB size of 1.22 mV. To achieve this, the designer must be conscious of noise both in the ADC itself and in the preceding C1 C2 ANALOG 10µF 0.1µF analog circuitry. Switching mode power supplies are not recom- INPUT LK1 V+ mended, as the switching spikes will feed through to the com- SKT1 + parator causing noisy code transitions. Other causes of concern IC1 TO ADC – are ground loops and digital feedthrough from microprocessors. V– These are factors which influence any ADC, and a proper PCB layout which minimizes these effects is essential for best C4 C3 performance. 0.1µF 10µF LAYOUT HINTS AA V– Ensure that the layout for the printed circuit board has the digi- ABA tal and analog signal lines separated as much as possible. Take LK3 care not to run digital tracks alongside analog signal tracks. Figure 21. Analog Input Buffering Guard (screen) the analog input with AGND. When it is required to drive the AD7880 with the 0 V to 10 V Establish a single point analog ground (star ground) separate input range, an external supply must be connected to V+ (see from the logic system ground at the AD7880 AGND pin or as Figure 21). close as possible to the AD7880. Connect all other grounds and the AD7880 DGND to this single analog ground point. Do not In bipolar operation, positive and negative supplies must be connect any other digital grounds to this analog ground point. connected to V+ and V–. Low impedance analog and digital power supply common re- The AD711 is a general purpose op amp which could be used turns are essential to low noise operation of the ADC, so make to drive the analog input of the AD7880. the foil width for these tracks as wide as possible. The use of ground planes minimizes impedance paths and also guards the POWER-DOWN CONTROL (MODE INPUT) analog circuitry from digital noise. The circuit layout of Fig- The AD7880 is designed for systems which need to have mini- ures 26 and 27 have both analog and digital ground planes mum power consumption. This includes such applications as which are kept separated and only joined together at the hand held, portable battery powered systems and remote moni- AD7880 AGND pin. toring systems. As well as consuming minimum power under normal operating conditions, typically 20 mW, the AD7880 NOISE can be put into a power-down or sleep mode when not required Keep the input signal leads to V and signal return leads from IN to convert signals. When in this power-down mode, the AGND as short as possible to minimize input noise coupling. In AD7880 consumes approximately 2 mW of power. applications where this is not possible, use a shielded cable be- The AD7880 is powered down by bringing the MODE input tween the source and the ADC. Reduce the ground circuit im- pin to a Logic Low in conjunction with keeping the RD input pedance as much as possible since any potential difference in control High. The AD7880 will remain in the power-down grounds between the signal source and the ADC appears as an mode until MODE is brought to a Logic High again. The error voltage in series with the input signal. MODE input should be driven with CD4000 or HCMOS logic ANALOG INPUT BUFFERING levels. To achieve specified performance, it is recommended that the It is recommended that one “dummy” conversion be imple- analog input (V , V ) be driven from a low impedance INA INB mented before reading conversion data from the AD7880 after source. This necessitates the use of an input buffer amplifier. it has been in the power-down mode. This is required to reset The choice of op amp will be a function of the particular appli- all internal logic and control circuitry. In a remote monitoring cation and the desired analog input range. The data acquisition system where, say, 10 conversions are required to be taken with circuit, described in this data sheet allows for various op amp a sampling interval of 1 second, an additional 11th conversion configurations. Figure 21 shows the analog input buffer circuit. must be carried out. Figure 22 gives a plot of power consumption The options available to drive the supply of the op amp are: CONVERTING CONVERTING 20 Single +5 V (derived from PCB 5 V supply) AAAAAAPOWER Dual Supply (externally supplied to V+ and V–) CONSUMPTION – mW POWER-DOWNAAAPOWER-DOWNAAAAA ±5 V, ±12 V or ±15 V 2 AAAAAAAAAAAAAAAAA–4 01 1.65 x 10 2 The simplest configuration is the 0 V to 5 V range of Figure 5. TIME – secs A single supply 5 V op amp is recommended for such an imple- Figure 22. Power Consumption for Normal Operation mentation. This will allow for operation of the AD7880 in the 0 and Power-Down Operation vs. Time V to 5 V unipolar range without supplying an external supply to V+ and V–. The 5 V supply is derived from the systems +5 V V supply. DD REV. 0 –11– AAAAAA AD7880 as a function of time for such operation. The total conversion LK1 Connects the analog input to a buffer amplifier. The time for each cycle is 11 × 15 μs (where 15 μs is the time taken analog input may also be connected to a component –4 for a single conversion) corresponding to 1.65 × 10 secs. grid for signal conditioning. Hence: LK2, LK3 Allows for various op amp power supplies to be Average Power = Power + Power CONVERTING POWER-DOWN used to drive the input buffer of the AD7880. Ex- –4 ternal supplies may be connected to V+ and V–. = {20 mW × (1.65 × 10 )/(10)} Alternatively, the AD7880’s +5 V system supply + {2 mW × (9.9998)/(10)} and AGND can be selected to drive a single supply = 2.029 mW op amp. LK4 Configures the various analog input ranges, 0 V to AD7880 DATA ACQUISITION LAYOUT 5 V, 0 V to 10 V or ±5 V. Figure 24 shows the AD7880 in a data acquisition circuit. The LK5 Selects reference input to V of AD7880. Nor- REF corresponding printed circuit board (PCB) layout and mally connected to V . An external reference DD silkscreen are shown in Figures 25 to 27. could also be wired in. The only additional component required for a full data acquisi- LK6 Selects power-down or sleep mode. The shorting tion system is an antialiasing filter. There is a component grid plug is connected to V for normal operation. DD provided near the analog input on the PCB which may be used LK7 Connects the AD7880 RD input directly to the RD for such a filter or any other input conditioning circuitry. To fa- input of SKT4 or to a decoded STRB and R/W cilitate this option there is a shorting link (labeled LK1 on the input. This shorting plug setting depends on the PCB) on the analog input track. With LK1 in place, the analog microprocessor, e.g., the TMS320C25 requires a input connects to the buffer amplifier driving the AD7880. decoded RD signal. With LK1 removed, a wire link is needed to connect the analog input to the PCB component grid. 1 2 R/W STRB 3 4 N/C RD INTERFACE CONNECTIONS The data acquisition board contains a parallel connection port 5 6 CS N/C labeled SKT4. This is a 26-contact IDC Connector and pro- BUSY 7 8 BUSY vides for direct microprocessor connection to the board. This N/C 9 10 N/C connector, the pinout of which is shown in Figure 23, contains all data, control and status signals of the AD7880 (with the ex- DB10 11 12 DB11 ception of the CONVST and the CLKIN inputs both of which 13 14 DB8 DB9 are provided via SKT2 and SKT3 respectively). It also contains decoded R/W and STRB inputs which are necessary for inter- DB6 15 16 DB7 facing to many microprocessors including the TMS320C25 and DB4 17 18 DB5 the Motorola 68000 series. Link LK7 selects RD directly or al- DB2 19 20 DB3 ternatively, the decoded version. Note that the AD7880 CS in- put must be decoded prior to the AD7880 evaluation board. DB0 21 22 DB1 SKT1, SKT2 and SKT3 are three sub-miniature connectors +5V 23 24 +5V (SMC) which provide input connections for the analog input, GND 25 26 GND the CONVST input and the CLKIN input. Three different in- put ranges can be accepted by the AD7880 each of which is Figure 23. SKT4, IDC Connector Pinout configured by selecting shorting plug options A, B or C of LK4. Position A corresponds to the 0 V to 5 V unipolar configuration COMPONENT LIST of Figure 5, position B corresponds to the bipolar ±5 V configu- IC1 Op Amp* ration of Figure 7 and position C allows for a 0 V to +10 V uni- IC2 AD7880 Analog-to-Digital Converter polar range as shown in Figure 6. IC3 74HC00 Quad NAND Gate POWER SUPPLY CONNECTIONS C1, C3, C5 10 μF Capacitors The PCB requires a single +5 V power supply (labeled V ). DD C2, C4, C6, C7 0.1 μF Capacitors Good decoupling allows this supply to drive the AD7880 V DD R1, R2 10 kΩ Pull-up Resistors which also drives the V input as well as the op amp power REF supply. In circumstances where bipolar ±5 V or a unipolar 0 V LK1, LK2, LK3 Shorting Links to 10 V input ranges are required, provision has been allowed LK4, LK5, LK6 for the connection of separate op amp power supplies (±15 V, LK7 ±12 V, ±5 V, etc.) to V+ and V–. LK2 and LK3 shorting links SKT1, SKT2, SKT3 Sub-Miniature Connectors allow for the selection of user defined op amp power supplies or Vendor No: Sealectro 50-051-0000 (Socket) the on-board single +5 V supply. Vendor No: Sealectro 50-007-0000 (Plug) SKT4 26-Contact (2 Row) IDC Connector LINK OPTIONS There are seven link options which must be set before using the NOTE *See ANALOG INPUT BUFFERING section. board. These are outlined below: . REV. 0 –12– AD7880 Figure 24. Data Acquisition Circuit Using the AD7880 Figure 25. PCB Silkscreen for Figure 24 REV. 0 –13– AD7880 Figure 26. PCB Component Side Layout for Figure 24 Figure 27. PCB Solder Side Layout for Figure 24 REV. 0 –14– AD7880 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 1.228 (31.19) 1.226 (31.14) 24 13 0.260 ± 0.001 (6.61 ± 0.03) 112 0.32 (8.128) 0.30 (7.62) PIN 1 0.130 (3.30) 0.128 (3.25) SEATING 0.011 (0.28) PLANE 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 0.009 (0.23) 0.016 (0.41) 0.09 (2.28) 0.05 (1.27) 15° 0 NOTES: 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 24-Lead Cerdip (Q-24) 24 13 0.295 (7.493) MAX 1 12 0.320 (8.128) 0.291 (7.4) 1.290 (32.77) MAX 0.225 0.180 (5.715) (4.572) MAX MAX SEATING PLANE 0.125 0.070 (1.778) (3.175) 0.012 (0.305) MIN 0.110 (2.794) 0.020 (0.508) 0.021 (0.533) 0.065 (1.651) 15° 0.008 (0.203) 0.009 (2.286) 0° 0.015 (0.381) 0.055 (1.397) TYP TYP 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 24-Lead SOIC (R-24) 0.614 (15.6) 0.598 (15.2) 24 13 0.299 (7.6) 0.419 (10.65) 0.291 (7.4) 0.394 (10.00) 1 12 PIN 1 0.104 (2.65) 0.03 (0.75) 0.093 (2.35) 0.01 (0.25) 8° 0.012 (0.3) 0.05 0.019 (0.49) 0° 0.05 (1.27) 0.013 (0.32) (1.27) 0.004 (0.1) 0.014 (0.35) 0.016 (0.40) BSC 0.009 (0.23) REV. 0 –15– –16– PRINTED IN U.S.A. C1414–10–6/90