ANALOG DEVICES AD7873

Touch Screen Digitizer AD7873 FEATURES FUNCTIONAL BLOCK DIAGRAM +V 4-wire touch screen interface CC PENIRQ On-chip temperature sensor: −40°C to +85°C On-chip 2.5 V reference PEN Direct battery measurement (0 V to 6 V) TEMP INTERRUPT X+ SENSOR Touch pressure measurement X– Specified throughput rate of 125 kSPS AD7873 Y+ Single supply, VCC of 2.2 V to 5.25 V T/H Y– Ratiometric conversion 6-TO-1 I/P High speed serial interface MUX AUX Programmable 8-bit or 12-bit resolution COMP One auxiliary analog input BATTERY MONITOR Shutdown mode: 1 μA maximum V BAT 16-lead QSOP, TSSOP, and LFCSP packages V REF APPLICATIONS GND Personal digital assistants CHARGE Smart hand-held devices REDISTRIBUTION +V DAC CC 2.5V Touch screen monitors BUF REF Point-of-sale terminals Pagers SAR + ADC CONTROL LOGIC GENERAL DESCRIPTION The AD7873 is a 12-bit successive approximation ADC with a SPORT synchronous serial interface and low on resistance switches for driving touch screens. The AD7873 operates from a single 2.2 V DIN CS DOUT DCLK BUSY to 5.25 V power supply and features throughput rates greater Figure 1. than 125 kSPS. PRODUCT HIGHLIGHTS The AD7873 features direct battery measurement, temperature 1. Ratiometric conversion mode available, eliminating errors measurement, and touch pressure measurement. The AD7873 due to on-board switch resistances. also has an on-board reference of 2.5 V that can be used for the auxiliary input, battery monitor, and temperature measurement 2. On-board temperature sensor: −40°C to +85°C. modes. When not in use, the internal reference can be shut 3. Battery monitor input. down to conserve power. An external reference can also be 4. Touch pressure measurement capability. applied and can be varied from 1 V to VCC and the analog input range is from 0 V to VREF. The device includes a shutdown 5. Low power consumption of 1.37 mW maximum with the mode that reduces the current consumption to less than 1 μA. reference off, or 2.41 mW typical with the reference on, at 125 kSPS and V at 3.6 V. CC The AD7873 features on-board switches. This, coupled with low 6. Package options include 4 mm × 4 mm LFCSP. power and high speed operation, makes the device ideal for battery-powered systems such as personal digital assistants with 7. Analog input range from 0 V to V . REF resistive touch screens and other portable equipment. The part 8. Versatile serial I/O ports. is available in a 16-lead, 0.15" quarter size outline package (QSOP), a 16-lead, thin shrink small outline package (TSSOP), and a 16-lead, lead frame chip scale package (LFCSP). Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02164-001 AD7873 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information........................................................................ 13 Applications....................................................................................... 1 ADC Transfer Function............................................................. 13 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 13 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 14 Product Highlights ........................................................................... 1 Measurements............................................................................. 16 Revision History ............................................................................... 2 Pen Interrupt Request................................................................ 18 Specifications..................................................................................... 3 Control Register ......................................................................... 19 Timing Specifications .................................................................. 5 Power vs. Throughput Rate....................................................... 20 Absolute Maximum Ratings............................................................ 6 Serial Interface ............................................................................ 21 Thermal Resistance ...................................................................... 6 Grounding and Layout .................................................................. 23 ESD Caution.................................................................................. 6 PCB Design Guidelines for Chip Scale Package .................... 23 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 24 Terminology ...................................................................................... 8 Ordering Guide .......................................................................... 25 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 9/06—Rev. D to Rev. E 1/02—Rev. A to Rev. B Changes to Figure 13 Caption....................................................... 10 Addition of 16-Lead Lead Frame Chip Scale Package ..Universal Updated Outline Dimensions ....................................................... 24 Edits to Features.................................................................................1 Changes to Ordering Guide .......................................................... 25 Edits to General Description ...........................................................1 Addition of LFCSP Pin Configuration ...........................................4 6/04—Rev. C to Rev. D Edit to Absolute Maximum Ratings................................................4 Updated Format..................................................................Universal Addition to Ordering Guide ............................................................4 Changes to Absolute Maximum Ratings ....................................... 6 Addition of CP-16 Outline Dimensions ..................................... 19 Additions to PD0 and PD1 Description...................................... 21 PBC Guidelines for Chip Scale Package Added ......................... 23 2/01—Rev. 0 to Rev A Additions to Ordering Guide........................................................ 25 Edits to Notes in the Ordering Guide 4/03—Rev. B to Rev. C Changes to Formatting ......................................................Universal Updated Outline Dimensions ....................................................... 19 Rev. E | Page 2 of 28 AD7873 SPECIFICATIONS VCC = 2.7 V to 3.6 V, VREF = 2.5 V internal or external, fDCLK = 2 MHz; TA = −40°C to +85°C, unless otherwise noted. Table 1. 1 1 Parameter AD7873A AD7873B Unit Test Conditions/Comments DC ACCURACY Resolution 12 12 Bits No Missing Codes 11 12 Bits min 2 Integral Nonlinearity ±2 ± 1 LSB max 2 Differential Nonlinearity –0.9/+1.5 LSB max 2 Offset Error ±6 ±6 LSB max +V = 2.7 V CC 2 Gain Error ±4 ±4 LSB max External reference Noise 70 70 μV rms typ Power Supply Rejection 70 70 dB typ SWITCH DRIVERS 2 On Resistance Y+, X+ 5 5 Ω typ Y–, X– 6 6 Ω typ ANALOG INPUT Input Voltage Ranges 0 to VREF 0 to VREF V DC Leakage Current ±0.1 ±0.1 μA typ Input Capacitance 37 37 pF typ REFERENCE INPUT/OUTPUT Internal Reference Voltage 2.45/2.55 2.45/2.55 V min/max Internal Reference Tempco ±15 ±15 ppm/°C typ V Input Voltage Range 1/V 1/V V min/max REF CC CC DC Leakage Current ±1 ± 1 μA max VREF Input Impedance 1 1 GΩ typ CS = GND or +VCC; typically 260 Ω when the on-board reference is enabled TEMPERATURE MEASUREMENT Temperature Range –40/+85 –40/+85 °C min/max Resolution 3 Differential Method 1.6 1.6 °C typ 4 Single Conversion Method 0.3 0.3 °C typ Accuracy 3 Differential Method ±2 ±2 °C typ 4 Single Conversion Method ±2 ±2 °C typ BATTERY MONITOR Input Voltage Range 0/6 0/6 V min/max Input Impedance 10 10 kΩ typ Sampling; 1 GΩ when battery monitor is off Accuracy ±2.5 ±2 % max External reference ±3 ±3 % max Internal reference LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min INH Input Low Voltage, V 0.4 0.4 V max INL Input Current, I ±1 ±1 μA max Typically 10 nA, V = 0 V or +V IN IN CC 5 Input Capacitance, CIN 10 10 pF max Rev. E | Page 3 of 28 AD7873 1 Parameter AD7873A AD7873B Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VCC – 0.2 VCC – 0.2 V min ISOURCE = 250 μA; VCC = 2.2 V to 5.25 V Output Low Voltage, VOL 0.4 0.4 V max ISINK = 250 μA PENIRQ Output Low Voltage, V 0.4 0.4 V max 100 kΩ pull-up; I = 250 μA OL SINK Floating-State Leakage Current ±10 ±10 μA max 5 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 12 12 DCLK cycles max Track-and-Hold Acquisition Time 3 3 DCLK cycles min Throughput Rate 125 125 kSPS max POWER REQUIREMENTS +V (Specified Performance) 2.7/3.6 2.7/3.6 V min/max Functional from 2.2 V to 5.25 V CC 6 I Digital I/Ps = 0 V or V CC CC Normal Mode (fSAMPLE = 125 kSPS) 380 380 μA max Internal reference off, VCC = 3.6 V, 240 μA typ 670 670 μA typ Internal reference on, VCC = 3.6 V Normal Mode (fSAMPLE = 12.5 kSPS) 170 170 μA typ Internal reference off, VCC = 2.7 V, fDCLK = 200 kHz Normal Mode (Static) 150 150 μA typ Internal reference off, V = 3.6 V CC 580 580 μA typ Internal reference on, V = 3.6 V CC Shutdown Mode (Static) 1 1 μA max 200 nA typ 6 Power Dissipation Normal Mode (fSAMPLE = 125 kSPS) 1.368 1.368 mW max Internal reference off, VCC = 3.6 V 2.412 2.412 mW typ Internal reference on, VCC = 3.6 V Shutdown 3.6 3.6 μW max V = 3.6 V CC 1 Temperature range as follows: A, B Versions: –40°C to +85°C. 2 See the Terminology section. 3 Difference between TEMP0 and TEMP1 measurement. No calibration necessary. 4 Temperature drift is –2.1 mV/°C. 5 Sample tested @ 25°C to ensure compliance. 6 See the Power vs. Throughput Rate section. Rev. E | Page 4 of 28 AD7873 TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 5.25 V, VREF = 2.5 V. 1 Table 2. Timing Specifications Parameter Limit at TMIN, TMAX Unit Description 2 f 10 kHz min DCLK 2 MHz max tACQ 1.5 μs min Acquisition time t 10 ns min CS falling edge to first DCLK rising edge 1 CS falling edge to busy three-state disabled t2 60 ns max 3 CS falling edge to DOUT three-state disabled t3 60 ns max t4 200 ns min DCLK high pulse width t5 200 ns min DCLK low pulse width t6 60 ns max DCLK falling edge to BUSY rising edge t 10 ns min Data setup time prior to DCLK rising edge 7 t 10 ns min Data valid to DCLK hold time 8 3 t 200 ns max Data access time after DCLK falling edge 9 t 0 ns min CS rising edge to DCLK ignored 10 t 100 ns max CS rising edge to BUSY high impedance 11 4 t 100 ns max CS rising edge to DOUT high impedance 12 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the DCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V. 4 t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. E | Page 5 of 28 02164-002 AD7873 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational +V to GND –0.3 V to +7 V CC section of this specification is not implied. Exposure to absolute Analog Input Voltage to GND –0.3 V to V + 0.3 V CC maximum rating conditions for extended periods may affect Digital Input Voltage to GND –0.3 V to VCC + 0.3 V device reliability. Digital Output Voltage to GND –0.3 V to VCC + 0.3 V VREF to GND –0.3 V to VCC + 0.3 V THERMAL RESISTANCE 1 Input Current to Any Pin Except Supplies ±10 mA θ is specified for the worst-case conditions, that is, a device JA Operating Temperature Range soldered in a circuit board for surface-mount packages. Commercial (A, B Versions) –40°C to +85°C Table 4. Thermal Resistance Storage Temperature Range –65°C to +150°C Package Type θ θ Unit JA JC Junction Temperature 150°C 16-Lead QSOP 149.97 38.8 °C/W Power Dissipation 450 mW 16-Lead TSSOP 150.4 27.6 °C/W IR Reflow Soldering 16-Lead LFCSP 135.7 °C/W Peak Temperature 220°C (±5°C) Time-to-Peak Temperature 10 sec to 30 sec Ramp-Down Rate 6°C/sec max ESD CAUTION Pb-free Parts Only Peak Temperature 250°C Time-to-Peak Temperature 20 sec to 40 sec Ramp-Up Rate 3°C/sec max Ramp-Down Rate 6°C/sec max 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. E | Page 6 of 28 AD7873 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS +V 1 16 DCLK CC X+ 2 15 CS 3 14 Y+ AD7873 DIN PIN 1 TOP VIEW INDICATOR 4 13 AUX 1 12 Y+ X– BUSY (Not to Scale) 11 X+ V 2 REF 5 12 AD7873 Y– DOUT +V 3 10 +V CC TOP VIEW CC 6 11 GND PENIRQ (Not to Scale) PENIRQ 4 9 DCLK V 7 10 +V BAT CC 8 9 AUX V REF Figure 3. LFCSP Pin Configuration Figure 4. QSOP/TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. QSOP/ Mnemonic Function LFCSP TSSOP 3, 10 1, 10 +VCC Power Supply Input. The +VCC range for the AD7873 is from 2.2 V to 5.25 V. Both +VCC pins should be connected directly together. 11 2 X+ X+ Position Input. ADC Input Channel 1. 12 3 Y+ Y+ Position Input. ADC Input Channel 2. 13 4 X– X– Position Input. 14 5 Y– Y– Position Input. ADC Input Channel 3. 15 6 GND Analog Ground. Ground reference point for all circuitry on the AD7873. All analog input signals and any external reference signals should be referred to this GND voltage. 16 7 V Battery Monitor Input. ADC Input Channel 4. BAT 1 8 AUX Auxiliary Input. ADC Input Channel 5. 2 9 V Reference Output for the AD7873. Alternatively, an external reference can be applied to this input. REF The voltage range for the external reference is 1.0 V to +VCC. For specified performance, it is 2.5 V on the AD7873. The internal 2.5 V reference is available on this pin for use external to the device. The reference output must be buffered before it is applied elsewhere in a system. A 0.1 μF capacitor is recommended between this pin and GND to reduce system noise effects. 4 11 PENIRQ Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally). 5 12 DOUT Data Out. Logic output. The conversion result from the AD7873 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high. 6 13 BUSY BUSY Output. Logic output. This output is high impedance when CS is high. 7 14 DIN Data In. Logic Input. Data to be written to the AD7873 control register is provided on this input and is clocked into the register on the rising edge of DCLK (see the Control Register section). 8 15 CS Chip Select Input. Active low logic input. This input provides the dual function of initiating conversions on the AD7873 and enabling the serial input/output register. 9 16 DCLK External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7873 conversion process. Rev. E | Page 7 of 28 02164-003 02164-004 DOUT 5 16 V BAT BUSY 6 15 GND DIN 7 14 Y– CS 8 13 X– AD7873 TERMINOLOGY Integral Nonlinearity Gain Error Integral nonlinearity is the maximum deviation from a straight Gain error is the deviation of the last code transition (111…110) line passing through the endpoints of the ADC transfer function. to (111…111) from the ideal (that is, VREF – 1 LSB) after the The endpoints of the transfer function are zero scale, a point 1 LSB offset error is adjusted out. below the first code transition, and full scale, a point 1 LSB Track-and-Hold Acquisition Time above the last code transition. The track-and-hold amplifier enters the acquisition phase on Differential Nonlinearity the fifth falling edge of DCLK after the start bit has been Differential nonlinearity is the difference between the measured detected. Three DCLK cycles are allowed for the track-and-hold and the ideal 1 LSB change between any two adjacent codes in acquisition time. The input signal is fully acquired to the 12-bit the ADC. level within this time even with the maximum specified DCLK frequency. See the Analog Input section for more details. Offset Error Offset error is the deviation of the first code transition (00…000) On Resistance to (00…001) from the ideal, that is, AGND + 1 LSB. On resistance is a measure of the ohmic resistance between the drain and source of the switch drivers. Rev. E | Page 8 of 28 AD7873 TYPICAL PERFORMANCE CHARACTERISTICS 207 141 206 140 205 139 204 138 203 202 137 201 136 200 135 199 134 198 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Power-Down Supply Current vs. Temperature Figure 5. Supply Current vs. Temperature 1000 230 f = 12.5kHz 220 SAMPLE V =+V REF CC 210 200 190 V =+V 180 REF CC 170 160 150 100 2.2 2.7 3.2 3.7 4.2 4.7 5.2 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 +V (V) CC +V (V) CC Figure 9. Maximum Sample Rate vs. +VCC Figure 6. Supply Current vs. +V CC 0.6 0.20 0.15 0.4 0.10 0.2 0.05 0 0 –0.05 –0.2 –0.10 –0.4 –0.15 –0.20 –0.6 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Change in Gain vs. Temperature Figure 10. Change in Offset vs. Temperature Rev. E | Page 9 of 28 DELTA FROM 25°C (LSB) SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 02164-007 02164-006 02164-005 DELTA FROM 25°C (LSB) SUPPLY CURRENT (nA) SAMPLE RATE (kSPS) 02164-009 02164-010 02164-008 AD7873 7.5 14 13 6.5 12 11 5.5 10 9 4.5 8 3.5 7 6 2.5 5 4 1.5 3 0.5 2 10 25 40 55 70 85 100 115 130 –40 –20 020 40 60 80 SAMPLE RATE (kHz) TEMPERATURE (°C) Figure 11. Reference Current vs. Sample Rate Figure 14. Reference Current vs. Temperature 10 9 9 8 Y+ Y+ X+ X+ 8 7 X– 7 6 Y– X– 6 5 Y– 5 4 4 3 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100 +V (V) TEMPERATURE (°C) CC Figure 12. Switch On Resistance vs. +VCC Figure 15. Switch On Resistance vs. Temperature (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) 2.0 2.5006 1.8 2.5004 1.6 2.5002 INL: R = 2kΩ 1.4 2.5000 1.2 INL: R = 500Ω 2.4998 1.0 2.4996 0.8 DNL: R = 2kΩ 2.4994 0.6 2.4992 0.4 DNL: R = 500Ω 2.4990 0.2 0 2.4988 15 35 55 75 95 115 135 155 175 195 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 SAMPLING RATE (kSPS) TEMPERATURE (°C) Figure 13. Linearity Error vs. Sampling Rate for Various R Figure 16. Internal V vs. Temperature IN REF Rev. E | Page 10 of 28 ERROR (LSB) REFERENCE CURRENT (µA) R (Ω) ON 02164-013 02164-012 02164-011 INTERNAL V (V) REF R (Ω) ON REFERENCE CURRENT (µA) 02164-014 02164-015 02164-016 AD7873 2.504 5 2.502 2.500 4 2.498 2.496 3 2.494 NO CAP (7µs) 2.492 2 SETTLING TIME 2.490 1µF CAP (1800µs) 2.488 1 SETTLING TIME 2.486 2.484 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 0 200 400 600 800 1000 1200 1400 1600 1800 TURN-ON TIME (µs) +V (V) CC Figure 17. Internal VREF vs. +VCC Figure 20. Internal VREF vs. Turn-on Time 850 610 609 800 TEMP1 608 95.95mV 750 607 700 606 650 605 604 600 TEMP0 603 142.15mV 550 602 500 601 450 600 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (°C) V (V) SUPPLY Figure 18. Temp Diode Voltage vs. Temperature (2.7 V Supply) Figure 21. TEMP0 Diode Voltage vs. VSUPPLY (25°C) 730 0 f = 125kHz 729 SAMPLE f = 15kHz IN 20 728 SNR = 68.34dB 727 40 726 725 60 724 80 723 722 100 721 720 120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 60.0 2.7 3.0 3.3 3.6 FREQUENCY (kHz) V (V) SUPPLY Figure 19. TEMP1 Diode Voltage vs. VSUPPLY (25°C) Figure 22. Auxiliary Channel Dynamic Performance (fSAMPLE =125 kHz, fINPUT = 15 kHz) Rev. E | Page 11 of 28 V (V) TEMP1 DIODE VOLTAGE (mV) REF TEMP DIODE VOLTAGE (mV) 02164-018 02164-019 02164-017 INTERNAL V (V) TEMP0 DIODE VOLTAGE (mV) REF SNR (dB) 02164-022 02164-021 02164-020 AD7873 0 Figure 23 shows the power supply rejection ratio vs. V supply DD V =3V CC frequency for the AD7873. The power supply rejection ratio is 100mV p-p SINE WAVE ON +V CC –20 V = 2.5V EXT REFERENCE REF defined as the ratio of the power in the ADC output at full-scale f = 125kHz, f = 20kHz SAMPLE IN frequency, f, to the power of a 100 mV sine wave applied to the –40 ADC VCC supply of frequency fS PSSR (dB) = 10log(Pf/Pfs) –60 where: –80 Pf is power at frequency, f, in ADC output. –100 Pf is power at frequency, f , coupled onto the ADC V supply. s s CC Here a 100 mV p-p sine wave is coupled onto the V supply. CC –120 0 1020 30 40 50 6070 80 90 100 Decoupling capacitors of 10 μF and 0.1 μF were used on the supply. V RIPPLE FREQUENCY (kHz) CC Figure 23. AC PSRR vs. Supply Ripple Frequency Rev. E | Page 12 of 28 PSRR (dB) 02164-023 AD7873 CIRCUIT INFORMATION The AD7873 is a fast, low power, 12-bit, single-supply analog- 111...111 to-digital converter (ADC). The AD7873 can be operated from 111...110 a 2.2 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7873 is capable of throughput 111...000 1LSB = V /4096 REF rates of 125 kSPS when provided with a 2 MHz clock. 011...111 The AD7873 provides the user with on-chip track-and-hold, 000...010 multiplexer, ADC, reference, temperature sensor, and serial 000...001 000...000 interface, housed in a tiny 16-lead QSOP, TSSOP, or LFCSP 1LSB +V –1LSB REF 0V ANALOG INPUT package, offering the user considerable space-saving advantages Figure 24. Transfer Characteristic over alternative solutions. The serial clock input (DCLK) accesses data from the part and also provides the clock source for the successive approximation ADC. The analog input range TYPICAL CONNECTION DIAGRAM is 0 V to V (where the externally applied V can be between REF REF Figure 25 shows a typical connection diagram for the AD7873 1 V and +V ). The AD7873 has a 2.5 V reference on-board CC in a touch screen control application. The AD7873 features an with this reference voltage available for use externally if buffered. internal reference, but this can be overdriven with an external The analog input to the ADC is provided via an on-chip low impedance source between 1 V and +VCC. The value of the multiplexer. This analog input can be any one of the X, Y, and Z reference voltage sets the input range of the converter. The panel coordinates, the battery voltage, or the chip temperature. conversion result is output MSB first, followed by the remaining The multiplexer is configured with low resistance switches that 11 bits and three trailing zeros, depending on the number of allow an unselected ADC input channel to provide power and clocks used per conversion (see the Serial Interface section). For an accompanying pin to provide ground for an external device. applications where power consumption is a concern, the power For some measurements, the on resistance of the switches could management option should be used to improve power perform- present a source of error. However, with a differential input to ance. See Table 8 for available power management options. the converter and a differential reference architecture, this error can be negated. ADC TRANSFER FUNCTION The output coding of the AD7873 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is VREF/4096. The ideal transfer characteristic for the AD7873 is shown in Figure 24. 2.2V TO 5V ++ 1µF TO 10µF 0.1µF +V DCLK 1 CC 16 SERIAL/CONVERSION CLOCK (OPTIONAL) 2 CHIP SELECT X+ CS 15 AD7873 3 Y+ DIN 14 SERIAL DATA IN 4 X– CONVERTER STATUS BUSY 13 TOUCH 5 Y– 12 SERIAL DATA OUT DOUT SCREEN TO BATTERY 6 11 GND PEN INTERRUPT PENIRQ +V 7 V 10 BAT CC AUXILIARY 50kΩ AUX 8 V 9 REF + INPUT 0.1µF VOLTAGE REGULATOR Figure 25. Typical Application Circuit Rev. E | Page 13 of 28 ADC CODE 02164-025 02164-024 AD7873 ANALOG INPUT Figure 26 shows an equivalent circuit of the analog input V CC structure of the AD7873 that contains a block diagram of the input multiplexer, the differential input of the ADC, and the X+ differential reference. X– Table 6 shows the multiplexer address corresponding to each Y+ REF INT/ analog input, both for the SER/ bit in the control register DFR Y– X+ Y+ EXT set high and low. The control bits are provided serially to the device via the DIN pin. For more information on the control 3-TO-1 ON-CHIP SWITCHES register, see the Control Register section. MUX When the converter enters hold mode, the voltage difference X+ between the +IN and –IN inputs (see Figure 26) is captured on Y+ REF+ IN+ IN+ ADC CORE DATA OUT Y– the internal capacitor array. The input current on the analog 6-TO-1 IN– REF– MUX inputs depends on the conversion rate of the device. During the V BAT sample period, the source must charge the internal sampling AUX 3-TO-1 capacitor (typically 37 pF). Once the capacitor is fully charged, TEMP MUX there is no further input current. The rate of charge transfer from the analog source to the converter is a function of X– Y– GND conversion rate. Figure 26. Equivalent Analog Input Circuit Table 6. Analog Input, Reference, and Touch Screen Control 1 1 SER/ DFR A2 A1 A0 Analog Input X Switches Y Switches +REF –REF 0 0 0 1 TEMP0 Off Off VREF GND 0 0 1 1 X+ Off On VREF GND 0 1 0 1 VBAT Off Off V GND REF 0 1 1 1 X+ (Z1) X+ Off Y+ On V GND REF X– On Y– Off 1 0 0 1 Y– (Z2) X+ Off Y+ On VREF GND X– On Y– Off 1 0 1 1 Y+ On Off VREF GND 1 1 0 1 AUX Off Off V GND REF 1 1 1 1 TEMP1 Off Off V GND REF 0 0 0 0 Invalid Address. Test Mode: Switches out the TEMP0 diode to the PENIRQ pin. 0 0 1 0 X+ Off On Y+ Y– 0 1 0 0 Invalid Address 0 1 1 0 X+ (Z1) X+ Off Y+ On Y+ X– X– On Y– Off 1 0 0 0 Y– (Z2) X+ Off Y+ On Y+ X– X– On Y– Off 1 0 1 0 Y+ ON Off X+ X– 1 1 0 0 Outputs Identity Code, 1000 0000 0000. 1 1 1 0 Invalid address. Test mode: Switches out the TEMP1 diode to the PENIRQ pin. 1 Internal node, not directly accessible by the user. Rev. E | Page 14 of 28 02164-026 AD7873 time of the 2.5 V reference is typically 10 μs without a load; Acquisition Time however, a 0.1 μF capacitor on the V pin is recommended for REF The track-and-hold amplifier enters tracking mode on the optimum performance because it affects the power-up time (see falling edge of the fifth DCLK after the start bit is detected (see Figure 20). Figure 35). The time required for the track-and-hold amplifier X+ to acquire an input signal depends on how quickly the 37 pF 3-TO-1 ADC Y+ MUX input capacitance is charged. With zero source impedance on the analog input, three DCLK cycles are always sufficient to 260Ω acquire the signal to the 12-bit level. With a source impedance V REF (R ) on the analog input, the actual acquisition time required is IN SW1 calculated using the formula: t = 8.4×(R + 100 Ω)× 37 pF 2.5V ACQ IN BUF REF where RIN is the source impedance of the input signal, and 100 Ω, Figure 27. On-Chip Reference Circuitry 37 pF is the input RC. Depending on the frequency of DCLK used, three DCLK cycles may or may not be sufficient to acquire the analog input signal with various source impedance values. Reference Input Touch Screen Settling The voltage difference between +REF and −REF (see Figure 26) In some applications, external capacitors could be required sets the analog input range. The AD7873 operates with a refer- across the touch screen to filter noise associated with it, for ence input in the range of 1 V to +VCC. Figure 27 shows the example, noise generated by the LCD panel or backlight on-chip reference circuitry on the AD7873. The internal circuitry. The value of these capacitors causes a settling time reference on the AD7873 can be overdriven with an external requirement when the panel is touched. The settling time reference; for best performance, however, the internal reference typically appears as a gain error. There are several methods for should be disabled when an external reference is applied, minimizing or eliminating this issue. The problem can be that because SW1 in Figure 27 opens on the AD7873 when the the input signal, reference, or both, have not settled to their internal reference is disabled. The on-chip reference always is final value before the sampling instant of the ADC. Additionally, available at the VREF pin as long as the reference is enabled. The the reference voltage could still be changing during the conversion input impedance seen at the VREF pin is approximately cycle. One option is to stop or slow down the DCLK for the 260 Ω when the internal reference is enabled. When it is required touch screen settling time. This allows the input and disabled, the input impedance seen at the V pin is in the REF reference to stabilize for the acquisition time, resolving the issue GΩ region. for both single-ended and differential modes. When making touch screen measurements, conversions can be The other option is to operate the AD7873 in differential mode made in differential (ratiometric) mode or single-ended mode. only for the touch screen, and program the AD7873 to keep If the SER/DFR bit is set to 1 in the control register, then a the touch screen drivers on and not go into power-down single-ended conversion is performed. Figure 28 shows the (PD0 = PD1 = 1). Several conversions could be required, configuration for a single-ended Y coordinate measurement. depending on the settling time required and the AD7873 data The X+ input is connected to the analog-to-digital converter, rate. Once the required number of conversions have been made, the Y+ and Y− drivers are turned on, and the voltage on X+ is the AD7873 can then be placed in a power-down state on the digitized. The conversion is performed with the ADC referenced last measurement. The last method is to use the 15-DCLK cycle from GND to VREF. This VREF is either the on-chip reference or mode, maintaining the touch screen drivers on until it is the voltage applied at the VREF pin externally, and is determined commanded by the processor to stop. by the setting of the power management Bit PD0 and Bit PD1 Internal Reference (see Table 7). The advantage of this mode is that the switches that supply the external touch screen can be turned off once the The AD7873 has an internal reference voltage of 2.5 V. The acquisition is complete, resulting in a power savings. However, internal reference is available on the V pin for external use in REF the on resistance of the Y drivers affects the input voltage that the system; however, it must be buffered before it is applied can be acquired. The full touch screen resistance could be in the elsewhere. The on-chip reference can be turned on or off with order of 200 Ω to 900 Ω, depending on the manufacturer. Thus, the power-down address, PD1 = 1 (see Table 8 and Figure 27). if the on resistance of the switches is approximately 6 Ω, true Typically, the reference voltage is only used in single-ended full-scale and zero-scale voltages cannot be acquired, regardless mode for battery monitoring, temperature measurement, and of where the pen/stylus is on the touch screen. Note that the for using the auxiliary input. Optimal touch screen performance minimum touch screen resistance recommended for use with is achieved when using the differential mode. The power-up Rev. E | Page 15 of 28 02164-027 AD7873 the AD7873 is approximately 70 Ω. In this mode of operation, In the single conversion method, a diode voltage is digitized therefore, some voltage is likely to be lost across the internal and recorded at a fixed calibration temperature. Any subsequent switches, and it is unlikely that the internal switch resistance polling of the diode provides an estimate of the ambient tempera- will track the resistance of the touch screen over temperature ture through extrapolation from the calibration temperature and supply, providing an additional source of error. diode result. This assumes a diode temperature drift of approximately –2.1 mV/°C. This method provides a resolution +V CC of approximately 0.3°C and a predicted accuracy of ±3°C. Y+ The differential conversion method is a two-point measurement. V REF The first measurement is performed with a fixed bias current into a diode, and the second measurement is performed with a REF+ X+ IN+ IN+ ADC CORE fixed multiple of the bias current into the same diode. The REF– IN– voltage difference in the diode readings is proportional to Y– absolute temperature and is given by the following formula: ΔV =(kT / q)×(ln N) BE GND Figure 28. Single-Ended Reference Mode (SER/DFR = 1) where: The alternative to this situation is to set the SER/ bit low. DFR VBE represents the diode voltage. Again, making a Y coordinate measurement is considered, but N is the bias current multiple. now the +REF and –REF nodes of the ADC are connected k is Boltzmann’s constant. directly to the Y+ and Y– pins. This means the analog-to-digital q is the electron charge. conversion is ratiometric. The result of the conversion is always This method provides more accurate absolute temperature a percentage of the external resistance, independent of how it measurement of ±2°C. However, the resolution is reduced to could change with respect to the on resistance of the internal approximately 1.6°C. Assuming a current multiple of 105 switches. Figure 29 shows the configuration for a ratiometric (typical for the AD7873) taking Boltzmann’s constant, Y coordinate measurement. –23 k = 1.38054 ×10 electrons volts/degrees Kelvin, the electron +V CC –19 charge q = 1.602189 × 10 , then T, the ambient temperature in degrees centigrade, can be calculated as follows: Y+ ΔV =(kT / q)×(ln N) BE ()() T= ΔV × q / k× ln N BE REF+ X+ IN+ 3 IN+ ADC CORE T(°C)= 2.49× 10 ×ΔV − 273 Κ BE REF– IN– Y– where ΔV is calculated from the difference in readings from BE the first conversion and second conversion. GND Figure 30 shows a block diagram of the temperature DFR Figure 29. Differential Reference Mode (SER/ = 0) measurement mode. The disadvantage of this mode of operation is that during both TEMP0 TEMP1 the acquisition phase and conversion process, the external 105 × I I touch screen must remain powered. This results in additional supply current for the duration of the conversion. MUX ADC MEASUREMENTS Temperature Measurement Two temperature measurement options are available on the Figure 30. Block Diagram of Temperature Measurement Circuit AD7873, the single conversion method and the differential conversion method. Both methods are based on an on-chip diode measurement. Rev. E | Page 16 of 28 02164-029 02164-028 02164-030 AD7873 Battery Measurement Pressure Measurement The AD7873 can monitor a battery voltage from 0 V to 6 V. The pressure applied to the touch screen via a pen or finger Figure 31 shows a block diagram of a battery voltage monitored can also be measured with the AD7873 with some simple through the VBAT pin. The voltage to the +VCC of the AD7873 is calculations. The 8-bit resolution mode would be sufficient for maintained at the desired supply voltage via the dc-to-dc this measurement, but the following calculations are shown regulator while the input to the regulator is monitored. This with the 12-bit resolution mode. The contact resistance between voltage on V is divided by 4 so that a 6 V battery voltage is the X and Y plates is measured, providing a good indication of BAT presented to the ADC as 1.5 V. To conserve power, the divider is the size of the depressed area and the applied pressure. The area on only during the sampling of a voltage on V . Table 6 shows of the spot touched is proportional to the size of the object BAT the control bit settings required to perform a battery touching it. The size of this resistance (RTOUCH) can be calculated measurement. using two different methods. DC/DC The first method requires the user to know the total resistance CONVERTER + BATTERY of the X-plate tablet. Three touch screen conversions are 0V TO 6V required, a measurement of the X-position, Z -position, and 1 +V CC Z -position (see Figure 32). The following equation calculates 2 V BAT 0V TO 1.5V the touch resistance: ADC CORE 7.5kΩ R =(R )×(X / 4095)×[(Z / Z )− 1] 2 1 TOUCH XPLATE POSITION 2.5kΩ The second method requires that the resistance of both the X-plate and Y-plate tablets are known. Again three touch screen conversions are required, a measurement of the X-position, Figure 31. Block Diagram of Battery Measurement Circuit Y-position, and Z -position (see Figure 32). 1 The following equation also calculates the touch resistance: R ={(R / Z )×(X / 4095)×[(4096 / Z )− 1]} TOUCH XPLATE 1 POSITION 1 −[] R ×() Y / 4095 YPLATE POSITION MEASURE X-POSITION X+ Y+ TOUCH + – X-POSITION X– Y– MEASURE Z -POSITION 1 Y+ Y+ X+ X+ TOUCH TOUCH + + – – Z -POSITION Z -POSITION 2 1 X– Y– Y– X– MEASURE Z -POSITION 2 Figure 32. Pressure Measurement Block Diagram Rev. E | Page 17 of 28 02164-031 02164-032 AD7873 PEN INTERRUPT REQUEST Figure 34, then once the conversion is complete, the PENIRQ The pen interrupt equivalent circuitry is outlined in Figure 33. output again responds to a screen touch. The fact that PENIRQ By connecting a pull-up resistor (10 kΩ to 100 kΩ) between +VCC returns high almost immediately after the fourth falling edge of and this CMOS logic open-drain output, the PENIRQ output DCLK means the user avoids any spurious interrupts on the remains high normally. If is enabled (see Table 8), when PENIRQ microprocessor or DSP, which can occur if the interrupt request the touch screen connected to the AD7873 is touched by a pen line on the micro/DSP were unmasked during or toward the or finger, the PENIRQ output goes low, initiating an interrupt to end of conversion and the pin was still low. Once the PENIRQ a microprocessor. This can then instruct a control word to be next start bit is detected by the AD7843, the PENIRQ function written to the AD7873 to initiate a conversion. This output can is again disabled. also be enabled between conversions during power-down (see Table 8), allowing power-up to be initiated only when the If the control register write operation overlaps with the data screen is touched. The result of the first touch screen coordinate read, a start bit is always detected prior to the end of conversion after power-up is valid, assuming any external conversion, meaning that even if the PENIRQ function is reference is settled to the 12-bit or 8-bit level as required. enabled in the control register, it is disabled by the start bit again before the end of the conversion is reached, so the Figure 34 assumes that the PENIRQ function was enabled in function effectively cannot be used in this mode. PENIRQ the last write or that the part was just powered up so PENIRQ is However, as conversions are occurring continuously, the enabled by default. Once the screen is touched, the PENIRQ PENIRQ function is not necessary and is therefore redundant. output goes low a time tPEN later. This delay is approximately 5 μs, assuming a 10 nF touch screen capacitance, and varies +V CC with the touch screen resistance actually used. Once the START EXTERNAL 100kΩ bit is detected, the pen interrupt function is disabled and the PULL-UP cannot respond to screen touches. The PENIRQ PENIRQ PENIRQ Y+ +V CC output remains low until the fourth falling edge of DCLK after the START bit is clocked in, at which point it returns high as soon as possible, irrespective of the touch screen capacitance. X+ TOUCH This does not mean that the pen interrupt function is now PENIRQ SCREEN ENABLE enabled again because the power-down bits have not yet been loaded to the control register. Regardless of whether PENIRQ is Y– ON to be enabled again, the output normally always idles PENIRQ high. Assuming the PENIRQ is enabled again as shown in Figure 33. PENIRQ Functional Block Diagram SCREEN TOUCHED PD1 = 1, PD0 = 0, PENIRQ t HERE PEN NO RESPONSE TO TOUCH ENABLED AGAIN PENIRQ INTERRUPT PROCESSOR CS 1 8 1 13 16 DCLK SER/ MODE SA2 A1 A0 1 0 DFR DIN (START) PENIRQ Figure 34. Timing Diagram Rev. E | Page 18 of 28 02164-034 02164-033 AD7873 CONTROL REGISTER screen. In single-ended mode, the reference voltage to the The control word provided to the ADC via the DIN pin is converter is always the difference between the VREF and GND shown in Table 7. This provides the conversion start, channel pins. See Table 6 and Figure 26 through Figure 29 for further addressing, ADC conversion resolution, configuration, and information. power-down of the AD7873. Table 7 provides detailed information on the order and description of these control bits If X-position, Y-position, and pressure touch are measured in within the control word. single-ended mode, an external reference voltage or +V is CC required for maximum dynamic range. The internal reference Initiate START can be used for these single-ended measurements; however, a The first bit, the S bit, must always be set to 1 to initiate the start loss in dynamic range is incurred. If an external reference is of the control word. The AD7873 ignores any inputs on the used, the AD7873 should also be powered from the external DIN line until the start bit is detected. reference. Because the supply current required by the device is so low, a precision reference can be used as the supply source to Channel Addressing the AD7873. It might also be necessary to power the touch The next three bits in the control register, A2, A1, and A0, select screen from the reference, which can require 5 mA to 10 mA. A the active input channel(s) of the input multiplexer (see Table 6 REF19x voltage reference can source up to 30 mA, and, as such, and Figure 26), touch screen drivers, and the reference inputs. could supply both the ADC and the touch screen. Care must be Mode taken, however, to ensure that the input voltage applied to the ADC does not exceed the reference voltage and therefore the The MODE bit sets the resolution of the analog-to-digital supply voltage. See the Absolute Maximum Ratings section. converter. With a 0 in this bit, the following conversion has 12 bits of resolution. With a 1 in this bit, the following Note that the differential mode can only be used for X-position, conversion has eight bits of resolution. Y-position, and pressure touch measurements. All other measurements require single-ended mode. SER/ DFR The SER/DFR bit controls the reference mode, set to either PD0 and PD1 single-ended or differential when a 1 or a 0 is written to this bit, The power management options are selected by programming respectively. The differential mode is also referred to as the the power management bits, PD0 and PD1, in the control ratiometric conversion mode. This mode is optimum for register. Table 8 summarizes the options available and the X-position, Y-position, and pressure-touch measurements. The internal reference voltage configurations. The internal reference reference is derived from the voltage at the switch drivers, can be turned on or off independent of the analog-to-digital which is almost the same as the voltage to the touch screen. In converter, allowing power saving between conversions using the this case, a separate reference voltage is not needed because the power management options. On power-up, PD0 defaults to 0, reference voltage to the ADC is the voltage across the touch while PD1 defaults to 1. MSB LSB S A2 A1 A0 MODE SER/DFR PD1 PD0 Table 7. Control Register Bit Function Description Bit No. Mnemonic Comment 7 S Start Bit. The control word starts with the first high bit on DIN. A new control word can start every 15th DCLK cycle when in the 12-bit conversion mode or every 11th DCLK cycle when in 8-bit conversion mode. 6 to 4 A2 to A0 Channel Select Bits. These three address bits along with the SER/DFR bit control the setting of the multiplexer input, switches, and reference inputs, as detailed in Table 6. 3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the resolution of the following conversion. With a 0 in this bit, the conversion has 12-bit resolution or, with a 1 in this bit, 8-bit resolution. 2 SER/DFR Single-Ended/Differential Reference Select Bit. Together with Bit A2 to Bit A0, this bit controls the setting of the multiplexer input, switches, and reference inputs as described in Table 6. 1, 0 PD1, PD0 Power Management Bits. These two bits decode the power-down mode of the AD7873 as shown in Table 8. Rev. E | Page 19 of 28 AD7873 Table 8. Power Management Options PENIRQ PD1 PD0 Description 0 0 Enabled This configuration results in immediate power-down of the on-chip reference as soon as PD1 is set to 0. The ADC powers down only between conversions. When PD0 is set to 0, the conversion is performed first and the ADC powers down upon completion of that conversion (or upon the rising edge of CS, if it occurs first). At the start of the next conversion, the ADC instantly powers up to full power. This means if the device is being used in the differential mode, or an external reference is used, there is no need for additional delays to ensure full operation and the very first conversion is valid. The Y– switch is on while in power-down. When the device is performing differential table conversions, the reference and reference buffer do not attempt to power up with Bit PD1 and Bit PD0 programmed in this way. 0 1 Enabled This configuration results in switching the reference off immediately and the ADC on permanently. When the device is performing differential tablet conversions, the reference and reference buffer do not attempt to power up with Bit PD1 and Bit PD0 programmed in this way. 1 0 Enabled This configuration results in switching the reference on and powering the ADC down between conversions. The ADC powers down only between conversions. When PD0 is set to 0, the conversion is performed first, and the ADC powers down upon completion of the conversion (or upon the rising edge of CS if it occurs first). At the start of the next conversion, the ADC instantly powers up to full power. There is no need for additional delays to ensure full operation as the reference remains permanently powered up. 1 1 Disabled This configuration results in always keeping the device powered up. The reference and the ADC are on. For example, if the AD7873 is operated in a 24-DCLK continuous POWER VS. THROUGHPUT RATE sampling mode, with a throughput rate of 10 kSPS and a DCLK By using the power-down options on the AD7873 when not of 2 MHz, and the device is placed in the power-down mode converting, the average power consumption of the device between conversions, (PD0, PD1 = 0, 0), that is, the ADC shuts decreases at lower throughput rates. Figure 35 shows how, as the down between conversions but the reference remains powered throughput rate is reduced while maintaining the DCLK down permanently, then the current consumption is calculated frequency at 2 MHz, the device remains in its power-down state as follows. The current consumption during normal operation longer and the average current consumption over time drops with a 2 MHz DCLK is 210 μA (VCC = 2.7 V). Assuming an accordingly. external reference is used, the power-up time of the ADC is 1000 instantaneous, so when the part is converting, it consumes 210 μA. In this mode of operation, the part powers up on the f =16×f DCLK SAMPLE fourth falling edge of DCLK after the start bit is recognized. It goes back into power-down at the end of conversion on the 100 20th falling edge of DCLK, meaning that the part consumes 210 μA for 16 DCLK cycles only, 8 μs during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 μs f =2MHz and the average power dissipated during each cycle is DCLK 10 (8/100) × (210 μA) = 16.8 μA. V =2.7V CC T = –40°C TO +85°C A 1 02 0 0 40 60 80 100 120 THROUGHPUT (kSPS) Figure 35. Supply Current vs. Throughput (μA) Rev. E | Page 20 of 28 SUPPLY CURRENT (µA) 02164-035 AD7873 SERIAL INTERFACE updated) and the converter enters conversion mode. At this Figure 36 shows the typical operation of the serial interface of point, track-and-hold goes into hold mode, the input signal is the AD7873. The serial clock provides the conversion clock and sampled, and the BUSY output goes high (BUSY returns low on also controls the transfer of information to and from the AD7873. the next falling edge of DCLK). The internal switches can also One complete conversion can be achieved with 24 DCLK cycles. turn off at this point if in single-ended mode, battery-monitor The signal initiates the data transfer and conversion process. mode, or temperature measurement mode. CS The falling edge of CS takes the BUSY output and the serial bus The next 12 DCLK cycles are used to perform the conversion out of three-state. The first eight DCLK cycles are used to write and to clock out the conversion result. If the conversion is to the control register via the DIN pin. The control register is ratiometric (SER/DFR low), the internal switches are on during updated in stages as each bit is clocked in. Once the converter the conversion. A 13th DCLK cycle is needed to allow the has enough information about the following conversion to set DSP/micro to clock in the LSB. Three more DCLK cycles clock the input multiplexer and switches appropriately, the converter out the three trailing zeros and complete the 24 DCLK transfer. enters the acquisition mode and, if required, the internal switches The 24 DCLK cycles can be provided from a DSP or via three are turned on. During acquisition mode, the reference input bursts of eight clock cycles from a microcontroller. data is updated. After the three DCLK cycles of acquisition, the control word is complete (the power management bits are now CS t ACQ DCLK18 1 8 1 8 SER/ SA2 A1 A0 MODE PD1PD0 DIN DFR (START) IDLE ACQUIRE CONVERSION IDLE THREE-STATE THREE-STATE BUSY THREE-STATE THREE-STATE DOUT 11 10 9 8 7 6 5 4 3 2 1 0 ZERO FILLED (MSB) (LSB) 1 X/Y SWITCHES OFF OFF ON (SER/DFR HIGH) 1, 2 X/Y SWITCHES OFF OFF ON (SER/DFR LOW) NOTES 1 Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 101). WHEN PD1, PD0 = 00, 01 OR 10, Y– WILL TURN ON AT THE END OF THE CONVERSION. 2 DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE, OR POWER-DOWN MODE IS CHANGED, OR CS IS HIGH. Figure 36. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. CS t t t t 9 t 4 6 6 1 t t 10 5 DCLK t 8 t 7 PD0 DIN t 2 t 11 BUSY t 12 t 3 DOUT DB11 DB10 Figure 37. Detail Timing Diagram Rev. E | Page 21 of 28 02164-037 02164-036 AD7873 using 12 DCLKs to perform the conversion and 3 DCLKs to 16 Clocks per Cycle acquire the analog input. This effectively increases the The control bits for the next conversion can be overlapped with throughput rate of the AD7873 beyond that used for the the current conversion to allow for a conversion every 16 DCLK specifications that are tested using 16 DCLKs per cycle, and cycles, as shown in Figure 38. This timing diagram also allows DCLK = 2 MHz. the possibility of communication with other serial peripherals between each byte (eight DCLKs) transfer between the 8-Bit Conversion processor and the converter. However, the conversion must The AD7873 can be set up to operate in an 8-bit mode rather complete within a short enough time frame to avoid capacitive than a 12-bit mode by setting the MODE bit in the control droop effects that could distort the conversion result. It should register to 1. This mode allows a faster throughput rate to be also be noted that the AD7873 is fully powered while other achieved, assuming 8-bit resolution is sufficient. When using 8-bit serial communications are taking place between byte transfers. mode, a conversion is complete four clock cycles earlier than in 12-bit mode. This can be used with serial interfaces that provide 15 Clocks per Cycle 12 clock transfers, or two conversions can be completed with Figure 39 shows the fastest way to clock the AD7873. This three 8-clock transfers. The throughput rate increases by 25% as scheme does not work with most microcontrollers or DSPs a result of the shorter conversion cycle, but the conversion itself because they are not capable of generating a 15 clock cycle per can occur at a faster clock rate because the internal settling time serial transfer. However, some DSPs allow the number of clocks of the AD7873 is not as critical, because settling to eight bits is per cycle to be programmed. This method can also be used with all that is required. The clock rate can be as much as 50% faster. FPGAs (field programmable gate arrays) or ASICs (application The faster clock rate and fewer clock cycles combine to provide specific integrated circuits). As in the 16 clocks per cycle case, double the conversion rate. the control bits for the next conversion are overlapped with the current conversion to allow a conversion every 15 DCLK cycles CS 1 8811 8 1 DCLK S S DIN CONTROL BITS CONTROL BITS BUSY 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 DOUT Figure 38. Conversion Timing, 16 DCLKs per Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. CS DCLK 1 15 1 15 1 SER/ SER/ DIN SA2 A1 A0 MODE PD1PD0 SA2 A1 A0 MODE PD1 PD0 SA2 DFR DFR BUSY 11 10 98 7 6 54 3 2 1 0 11 10 9 8 76 5 4 DOUT Figure 39. Conversion Timing, 15 DCLKs per Cycle, Maximum Throughput Rate Rev. E | Page 22 of 28 02164-038 02164-039 AD7873 GROUNDING AND LAYOUT should be a clearance of at least 0.25 mm between the thermal For information on grounding and layout considerations for the pad and the inner edges of the pad pattern. This ensures that AD7873, refer to Application Note AN-577, Layout and shorting is avoided. Grounding Recommendations for Touch Screen Digitizers. Thermal vias can be used on the printed circuit board thermal PCB DESIGN GUIDELINES FOR pad to improve thermal performance of the package. If vias are CHIP SCALE PACKAGE used, they should be incorporated in the thermal pad at 1.2 mm The lands on the chip scale package (CP-32) are rectangular. pitch grid. The via diameter should be between 0.3 mm and The printed circuit board pad for these should be 0.1 mm 0.33 mm and the via barrel should be plated with 1 oz. copper longer than the package land length and 0.05 mm wider than to plug the via. the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The user should connect the printed circuit board thermal pad to GND. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there Rev. E | Page 23 of 28 2.25 2.10 SQ 1.95 AD7873 OUTLINE DIMENSIONS 5.10 0.197 5.00 0.193 4.90 0.189 16 9 16 9 4.50 0.158 6.40 4.40 BSC 0.154 4.30 0.244 0.150 1 0.236 8 1 8 0.228 PIN 1 PIN 1 1.20 MAX 0.069 0.065 0.15 0.20 0.053 0.049 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 8° 0.45 0.19 SEATING 0.010 BSC 0.025 0° PLANE 0.012 0.050 0.004 SEATING 0.010 BSC COPLANARITY 0.008 0.016 PLANE COPLANARITY 0.006 0.10 0.004 COMPLIANT TO JEDEC STANDARDS MO-153-AB COMPLIANT TO JEDEC STANDARDS MO-137-AB Figure 40. 16-Lead Shrink Small Outline Package [QSOP] Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RQ-16) (RU-16) Dimensions shown in inches Dimensions shown in millimeters 4.00 0.60 MAX BSC SQ (BOTTOM VIEW) 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC INDICATOR TOP 3.75 EXPOSED VIEW BSC SQ PAD 0.75 9 0.60 4 8 5 0.50 0.25 MIN 1.95 BSC 0.80 MAX 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.35 0.80 0.20 REF 0.30 COPLANARITY SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 42. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters Rev. E | Page 24 of 28 010606-0 AD7873 ORDERING GUIDE 1 2 Model Temperature Range Package Description Linearity Error (LSB) Package Option AD7873ARQ –40°C to +85°C 16-Lead QSOP ±2 RQ-16 AD7873ARQ-REEL –40°C to +85°C 16-Lead QSOP ±2 RQ-16 AD7873ARQ-REEL7 –40°C to +85°C 16-Lead QSOP ±2 RQ-16 3 AD7873ARQZ –40°C to +85°C 16-Lead QSOP ±2 RQ-16 3 AD7873ARQZ-REEL –40°C to +85°C 16-Lead QSOP ±2 RQ-16 3 AD7873ARQZ-REEL7 –40°C to +85°C 16-Lead QSOP ±2 RQ-16 AD7873BRQ –40°C to +85°C 16-Lead QSOP ±1 RQ-16 AD7873BRQ-REEL –40°C to +85°C 16-Lead QSOP ±1 RQ-16 AD7873BRQ-REEL7 –40°C to +85°C 16-Lead QSOP ±1 RQ-16 3 AD7873BRQZ –40°C to +85°C 16-Lead QSOP ±1 RQ-16 3 AD7873BRQZ-REEL –40°C to +85°C 16-Lead QSOP ±1 RQ-16 3 AD7873BRQZ-REEL7 –40°C to +85°C 16-Lead QSOP ±1 RQ-16 AD7873ARU –40°C to +85°C 16-Lead TSSOP ±2 RU-16 AD7873ARU-REEL –40°C to +85°C 16-Lead TSSOP ±2 RU-16 AD7873ARU-REEL7 –40°C to +85°C 16-Lead TSSOP ±2 RU-16 3 AD7873ARUZ –40°C to +85°C 16-Lead TSSOP ±2 RU-16 3 AD7873ARUZ-REEL –40°C to +85°C 16-Lead TSSOP ±2 RU-16 3 AD7873ARUZ-REEL7 –40°C to +85°C 16-Lead TSSOP ±2 RU-16 AD7873ACP –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 AD7873ACP-REEL –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 AD7873ACP-REEL7 –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 3 AD7873ACPZ –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 3 AD7873ACPZ-REEL –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 3 AD7873ACPZ-REEL7 –40°C to +85°C 16-Lead LFCSP_VQ ±2 CP-16-4 AD7873BCP –40°C to +85°C 16-Lead LFCSP_VQ ±1 CP-16-4 AD7873BCP-REEL –40°C to +85°C 16-Lead LFCSP_VQ ±1 CP-16-4 AD7873BCP-REEL7 –40°C to +85°C 16-Lead LFCSP_VQ ±1 CP-16-4 3 AD7873BCPZ –40°C to +85°C 16-Lead LFCSP_VQ ±1 CP-16-4 3 AD7873BCPZ-REEL7 –40°C to +85°C 16-Lead LFCSP_VQ ±1 CP-16-4 4 EVAL-AD7873CB Evaluation Board 5 EVAL-CONTROL BRD2 Controller Board 1 Linearity error here refers to integral linearity error. 2 RQ = QSOP = 0.15” quarter size outline package; RU = TSSOP, CP = LFCSP. 3 Z = Pb-free part. 4 This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. 5 This evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators. Rev. E | Page 25 of 28 AD7873 NOTES Rev. E | Page 26 of 28 AD7873 NOTES Rev. E | Page 27 of 28 AD7873 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02164-0-9/06(E) TTTT Rev. E | Page 28 of 28