ANALOG DEVICES AD7863

Simultaneous Sampling Dual 175 kSPS 14-Bit ADC AD7863 FEATURES FUNCTIONAL BLOCK DIAGRAM Two fast 14-bit ADCs V V REF DD Four input channels 2kΩ 2.5V Simultaneous sampling and conversion REFERENCE 5.2 μs conversion time AD7863 Single supply operation Selection of input ranges SIGNAL TRACK/ V A1 SCALING HOLD ±10 V for AD7863-10 14-BIT MUX ADC SIGNAL ±2.5 V for AD7863-3 V B1 DB0 SCALING OUTPUT 0 V to 2.5 V for AD7863-2 LATCH TRACK/ SIGNAL DB13 High speed parallel interface V A2 HOLD SCALING 14-BIT MUX ADC Low power, 70 mW typical SIGNAL V CS B2 SCALING Power saving mode, 105 μW maximum RD Overvoltage protection on analog inputs CONVERSION CLOCK 14-bit lead compatible upgrade to AD7862 CONTROL LOGIC GENERAL DESCRIPTION A0 BUSY AGND AGND DGND CONVST Figure 1. The AD7863 is a high speed, low power, dual 14-bit analog-to- digital converter that operates from a single 5 V supply. process that combines precision bipolar circuits with low power The part contains two 5.2 μs successive approximation ADCs, two CMOS logic. It is available in 28-lead SOIC_W and SSOP. track/hold amplifiers, an internal 2.5 V reference and a high speed parallel interface. Four analog inputs are grouped into two channels PRODUCT HIGHLIGHTS (A and B) selected by the A0 input. Each channel has two inputs 1. The AD7863 features two complete ADC functions (VA1 and VA2 or VB1 and VB2) that can be sampled and converted allowing simultaneous sampling and conversion of two simultaneously, thus preserving the relative phase information of channels. Each ADC has a two-channel input mux. The the signals on both analog inputs. The part accepts an analog input conversion result for both channels is available 5.2 μs after range of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to initiating conversion. 2.5 V (AD7863-2). Overvoltage protection on the analog inputs 2. The AD7863 operates from a single 5 V supply and for the part allows the input voltage to go to ±17 V, ±7 V, or +7 V consumes 70 mW typical. The automatic power-down respectively, without causing damage. mode, where the part goes into power-down once conversion is complete and wakes up before the next A single conversion start signal (CONVST) simultaneously places conversion cycle, makes the AD7863 ideal for battery- both track/holds into hold and initiates conversion on both powered or portable applications. channels. The BUSY signal indicates the end of conversion and at 3. The part offers a high speed parallel interface for easy this time the conversion results for both channels are available to be connection to microprocessors, microcontrollers, and read. The first read after a conversion accesses the result from V A1 digital signal processors. or V , and the second read accesses the result from V or V , B1 A2 B2 4. The part is offered in three versions with different analog depending on whether the multiplexer select (A0) is low or high, input ranges. The AD7863-10 offers the standard industrial respectively. Data is read from the part via a 14-bit parallel data bus input range of ±10 V; the AD7863-3 offers the common with standard CS and RD signals. In addition to the traditional dc signal processing input range of ±2.5 V, while the AD7863-2 accuracy specifications such as linearity, gain, and offset errors, the can be used in unipolar 0 V to 2.5 V applications. part is also specified for dynamic performance parameters 5. The part features very tight aperture delay matching including harmonic distortion and signal-to-noise ratio. between the two input sample and hold amplifiers. The AD7863 is fabricated in the Analog Devices, Inc. linear 2 compatible CMOS (LC MOS) process, a mixed technology Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06411-001 AD7863 TABLE OF CONTENTS Features .............................................................................................. 1 Effective Number of Bits ........................................................... 14 General Description ......................................................................... 1 Total Harmonic Distortion (THD).......................................... 15 Functional Block Diagram .............................................................. 1 Intermodulation Distortion ...................................................... 15 Product Highlights ........................................................................... 1 Peak Harmonic or Spurious Noise........................................... 15 Revision History ............................................................................... 2 DC Linearity Plot ....................................................................... 15 Specifications..................................................................................... 3 Power Considerations................................................................ 16 Timing Characteristics ................................................................ 5 Microprocessor Interfacing........................................................... 17 Absolute Maximum Ratings............................................................ 6 AD7863 to ADSP-2100 Interface ............................................. 17 ESD Caution.................................................................................. 6 AD7863 to ADSP-2101/ADSP-2102 Interface ....................... 17 Pin Configuration and Function Descriptions............................. 7 AD7863 to TMS32010 Interface .............................................. 17 Terminology ...................................................................................... 8 AD7863 to TMS320C25 Interface............................................ 17 Converter Details.............................................................................. 9 AD7863 to MC68000 Interface ................................................ 18 Track-and-Hold Section .............................................................. 9 AD7863 to 80C196 Interface .................................................... 18 Reference Section ......................................................................... 9 Vector Motor Control ................................................................ 18 Circuit Description......................................................................... 10 Multiple AD7863s ...................................................................... 19 Analog Input Section ................................................................. 10 Applications Hints.......................................................................... 20 Offset and Full-Scale Adjustment ............................................ 10 PC Board Layout Considerations............................................. 20 Timing and Control ................................................................... 11 Ground Planes ............................................................................ 20 Operating Modes ............................................................................ 13 Power Planes ............................................................................... 20 Mode 1 Operation ...................................................................... 13 Supply Decoupling ..................................................................... 20 Mode 2 Operation ...................................................................... 13 Outline Dimensions....................................................................... 21 AD7863 Dynamic Specifications ............................................. 14 Ordering Guide .......................................................................... 22 Signal-to-Noise Ratio (SNR)..................................................... 14 REVISION HISTORY 11/06—Rev. A to Rev. B Updated Format..................................................................Universal Deleted Applications ........................................................................ 1 Changes to Specifications................................................................ 3 Changes to Absolute Maximum Ratings ....................................... 6 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 5/99—Rev. 0 to Rev. A Rev. B | Page 2 of 24 AD7863 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 Parameter A Version B Version Unit Test Conditions/Comments SAMPLE AND HOLD −3 dB Small Signal Bandwidth 7 7 MHz typ 2 Aperture Delay 35 35 ns max 2 Aperture Jitter 50 50 ps typ 2 Aperture Delay Matching 350 350 ps max 3 DYNAMIC PERFORMANCE fIN = 80.0 kHz, fS = 175 kSPS 4 Signal-to-(Noise + Distortion) Ratio @ 25°C 78 78 dB min T to T 77 77 dB min MIN MAX 4 Total Harmonic Distortion −82 −82 dB max −87 dB typ 4 Peak Harmonic or Spurious Noise −82 −82 dB max −90 dB typ 4 Intermodulation Distortion fa = 49 kHz, fb = 50 kHz Second Order Terms −93 −93 dB typ Third Order Terms −89 −89 dB typ 4 Channel-to-Channel Isolation −86 −86 dB typ f = 50 kHz sine wave IN DC ACCURACY Any channel Resolution 14 14 Bits Minimum Resolution for Which No Missing Codes are Guaranteed 14 14 Bits 4 Relative Accuracy ±2.5 ±2 LSB max 4 Differential Nonlinearity +2 to −1 +2 to −1 LSB max AD7863-10, AD7863-3 4 Positive Gain Error ±10 ±8 LSB max 4 Positive Gain Error Match 10 10 LSB max 4 Negative Gain Error ±10 ±8 LSB max 4 Negative Gain Error Match 10 10 LSB max Bipolar Zero Error ±10 ±8 LSB max Bipolar Zero Error Match 8 6 LSB max AD7863-2 4 Positive Gain Error ±14 LSB max 4 Positive Gain Error Match 16 LSB max Unipolar Offset Error ±14 LSB max Unipolar Offset Error Match 10 LSB max ANALOG INPUTS AD7863-10 Input Voltage Range ±10 ±10 V Input Resistance 9 9 kΩ typ AD7863-3 Input Voltage Range ±2.5 ±2.5 V Input Resistance 3 3 kΩ typ AD7863-2 Input Voltage Range 2.5 2.5 V Input Current 100 100 nA max Rev. B | Page 3 of 24 AD7863 1 1 Parameter A Version B Version Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT REF IN Input Voltage Range 2.375 to 2.625 2.375 to 2.625 V 2.5 V ± 5% REF IN Input Current ±100 ±100 μA max REF OUT Output Voltage 2.5 2.5 V nom REF OUT Error @ 25°C ±10 ±10 mV max REF OUT Error T to T ±20 ±20 mV max MIN MAX REF OUT Temperature Coefficient 25 25 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 μA max 5 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 V min ISOURCE = 200 μA Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK DB11 to DB0 Floating-State Leakage Current ±10 ±10 μA max 5 Floating-State Capacitance 10 10 pF max Output Coding AD7863-10, AD7863-3 Twos complement AD7863-2 Straight (natural) binary CONVERSION RATE Conversion Time Mode 1 Operation 5.2 5.2 μs max For both channels 6 Mode 2 Operation 10.0 10.0 μs max For both channels 4, 7 Track/Hold Acquisition Time 0.5 0.5 μs max POWER REQUIREMENTS V 5 5 V nom ±5% for specified performance DD IDD Normal Mode (Mode 1) AD7863-10 18 18 mA max AD7863-3 16 16 mA max AD7863-2 11 11 mA max Power-Down Mode (Mode 2) 8 IDD @ 25°C 20 20 μA max 40 nA typ. Logic inputs = 0 V or VDD Power Dissipation Normal Mode (Mode 1) AD7863-10 94.50 94.50 mW max V = 5.25 V, 70 mW typ DD AD7863-3 84 84 mW max V = 5.25 V, 70 mW typ DD AD7863-2 57.75 57.75 mW max VDD = 5.25 V, 45 mW typ Power-Down Mode @ 25°C 105 105 μW max 210 nW typ, VDD = 5.25 V 1 Temperature ranges are as follows: A Version and B Version, −40°C to +85°C. 2 Sample tested during initial release. 3 Applies to Mode 1 operation. See Operating Modes section. 4 See Terminology section. 5 Sample tested @ 25°C to ensure compliance. 6 CONVST This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of , whereas conversion is timed from the falling edge of CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if CONVST the pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs. 7 Performance measured through full channel (multiplexer, SHA, and ADC). 8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the V pin and DD 2 × 0.1 μF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane. Rev. B | Page 4 of 24 AD7863 TIMING CHARACTERISTICS VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1, 2 Parameter A, B Versions Unit Test Conditions/Comments t 5.2 μs max Conversion time CONV tACQ 0.5 μs max Acquisition time Parallel Interface t1 0 ns min CS to RD setup time t 0 ns min CS to RD hold time 2 t 35 ns min CONVST pulse width 3 t4 45 ns min RD pulse width 3 t5 30 ns min Data access time after falling edge of RD 4 t6 5 ns min Bus relinquish time after rising edge of RD 30 ns max t 10 ns min Time between consecutive reads 7 t 400 ns min Quiet time 8 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. t ACQ t 8 CONVST t 3 BUSY t = 5.2µs CONV A0 CS t t t 1 2 7 t 4 RD t t 5 6 V V V V DATA A1 A2 B1 B2 Figure 2. Timing Diagram 1.6mA TO OUTPUT PIN 50pF 200µA Figure 3. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 5 of 24 06411-003 06411-002 AD7863 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Ratings rating only; functional operation of the device at these or any V to AGND −0.3 V to +7 V DD other conditions above those indicated in the operational V to DGND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Analog Input Voltage to AGND maximum rating conditions for extended periods may affect AD7863-10 ±17 V device reliability. AD7863-3 ±7 V AD7863-2 7 V ESD CAUTION Reference Input Voltage to AGND −0.3 V to V + 0.3 V DD Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A Version and B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOIC Package, Power Dissipation 450 mW θJA Thermal Impedance 71.40°C/W θJC Thermal Impedance 23.0°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C SSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 109°C/W θ Thermal Impedance 39.0°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. B | Page 6 of 24 AD7863 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB12 1 DB13 28 DB11 2 AGND 27 DB10 3 V 26 B1 DB9 4 V 25 A1 DB8 5 V 24 DD DB7 6 BUSY 23 AD7863 DGND 7 22 RD TOP VIEW (Not to Scale) 8 CONVST 21 CS DB6 9 A0 20 DB5 10 V 19 REF DB4 11 V 18 A2 DB3 12 17 V B2 DB2 13 16 AGND DB1 14 15 DB0 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 to 6 DB12 to DB7 Data Bit 12 to Data Bit 7. Three-state TTL outputs. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 CONVST Convert Start Input. Logic input. A high-to-low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. 9 to 15 DB6 to DB0 Data Bit 6 to Data Bit 0. Three-state TTL outputs. 16 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 17 VB2 Input Number 2 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 18 V Input Number 2 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to A2 2.5 V (AD7863-2). 19 VREF Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. 20 A0 Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels the conversion is to be performed. If A0 is low when the conversion is initiated, then channels V and V are A1 A2 selected. If A0 is high when the conversion is initiated, channels V and V are selected. B1 B2 21 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 22 RD Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data outputs and read a conversion result from the AD7863. 23 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. 24 VDD Analog and Digital Positive Supply Voltage, 5.0 V ± 5%. 25 VA1 Input Number 1 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 26 VB1 Input Number 1 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 27 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 28 DB13 Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and AD7863-3. Output coding is straight (natural) binary for the AD7863-2. Rev. B | Page 7 of 24 06411-004 AD7863 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Channel-to-Channel Isolation This is the measured ratio of signal to (noise + distortion) at the Channel-to-channel isolation is a measure of the level of output of the analog-to-digital converter. The signal is the rms crosstalk between channels. It is measured by applying a full- amplitude of the fundamental. Noise is the rms sum of all non- scale 50 kHz sine wave signal to all nonselected channels and fundamental signals up to half the sampling frequency (f /2), determining how much that signal is attenuated in the selected S excluding dc. The ratio is dependent upon the number of channel. The figure given is the worst case across all channels. quantization levels in the digitization process; the more levels, Relative Accuracy the smaller the quantization noise. The theoretical signal-to- Relative accuracy or endpoint nonlinearity is the maximum (noise + distortion) ratio for an ideal N-bit converter with a sine deviation from a straight line passing through the endpoints of wave input is given by the ADC transfer function. Signal to (Noise + Distortion) = (6.02N + 1.76) dB Differential Nonlinearity For a 14-bit converter, this is 86.04 dB. This is the difference between the measured and the ideal 1 LSB Total Harmonic Distortion change between any two adjacent codes in the ADC. Total harmonic distortion (THD) is the ratio of the rms sum of Positive Gain Error (AD7863-10, ±10 V, AD7863-3, ±2.5 V) harmonics to the fundamental. For the AD7863 it is defined as This is the deviation of the last code transition (01 . . . 110 to 2 2 2 2 − 1 LSB (AD7863-10, ±10 V 01 . . . 111) from the ideal 4 × VREF V +V +V +V 2 3 4 5 () THD dB = 20 log range) or VREF − 1 LSB (AD7863-3, ±2.5 V range), after the V 1 bipolar offset error has been adjusted out. where: Positive Gain Error (AD7863-2, 0 V to 2.5 V) V1 is the rms amplitude of the fundamental. This is the deviation of the last code transition (11 . . . 110 to V , V , V , and V are the rms amplitudes of the second through 2 3 4 5 11 . . . 111) from the ideal V − 1 LSB, after the unipolar offset REF the fifth harmonics. error has been adjusted out. Peak Harmonic or Spurious Noise Bipolar Zero Error (AD7863-10, ±10 V, AD7863-3, ±2.5 V) Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the midscale transition (all 0s to all 1s) rms value of the next largest component in the ADC output from the ideal 0 V (AGND). spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is Unipolar Offset Error (AD7863-2, 0 V to 2.5 V) determined by the largest harmonic in the spectrum, but for This is the deviation of the first code transition (00 . . . 000 to parts where the harmonics are buried in the noise floor, it is 00 . . . 001) from the ideal AGND + 1 LSB. a noise peak. Negative Gain Error (AD7863-10, ±10 V, AD7863-3, ±2.5 V) Intermodulation Distortion This is the deviation of the first code transition (10 . . . 000 to With inputs consisting of sine waves at two frequencies, fa and 10 . . . 001) from the ideal −4 × V + 1 LSB (AD7863-10, ±10 V REF fb, any active device with nonlinearities creates distortion range) or –VREF + 1 LSB (AD7863-3, ±2.5 V range), after bipolar products at sum and difference frequencies of mfa ± nfb where zero error has been adjusted out. m, n = 0, 1, 2, 3. Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second order Track-and-Hold Acquisition Time terms include (fa + fb) and (fa − fb), and the third order terms Track-and-hold acquisition time is the time required for the include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). output of the track/hold amplifier to reach its final value, with ±½ LSB, after the end of conversion (the point at which the The AD7863 is tested using two input frequencies. In this case, track-and-hold returns to track mode). It also applies to the second and third order terms are of different significance. situations where a change in the selected input channel takes The second order terms are usually distanced in frequency from place or where there is a step input change on the input voltage the original sine waves, and the third order terms are usually at applied to the selected VAX/BX input of the AD7863. It means a frequency close to the input frequencies. As a result, the that the user must wait for the duration of the track-and-hold second and third order terms are specified separately. The acquisition time after the end of conversion or after a channel calculation of the intermodulation distortion is as per the THD change/step input change to V before starting another AX/BX specification where it is the ratio of the rms sum of the conversion, to ensure that the part operates to specification. individual distortion products to the rms amplitude of the fundamental, expressed in decibels (dB). Rev. B | Page 8 of 24 AD7863 CONVERTER DETAILS The AD7863 is a high speed, low power, dual 14-bit analog-to- The track-and-hold amplifiers acquire input signals to 14-bit digital converter that operates from a single 5 V supply. The accuracy in less than 500 ns. The operation of the track-and- part contains two 5.2 μs successive approximation ADCs, two holds is essentially transparent to the user. The two track-and-hold track-and-hold amplifiers, an internal 2.5 V reference, and a amplifiers sample their respective input channels simultaneously, high speed parallel interface. Four analog inputs are grouped CONVST on the falling edge of . The aperture time for the into two channels (A and B) selected by the A0 input. Each track-and-holds (that is, the delay time between the external channel has two inputs (V and V or V and V ) that can be A1 A2 B1 B2 CONVST signal and the track-and-hold actually going into sampled and converted simultaneously, thus preserving the hold) is well-matched across the two track-and-holds on one relative phase information of the signals on both analog inputs. device and also well-matched from device to device. This allows The part accepts an analog input range of ±10 V (AD7863-10), the relative phase information between different input channels ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage to be accurately preserved. It also allows multiple AD7863s to protection on the analog inputs for the part allows the input simultaneously sample more than two channels. At the end of voltage to go to ±17 V, ±7 V, or +7 V, respectively, without conversion, the part returns to its tracking mode. The acquisition causing damage. The AD7863 has two operating modes, the high time of the track-and-hold amplifiers begins at this point. sampling mode and the auto sleep mode, where the part auto- REFERENCE SECTION matically goes into sleep after the end of conversion. These modes are discussed in more detail in the Timing and Control section. The AD7863 contains a single reference pin, labeled VREF, that provides access to the part’s own 2.5 V reference. Alternatively, Conversion is initiated on the AD7863 by pulsing the CONVST an external 2.5 V reference can be connected to this pin, thus input. On the falling edge of CONVST, both on-chip track-and- providing the reference source for the part. The part is specified holds are simultaneously placed into hold and the conversion with a 2.5 V reference voltage. Errors in the reference source sequence is started on both channels. The conversion clock for result in gain errors in the AD7863 transfer function and add to the part is generated internally using a laser-trimmed clock the specified full-scale errors on the part. On the AD7863-10 oscillator circuit. The BUSY signal indicates the end of and AD7863-3, it also results in an offset error injected in the conversion and at this time the conversion results for both attenuator stage. channels are available to be read. The first read after a conver- The AD7863 contains an on-chip 2.5 V reference. To use this sion accesses the result from VA1 or VB1, and the second read reference as the reference source for the AD7863, connect two accesses the result from VA2 or VB2, depending on whether the 0.1 μF disc ceramic capacitors from the V pin to AGND. The multiplexer select A0 is low or high, respectively, before the REF conversion is initiated. Data is read from the part via a 14-bit voltage that appears at this pin is internally buffered before CS RD being applied to the ADC. If this reference is required for use parallel data bus with standard and signals. external to the AD7863, it should be buffered because the part Conversion time for the AD7863 is 5.2 μs in the high sampling has a FET switch in series with the reference output resulting in mode (10 μs for the auto sleep mode), and the track/hold a source impedance for this output of 5.5 kΩ nominal. The acquisition time is 0.5 μs. To obtain optimum performance tolerance on the internal reference is ±10 mV at 25°C with a from the part, the read operation should not occur during the typical temperature coefficient of 25 ppm/°C and a maximum conversion or during the 400 ns prior to the next conversion. error over temperature of ±25 mV. This allows the part to operate at throughput rates up to 175 kHz If the application requires a reference with a tighter tolerance or and achieve data sheet specifications. the AD7863 needs to be used with a system reference, the user TRACK-AND-HOLD SECTION has the option of connecting an external reference to this VREF pin. The external reference effectively overdrives the internal The track-and-hold amplifiers on the AD7863 allow the ADCs reference and thus provides the reference source for the ADC. to accurately convert an input sine wave of full-scale amplitude The reference input is buffered before being applied to the ADC to 14-bit accuracy. The input bandwidth of the track-and-hold with a maximum input current of ±100 μA. A suitable reference is greater than the Nyquist rate of the ADC, even when the source for the AD7863 is the AD780 precision 2.5 V reference. ADC is operated at its maximum throughput rate of 175 kHz (that is, the track-and hold can handle input frequencies in excess of 87.5 kHz). Rev. B | Page 9 of 24 AD7863 CIRCUIT DESCRIPTION input current of less than 100 nA. This input is benign, with no ANALOG INPUT SECTION dynamic charging currents. Once again, the designed code The AD7863 is offered as three part types: the AD7863-10, transitions occur on successive integer LSB values. Output which handles a ±10 V input voltage range, the AD7863-3, coding is straight (natural) binary with 1 LSB = FS/16,384 = which handles input voltage range ±2.5 V and the AD7863-2, 2.5 V/16,384 = 0.15 mV. Table 6 shows the ideal input/output which handles a 0 V to 2.5 V input voltage range. transfer function for the AD7863-2. 2.5V Table 6. Ideal Input/Output Code (AD7863-2) REFERENCE 2kΩ 1 Analog Input Digital Output Code Transition AD7863-10/AD7863-3 V 2 REF +FSR − 1 LSB 111 . . . 110 to 111 . . . 111 TO ADC +FSR − 2 LSB 111 . . . 101 to 111 . . . 110 REFERENCE CIRCUITRY +FSR − 3 LSB 111 . . . 100 to 111 . . . 101 R2 R1 GND + 3 LSB 000 . . . 010 to 000 . . . 011 TO INTERNAL V AX MUX COMPARATOR GND + 2 LSB 000 . . . 001 to 000 . . . 010 R3 TRACK/ HOLD GND + 1 LSB 000 . . . 000 to 000 . . . 001 AGND 1 FSR is full-scale range = 2.5 V for AD7863-2 with V = 2.5 V. REF 2 Figure 5. AD7863-10/AD7863-3 Analog Input Structure 1 LSB = FSR/16,384 = 0.15 mV for AD7863-2 with VREF = 2.5 V. OFFSET AND FULL-SCALE ADJUSTMENT Figure 5 shows the analog input section for the AD7863-10 and In most digital signal processing (DSP) applications, offset and AD7863-3. The analog input range of the AD7863-10 is ±10 V full-scale errors have little or no effect on system performance. into an input resistance of typically 9 kΩ. The analog input Offset error can always be eliminated in the analog domain by range of the AD7863-3 is ±2.5 V into an input resistance of ac coupling. Full-scale error effect is linear and does not cause typically 3 kΩ. This input is benign, with no dynamic charging problems as long as the input signal is within the full dynamic currents because the resistor stage is followed by a high input range of the ADC. Invariably, some applications require that the impedance stage of the track-and-hold amplifier. For the input signal span the full analog input dynamic range. In such AD7863-10, R1 = 8 kΩ, R2 = 2 kΩ and R3 = 2 kΩ. For the applications, offset and full-scale error have to be adjusted to zero. AD7863-3, R1 = R2 = 2 kΩ and R3 is open circuit. Figure 6 shows a typical circuit that can be used to adjust the For the AD7863-10 and AD7863-3, the designed code offset and full-scale errors on the AD7863 (V on the A1 transitions occur on successive integer LSB values (that is, 1 LSB, AD7863-10 version is shown for example purposes only). 2 LSBs, 3 LSBs . . .). Output coding is twos complement binary Where adjustment is required, offset error must be adjusted with 1 LSB = FS/16,384. The ideal input/output transfer before full-scale error. This is achieved by trimming the offset function for the AD7863-10 and AD7863-3 is shown in Table 5. of the op amp driving the analog input of the AD7863 while the input voltage is ½ LSB below analog ground. The trim Table 5. Ideal Input/Output Code (AD7863-10/AD7863-3) 1 procedure is as follows: apply a voltage of −0.61 mV (−½ LSB) Analog Input Digital Output Code Transition 2 at V in Figure 6 and adjust the op amp offset voltage until the 1 +FSR/2 − 1 LSB 011 . . . 110 to 011 . . . 111 ADC output code flickers between 11 1111 1111 1111 and +FSR/2 − 2 LSBs 011 . . . 101 to 011 . . . 110 00 0000 0000 0000. +FSR/2 − 3 LSBs 011 . . . 100 to 011 . . . 101 GND + 1 LSB 000 . . . 000 to 000 . . . 001 GND 111 . . . 111 to 000 . . . 000 INPUT RANGE = ±10V V GND − 1 LSB 111 . . . 110 to 111 . . . 111 1 −FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 R1 10kΩ −FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 R2 −FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 500Ω V A1 1 FSR is full-scale range = 20 V (AD7863-10) and = 5 V (AD7863-3) with VREF = 2.5 V. R3 2 R4 1 LSB = FSR/16,384 = 1.22 mV (AD7863-10) and 0.3 mV (AD7863-3) with 10kΩ AD7863* 10kΩ VREF = 2.5 V. R5 10kΩ The analog input section for the AD7863-2 contains no biasing AGND resistors and the VAX/BX pin drives the input directly to the multiplexer and track-and-hold amplifier circuitry. The analog *ADDITIONAL PINS OMITTED FOR CLARITY. input range is 0 V to 2.5 V into a high impedance stage with an Figure 6. Full-Scale Adjust Circuit Rev. B | Page 10 of 24 06411-005 06411-006 AD7863 signal indicates the end of conversion and at this time the Gain error can be adjusted at either the first code transition (ADC conversion results for both channels are available to be read. A negative full scale) or the last code transition (ADC positive full second conversion is then initiated. If the multiplexer select (A0) scale). The trim procedures for both cases are as follows: is low, the first and second read pulses after the first conversion Positive Full-Scale Adjust (−10 Version) accesses the result from Channel A (VA1 and VA2, respectively). The third and fourth read pulses, after the second conversion Apply a voltage of 9.9927 V (FS/2 – 1 LSBs) at V1. Adjust R2 and A0 high, accesses the result from Channel B (VB1 and VB2, until the ADC output code flickers between 01 1111 1111 1110 respectively). The state of A0 can be changed any time after the and 01 1111 1111 1111. CONVST goes high, that is, track-and-holds into hold and 500 ns Negative Full-Scale Adjust (−10 Version) CONVST prior to the next falling edge of . Note that A0 should Apply a voltage of −9.9976 V (−FS + 1 LSB) at V1. Adjust R2 not be changed during conversion if the nonselected channels until the ADC output code flickers between 10 0000 0000 0000 have negative voltages applied to them, which are outside the and 10 0000 0000 0001. input range of the AD7863, because this affects the conversion in progress. Data is read from the part via a 14-bit parallel data An alternative scheme for adjusting full-scale error in systems CS RD bus with standard and signal, that is, the read operation that use an external reference is to adjust the voltage at the V REF CS consists of a negative going pulse on the pin combined with pin until the full-scale error for any of the channels is adjusted RD CS two negative going pulses on the pin (while the is low), out. The good full-scale matching of the channels ensures small accessing the two 14-bit results. Once the read operation has full-scale errors on the other channels. taken place, a further 400 ns should be allowed before the next TIMING AND CONTROL falling edge of CONVST to optimize the settling of the track- and-hold amplifier before the next conversion is initiated. Figure 7 shows the timing and control sequence required to The achievable throughput rate for the part is 5.2 μs (conversion obtain optimum performance (Mode 1) from the AD7863. In time) plus 100 ns (read time) plus 0.4 μs (quiet time). This the sequence shown, a conversion is initiated on the falling edge results in a minimum throughput time of 5.7 μs (equivalent to of CONVST. This places both track-and-holds into hold a throughput rate of 175 kHz). simultaneously and new data from this conversion is available in the output register of the AD7863 5.2 μs later. The BUSY t ACQ t 8 CONVST t 3 BUSY t = 5.2µs CONV A0 CS t t t 1 2 7 t 4 RD t t 5 6 DATA V V V V A1 A2 B1 B2 Figure 7. Mode 1 Timing Operation Diagram for High Sampling Performance Rev. B | Page 11 of 24 06411-007 AD7863 Read Options CS Apart from the read operation previously described and displayed in Figure 7, other CS and RD combinations can result in different RD channels/inputs being read in different combinations. Suitable combinations are shown in Figure 8, Figure 9, and Figure 10. V V V DATA A1 A2 A1 CS Figure 9. Read Option B (A0 is Low) RD A0 DATA V V A1 A2 CS Figure 8. Read Option A (A0 is Low) RD DATA V V A1 A2 Figure 10. Read Option C Rev. B | Page 12 of 24 06411-008 06411-009 06411-010 AD7863 OPERATING MODES MODE 1 OPERATION keeping CONVST low at the end of the second conversion, whereas it was high at the end of the second conversion for Normal Power, High Sampling Performance Mode 1 operation. The timing diagram in Figure 7 is for optimum performance in operating Mode 1 where the falling edge of CONVST starts The operation shown in Figure 11 shows how to access data conversion and puts the track-and-hold amplifiers into their from both Channel A and Channel B, followed by the auto sleep hold mode. This falling edge of CONVST also causes the BUSY mode. One can also set up the timing to access data from signal to go high to indicate that a conversion is taking place. Channel A only or Channel B only (see the Read Options The BUSY signal goes low when the conversion is complete, section) and then go into auto sleep mode. The rising edge of CONVST which is 5.2 μs max after the falling edge of and new CONVST wakes up the part. This wake-up time is 4.8 μs when data from this conversion is available in the output latch of the using an external reference and 5 ms when using the internal AD7863. A read operation accesses this data. If the multiplexer reference, at which point the track-and-hold amplifiers go into select A0 is low, the first and second read pulses after the first CONVST their hold mode, provided the has gone low. The conversion accesses the result from Channel A (VA1 and VA2, conversion takes 5.2 μs after this giving a total of 10 μs (external respectively). The third and fourth read pulses, after the second reference, 5.005 ms for internal reference) from the rising edge conversion and A0 high, access the result from Channel B (V B1 CONVST of to the conversion being complete, which is and V , respectively). Data is read from the part via a 14-bit B2 indicated by the BUSY going low. CS RD parallel data bus with standard and signals. This data Note that because the wake-up time from the rising edge of read operation consists of a negative going pulse on the CS pin CONVST is 4.8 μs, if the CONVST pulse width is greater than combined with two negative going pulses on the RD pin (while 5.2 μs the conversion takes more than the 10 μs (4.8 μs wake-up the CS is low), accessing the two 14-bit results. For the fastest time + 5.2 μs conversion time) shown in Figure 11 from the throughput rate the read operation takes 100 ns. The read CONVST rising edge of . This is because the track-and-hold operation must be complete at least 400 ns before the falling amplifiers go into their hold mode on the falling edge of CONVST edge of the next and this gives a total time of 5.7 μs CONVST and the conversion does not complete for a further for the full throughput time (equivalent to 175 kHz). This mode 5.2 μs. In this case, the BUSY is the best indicator of when the of operation should be used for high sampling applications. conversion is complete. Even though the part is in sleep mode, MODE 2 OPERATION data can still be read from the part. Power-Down, Auto-Sleep After Conversion The read operation is identical to that in Mode 1 operation and The timing diagram in Figure 11 is for optimum performance must also be complete at least 400 ns before the falling edge of in operating Mode 2 where the part automatically goes into CONVST the next to allow the track-and-hold amplifiers to sleep mode once BUSY goes low after conversion and wakes up have enough time to settle. This mode is very useful when the before the next conversion takes place. This is achieved by part is converting at a slow rate because the power consumption is significantly reduced from that of Mode 1 operation. 4.8µs*/5ms** t ACQ WAKE-UP TIME t 8 CONVST t t 3 3 BUSY t = 5.2µs t = 5.2µs CONV CONV A0 CS RD V V V V DATA B1 B2 A1 A2 * WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 4.8µs. ** WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms. Figure 11. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated Rev. B | Page 13 of 24 06411-011 AD7863 frequency of 175 kHz. The SNR obtained from this graph is AD7863 DYNAMIC SPECIFICATIONS −80.72 dB. It should be noted that the harmonics are taken into The AD7863 is specified and tested for dynamic performance as account when calculating the SNR. well as traditional dc specifications such as integral and 0 differential nonlinearity. These ac specifications are required for –10 f = 175kHz SAMPLE the signal processing applications such as phased array sonar, f = 10kHz –20 IN SNR = +80.72dB adaptive filters, and spectrum analysis. These applications –30 THD = –92.96dB –40 require information on the ADC’s effect on the spectral content –50 of the input signal. Hence, the parameters for which the –60 AD7863 is specified include SNR, harmonic distortion, –70 –80 intermodulation distortion, and peak harmonics. These terms –90 are discussed in more detail in the following sections. –100 –110 SIGNAL-TO-NOISE RATIO (SNR) –120 –130 SNR is the measured signal-to-noise ratio at the output of the –140 ADC. The signal is the rms magnitude of the fundamental. –150 0 1020 304050 607080 90 Noise is the rms sum of all the nonfundamental signals up to FREQUENCY (kHz) half the sampling frequency (f /2), excluding dc; SNR is S Figure 13. AD7863 FFT Plot dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the EFFECTIVE NUMBER OF BITS quantization noise. The theoretical signal-to-noise ratio for a The formula given in Equation 1 relates the SNR to the number sine wave input is given by of bits. Rewriting the formula, as in Equation 2, it is possible to SNR = (6.02N + 1.76) dB (1) obtain a measure of performance expressed in effective number of bits (N). where N is the number of bits. SNR− 1.76 N= (2) Thus for an ideal 14-bit converter, SNR = 86.04 dB. 6.02 Figure 12 shows a histogram plot for 8192 conversions of a dc The effective number of bits for a device can be calculated input using the AD7863 with 5 V supply. The analog input was directly from its measured SNR. set at the center of a code transition. It can be seen that the Figure 14 shows a typical plot of effective numbers of bits vs. codes appear mainly in the one output bin, indicating very good frequency for an AD7863-2 with a sampling frequency of noise performance from the ADC. 175 kHz. The effective number of bits typically falls between 8000 13.11 and 11.05 corresponding to SNR figures of 80.68 dB 7000 and 68.28 dB. 6000 14.0 5000 13.5 4000 13.0 12.5 3000 12.0 2000 11.5 1000 0 11.0 746 747 748 749 750 751 752 753 754 755 CODE 10.5 Figure 12. Histogram of 8192 Conversions of a DC Input 10.0 0 200 400 600 800 1000 The output spectrum from the ADC is evaluated by applying FREQUENCY (kHz) a sine wave signal of very low distortion to the VAX/BX input, Figure 14. Effective Numbers of Bits vs. Frequency which is sampled at a 175 kHz sampling rate. A fast fourier transform (FFT) plot is generated from which the SNR data can be obtained. Figure 13 shows a typical 8192 point FFT plot of the AD7863 with an input signal of 10 kHz and a sampling Rev. B | Page 14 of 24 COUNTS 06411-012 ENOB (dB) 06411-014 06411-013 AD7863 TOTAL HARMONIC DISTORTION (THD) PEAK HARMONIC OR SPURIOUS NOISE Total harmonic distortion (THD) is the ratio of the rms sum of Harmonic or spurious noise is defined as the ratio of the rms harmonics to the rms value of the fundamental. For the value of the next largest component in the ADC output AD7863, THD is defined as spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is 2 2 2 2 V +V +V +V 2 3 4 5 determined by the largest harmonic in the spectrum, but for THD() dB = 20 log (3) V parts where the harmonics are buried in the noise floor, the 1 peak is a noise peak. where: DC LINEARITY PLOT V1 is the rms amplitude of the fundamental. Figure 16 and Figure 17 show typical DNL and INL plots for the AD7863. V2, V3, V4, and V5 are the rms amplitudes of the second through the fifth harmonic. 1.0 THD is also derived from the FFT plot of the ADC output spectrum. 0.5 INTERMODULATION DISTORTION With inputs consisting of sine waves at two frequencies, fa and 0 fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3 . . . Intermodulation terms are those for which –0.5 neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa − fb) and the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). –1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 In this case, the second and third order terms are of different ADC CODE significance. The second order terms are usually distanced in Figure 16. DC DNL Plot frequency from the original sine waves while the third order 1.0 terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is 0.5 as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input 0 consists of two equal amplitude, low distortion sine waves. Figure 15 shows a typical IMD plot for the AD7863. –0.5 0 –10 INPUT FREQUENCIES F1 = 50.13kHz –20 F2 = 49.13kHz –30 f = 175kHz SAMPLE –1.0 –40 IMD 0 2048 4096 6144 8192 10240 12288 14336 16383 2ND ORDER TERM –50 ADC CODE –98.21dB –60 3RD ORDER TERM Figure 17. DC INL Plot –93.91dB –70 –80 –90 –100 –110 –120 –130 –140 –150 0 1020 30 405060 708090 FREQUENCY (kHz) Figure 15. IMD Plot Rev. B | Page 15 of 24 (dB) 06411-015 INL ERROR (LSB) DNL ERROR (LSB) 06411-017 06411-016 AD7863 POWER CONSIDERATIONS In the automatic power-down mode the part can be operated at a sample rate that is considerably less than 175 kHz. In this case, the power consumption is reduced and depends on the sample rate. Figure 18 shows a graph of the power consumption vs. sampling rates from 1 Hz to 100 kHz in the automatic power- down mode. The conditions are 5 V supply at 25°C. 50 45 40 35 30 25 20 15 10 5 0 0 102030405060708090 100 FREQUENCY (kHz) Figure 18. Power vs. Sample Rate in Auto Power-Down Rev. B | Page 16 of 24 POWER (mW) 06411-018 AD7863 MICROPROCESSOR INTERFACING The AD7863 high speed bus timing allows direct interfacing to AD7863 TO TMS32010 INTERFACE DSP processors as well as modern 16-bit microprocessors. An interface between the AD7863 and the TMS32010 is shown Suitable microprocessor interfaces are shown in Figure 19 CONVST in Figure 20. Once again the signal can be supplied through Figure 23. from the TMS32010 or from an external source, and the TMS32010 is interrupted when both conversions have been AD7863 TO ADSP-2100 INTERFACE completed. The following instruction is used to read the Figure 19 shows an interface between the AD7863 and the conversion results from the AD7863: ADSP-2100. The CONVST signal can be supplied from the IN D, ADC ADSP-2100 or from an external source. The AD7863 BUSY line provides an interrupt to the ADSP-2100 when conversion is where: completed on both channels. The two conversion results can then be read from the AD7863 using two successive reads to the D is data memory address. same memory address. The following instruction reads one of ADC is the AD7863 address. the two results: OPTIONAL PA2 MR0 = DM (ADC) ADDRESS BUS PA0 where: CONVST ADDRESS TMS32010 CS DECODE EN MEN A0 MR0 is the ADSP-2100 MR0 register. AD7863* ADC is the AD7863 address. INT BUSY DEN RD OPTIONAL DMA13 DB13 ADDRESS BUS DMA0 DB0 CONVST ADDR D15 ADSP-2100 CS DECODE DATA BUS (ADSP-2101/ D0 ADSP-2102) DMS EN A0 *ADDITIONAL PINS OMITTED FOR CLARITY. AD7863* IRQn BUSY Figure 20. AD7863 to TMS32010 Interface DMRD (RD) RD AD7863 TO TMS320C25 INTERFACE DB13 Figure 21 shows an interface between the AD7863 and the DB0 DMD15 TMS320C25. As with the two previous interfaces, conversion DATA BUS DMD0 can be initiated from the TMS320C25 or from an external *ADDITIONAL PINS OMITTED FOR CLARITY. source, and the processor is interrupted when the conversion Figure 19. AD7863 to ADSP-2100 Interface sequence is completed. The TMS320C25 does not have a RD RD separate output to drive the AD7863 input directly. This AD7863 TO ADSP-2101/ADSP-2102 INTERFACE STRB W has to be generated from the processor and R/ outputs The interface outlined in Figure 19 also forms the basis for an RD with the addition of some logic gates. The signal is OR interface between the AD7863 and the ADSP-2101/ADSP-2102. MSC gated with the signal to provide the one WAIT state The READ line of the ADSP-2101/ADSP-2102 is labeled RD. In required in the read cycle for correct interface timing. this interface, the RD pulse width of the processor can be Conversion results are read from the AD7863 using the programmed using the data memory wait state control register. following instruction: The instruction used to read one of the two results is as outlined IN D, ADC for the ADSP-2100. where: D is data memory address. ADC is the AD7863 address. Rev. B | Page 17 of 24 06411-019 06411-020 AD7863 OPTIONAL OPTIONAL A15 A15 ADDRESS BUS ADDRESS BUS A0 A0 TMS320C25 CONVST CONVST ADDRESS CS ADDRESS MC68000 A0 DECODE DECODE IS EN A0 EN CS AD7863* INTn BUSY DTACK STRB AD7863* RD AS RD R/W R/W READY DB13 MSC DB0 DB13 D15 DATA BUS DB0 D0 *ADDITIONAL PINS OMITTED FOR CLARITY. DMD15 DATA BUS Figure 22. AD7863 to MC68000 Interface DMD0 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 21. AD7863 to TMS320C25 Interface AD7863 TO 80C196 INTERFACE Figure 23 shows an interface between the AD7863 and the Some applications may require that the conversion be initiated 80C196 microprocessor. Here, the microprocessor initiates by the microprocessor rather than an external timer. One WR conversion. This is achieved by gating the 80C196 signal option is to decode the AD7863 CONVST from the address bus CS with a decoded address output (different from the AD7863 so that a write operation starts a conversion. Data is read at the address). The AD7863 BUSY line is used to interrupt the end of the conversion sequence as before. Figure 23 shows an microprocessor when the conversion sequence is completed. example of initiating conversion using this method. Note that for all interfaces, it is preferred that a read operation not be A15 attempted during conversion. ADDRESS BUS A1 AD7863 TO MC68000 INTERFACE ADDRESS 80C196 CS DECODE A0 An interface between the AD7863 and the MC68000 is shown EN in Figure 22. As before, conversion can be supplied from the AD7863* MC68000 or from an external source. The AD7863 BUSY line BUSY can be used to interrupt the processor or, alternatively, software WR RD RD delays can ensure that conversion has been completed before a DB13 read to the AD7863 is attempted. Because of the nature of its DB0 interrupts, the MC68000 requires additional logic (not shown D15 DATA BUS in Figure 23) to allow it to be interrupted correctly. For further D0 *ADDITIONAL PINS OMITTED FOR CLARITY. information on MC68000 interrupts, consult the MC68000 Figure 23. AD7863–80C196 Interface users manual. VECTOR MOTOR CONTROL The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7863. CS is used to drive The current drawn by a motor can be split into two components: the MC68000 DTACK input to allow the processor to execute one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components a normal read operation to the AD7863. The conversion results are read using the following MC68000 instruction: should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) MOVE.W ADC, D0 supplied to the motor and the frequency of the drive are the where: basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling D0 is the 68000 D0 register. effect can reduce the performance of the motor because, for ADC is the AD7863 address. example, if the torque is increased by increasing the frequency, the flux tends to decrease. Rev. B | Page 18 of 24 06411-021 06411-023 06411-022 AD7863 MULTIPLE AD7863S Vector control of an ac motor involves controlling the phase in addition to drive and current frequency. Controlling the phase Figure 25 shows a system where a number of AD7863s can be of the motor requires feedback information on the position of configured to handle multiple input channels. This type of the rotor relative to the rotating magnetic field in the motor. configuration is common in applications such as sonar and Using this information, a vector controller mathematically radar. The AD7863 is specified with typical limits on aperture transforms the three phase drive currents into separate torque delay. This means that the user knows the difference in the and flux components. The AD7863 is ideally suited for use in sampling instant between all channels. This allows the user to vector motor control applications. maintain relative phase information between the different channels. A block diagram of a vector motor control application using the AD7863 is shown in Figure 24. The position of the field is V A1 RD RD derived by determining the current in each phase of the motor. V B1 AD7863 V A2 Only two phase currents need to be measured because the third (1) V B2 can be calculated if two phases are known. VA1 and VA2 of the CS V REF AD7863 are used to digitize this information. V A1 Simultaneous sampling is critical to maintaining the relative RD V B1 phase information between the two channels. A current sensing V AD7863 A2 isolation amplifier, transformer, or Hall effect sensor is used (2) V B2 ADDRESS between the motor and the AD7863. Rotor information is ADDRESS CS DECODE V REF obtained by measuring the voltage from two of the inputs to the motor. VB1 and VB2 of the AD7863 are used to obtain this V RD REF information. Once again the relative phase of the two channels V A1 is important. A DSP microprocessor is used to perform the V B1 AD7863 (n) V mathematical transformations and control loop calculations on A2 CS V B2 the information fed back by the AD7863. Figure 25. Multiple AD7863s in Multichannel System DSP MICROPROCESSOR I C DAC TORQUE AND FLUX A common read signal from the microprocessor drives the RD CONTROL LOOP THREE I V CALCULATIONS AND B B DRIVE PHASE input of all AD7863s. Each AD7863 is designated a unique DAC TWO TO THREE CIRCUITRY MOTOR PHASE I V address selected by the address decoder. The reference output of A A INFORMATION DAC AD7863 Number 1 is used to drive the reference input of all TORQUE other AD7863s in the circuit shown in Figure 25. One V can ISOLATION REF SETPOINT AMPLIFIERS be used to provide the reference to several other AD7863s. FLUX SETPOINT V A1 Alternatively, an external or system reference can be used to V A2 drive all VREF inputs. A common reference ensures good full- TRANSFORMATION TO TORQUE AND AD7863* scale tracking between all channels. FLUX CURRENT COMPONENTS V B1 V B2 *ADDITIONAL PINS OMITTED FOR CLARITY. VOLTAGE ATTENUATORS Figure 24. Vector Motor Control Using the AD7863 Rev. B | Page 19 of 24 06411-024 06411-025 AD7863 APPLICATIONS HINTS Fair-Rite 274300111 or Murata BL01/02/03) should be located PC BOARD LAYOUT CONSIDERATIONS within three inches of the AD7863. The AD7863 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the The PCB power plane (VCC) should provide power to all digital excellent noise performance of the AD7863 it is imperative that logic on the PC board, and the analog power plane (VDD) should great care be given to the PC board layout. Figure 26 shows a provide power to all AD7863 power pins, voltage reference recommended connection diagram for the AD7863. circuitry and any input amplifiers, if needed. A suitable low noise amplifier for the AD7863 is the AD797, one for each GROUND PLANES input. Ensure that the +V and the −V supplies to each S S The AD7863 and associated analog circuitry should have a amplifier are individually decoupled to AGND. separate ground plane, referred to as the analog ground plane The PCB power (VCC) and ground (DGND) should not overlay (AGND). This analog ground plane should encompass all portions of the analog power plane (VDD). Keeping the VCC AD7863 ground pins (including the DGND pin), voltage power and the DGND planes from overlaying the VDD contributes reference circuitry, power supply bypass circuitry, the analog to a reduction in plane-to-plane noise coupling. input traces, and any associated input/buffer amplifiers. SUPPLY DECOUPLING The regular PCB ground plane (referred to as the DGND for this discussion) area should encompass all digital signal traces, Noise on the analog power plane (VDD) can be further reduced excluding the ground pins, leading up to the AD7863. by use of multiple decoupling capacitors (Figure 26). POWER PLANES Optimum performance is achieved by the use of disc ceramic capacitors. The V and reference pins (whether using an DD The PC board layout should have two distinct power planes, external or an internal reference) should be individually one for analog circuitry and one for digital circuitry. The analog decoupled to the analog ground plane (AGND). This should be power plane should encompass the AD7863 (V ) and all DD done by placing the capacitors as close as possible to the associated analog circuitry. This power plane should be AD7863 pins with the capacitor leads as short as possible, thus connected to the regular PCB power plane (VCC) at a single minimizing lead inductance. point, if necessary through a ferrite bead, as illustrated in Figure 26. This bead (part numbers for reference: L (FERRITE BEAD) ANALOG SUPPLY +5V V 0.1µF 10µF 47µF IN TEMP AD780 0.1µF V OUT V DD +15V V REF 0.1µF 0.1µF 0.1µF AGND DGND +V S AGND V A1 V A1 AD7863 V B1 V B1 V A2 V A2 V B2 V B2 ANALOG –V S SUPPLY –15V 0.1µF 4 × AD797s Figure 26. Typical Connections Diagram Including the Relevant Decoupling Rev. B | Page 20 of 24 06411-026 AD7863 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 14 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.10 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 27. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 1.85 0.25 2.00 MAX 1.75 0.09 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 28. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters Rev. B | Page 21 of 24 0.75 (0.0295) 0.25 (0.0098) 060106-A 060706-A AD7863 ORDERING GUIDE Model Input Range Relative Accuracy Temperature Range Package Description Package Option AD7863AR-10 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-10REEL ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-10REEL7 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-10 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-10REEL ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-10REEL7 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863ARS-10 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-10REEL ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-10REEL7 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-10 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-10REEL ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-10REEL7 ±10 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863BR-10 ±10 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863BR-10REEL ±10 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863BR-10REEL7 ±10 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863BRZ-10 ±10 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-3 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-3REEL ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-3REEL7 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-3 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863ARS-3 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-3REEL ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-3REEL7 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-3 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-3REEL ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-3REEL7 ±2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863BR-3 ±2.5 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863BR-3REEL ±2.5 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863BR-3REEL7 ±2.5 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863BRZ-3 ±2.5 V ±2.0 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-2 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-2REEL 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863AR-2REEL7 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-2 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-2REEL 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 1 AD7863ARZ-2REEL7 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SOIC_W RW-28 AD7863ARS-2 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-2REEL 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 AD7863ARS-2REEL7 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-2 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-2REEL 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 1 AD7863ARSZ-2REEL7 0 V to 2.5 V ±2.5 LSB –40°C to +85°C 28-Lead SSOP RS-28 EVAL-AD7863CB Evaluation Board 1 Z = Pb-free part. Rev. B | Page 22 of 24 AD7863 NOTES Rev. B | Page 23 of 24 AD7863 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06411-0-11/06(B) Rev. B | Page 24 of 24