ANALOG DEVICES AD7862

Simultaneous Sampling a Dual 250 kSPS 12-Bit ADC AD7862 FEATURES FUNCTIONAL BLOCK DIAGRAM Two Fast 12-Bit ADCs V V REF DD Four Input Channels Simultaneous Sampling & Conversion +2.5V REFERENCE 2kΩ 4 ms Throughput Time AD7862 Single Supply Operation Selection of Input Ranges: 610 V for AD7862-10 SIGNAL TRACK/ V A1 SCALING 62.5 V for AD7862-3 HOLD MUX 12-BIT SIGNAL 0 V to 2.5 V for AD7862-2 ADC V B1 DB0 SCALING High Speed Parallel Interface OUTPUT SIGNAL LATCH V DB11 A2 Low Power, 60 mW typ SCALING TRACK/ MUX HOLD 12-BIT Power Saving Mode, 50 mW typ SIGNAL V B2 SCALING ADC Overvoltage Protection on Analog Inputs 14-Bit Pin Compatible Upgrade (AD7863) CS CONVERSION CLOCK RD CONTROL LOGIC APPLICATIONS AC Motor Control Uninterrupted Power Supplies A0 BUSY CONVST AGND AGND DGND Data Acquisition Systems Communications GENERAL DESCRIPTION The AD7862 is fabricated in Analog Devices’ Linear Compat- 2 The AD7862 is a high speed, low power, dual 12-bit A/D ible CMOS (LC MOS) process, a mixed technology process converter that operates from a single +5 V supply. The part that combines precision bipolar circuits with low power CMOS contains two 4 μs successive approximation ADCs, two track/ logic. It is available in 28-lead SSOP, SOIC and DIP. hold amplifiers, an internal +2.5 V reference and a high speed parallel interface. There are four analog inputs that are grouped PRODUCT HIGHLIGHTS into two channels (A & B) selected by the A0 input. Each 1. The AD7862 features two complete ADC functions allowing channel has two inputs (V & V or V & V ) that can be simultaneous sampling and conversion of two channels. Each A1 A2 B1 B2 sampled and converted simultaneously thus preserving the ADC has a 2-channel input mux. The conversion result for relative phase information of the signals on both analog inputs. both channels is available 3.6 μs after initiating conversion. The part accepts an analog input range of ±10 V (AD7862-10), 2. The AD7862 operates from a single +5 V supply and ±2.5 V (AD7862-3) and 0–2.5 V (AD7862-2). Overvoltage consumes 60 mW typ. The automatic power-down mode, protection on the analog inputs for the part allows the input where the part goes into power down once conversion is voltage to go to ±17 V, ±7 V or +7 V, respectively, without complete and “wakes up” before the next conversion cycle, causing damage. makes the AD7862 ideal for battery-powered or portable A single conversion start signal (CONVST) places both track/ applications. holds into hold simultaneously and initiates conversion on both 3. The part offers a high speed parallel interface for easy con- inputs. The BUSY signal indicates the end of conversion, and nection to microprocessors, microcontrollers and digital at this time the conversion results for both channels are avail- signal processors. able to be read. The first read after a conversion accesses the 4. The part is offered in three versions with different analog result from V or V , while the second read accesses the result A1 B1 input ranges. The AD7862-10 offers the standard industrial from V or V , depending on whether the multiplexer select A2 B2 input range of ±10 V; the AD7862-3 offers the common A0 is low or high, respectively. Data is read from the part via a signal processing input range of ±2.5 V; while the AD7862-2 12-bit parallel data bus with standard CS and RD signals. can be used in unipolar 0 V – +2.5 V applications. In addition to the traditional dc accuracy specifications such as 5. The part features very tight aperture delay matching between linearity, full-scale and offset errors, the part is also specified for the two input sample-and-hold amplifiers. dynamic performance parameters including harmonic distortion and signal-to-noise ratio. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1996 (V = +5 V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications T to T DD MIN MAX AD7862–SPECIFICATIONS unless otherwise noted.) AB S 1 Parameter Version Version Version Units Test Conditions/Comments SAMPLE AND HOLD –3 dB Small Signal Bandwidth 3 3 3 MHz typ Aperture Delay 20 20 20 ns typ Aperture Jitter 100 100 100 ps typ Aperture Delay Matching 200 200 200 ps typ 2 DYNAMIC PERFORMANCE f = 100.0 kHz, f = 250 kSPS IN S 3 Signal to (Noise+Distortion) Ratio @ +25°C 70 71 70 dB min T to T 70 70 70 dB min MIN MAX 3 Total Harmonic Distortion –78 –78 –78 dB max 3 Peak Harmonic or Spurious Noise –85 –85 –85 dB typ 3 Intermodulation Distortion fa = 49 kHz, fb = 50 kHz 2nd Order Terms –85 –85 –85 dB typ 3rd Order Terms –85 –85 –85 dB typ 3 Channel to Channel Isolation –80 –80 –80 dB max f = 100 kHz Sine Wave IN DC ACCURACY Any Channel Resolution 12 12 12 Bits Minimum Resolution for which No Missing Codes are Guaranteed 12 12 12 Bits 3 Relative Accuracy ±1 ±1 ±1 LSB max Typically 0.4 LSB 3 Differential Nonlinearity ±1 ±1 ±1 LSB max 3 Positive Gain Error ±4 ±3 ±4 LSB max 3 Positive Gain Error Match 4 3 4 LSB max AD7862-10 3 Negative Gain Error ±4 ±3 ±4 LSB max Bipolar Zero Error ±4 ±3 ±4 LSB max Bipolar Zero Error Match 4 3 4 LSB max AD7862-3 3 Negative Gain Error ±4 ±3 ±4 LSB max Bipolar Zero Error ±4 ±3 ±4 LSB max Bipolar Zero Error Match 4 3 4 LSB max AD7862-2 Unipolar Offset Error +4 +3 +4 LSB max Unipolar Offset Error Match 4 3.5 4 LSB max ANALOG INPUTS AD7862-10 Input Voltage Range ±10 ±10 ±10 Volts Input Input Resistance 24 24 24 kΩ min AD7862-3 Input Voltage Range ±2.5 ±2.5 ±2.5 Volts Input Input Resistance 6 6 6 kΩ min AD7862-2 Input Voltage Range +2.5 +2.5 +2.5 Volts Input Input Current 500 500 500 nA max REFERENCE INPUT/OUTPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% 4 REF IN Input Capacitance 10 10 10 pF max REF OUT Output Voltage 2.5 2.5 2.5 V nom REF OUT Error @ +25°C ±10 ±10 ±10 mV max to T ±25 ±25 ±25 mV max REF OUT Error T MIN MAX REF OUT Temperature Coefficient 25 25 25 ppm/°C typ REF OUT Output Impedance 2 2 2 kΩ nom LOGIC INPUTS Input High Voltage, V 2.4 2.4 2.4 V min V = 5 V ± 5% INH DD Input Low Voltage, V 0.8 0.8 0.8 V max V = 5 V ± 5% INL DD Input Current, I ±10 ±10 ±10 μA max IN 4 Input Capacitance, C 10 10 10 pF max IN REV. 0 –2– AD7862 AB S 1 Parameter Version Version Version Units Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 4.0 V min I = 200 μA OH SOURCE Output Low Voltage, V 0.4 0.4 0.4 V max I = 1.6 mA OL SINK DB11–DB0 Floating-State Leakage Current ±10 ±10 ±10 μA max 4 Floating-State Capacitance 10 10 10 pF max Output Coding AD7862-10, AD7862-3 Twos Complement AD7863-2 Straight (Natural) Binary CONVERSION RATE Conversion Time 3.6 3.6 3.6 μs max For Both Channels 2, 3 Track/Hold Acquisition Time 0.3 0.3 0.3 μs max POWER REQUIREMENTS V +5 +5 +5 V nom ±5% for Specified Performance DD I DD Normal Mode 15 15 15 mA max Standby Mode 25 25 25 μA max Logic Inputs = 0 V or V DD Power Dissipation Normal Mode 75 75 75 mW max Typically 60 mW Standby Mode 125 125 125 μW max Typically 75 μW NOTES 1 4 Temperature ranges are as follows: A, B Versions: –40°C to +85°C; Sample tested @ +25°C to ensure compliance. S Version: –55°C to +125°C. Specifications subject to change without notice. 2 Performance measured through full channel (multiplexer, SHA and ADC). 3 See Terminology. ABSOLUTE MAXIMUM RATINGS* Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C Ceramic DIP Package, Power Dissipation . . . . . . . . . 670 mW (T = +25°C unless otherwise noted) A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V JA DD Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W Analog Input Voltage to AGND JA Lead Temperature, Soldering AD7862-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C AD7862-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C AD7862-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW Reference Input Voltage to AGND . . . –0.3 V to V + 0.3 V DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W Digital Input Voltage to DGND . . . . . –0.3 V to V + 0.3 V JA DD Lead Temperature, Soldering Digital Output Voltage to DGND . . . . –0.3 V to V + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . –40°C to +85°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C *Stresses above those listed under “Absolute Maximum Ratings” may cause Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C operational sections of this specification is not implied. Exposure to absolute Plastic DIP Package, Power Dissipation . . . . . . . . . . 670 mW maximum rating conditions for extended periods may affect device reliability. θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W JA ORDERING GUIDE Input Relative Temperature Package Package Model Input Accuracy Range Description Option AD7862AR-10 ±10 V ±1 LSB –40°C to +85°C 28-Bit Small Outline Package R-28 AD7862BR-10 ±10 V ±1 LSB –40°C to +85°C 28-Bit Small Outline Package R-28 AD7862ARS-10 ±10 V ±1 LSB –40°C to +85°C 28-Bit Shrink Small Outline Package RS-28 AD7862AN-10 ±10 V ±1 LSB –40°C to +85°C 28-Bit Plastic DIP N-28 AD7862SQ-10 ±10 V ±1 LSB –55°C to +125°C 28-Bit Cerdip Q-28 AD7862AR-3 ±2.5 V ±1 LSB –40°C to +85°C 28-Bit Small Outline Package R-28 AD7862BR-3 ±2.5 V ±1 LSB –40°C to +85°C 28-Bit Small Outline Package R-28 AD7862ARS-3 ±2.5 V ±1 LSB –40°C to +85°C 28-Bit Shrink Small Outline Package RS-28 AD7862AN-3 ±2.5 V ±1 LSB –40°C to +85°C 28-Plastic DIP N-28 AD7862AR-2 0 V to 2.5 V ±1 LSB –40°C to +85°C 28-Bit Small Outline Package R-28 AD7862ARS-2 0 V to 2.5 V ±1 LSB –40°C to +85°C 28-Bit Shrink Small Outline Package RS-28 REV. 0 –3– AD7862 (V = +5 V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications T to T unless DD MIN MAX 1, 2 TIMING CHARACTERISTICS otherwise noted.) A, B S Parameter Versions Version Units Test Conditions/Comments t 3.6 3.6 μs max Conversion Time CONV t 0.3 0.3 us max Acquisition Time ACQ Parallel Interface t 0 0 ns min CS to RD Setup Time 1 t 0 0 ns min CS to RD Hold Time 2 t 35 45 ns min CONVST Pulse Width 3 t 35 45 ns min Read Pulse Width 4 3 t 12 12 ns min Data Access Time After Falling Edge of RD 5 60 70 ns max 4 t 5 5 ns min Bus Relinquish Time After Rising Edge of RD 6 30 40 ns max t 40 40 ns min Time Between Consecutive Reads 7 NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figure 1. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. CONVST t 3 BUSY t CONV A0 CS ......... ......... t t t 1 7 2 t RD 4 t 5 t 6 V DATA V V V A1 A2 B1 B2 Figure 1. Timing Diagram 1.6mA TO OUTPUT +1.6V PIN 50pF 200µA Figure 2. Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –4– AD7862 PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1 NC No Connect 2 DB11 Data Bit 11 (MSB). Three-state TTL output. Output coding is twos complement for the AD7862- 10 and AD7862-3. Output coding is straight (natural) binary for the AD7862-2. 3–6 DB10–DB7 Data Bit 10 to Data Bit 7. Three-state TTL outputs. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 CONVST Convert Start Input. Logic Input. A high to low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. 9–15 DB6–DB0 Data Bit 6 to Data Bit 0. Three-state TTL outputs. 16 AGND Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry. 17 V Input Number 2 of Channel B. Analog Input voltage ranges of ±10 V (AD7862-10), ±2.5 V B2 (AD7862-3) and 0 V–2.5 V (AD7862-2). 18 V Input Number 2 of Channel A. Analog Input voltage ranges of ±10 V (AD7862-10), ±2.5 V A2 (AD7862-3) and 0 V–2.5 V (AD7862-2). 19 VREF Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. 20 A0 Multiplexer Select. This input is used in conjunction with RD and CS low to enable the data outputs. With A0 logic low, one read after a conversion will read the data from each of the ADCs in the sequence, V , V , and a subsequent read, when A0 goes high, reads the data from V , V . A1 A2 B1 B2 21 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 22 RD Read Input. Active low logic input. This input is used in conjunction with A0 and CS low to enable the data outputs. With A0 logic low, one read after a conversion will read the data from each of the ADCs in the sequence, V , V , and a subsequent read, when A0 goes high, reads the data from V A1 A2 B1, V . B2 23 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. 24 VDD Analog and Digital Positive Supply Voltage, +5.0 V ± 5%. 25 V Input Number 1 of Channel A. Analog Input voltage ranges of ±10 V (AD7862-10), ±2.5 V A1 (AD7862-3) and 0 V–2.5 V (AD7862-2). 26 V Input Number 1 of Channel B. Analog Input voltage ranges of ±10 V (AD7862-10), ±2.5 V B1 (AD7862-3) and 0 V–2.5 V (AD7862-2). 27 AGND Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry. 28 NC No Connect PIN CONFIGURATION NC 1 28 NC DB11 2 27 AGND DB10 3 26 V B1 DB9 4 25 V A1 DB8 5 24 V DD AD7862 DB7 6 23 BUSY TOP VIEW (Not to Scale) DGND 7 22 RD CONVST 8 21 CS DB6 9 20 A0 DB5 10 19 V REF DB4 11 18 V A2 DB3 12 17 V B2 DB2 13 16 AGND DB1 14 15 DB0 NC = NO CONNECT REV. 0 –5– AD7862 TERMINOLOGY Channel-to-Channel Isolation Signal to (Noise + Distortion) Ratio Channel-to-Channel isolation is a measure of the level of This is the measured ratio of signal to (noise + distortion) at the crosstalk between channels. It is measured by applying a full- output of the A/D converter. The signal is the rms amplitude of scale 100 kHz sine wave signal to each of the four inputs the fundamental. Noise is the rms sum of all nonfundamental individually. These, in turn, are individually referenced to the signals up to half the sampling frequency (f /2), excluding dc. other three channels whose inputs are grounded, and the ADC S The ratio is dependent upon the number of quantization levels output is measured to determine the level of crosstalk from the in the digitization process; the more levels, the smaller the other channel. The figure given is the worst case across all four quantization noise. The theoretical signal to (noise + distortion) channels. ratio for an ideal N-bit converter with a sine wave input is given Relative Accuracy by: Relative accuracy or endpoint nonlinearity is the maximum Signal to (Noise + Distortion) = (6.02 N + 1.76) dB deviation from a straight line passing through the endpoints of the ADC transfer function. Thus for a 12-bit converter, this is 74 dB. Differential Nonlinearity Total Harmonic Distortion This is the difference between the measured and the ideal 1 LSB Total harmonic distortion (THD) is the ratio of the rms sum of change between any two adjacent codes in the ADC. harmonics to the fundamental. For the AD7862 it is defined as: Positive Full-Scale Error 2 2 2 2 V +V +V +V This is the deviation of the last code transition (01 . . . 110 to 2 3 4 5 THD dB= 20 log () 01 . . . 111) from the ideal 4 × VREF – 3/2 LSB (AD7862-10 V 1 ±10 V range) or VREF – 3/2 LSB (AD7862-3, ±2.5 V range) where V is the rms amplitude of the fundamental and V , V , V 1 2 3 4 after the Bipolar Offset Error has been adjusted out. and V are the rms amplitudes of the second through the fifth 5 Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V) harmonics. This is the deviation of the last code transition (01 . . . 110 to Peak Harmonic or Spurious Noise 01 . . . 111) from the ideal VREF – 3/2 LSB after the unipolar Peak harmonic or spurious noise is defined as the ratio of the offset error has been adjusted out. rms value of the next largest component in the ADC output Bipolar Zero Error (AD7862-10, 610 V, AD7862-3, 62.5 V) spectrum (up to f /2 and excluding dc) to the rms value of the S This is the deviation of the midscale transition (all 1s to all 0s) fundamental. Normally, the value of this specification is deter- from the ideal AGND – 1/2 LSB. mined by the largest harmonic in the spectrum, but for parts Unipolar Offset Error (AD7862-2, 0 V to 2.5 V) where the harmonics are buried in the noise floor, it will be a This is the deviation of the first code transition (00 . . . 000 to noise peak. 00 . . . 001) from the ideal AGND + 1/2 LSB. Intermodulation Distortion Negative Full-Scale Error (AD7862-1, 610 V; AD7862-3, With inputs consisting of sine waves at two frequencies, fa and 62.5 V) fb, any active device with nonlinearities will create distortion This is the deviation of the first code transition (10 . . . 000 to products at sum and difference frequencies of mfa ± nfb where 10 . . . 001) from the ideal –4 × VREF + 1/2 LSB (AD7862-10 m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for ±10 V range) or –VREF + 1/2 LSB (AD7862-3, ±2.5 V range) which neither m nor n are equal to zero. For example, the after Bipolar Zero Error has been adjusted out. second order terms include (fa + fb) and (fa – fb), while the third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and Track/Hold Acquisition Time (fa – 2 fb). Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within The AD7862 is tested using the CCIF standard where two input ±1/2 LSB, after the end of conversion (the point at which the frequencies near the top end of the input bandwidth are used. track/hold returns to track mode). It also applies to situations In this case, the second and third order terms are of different where a change in the selected input channel takes place or significance. The second order terms are usually distanced in where there is a step input change on the input voltage applied frequency from the original sine waves, while the third order to the selected V input of the AD7862. It means that the AX/BX terms are usually at a frequency close to the input frequencies. user must wait for the duration of the track/hold acquisition As a result, the second and third order terms are specified time, after the end of conversion or after a channel change/step separately. The calculation of the intermodulation distortion is input change to V , before starting another conversion to AX/BX as per the THD specification where it is the ratio of the rms sum ensure that the part operates to specification. of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. REV. 0 –6– AD7862 CONVERTER DETAILS The acquisition time of the track/hold amplifiers begins at The AD7862 is a high speed, low power, dual 12-bit A/D this point. converter that operates from a single +5 V supply. The part Reference Section contains two 4 μs successive approximation ADCs, two track/ The AD7862 contains a single reference pin, labelled VREF, hold amplifiers, an internal +2.5 V reference and a high speed which either provides access to the part’s own +2.5 V reference parallel interface. There are four analog inputs that are grouped or to which an external +2.5 V reference can be connected to into two channels (A & B) selected by the A0 input. Each provide the reference source for the part. The part is specified channel has two inputs (V & V or V & V ) that can be A1 A2 B1 B2 with a +2.5 V reference voltage. Errors in the reference source sampled and converted simultaneously thus preserving the will result in gain errors in the AD7862’s transfer function and relative phase information of the signals on both analog inputs. will add to the specified full-scale errors on the part. On the The part accepts an analog input range of ±10 V (AD7862-10), AD7862-10 and the AD7862-3, it will also result in an offset ±2.5 V (AD7862-3) and 0 V–2.5 V (AD7862-2). Overvoltage error injected in the attenuator stage. protection on the analog inputs for the part allows the input The AD7862 contains an on-chip +2.5 V reference. To use this voltage to go to ±17 V, ±7 V or +7 V, respectively, without reference as the reference source for the AD7862, simply causing damage. The AD7862 has two operating modes, the connect a 0.1 μF disc ceramic capacitor from the VREF pin to high sampling mode and the auto sleep mode where the part AGND. The voltage that appears at this pin is internally automatically goes into sleep after the end of conversion. These buffered before being applied to the ADC. If this reference is modes are discussed in more detail in the Timing and Control required for use external to the AD7862, it should be buffered Section. as the part has a FET switch in series with the reference output, Conversion is initiated on the AD7862 by pulsing the CONVST resulting in a source impedance for this output of 3 kΩ nominal. input. On the falling edge of CONVST, both on-chip track/ The tolerance on the internal reference is ±10 mV at 25°C with holds are placed into hold simultaneously, and the conversion a typical temperature coefficient of 25 ppm/°C and a maximum sequence is started on both channels. The conversion clock for error over temperature of ±25 mV. the part is generated internally using a laser-trimmed clock If the application requires a reference with a tighter tolerance or oscillator circuit. The BUSY signal indicates the end of the AD7862 needs to be used with a system reference, the user conversion, and at this time the conversion results for both has the option of connecting an external reference to this VREF channels are available to be read. The first read after a conver- pin. The external reference will effectively overdrive the internal sion accesses the result from V or V while the second read A1 B1 reference and provide the reference source for the ADC. The accesses the result from V or V , depending on whether the A2 B2 reference input is buffered before being applied to the ADC multiplexer select A0 is low or high, respectively. Data is read with the maximum input current of ±100 μA. Suitable reference from the part via a 12-bit parallel data bus with standard CS sources for the AD7862 include the AD680, AD780 and and RD signals. REF43 precision +2.5 V references. Conversion time for the AD7862 is 3.6 μs in the high sampling mode (6 μs for the auto sleep mode), and the track/hold CIRCUIT DESCRIPTION acquisition time is 0.3 μs. To obtain optimum performance Analog Input Section from the part, the read operation should not occur during the The AD7862 is offered as three part types; the AD7862-10, conversion or during 300 ns prior to the next conversion. This which handles a ±10 V input voltage range; the AD7862-3, allows the part to operate at throughput rates up to 250 kHz which handles input voltage range ±2.5 V; and the AD7862-2, and achieve data sheet specifications. which handles a 0 V to +2.5 V input voltage range. Track/Hold Section The track/hold amplifiers on the AD7862 allow the ADCs to +2.5V accurately convert an input sine wave of full-scale amplitude to REFERENCE 2kΩ 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC V REF is operated at its maximum throughput rate of 250 kHz (i.e., TO ADC the track/hold can handle input frequencies in excess of 125 kHz). REFERENCE CIRCUITRY The track/hold amplifiers acquire input signals to 12-bit R2 R1 accuracy in less than 400 ns. The operation of the track/holds is TO INTERNAL V MUX AX COMPARATOR essentially transparent to the user. The two track/hold amplifi- TRACK/ R3 HOLD ers sample their respective input channels simultaneously on the AGND falling edge of CONVST. The aperture time for the track/holds AD7862-10/AD7862-3 (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, Figure 3. AD7862-10/-3 Analog Input Structure more importantly, is well matched across the two track/holds on one device and also well matched from device to device. This Figure 3 shows the analog input section for the AD7862-10 and allows the relative phase information between different input AD7862-3. The analog input range of the AD7862-10 is ±10 V channels to be accurately preserved. It also allows multiple into an input resistance of typically 33 kΩ. The analog input AD7862s to sample more than two channels simultaneously. At range of the AD7862-3 is ±2.5 V into an input resistance of the end of conversion, the part returns to its tracking mode. typically 12 kΩ. This input is benign with no dynamic charging REV. 0 –7– AD7862 currents, as the resistor stage is followed by a high input applications, offset and full-scale error will have to be adjusted impedance stage of the track/hold amplifier. For the AD7862-10, to zero. R1 = 30 kΩ, R2 = 7.5 kΩ, and R3 = 10 kΩ. For the AD7862-3, Figure 4 shows a circuit that can be used to adjust the offset and R1 = R2 = 6.5 kΩ and R3 is open circuit. full-scale errors on the AD7862 (V on the AD7862-10 version A1 For the AD7862-10 and AD7862-3, the designed code transi- is shown for example purposes only). Where adjustment is tions occur on successive integer LSB values (i.e., 1 LSB, required, offset error must be adjusted before full-scale error. 2 LSBs, 3 LSBs . . .). Output coding is twos complement This is achieved by trimming the offset of the op amp driving binary with 1 LSB = FS/4096. The ideal input/output transfer the analog input of the AD7862 while the input voltage is a function for the AD7862-10 and AD7862-3 is shown in Table I. 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of –2.44 mV (–1/2 LSB) at V (see Figure 4) A1 Table I. Ideal Input/Output Code Table for the AD7862-10/-3 and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. l Analog Input Digital Output Code Transition INPUT 2 RANGE = ±10V +FSR/2 – 1 LSB 011 . . . 110 to 011 . . . 111 V 1 +FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110 +FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101 R1 10kΩ GND + 1 LSB 000 . . . 000 to 000 . . . 001 R2 GND 111 . . . 111 to 000 . . . 000 500Ω V A1 GND – 1 LSB 111 . . . 110 to 111 . . . 111 R4 –FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 AD7862* 10kΩ –FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 R3 R5 10kΩ 10kΩ –FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 AGND NOTES 1 FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with REF IN = +2.5 V. 2 1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with *ADDITIONAL PINS OMITTED FOR CLARITY REF IN = +2.5 V. The analog input section for the AD7862-2 contains no biasing Figure 4. Full-Scale Adjust Circuit resistors, and the V pin drives the input to the multiplexer AX/BX Gain error can be adjusted at either the first code transition and track/hold amplifier circuitry directly. The analog input (ADC negative full scale) or the last code transition (ADC range is 0 V to +2.5 V into a high impedance stage with an positive full scale). The trim procedures for both cases are as input current of less than 500 nA. This input is benign with no follows: dynamic charging currents. Once again, the designed code transitions occur on successive integer LSB values. Output Positive Full-Scale Adjust coding is straight (natural) binary with 1 LSB = FS/4096 = Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V . Adjust A1 2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output R2 until the ADC output code flickers between 0111 1111 1110 transfer function for the AD7862-2. and 0111 1111 1111. Negative Full-Scale Adjust Table II. Ideal Input/Output Code Table for the AD7862-2 Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at V and adjust A1 1 R2 until the ADC output code flickers between 1000 0000 0000 Analog Input Digital Output Code Transition and 1000 0000 0001. 2 +FSR – 1 LSB 111 . . . 110 to 111 . . . 111 An alternative scheme for adjusting full-scale error in systems +FSR – 2 LSB 111 . . . 101 to 111 . . . 110 that use an external reference is to adjust the voltage at the +FSR – 3 LSB 111 . . . 100 to 111 . . . 101 VREF pin until the full-scale error for any of the channels is GND + 3 LSB 000 . . . 010 to 000 . . . 011 adjusted out. The good full-scale matching of the channels will GND + 2 LSB 000 . . . 001 to 000 . . . 010 ensure small full-scale errors on the other channels. GND + 1 LSB 000 . . . 000 to 000 . . . 001 NOTES TIMING AND CONTROL 1 FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V. Figure 5a shows the timing and control sequence required to 2 1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V. obtain optimum performance (Mode 1) from the AD7862. In the sequence shown, a conversion is initiated on the falling edge OFFSET AND FULL-SCALE ADJUSTMENT of CONVST. This places both track/holds into hold simulta- In most digital signal processing (DSP) applications, offset and neously, and new data from this conversion is available in the full-scale errors have little or no effect on system performance. output register of the AD7862 3.6 μs later. The BUSY signal Offset error can always be eliminated in the analog domain by indicates the end of conversion, and at this time the conversion ac coupling. Full-scale error effect is linear and does not cause results for both inputs are available to be read. A second problems as long as the input signal is within the full dynamic conversion is then initiated. If the multiplexer select A0 is low, range of the ADC. Invariably, some applications will require the the first and second read pulses after the first conversion accesses input signal to span the full analog input dynamic range. In such the result from channel A (V and V respectively). The third A1 A2 REV. 0 –8– AD7862 400ns 300ns CONVST t 3 BUSY t = 3.6µs CONV A0 CS t t t 1 7 2 t RD 4 t 5 t 6 V DATA V V V A1 A2 B1 B2 Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance and fourth read pulses, after the second conversion and A0 high, CS access the result from Channel B (V and V respectively). A0’s B1 B2 state can be changed any time after the CONVST goes high, i.e., track/holds into hold, and 400 ns prior to the next falling edge of CONVST. Data is read from the part via a 12-bit RD parallel data bus with standard CS and RD signal, i.e., the read operation consists of a negative going pulse on the CS pin combined with two negative going pulses on the RD pin (while DATA V V V A1 A2 A1 the CS is low), accessing the two 12-bit results. Once the read operation has taken place, a further 300 ns should be allowed Figure 5c. Read Option B before the next falling edge of CONVST to optimize the settling of the track/hold amplifier before the next conversion is initiated. With the internal clock frequency at its maximum (3.7 MHz—not A0 accessible externally), the achievable throughput rate for the part is 3.6 μs (conversion time) plus 100 ns (read time) plus 0.3 μs (acquisition time). This results in a minimum throughput CS time of 4 μs (equivalent to a throughput rate of 250 kHz). Read Options Apart from the read operation described above and displayed in RD Figure 5a, other CS and RD combinations can result in different channels/inputs being read in different combinations. Suitable combinations are shown in Figures 5b through 5d. DATA V V A1 B1 Figure 5d. Read Option C CS OPERATING MODES Mode 1 Operation (High Sampling Performance) RD The timing diagram in Figure 5a is for optimum performance in operating mode 1 where the falling edge of CONVST starts conversion and puts the track/hold amplifiers into their hold DATA V V A1 A2 mode. This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, Figure 5b. Read Option A which is 3.6 μs max after the falling edge of CONVST, and new data from this conversion is available in the output latch of the AD7862. A read operation accesses this data. If the multiplexer select A0 is low, the first and second read pulses after the first conversion access the result from Channel A (V and V A1 A2 REV. 0 –9– AD7862 respectively). The third and fourth read pulses, after the second because the track/hold amplifiers go into their hold mode on conversion and A0 high, access the result from Channel B (V the falling edge of CONVST, and the conversion will not be B1 and V respectively). Data is read from the part via a 12-bit complete for a further 3.6 μs. In this case the BUSY will be the B2 parallel data bus with standard CS and RD signals. This data best indicator for when the conversion is complete. Even though read operation consists of negative going pulse on the CS pin the part is in sleep mode, data can still be read from the part. combined with a negative going pulse on the RD pin; this repeated The read operation is identical to Mode 1 operation and must twice will access the two 12-bit results. For the fastest throughput also be complete at least 300 ns before the falling edge of the rate (with an internal clock of 3.7 MHz), the read operation will next CONVST to allow the track/hold amplifiers to have enough take 100 ns. The read operation must be complete at least 300 ns time to settle. This mode is very useful when the part is convert- before the falling edge of the next CONVST, and this gives a total ing at a slow rate, as the power consumption will be significantly time of 4 μs for the full throughput time (equivalent to 250 kHz). reduced from that of Mode 1 operation. This mode of operation should be used for high sampling applications. DYNAMIC SPECIFICATIONS The AD7862 is specified and 100% tested for dynamic perfor- Mode 2 Operation (Auto Sleep After Conversion) mance specifications as well as traditional dc specifications such The timing diagram in Figure 6 is for optimum performance in as Integral and Differential Nonlinearity. These ac specifications Operating Mode 2 where the part automatically goes into sleep are required for the signal processing applications such as phased mode once BUSY goes low after conversion and “wakes-up” array sonar, adaptive filters and spectrum analysis. These applica- before the next conversion takes place. This is achieved by keeping tions require information on the ADC’s effect on the spectral CONVST low at the end of the second conversion, whereas it content of the input signal. Hence, the parameters for which the was high at the end of the second conversion for Mode 1 opera- AD7862 is specified include SNR, harmonic distortion, inter- tion. The operation shown in Figure 6 shows how to access data modulation distortion and peak harmonics. These terms are from both Channels A and B followed by the Auto Sleep mode. discussed in more detail in the following sections. One can also setup the timing to access data from Channel A only or Channel B only (see Read Options section on previous Signal-to-Noise Ratio (SNR) page) and then go into Auto-Sleep mode. The rising edge of SNR is the measured signal-to-noise ratio at the output of the CONVST “wakes-up” the part. This wake-up time is 2.5 μs ADC. The signal is the rms magnitude of the fundamental. when using an external reference and 5 ms when using the Noise is the rms sum of all the nonfundamental signals up to internal reference at which point the Track/Hold amplifier’s go half the sampling frequency (f /2) excluding dc. SNR is depen- S into their hold mode, provided the CONVST has gone low. The dent upon the number of quantization levels used in the conversion takes 3.6 μs after this, giving a total of 6 μs (external digitization process; the more levels, the smaller the quantiza- reference, 5.0035 ms for internal reference) from the rising edge tion noise. The theoretical signal to noise ratio for a sine wave of CONVST to the conversion being complete, which is input is given by indicated by the BUSY going low. Note that since the wake-up SNR = (6.02N + 1.76) dB (1) time from the rising edge of CONVST is 2.5 μs, if the CONVST where N is the number of bits. pulse width is greater than 2.5 μs, the conversion will take more than the 6 μs (2.5 μs wake-up time + 3.6 μs conversion time) Thus for an ideal 12-bit converter, SNR = 74 dB. shown in the diagram from the rising edge of CONVST. This is 2.5µs*/5ms** WAKE-UP 400ns TIME 300ns CONVST t t 3 3 BUSY t = 3.5µs CONV t = 3.6µs CONV A0 CS RD V DATA V V V A1 A2 B1 B2 **WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 2.5µs **WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms Figure 6. Mode 2 Timing Where Automatic Sleep Function Is Initiated REV. 0 –10– AD7862 –0 Figure 7 shows a histogram plot for 8192 conversions of a dc F = 245760 SAMPLE –10 input using the AD7862 with 5 V supply. The analog input was F = 10kHz IN –20 SNR = –72.95dB set at the center of a code transition. It can be seen that all the THD = –89.99dB –30 codes appear in the one output bin indicating very good noise –40 performance from the ADC. –50 9000 –60 8000 –70 –80 7000 –90 6000 –100 5000 –110 –120 4000 0 10k 30k 50k 70k 90k 100k 12.2k 3000 Figure 9. AD7862 FFT Plot 2000 Effective Number of Bits 1000 The formula given in Equation 1 relates the SNR to the number 0 of bits. Rewriting the formula, as in Equation 2, it is possible to 746 747 748 749 750 751 752 753 754 755 756 get a measure of performance expressed in effective number of bits (N). Figure 7. Histogram of 8192 Conversions of a DC Input SNR − 1.76 The same data is presented in Figure 8 as in Figure 7 except N = (2) 6.02 that in this case the output data read for the device occurs during conversion. This has the effect of injecting noise onto the The effective number of bits for a device can be calculated die while bit decisions are being made and this increases the directly from its measured SNR. noise generated by the AD7862. The histogram plot for 8192 Figure 10 shows a typical plot of effective number of bits versus conversions of the same dc input now shows a larger spread of frequency for an AD7862BN with a sampling frequency of codes. This effect will vary depending on where the serial clock 245.76 kHz. The effective number of bits typically falls between edges appear with respect to the bit trials of the conversion 11.6 and 10.6 corresponding to SNR figures of 71.59 dB and process. It is possible to achieve the same level of performance 65.57 dB. when reading during conversion as when reading after conver- sion depending on the relationship of the serial clock edges to 12.0 the bit trial points. 11.8 The output spectrum from the ADC is evaluated by applying a 11.6 sine wave signal of very low distortion to the V input that is AX/BX sampled at a 245.76 kHz sampling rate. A Fast Fourier Trans- 11.4 form (FFT) plot is generated from which the SNR data can be 11.2 obtained. Figure 9 shows a typical 2048 point FFT plot of the 11.0 AD7862 with an input signal of 10 kHz and a sampling fre- quency of 245.76 kHz. The SNR obtained from this graph is 10.8 72.95 dB. It should be noted that the harmonics are taken into 10.6 account when calculating the SNR. 10.4 7000 10.2 0 200 400 600 800 1000 6000 FREQUENCY – kHz 5000 Figure 10. Effective Numbers of Bits vs. Frequency 4000 Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the rms sum 3000 of harmonics to the rms value of the fundamental. For the AD7862, THD is defined as 2000 2 2 2 2 V +V +V +V 2 3 4 5 1000 THD dB= 20 log () V 1 0 745 746 747 748 749 750 751 752 753 754 755 where V is the rms amplitude of the fundamental and V , V , 1 2 3 V and V are the rms amplitudes of the second through the 4 5 sixth harmonic. The THD is also derived from the FFT plot of Figure 8. Histogram of the 8192 Conversions with Read the ADC output spectrum. During Conversion REV. 0 –11– ENOB AD7862 where INL(i) is the integral linearity at code i. V(f ) and V(o) Intermodulation Distortion S are the estimated full-scale and offset transitions, and V(i) is the With inputs consisting of sine waves at two frequencies, fa and th estimated transition for the i code. fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where V(i), the estimated code transition point is derived as follows: m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for which neither m or n are equal to zero. For example, the second   π× cum i () V(i)=−A× Cos   order terms include (fa + fb) and (fa – fb) while the third order N     terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). Using the CCIF standard where two input frequencies near the where A is the peak signal amplitude, N is the number of top end of the input bandwidth are used, the second and third histogram samples order terms are of different significance. The second order terms i are usually distanced in frequency from the original sine waves and cum i = Vn occurrences () () ∑ while the third order terms are usually at a frequency close to n=0 the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the inter- LSB modulation distortion is as per the THD specification where it is 0.5 F = 10 kHz IN the ratio of the rms sum of the individual distortion products to F = 245.760 kHz IN 0.4 the rms amplitude of the fundamental expressed in dBs. In this T = 25°C A case the input consists of two, equal amplitude, low distortion 0.3 sine waves. Figure 11 shows a typical IMD plot for the AD7862. 0.2 –0 INPUT FREQUENCIES –10 F1 = 50010 Hz 0.1 F2 = 49110 Hz –20 F = 245760 Hz SAMPLE SNR = –60.62dB –30 0 THD = –89.22dB –40 IMD: –0.1 –50 2ND ORDER TERM –88.44 dB 3RD ORDER TERM –66.20 dB –60 –0.2 –70 –80 –0.3 –90 –0.4 –100 –110 –0.5 –120 0 10k 30k 50k 70k 90k 100k 12.3k Figure 12. AD7862 AC INL Plot Power Considerations Figure 11. AD7862 IMD Plot In the automatic power-down mode the part may be operated at Peak Harmonic or Spurious Noise a sample rate that is considerably less than 200 kHz. In this Harmonic or spurious noise is defined as the ratio of the rms case, the power consumption will be reduced and will depend value of the next largest component in the ADC output spec- on the sample rate. Figure 13 shows a graph of the power trum (up to f /2 and excluding dc) to the rms value of the S consumption versus sampling rates from 100 Hz to 90 kHz in fundamental. Normally, the value of this specification will be the automatic power-down mode. The conditions are 5 V determined by the largest harmonic in the spectrum, but for supply 25°C, and the data was read after conversion. parts where the harmonics are buried in the noise floor, the peak will be a noise peak. 40 AC Linearity Plot 35 When a sine wave of specified frequency is applied to the V IN 30 input of the AD7862, and several million samples are taken, a histogram showing the frequency of occurrence of each of the 25 4096 ADC codes can be generated. From this histogram data, it 20 is possible to generate an ac integral linearity plot as shown in Figure 12. This shows very good integral linearity performance 15 from the AD7862 at an input frequency of 10 kHz. The absence of large spikes in the plot shows good differential linearity. Sim- 10 plified versions of the formulas used are outlined below. 5   Vi −Vo × 4096 0 () () ()   0.1 10 20 30 40 50 60 70 80 90 INL(i) = −i FREQUENCY – kHz  Vf −Vo  () S ()   Figure 13. Power vs. Sample Rate in Auto Power-Down Mode REV. 0 –12– POWER – mW AD7862 OPTIONAL MICROPROCESSOR INTERFACING The AD7862 high speed bus timing allows direct interfacing to PA2 ADDRESS BUS DSP processors as well as modern 16-bit microprocessors. PA0 Suitable microprocessor interfaces are shown in Figures 14 CONVST through 18. ADDR DECODE A0 AD7862–ADSP-2100 Interface MEN EN CS Figure 14 shows an interface between the AD7862 and the ADSP-2100. The CONVST signal can be supplied from the TMS32010 AD7862* ADSP-2100 or from an external source. The AD7862 BUSY line provides an interrupt to the ADSP-2100 when conversion is completed on all four channels. The four conversion results can INT BUSY then be read from the AD7862 using four successive reads to DEN RD the same memory address. The following instruction reads one of the four results (this instruction is repeated four times to read DB11 all four results in sequence): DB0 MR0 = DM(ADC) D15 where MR0 is the ADSP-2100 MR0 register, and ADC is the DATA BUS D0 AD7862 address. * ADDITIONAL PINS OMITTED FOR CLARITY DMA13 Figure 15. AD7862–TMS32010 Interface OPTIONAL ADDRESS BUS DMA0 AD7862–TMS320C25 Interface Figure 16 shows an interface between the AD7862 and the CONVST ADDR CS TMS320C25. As with the two previous interfaces, conversion DECODE can be initiated from the TMS320C25 or from an external DMS EN A0 source, and the processor is interrupted when the conversion AD7862* ADSP-2100 sequence is completed. The TMS320C25 does not have a (ADSP-2101/ separate RD output to drive the AD7862 RD input directly. ADSP-2102) This has to be generated from the processor STRB and R/W outputs with the addition of some logic gates. The RD signal is IRQn BUSY OR-gated with the MSC signal to provide the one WAIT state DMRD (RD) RD required in the read cycle for correct interface timing. Conver- sion results are read from the AD7862 using the following DB11 instruction: DB0 IN D,ADC DMD15 DATA BUS where D is Data Memory address and ADC is the AD7862 DMD0 address. * ADDITIONAL PINS OMITTED FOR CLARITY OPTIONAL Figure 14. AD7862–ADSP-2100 Interface A15 ADDRESS BUS AD7862–ADSP-2101/ADSP-2102 INTERFACE A0 The interface outlined in Figure 14 also forms the basis for an interface between the AD7862 and the ADSP-2101/ADSP-2102. ADDR CONVST DECODE A0 The READ line of the ADSP-2101/ADSP-2102 is labeled RD. CS IS EN In this interface, the RD pulse width of the processor can be programmed using the Data Memory Wait State Control Register. TMS320C25 AD7862* The instruction used to read one of the four results is outlined INTn BUSY for the ADSP-2100. AD7862–TMS32010 Interface STRB RD R/W An interface between the AD7862 and the TMS32010 is shown in Figure 15. Once again, the CONVST signal can be supplied READY from the TMS32010 or from an external source, and the DB11 TMS32010 is interrupted when both conversions have been MSC DB0 completed. The following instruction is used to read the conver- sion results from the AD7862: D15 DATA BUS IN D,ADC D0 where D is Data Memory address, and ADC is the AD7862 *ADDITIONAL PINS OMITTED FOR CLARITY address. Figure 16. AD7862–TMS320C25 Interface REV. 0 –13– AD7862 Some applications may require that the conversion be initiated A15 by the microprocessor rather than an external timer. One option ADDRESS BUS A1 is to decode the AD7862 CONVST from the address bus so that a write operation starts a conversion. Data is read at the ADDR A0 80C196 end of the conversion sequence as before. Figure 18 shows an DECODE CS example of initiating conversion using this method. Note that for all interfaces, it is preferred that a read operation not be AD7862* attempted during conversion. AD7862–MC68000 Interface CONVST WR An interface between the AD7862 and the MC68000 is shown RD RD in Figure 17. As before, conversion can be supplied from the MC68000 or from an external source. The AD7862 BUSY line DB11 can be used to interrupt the processor or, alternatively, software DB0 delays can ensure that conversion has been completed before a read to the AD7862 is attempted. Because of the nature of its D15 interrupts, the 68000 requires additional logic (not shown in ADDRESS/DATA BUS D0 Figure 18) to allow it to be interrupted correctly. For further *ADDITIONAL PINS OMITTED FOR CLARITY information on 68000 interrupts, consult the 68000 user’s manual. Figure 18. AD7862–8086 Interface The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7862. CS is used to drive Vector Motor Control the 68000 DTACK input to allow the processor to execute a The current drawn by a motor can be split into two compo- normal read operation to the AD7862. The conversion results nents: one produces torque, and the other produces magnetic are read using the following 68000 instruction: flux. For optimal performance of the motor, these two compo- nents should be controlled independently. In conventional MOVE.W ADC,D0 methods of controlling a three-phase motor, the current (or where D0 is the 68000 D0 register, and ADC is the AD7862 voltage) supplied to the motor and the frequency of the drive are address. the basic control variables; however, both the torque and flux are functions of current (or voltage) and frequency. This OPTIONAL coupling effect can reduce the performance of the motor A15 ADDRESS BUS because, if the torque is increased by increasing the frequency, A0 for example, the flux tends to decrease. ADDR CONVST Vector control of an ac motor involves controlling phase in A0 DECODE addition to drive and current frequency. Controlling the phase MC68000 CS EN of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. AD7862* DTACK Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque AS RD and flux components. The AD7862, with its four-channel R/W simultaneous sampling capability, is ideally suited for use in vector motor control applications. DB11 A block diagram of a vector motor control application using the DB0 AD7862 is shown in Figure 19. The position of the field is derived by determining the current in each phase of the motor. D15 DATA BUS Only two phase currents need to be measured because the third D0 can be calculated if two phases are known. V and V of the A1 A2 *ADDITIONAL PINS OMITTED FOR CLARITY AD7862 are used to digitize this information. Figure 17. AD7862–MC68000 Interface Simultaneous sampling is critical to maintain the relative phase AD7862–80C196 Interface information between the two channels. A current sensing Figure 18 shows an interface between the AD7862 and the isolation amplifier, transformer or Hall effect sensor is used 80C196 microprocessor. Here, the microprocessor initiates between the motor and the AD7862. Rotor information is conversion. This is achieved by gating the 80C196 WR signal obtained by measuring the voltage from two of the inputs to the with a decoded address output (different to the AD7862 CS motor. V and V of the AD7862 are used to obtain this B1 B2 address). The AD7862 BUSY line is used to interrupt the information. Once again, the relative phase of the two channels microprocessor when the conversion sequence is completed. is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7862. REV. 0 –14– AD7862 of AD7862 number 1 is used to drive the reference input of all DSP MICROPROCESSOR other AD7862s in the circuit shown in Figure 20. One VREF I C pin can drive several AD7862 REF IN pins. Alternatively, an DAC TORQUE & FLUX external or system reference can be used to drive all VREF I V CONTROL LOOP 3 DRIVE B B PHASE CALCULATIONS & inputs. A common reference ensures good full-scale tracking DAC CIRCUITRY MOTOR TWO TO THREE V A PHASE between all channels. I INFORMATION A DAC TORQUE SETPOINT V A1 RD RD V B1 ISOLATION AMPLIFIERS AD7862(1) V FLUX A2 SETPOINT V A1 V CS B2 TRANSFORMATION TO TORQUE & VREF FLUX CURRENT V A2 COMPONENTS AD7862* V B1 V V A1 B2 RD V VOLTAGE B1 *ADDITIONAL PINS OMITTED FOR CLARITY ATTENUATORS AD7862(2) ADDRESS V A2 DECODE ADDRESS CS Figure 19. Vector Motor Control Using the AD7862 V B2 REF IN MULTIPLE AD7862S Figure 20 shows a system where a number of AD7862s can be configured to handle multiple input channels. This type of REF IN configuration is common in applications such as sonar, radar, RD V A1 etc. The AD7862 is specified with typical limits on aperture V delay. This means that the user knows the difference in the B1 AD7862(n) sampling instant between all channels. This allows the user to V A2 maintain relative phase information between the different CS V B2 channels. A common read signal from the microprocessor drives the RD Figure 20. Multiple AD7862s in Multichannel System input of all AD7862s. Each AD7862 is designated a unique address selected by the address decoder. The reference output REV. 0 –15– AD7862 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Plastic DIP 28-Pin Small Outline Package (N-28) (R-28) 1.565 (39.70) 0.7125 (18.10) 1.380 (35.10) 0.6969 (17.70) 28 15 28 15 0.580 (14.73) 0.485 (12.32) 1 14 0.625 (15.87) 0.195 (4.95) PIN 1 0.060 (1.52) 0.125 (3.18) 0.600 (15.24) 1 14 0.250 0.015 (0.38) (6.35) MAX 0.150 (3.81) PIN 1 0.1043 (2.65) 0.0291 (0.74) MIN x 45° 0.0926 (2.35) 0.015 (0.381) 0.0098 (0.25) 0.200 (5.05) 0.022 (0.558) 0.100 0.070 SEATING 0.008 (0.204) 0.125 (3.18) (2.54) (1.77) 0.014 (0.356) PLANE BSC MAX 0.0500 (1.27) 8° 0.0500 0.0118 (0.30) 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Pin Shrink Small Outline Package 28-Pin Cerdip (RS-28) (Q-28) 0.407 (10.34) 0.005 (0.13) MIN 0.100 (2.54) MAX 0.397 (10.08) 28 15 28 15 0.610 (15.49) 0.500 (12.70) 114 0.620 (15.75) PIN 1 0.015 1 14 1.490 (37.85) MAX 0.590 (14.99) (0.38) 0.225 MIN (5.72) 0.150 MAX 0.018 (0.46) (3.81) 0.07 (1.79) 0.078 (1.98) PIN 1 0.008 (0.20) MIN 0.066 (1.67) 0.068 (1.73) 0.200 (5.08) SEATING 15° 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) 0.125 (3.18) PLANE 0° 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE 0.002 (0.050) BSC 0.005 (0.127) –16– REV. 0 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.2992 (7.60) 0.205 (5.21) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. C2211–12–10/96