ANALOG DEVICES AD7861

11-Bit Resolution a Simultaneous Sampling A/D Converter AD7861 FEATURES FUNCTIONAL BLOCK DIAGRAM 11-Bit Resolution Analog-to-Digital Converter REF IN BUSY Seven Single-Ended Analog Inputs Four Input Channels Simultaneously Sampled 2.5V REF OUT A0 REFERENCE A1 Expansion with 4 Multiplexed Inputs Internal 2.5 V Reference VIN1 D0 12 3.2 �s Conversion Time per Channel VIN2 11-BIT D11 SHA OUTPUT ADC VIN3 User Definable Channel Sequencing REGISTERS RD Single Supply +5 V Operation CS Double Buffered Register Outputs CLKIN AUX0 6.25 MHz to 12.5 MHz Operating Clock Range AUX1 4-1 SGND MUX APPLICATIONS AUX2 AGND AUX3 Motor Control AD7861 DGND S0 V 3-Phase Power Measurement DD S1 Cellular Phones Data Acquisition CONVST RESET M0 M1 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7861 is a multichannel simultaneous sampling A/D Simultaneous Sampling of Four Inputs Converter (ADC) configured for the acquisition of voltage Four channel sample and hold amplifier (SHA) allows out of inputs in a motor control solution or three-phase power system. phase input signals to be sampled simultaneously, preserving the relative phase information. Sample-and-hold acquisition The AD7861 combined with Analog Devices’ 16-bit fixed- time is 1.6 µs and conversion time per channel is 3.2 µs (using point digital signal processor (DSP) provides a low cost 16-bit a 12.5 MHz system clock). fixed-point microcontroller solution. Flexible Analog Channel Sequencing The input stage has been designed to accommodate the types of AD7861 supports acquisition of 2, 3 or 4 channels per group. signals frequently found in motor drives. The VIN1, VIN2, and Converted channel results are stored in registers and the data VIN3 channels are simultaneously sampled inputs suitable for can be read in any order. The sampling and conversion time stator current acquisition. The AUX0–AUX3 channels are for two channels is 8 µs, three channels is 11.2 µs, and four multiplexed and are suitable for slower moving inputs such as channels is 14.4 µs (using a 12.5 MHz system clock). temperature and bus voltage of the diode rectifier output in a motor control application. Single 5 V dc Operation Low power, digital process. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 (V = 5 V � 5%; T = –40�C to +85�C; REFIN = 2.5 V; Ext CLK @ 12.5 MHz, unless DD A otherwise noted) AD7861–SPECIFICATIONS Parameter AD7861AP Units Conditions/Comments DC ACCURACY Resolution 11 Bits Twos Complement Data Format Relative Accuracy ±2 LSB max Integral Nonlinearity Differential Nonlinearity ±2.5 LSB max Bias Offset Error ±9 LSB max Any Channel Bias Offset Error Match 4 LSB max Between Channels Full-Scale Error ±13 LSB max Any Channel Full-Scale Error Match 4 LSB max Between Channels DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 60 dB min f = 1 kHz Sine Wave, f = 75 kHz IN SAMPLE Total Harmonic Distortion (THD) –60 dB max f = 1 kHz Sine Wave, f = 75 kHz IN SAMPLE Peak Harmonic or Spurious Noise –60 dB max f = 1 kHz Sine Wave, f = 75 kHz IN SAMPLE Channel-to-Channel Isolation M1 = 0 –58 dB max 1 kHz Sine Wave Applied to Unselected Channels M1 = 1 –53 dB max 1 kHz Sine Wave Applied to Unselected Channels REFERENCE Input Voltage Range (REF IN) 2.5 V Input Current 50 µA max Onboard Reference Output (REF OUT) 2.5 V Reference Tolerance ±5% Reference Drive Capability ±100 µA max SAMPLE-AND-HOLD Acquisition Time 1.6 µs 20 CLK Cycles @ 12.5 MHz Aperture Delay Time 200 ns max Aperture Delay Time Match 20 ns max Droop Rate 5 mV/ms max LOGIC Input High Voltage (V ) 2 V min IH Input Low Voltage (V ) 0.8 V max IL Input Leakage Current 1 µA max Input Capacitance 20 pF typ (V ) 4.5 V min I Current = 20 µA, V = 5 V OH SOURCE DD (V ) 0.4 V max I Current = 400 µA, V = 5 V OL SINK DD Three-State Leakage Current 1 µA max CONVERSION RATE Conversion Time/Channel 40 CLK Cycles CONVST Pulsewidth 2 CLK Cycles min ANALOG INPUTS Nominal Input Level 0–5 V VIN1, VIN2, VIN3, AUX0–AUX3 Input Current 100 µA Input Capacitance 10 pF SYSTEM CLOCK 6.25–12.5 MHz POWER REQUIREMENTS V 5V dc DD I 10 mA max DD – 2 – REV. B AD7861 Table I. AD7861 Timing Parameters (T = –40�C to +85�C and V = +5 V unless otherwise noted) A DD Number Symbol AD7861 Timing Requirements Min Max Units 1t csb_rdb CS Low Before Falling Edge of RD 0– ns su 2t addr_rdb ADDR Valid Before Falling Edge of RD 0– ns su 3t rdb_data DATA Valid After Falling Edge of RD –25 ns dly 4t rdb RD Pulsewidth, Low 25 – ns pwl 5t rdb RD Pulsewidth, High 25 – ns pwh 6t rdb_data DATA Hold After Rising Edge of RD 10 – ns hd 7t rdb_addr ADDR Hold After Rising Edge of RD 0– ns hd 8t rdb_csb CS Hold After Rising Edge of RD 0– ns hd 9t clk CLK Period 80 160 ns per 10 t clk CLK Pulsewidth, High 20 – ns pwh 11 t clk CLK Pulsewidth, Low 20 – ns pwl 12 t resetb RESET Pulsewidth, Low 2 × tperclk – ns pwl ABSOLUTE MAXIMUM RATINGS* Supply Voltage (V ) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V DD CLK Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V DD 1, 2 Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V DD CS Analog Reference Input Voltage . . . . . . . . . . . –0.3 V to V DD 7, 8 Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V DD Analog Reference Output Swing . . . . . . . . . . . –0.3 V to V DD A0–A1 Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C 4 5 Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C RD * Stresses above those listed under Absolute Maximum Ratings may cause perma- 3 6 nent damage to the device. This is a stress rating only; functional operation of the DATA device at these or any other conditions above those indicated in the operational BUS section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1. Clock and Reset Timing 9 10 11 ORDERING GUIDE CLK Model Temperature Range Package Option CLK AD7861AP –40°C to +85°C P-44A 12 RESET Figure 2. Write Cycle Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7861 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– AD7861 PIN DESCRIPTION PIN CONFIGURATION Pin Mnemonic Type Description 1 AUX0 I/P Auxiliary Input 0 2 REFIN I/P Analog Reference Input 64 5 4 3 21 44 4324140 3 AGND GND Analog Ground 4 REFOUT O/P Internal 2.5 Analog Reference PIN 1 D0 7 39 NC IDENTIFIER 5 S0 I/P Aux Channel Select 0 D1 8 38 NC 6 S1 I/P Aux Channel Select 1 D2 9 37 VIN1 7 D0 O/P Data Bit 0 LSB (Tied Low) D3 10 36 V DD 8 D1 O/P Data Bit 1 D4 11 35 SGND AD7861 9 D2 O/P Data Bit 2 D5 12 TOP VIEW 34 DGND (Not to Scale) 10 D3 O/P Data Bit 3 D6 13 33 DGND 11 D4 O/P Data Bit 4 D7 14 32 CLK 12 D5 O/P Data Bit 5 15 31 BUSY D8 13 D6 O/P Data Bit 6 16 30 NC D9 14 D7 O/P Data Bit 7 17 A0 D10 29 15 D8 O/P Data Bit 8 18 19 20 21 22 23 24 25 26 27 28 16 D9 O/P Data Bit 9 17 D10 O/P Data Bit 10 NC = NO CONNECT 18 D11 O/P Data Bit 11, MSB 19 DGND GND Logic Ground 20 DGND GND Logic Ground 21 V SUP +5 V Digital Supply DD 22 M0 I/P Conversion Mode Select 0 23 M1 I/P Conversion Mode Select 1 Pin Types Pin Types 24 CONVST I/P A/D Conversion Start I/P = Input Pin GND = Ground Pin 25 CS I/P Chip Select O/P = Output Pin SUP = Supply Pin 26 RD I/P Read Input 27 RESET I/P Chip Reset 28 A1 I/P Register Address Select 1 29 A0 I/P Register Address Select 0 30 NC NC No Connect 31 BUSY O/P Busy, Conversion in Process 32 CLK I/P External Clock Input 6.25 MHz-12.5 MHz 33–34 DGND GND Logic Ground 35 SGND GND Signal Ground 36 V SUP +5 V Analog Supply DD 37 VIN1 I/P Analog Input 1 38–39 NC NC No Connect 40 VIN2 I/P Analog Input 2 41 VIN3 I/P Analog Input 3 42 AUX3 I/P Auxiliary Input 3 43 AUX2 I/P Auxiliary Input 2 44 AUX1 I/P Auxiliary Input 1 –4– REV. B D11 S1 S0 DGND DGND REFOUT V AGND DD REFIN M0 M1 AUX0 CONVST AUX1 CS AUX2 AUX3 RD VIN3 RESET A1 VIN2 AD7861 ANALOG INPUT BLOCK The user must select which channels to convert using M0/M1, a The AD7861 is an 11-bit resolution, successive approximation minimum of two clock cycles before the start of conversion. analog-to-digital (A/D) converter with twos complement output The AD7861 provides 4 auxiliary input channels which can be data format. The analog input range is 0 V–5 V with a 2.5 V individually multiplexed into the auxiliary ADC channel. Pins S0/ reference as defined by the reference input pin (REFIN). The S1 are used to multiplex these auxiliary channels according to the AD7861 has an internal 2.5 V ± 5% reference, which is utilized following table. It is important to note that the ADC performs a by connecting the reference output pin (REFOUT) to the series of conversions based on the input voltage on each pin REFIN pin. (including the AUX pin) at the start of the CONVST conversion The A/D conversion time is determined by the system clock pulse. The user must select the auxiliary channel using S0/S1 frequency, which can range from 6.25 MHz to 12.5 MHz. a minimum of two clock cycles before the start of the conversion Forty clock cycles are required to complete each conversion. sequence. There is a 4-channel simultaneous sample and hold amplifier (SHA) at the AD7861 input stage. This allows up to 4 channels to S1 S0 Channel Selected be simultaneously held and sequentially digitized. The SHA 0 0 AUX0 acquisition time is 20 clock cycles and is independent of the 0 1 AUX1 number of channels sampled. 1 0 AUX2 The minimum throughput time can be calculated as follows: 1 1 AUX3 t = t + (n× t ) AA SHA CONV where t = analog acquisition time, t = SHA acquisition AA SHA DIGITAL INTERFACE time, n = # channels, t = conversion time per channel CONV The AD7861 is designed to interface with the ADSP-21xx (40 clock cycles). family of DSPs. The 12-bit parallel interface can also be used A/D conversions are initiated by an external analog sample with other DSPs and microcontrollers. clock pin (CONVST). The 11-bit A/D conversion output occupies the 11 most significant bits of the 12-bit interface. The LSB (Data Bit 0) is The CONVST input can be run asynchronous to the AD7861 tied low. system clock. When CONVST is run asynchronous from CLK, the falling edge of CLK subsequent to CONVST high initiates REGISTER BASED INPUT/OUTPUT the conversion. To facilitate integration into most designs, a register based input/output structure is provided. These registers can be BUSY memory mapped into the user’s system along with other The AD7861 BUSY pin goes low at the start of conversion, and memory mapped peripherals. remains low for 40 clock cycles per channel. When BUSY goes high, this indicates that the output data buffers have been REGISTER ADDRESSING updated. Data from the previous conversion can be read up to Two address lines (A0 through A1) are used in conjunction with (n × 40 – 1) clock cycles after the start of conversion (n = control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or number of channels converted). Refer to Figure 3. AUX. These control lines are active low. Timing and logical sense is as for the ADSP-2100 family. t = (n x 40 –1) CLOCK CYCLES t = 1 CLOCK CYCLE t = n x 40 CLOCK CYCLES Pin Function CLK CS Enables the AD7861 Register Interface (n x 40 –1) CLOCK CYCLES RD Places the Internal Register on the Data Bus BUSY REGISTER LISTING CONVST The output of each channel is stored in its respective register. The symbolic names and address locations are listed in the OLD DATA VALID NEW DATA VALID DATA following table. Figure 3. Busy Pulse Timing Name A1 A0 Register Function CHANNEL SELECTION VIN1 0 0 A/D Conversion Result Channel VIN1 Determining which channels are converted is dependent on the VIN2 0 1 A/D Conversion Result Channel VIN2 settings of M0 and M1. The available channel combinations are: VIN3 1 0 A/D Conversion Result Channel VIN3 AUX 1 1 A/D Conversion Result Channel AUX M1 M0 Channels Converted 0 0 VIN2, VIN3 0 1 VIN2, VIN3, AUX 1 0 VIN1, VIN2, VIN3 1 1 VIN1, VIN2, VIN3, AUX REV. B –5– AD7861 DESCRIPTION OF THE REGISTERS DIGITAL SIGNAL PROCESSOR INTERFACING VIN1, VIN2, VIN3 These registers contain the results from The AD7861 A/D converter is designed to be easily interfaced the conversion of the analog input voltages. to Analog Devices’ family of Digital Signal Processors (DSPs). Figure 5 shows the interface between the AD7861 and the AUX In the AD7861, this register contains the ADSP-2101/2105/2115 16-bit fixed point DSP, and the ADSP- conversion result of the auxiliary channel 2171 and ADSP-2181 DSP Microcomputers. FLAGOUT from which had been selected by S0, S1. the DSP is used to initiate the AD7861 conversion and is also Reading Results used in conjunction with the BUSY signal to provide an end of The A/D conversion results for channels VIN1, VIN2, VIN3 conversion interrupt for the DSP. With M0 and M1 tied low, and AUX are stored in the VIN1, VIN2, VIN3 and AUX the AD7861 is set up in the VIN2, VIN3 channel conversion registers respectively. The twos complement data is left justified mode. By mapping the 12-bit AD7861 data bus into the top 12 and the LSB (Data Bit 0) is set to zero. The relationship bits of the DSP data bus (D12–D23), full-scale outputs from the between input voltage and output coding is shown in Figure 4. AD7861 can be represented as ±1.0 in fixed point arithmetic. OUTPUT The AD7861 can operate with a clock frequency in the range of FULL-SCALE CODE TRANSITION 6.25 MHz to 12.5 MHz. For the ADSP-2101/2105/2115 the CLKOUT frequency is the system clock frequency. In the case 011111111110 of the ADSP-2171/2181, the system clock is internally scaled, a 10 MHz system clock will result in a 20 MHz CLKOUT FS = 5V frequency. If CLKOUT from the ADSP-2171/2181 is above 5V 000000000000 LSB = 12.5 MHz, then an external clock divide down circuit will be 2048 necessary. 100000000000 ADDRESS BUS 0V 5V-1LSB 2.5 INPUT VOLTAGE A0–A13 ADDRESS A0–A1 Figure 4. AD7861 Transfer Function DECODE CS DMS EN Power Supply Connections and Setup ADSP-2101/ The nominal power supply level (V ) is +5 V ± 5%. The DD BUSY ADSP-2105/ IRQ2 AD7861 positive power supply (V ) should be connected to Pins 21 DD ADSP-2115–12MHz CONVST FLAGOUT and 36. The SGND and DGND pins should be star point ADSP-2171–10MHz RD RD connected to AGND at a point close to the AD7861. ADSP-2181–10MHz CLKOUT CLK Power supplies should be bypassed at the power pins using a M0 0.1µF capacitor. A 200 nF capacitor should also be connected M1 D0–D23 D0–D11* between REFIN and SGND. DATA BUS Figure 5. ADI Digital Signal Processor/Microcomputer Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leadless Chip Carrier (P-44A) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.048 (1.21) 0.025 (0.63) 0.042 (1.07) 0.042 (1.07) 0.015 (0.38) 0.048 (1.21) 6 40 0.042 (1.07) 7 39 PIN 1 0.050 IDENTIFIER 0.63 (16.00) (1.27) BSC 0.59 (14.99) 0.021 (0.53) TOP VIEW (PINS DOWN) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.040 (1.01) 0.020 0.656 (16.66) (0.50) 0.025 (0.64) SQ R 0.650 (16.51) 0.110 (2.79) 0.695 (17.65) 0.085 (2.16) SQ 0.685 (17.40) –6– REV. B PRINTED IN U.S.A. C2073a–1.5–3/00 (rev. B)