ANALOG DEVICES AD7859

3 V to 5 V Single Supply, 200 kSPS a 8-Channel, 12-Bit Sampling ADCs AD7859/AD7859L FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for V of 3 V to 5.5 V DD AV AGND DD AD7859–200 kSPS; AD7859L–100 kSPS System and Self-Calibration Low Power AD7859/AD7859L AIN1 I/P Normal Operation T/H MUX DV AD7859: 15 mW (V = 3 V) DD AIN8 DD AD7859L: 5.5 mW (V = 3 V) DD 2.5V Using Automatic Power-Down After Conversion (25 mW) REFERENCE COMP AD7859: 1.3 mW (V = 3 V 10 kSPS) DD REF / IN AD7859L: 650 mW (V = 3 V 10 kSPS) REF BUF DD OUT DGND Flexible Parallel Interface: 16-Bit Parallel/8-Bit Parallel CHARGE 44-Pin PQFP and PLCC Packages REDISTRIBUTION C REF1 DAC APPLICATIONS CLKIN Battery-Powered Systems (Personal Digital Assistants, C REF2 CONVST SAR + ADC Medical Instruments, Mobile Communications) CALIBRATION MEMORY CONTROL BUSY AND Pen Computers CONTROLLER SLEEP Instrumentation and Control Systems CAL High Speed Modems PARALLEL INTERFACE/CONTROL REGISTER GENERAL DESCRIPTION The AD7859/AD7859L are high speed, low power, 8-channel, WR DB15 – DB0 RD CS W/B 12-bit ADCs which operate from a single 3 V or 5 V power supply, the AD7859 being optimized for speed and the AD7859L for low power. The ADC contains self-calibration PRODUCT HIGHLIGHTS and system calibration options to ensure accurate operation over 1. Operation with either 3 V or 5 V power supplies. time and temperature and have a number of power-down 2. Flexible power management options including automatic options for low power applications. power-down after conversion. The AD7859 is capable of 200 kHz throughput rate while the 3. By using the power management options a superior power AD7859L is capable of 100 kHz throughput rate. The input performance at slower throughput rates can be achieved. track-and-hold acquires a signal in 500 ns and features a pseudo- AD7859: 1 mW typ @ 10 kSPS differential sampling scheme. The AD7859 and AD7859L input AD7859L: 1 mW typ @ 20 kSPS voltage range is 0 to V (unipolar) and –V /2 to +V /2 REF REF REF 4. Operates with reference voltages from 1.2 V to the supply. about V /2 (bipolar) with both straight binary and 2s comple- REF 5. Analog input ranges from 0 V to V . DD ment output coding respectively. Input signal range is to the 6. Self and system calibration. supply and the part is capable of converting full-power signals to 100 kHz. 7. Versatile parallel I/O port. 8. Lower power version AD7859L. CMOS construction ensures low power dissipation of typically 5.4 mW for normal operation and 3.6 μW in power-down mode. The part is available in 44-pin, plastic quad flatpack package (PQFP) and plastic lead chip carrier (PLCC). See page 28 for data sheet index. REV. A Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1996 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 1, 2 (AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V AD7859/AD7859L–SPECIFICATIONS DD DD IN OUT External Reference, f = 4 MHz (for L Version: 1.8 MHz (08C to +708C) and 1 MHz (–408C to +858C)); f = 200 kHz (AD7859) 100 kHz CLKIN SAMPLE (AD7859L); SLEEP = Logic High; T = T to T , unless otherwise noted.) Specifications in () apply to the AD7859L. A MIN MAX 1 1 Parameter A Version B Version Units Test Conditions/Comments DYNAMIC PERFORMANCE 3 Signal to Noise + Distortion Ratio 70 71 dB min Typically SNR is 72 dB (SNR) V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (for L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Total Harmonic Distortion (THD) –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (for L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Peak Harmonic or Spurious Noise –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (for L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Intermodulation Distortion (IMD) = 200 kHz Second Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f SAMPLE (for L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Third Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 200 kHz SAMPLE (for L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Channel-to-Channel Isolation –80 –80 dB typ V = 25 kHz IN DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity ±1 ±0.5 LSB max 5 V Reference V = 5 V DD Differential Nonlinearity ±1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits Unipolar Offset Error ±5 ±5 LSB max ±2 ±2 LSB typ Unipolar Offset Error Match 2(3) 2 LSB max Positive Full-Scale Error ±5 ±5 LSB max ±2 ±2 LSB typ Negative Full-Scale Error ±2 ±2 LSB max Full-Scale Error Match 1 1 LSB max Bipolar Zero Error ±1 ±1 LSB typ Bipolar Zero Error Match 2 2 LSB typ ANALOG INPUT Input Voltage Ranges 0 to V 0 to V Volts i.e., AIN(+) – AIN(–) = 0 to V , AIN(–) Can Be REF REF REF Biased Up But AIN(+) Cannot Go Below AIN(–) ±V /2 ±V /2 Volts i.e., AIN(+) – AIN(–) = –V /2 to +V /2, AIN(–) REF REF REF REF Should Be Biased to +V /2 and AIN(+) Can Go REF Below AIN(–) But Cannot Go Below 0 V Leakage Current ±1 ±1 μA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REF Input Voltage Range 2.3/V 2.3/V V min/max Functional from 1.2 V IN DD DD Input Impedance 150 150 kΩ typ REF Output Voltage 2.3/2.7 2.3/2.7 V min/max OUT REF Tempco 20 20 ppm/°C typ OUT LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min AV = DV = 4.5 V to 5.5 V INH DD DD 2.1 2.1 V min AV = DV = 3.0 V to 3.6 V DD DD CAL Pin 3 3 V min AV = DV = 4.5 V to 5.5 V DD DD 2.4 2.4 V min AV = DV = 3.0 V to 3.6 V DD DD Input Low Voltage, V 0.8 0.8 V max AV = DV = 4.5 V to 5.5 V INL DD DD 0.6 0.6 V max AV = DV = 3.0 V to 3.6 V DD DD Input Current, I ±10 ±10 μA max Typically 10 nA, V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 4 4 V min AV = DV = 4.5 V to 5.5 V OH DD DD 2.4 2.4 V min AV = DV = 3.0 V to 3.6 V DD DD Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK Floating State Leakage Current ±10 ±10 μA max 4 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range 2s Complement Bipolar Input Range –2– REV. A AD7859/AD7859L 1 1 Parameter A Version B Version Units Test Conditions/Comments CONVERSION RATE t × 18 CLKIN Conversion Time 4.5 (10) 4.5 μs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN) Track/Hold Acquisition Time 0.5 (1) 0.5 μs min (L Versions Only, –40°C to +85°C, 1.8 MHz CLKIN) POWER REQUIREMENTS AV DV +3.0/+5.5 +3.0/+5.5 V min/max DD, DD I DD 5 Normal Mode 5.5 (1.95) 5.5 mA max AV = DV = 4.5 V to 5.5 V. Typically 4.5 mA DD DD 5.5 (1.95) 5.5 mA max AV = DV = 3.0 V to 3.6 V. Typically 4.0 mA DD DD 6 Sleep Mode With External Clock On 10 10 μA typ Full Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0. 400 400 μA typ Partial Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 5 5 μA max Typically 1 μA. Full Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0. 200 200 μA typ Partial Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 30 (10) 30 (10) mW max V = 5.5 V: Typically 25 mW (8); SLEEP = V DD DD 20 (6.5) 20 (6.5) mW max V = 3.6 V: Typically 15 mW (5.4); SLEEP = V DD DD Sleep Mode Power Dissipation With External Clock On 55 55 μW typ V = 5.5 V; SLEEP = 0 V DD 36 36 μW typ V = 3.6 V; SLEEP = 0 V DD With External Clock Off 27.5 27.5 μW max V = 5.5 V: Typically 5.5 μW; SLEEP = 0 V DD 18 18 μW max V = 3.6 V: Typically 3.6 μW; SLEEP = 0 V DD SYSTEM CALIBRATION 7 Offset Calibration Span +0.05 × V /–0.05 × V V max/min Allowable Offset Voltage Span for Calibration REF REF 7 Gain Calibration Span +1.025 × V /–0.975 × V V max/min Allowable Full-Scale Voltage Span for Calibration REF REF NOTES 1 Temperature range as follows: A, B Versions, –40°C to +85°C. 2 Specifications apply after calibration. 3 SNR calculation includes distortion and noise components. 4 Not production tested, guaranteed by characterization at initial product release. 5 All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV . No load on the digital outputs. Analog inputs @ AGND. DD 6 CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV . No load on the digital outputs. DD Analog inputs @ AGND. 7 The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V , REF and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V ± 0.025 × V ). REF REF This is explained in more detail in the calibration section of the data sheet. Specifications subject to change without notice. REV. A –3– AD7859/AD7859L (AV = DV = +3.0 V to +5.5 V; f = 4 MHz for AD7859 and 1.8 MHz for AD7859L; DD DD CLKIN 1 T = T to T , unless otherwise noted) TIMING SPECIFICATIONS A MIN MAX Limit at T , T MIN MAX (A, B Versions) Parameter 5 V 3 V Units Description 2 f 500 500 kHz min Master Clock Frequency CLKIN 4 4 MHz max 1.8 1.8 MHz max L Version 3 t 100 100 ns min CONVST Pulse Width 1 t 50 90 ns max CONVST to BUSY ↑ Propagation Delay 2 t 4.5 4.5 μs max Conversion Time = 18 t CONVERT CLKIN 10 10 μs max L Version 1.8 MHz CLKIN. Conversion Time = 18 t CLKIN t 15 15 ns min HBEN to RD Setup Time 3 t 5 5 ns min HBEN to RD Hold Time 4 t 0 0 ns min CS to RD to Setup Time 5 t 0 0 ns min CS to RD Hold Time 6 t 55 55 ns min RD Pulse Width 7 4 t 50 50 ns max Data Access Time After RD 8 5 t 5 5 ns min Bus Relinquish Time After RD 9 40 40 ns max Bus Relinquish Time After RD t 60 70 ns min Minimum Time Between Reads 10 t 0 0 ns min HBEN to WR Setup Time 11 t 5 5 ns max HBEN to WR Hold Time 12 t 0 0 ns min CS to WR Setup Time 13 t 0 0 ns max CS to WR Hold Time 14 t 55 70 ns min WR Pulse Width 15 t 10 10 ns min Data Setup Time Before WR 16 t 5 5 ns min Data Hold Time After WR 17 4 t 1/2 t 1/2 t ns min New Data Valid Before Falling Edge of BUSY 18 CLKIN CLKIN t 2.5 t 2.5 t ns max CS ↑ to BUSY ↑ in Calibration Sequence 19 CLKIN CLKIN 6 t 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013 CAL t ) CLKIN 6 t 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock CAL1 Dependent (111124 t ) CLKIN 6 t 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent CAL2 (13889 t ) CLKIN NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD 2 Mark/Space ratio for the master clock input is 40/60 to 60/40. 3 The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power- Down section). 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated 9 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 9 time of the part and is independent of the bus loading. 6 The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice. –4– REV. A AD7859/AD7859L 1 ABSOLUTE MAXIMUM RATINGS 1.6mA I OL (T = +25°C unless otherwise noted) A AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD TO OUTPUT +2.1V AV to DV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V PIN DD DD 50pF Analog Input Voltage to AGND . . . . –0.3 V to AV + 0.3 V DD Digital Input Voltage to DGND . . . . –0.3 V to DV + 0.3 V DD 200µA I Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V OH DD REF /REF to AGND . . . . . . . . . –0.3 V to AV + 0.3 V IN OUT DD 2 Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA Figure 1. Load Circuit for Digital Output Timing Operating Temperature Range Specifications Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C ORDERING GUIDE Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Linearity Power PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW Error Dissipation Package θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W JA 1 2 Lead Temperature, Soldering Model (LSB) (mW) Option Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C AD7859AP ±1 15 P-44A Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C AD7859AS ±1 15 S-44 PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW AD7859BS ±1/2 15 S-44 θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 55°C/W JA 3 AD7859LAS ±1 5.5 S-44 Lead Temperature, Soldering 4 EVAL-AD7859CB Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C 5 EVAL-CONTROL BOARD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kV NOTES 1 Linearity error refers to the integral linearity error. NOTES 2 P = PLCC; S = PQFP. 1 Stresses above those listed under “Absolute Maximum Ratings” may cause 3 L signifies the low power version. permanent damage to the device. This is a stress rating only and functional 4 This can be used as a stand-alone evaluation board or in conjunction with the operation of the device at these or any other conditions above those listed in the EVAL-CONTROL BOARD for evaluation/demonstration purposes. operational sections of this specification is not implied. Exposure to absolute 5 This board is a complete unit allowing a PC to control and communicate with maximum rating conditions for extended periods may affect device reliability. all Analog Devices, Inc. evaluation boards ending in the CB designators. 2 Transient currents of up to 100 mA will not cause SCR latchup. For more information on Analog Devices products and evaluation boards, visit our World Wide Web home page at http://www.analog.com. PINOUT FOR PQFP PINOUT FOR PLCC 6 5 4 3 21 44 43 42 41 40 NC 7 39 NC NC 1 PIN NO. 1 IDENTIFIER 33 NC 8 DB11 W/B 38 2 32 W/B DB11 REF /REF 37 9 DB10 IN OUT 3 REF /REF 31 DB10 IN OUT AV 36 10 DB9 DD AV 4 30 DD DB9 AGND 11 35 DB8/HBEN AD7859 AGND 5 29 DB8/HBEN C 12 34 TOP VIEW DGND REF1 AD7859 (Not to Scale) C 6 28 DGND REF1 C DV TOP VIEW 13 33 REF2 DD (Not to Scale) C 7 DV REF2 27 DD AIN0 14 32 DB7 AIN0 8 26 DB7 AIN1 15 31 DB6 16 30 AIN1 9 25 DB6 AIN2 DB5 17 29 10 AIN3 DB4 AIN2 24 DB5 11 23 AIN3 DB4 18 19 20 21 22 23 24 25 26 27 28 REV. A –5– AIN6 AIN7 AIN6 AIN7 AIN4 CS AIN5 RD WR CONVST CAL BUSY CLKIN SLEEP DB0 DB15 DB1 DB14 DB2 DB13 DB3 DB12 NC NC AIN4 12 44 CS AIN5 13 43 RD 14 42 WR 15 41 CONVST CAL 16 40 BUSY SLEEP 17 39 CLKIN DB0 18 38 DB15 DB1 19 37 DB14 DB2 20 36 DB13 DB3 21 35 DB12 22 34 NC NC AD7859/AD7859L TERMINOLOGY Total Harmonic Distortion Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum of This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7859/AD7859L, it is through the endpoints of the ADC transfer function. The end- defined as: points of the transfer function are zero scale, a point 1/2 LSB 2 2 2 2 2 below the first code transition, and full scale, a point 1/2 LSB (V +V +V +V +V ) 2 3 4 5 6 above the last code transition. THD (dB) = 20log V 1 Differential Nonlinearity where V is the rms amplitude of the fundamental and V , V , This is the difference between the measured and the ideal 1 LSB 1 2 3 V , V and V are the rms amplitudes of the second through the change between any two adjacent codes in the ADC. 4 5 6 sixth harmonics. Unipolar Offset Error Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000 to Peak harmonic or spurious noise is defined as the ratio of the 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) rms value of the next largest component in the ADC output when operating in the unipolar mode. spectrum (up to f /2 and excluding dc) to the rms value of the S Positive Full-Scale Error fundamental. Normally, the value of this specification is deter- This applies to the unipolar and bipolar modes and is the devia- mined by the largest harmonic in the spectrum, but for parts tion of the last code transition from the ideal AIN(+) voltage where the harmonics are buried in the noise floor, it will be a (AIN(–) + Full Scale – 1.5 LSB) after the offset error has been noise peak. adjusted out. Intermodulation Distortion Negative Full-Scale Error With inputs consisting of sine waves at two frequencies, fa and This applies to the bipolar mode only and is the deviation of the fb, any active device with nonlinearities will create distortion first code transition (10 . . . 000 to 10 . . . 001) from the ideal products at sum and difference frequencies of mfa ± nfb where AIN(+) voltage (AIN(–) – V /2 + 0.5 LSB). REF m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are Bipolar Zero Error those for which neither m nor n are equal to zero. For example, This is the deviation of the midscale transition (all 0s to all 1s) the second order terms include (fa + fb) and (fa – fb), while the from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Track/Hold Acquisition Time The track/hold amplifier returns into track mode and the end of Testing is performed using the CCIF standard where two input conversion. Track/Hold acquisition time is the time required for frequencies near the top end of the input bandwidth are used. In the output of the track/hold amplifier to reach its final value, this case, the second order terms are usually distanced in fre- within ±1/2 LSB, after the end of conversion. quency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a Signal to (Noise + Distortion) Ratio result, the second and third order terms are specified separately. This is the measured ratio of signal to (noise + distortion) at the The calculation of the intermodulation distortion is as per the output of the A/D converter. The signal is the rms amplitude of THD specification where it is the ratio of the rms sum of the the fundamental. Noise is the sum of all nonfundamental sig- individual distortion products to the rms amplitude of the sum nals up to half the sampling frequency (f /2), excluding dc. The S of the fundamentals expressed in dBs. ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N +1.76)dB Thus for a 12-bit converter, this is 74 dB. –6– REV. A AD7859/AD7859L PIN FUNCTION DESCRIPTION Mnemonic Description CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV . DD RD Read Input. Active low logic input. Used in conjunction with CS to read from internal registers. WR Write Input. Active low logic input. Used in conjunction with CS to write to internal registers. CS Chip Select Input. Active low logic input. The device is selected when this input is active. REF / Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the IN REF reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the OUT pin. This pin can be overdriven by an external reference or can be taken as high as AV . When this pin is tied to DD AV , then the C pin should also be tied to AV . DD REF1 DD AV Analog Supply Voltage, +3.0 V to +5.5 V. DD AGND Analog Ground. Ground reference for track/hold, reference and DAC. DV Digital Supply Voltage, +3.0 V to +5.5 V. DD DGND Digital Ground. Ground reference point for digital circuitry. C Reference Capacitor (0.1 μF multilayer ceramic). This external capacitor is used as a charge source for the inter- REF1 nal DAC. The capacitor should be tied between the pin and AGND. C Reference Capacitor (0.01 μF ceramic disc). This external capacitor is used in conjunction with the on-chip refer- REF2 ence. The capacitor should be tied between the pin and AGND. AIN1–AIN8 Analog Inputs. Eight analog inputs which can be used as eight single ended inputs (referenced to AGND) or four pseudo differential inputs. Channel configuration is selected by writing to the control register. None of the inputs can go below AGND or above AV at any time. See Table III for channel selection. DD W/B Word/Byte input. When this input is at a logic 1, data is transferred to and from the AD7859/AD7859L in 16-bit words on pins DB0 to DB15. When this pin is at a Logic 0, byte transfer mode is enabled. Data is transferred on pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality. DB0–DB7 Data Bits 0 to 7. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 7, a three state data I/O pin that is con- trolled by CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low, then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. DB9–DB15 Data Bits 9 to 15. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight bi- nary (unipolar mode) or twos complement (bipolar mode). CLKIN Master Clock Signal for the device (4 MHz for AD7859, 1.8 MHz for AD7859L). Sets the conversion and calibra- tion times. CAL Calibration Input. A logic 0 in this pin resets all logic. A rising edge on this pin initiates a calibration. This input overrides all other internal operations. BUSY Busy Output. The busy output is triggered high when a conversion or a calibration is initiated, and remains high until the conversion or calibration is completed. SLEEP Sleep Input. This pin is used in conjunction with the PGMT0 and PGMT1 bits in the control register to deter- mine the power-down mode. Please see the “Power-Down Options” section for details. NC No connect pins. These pins should be left unconnected. REV. A –7– AD7859/AD7859L AD7859/AD7859L ON-CHIP REGISTERS The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu- ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power- down and a full self-calibration. Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali- bration, and software conversion start can be selected by writing to the part. The AD7859/AD7859L contains a Control register, ADC output data register, Status register, Test register and 10 Cali- bration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to. Addressing the On-Chip Registers Writing When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit word, or as two 8-bit bytes, depending on the logic level at the W/B pin. When W/B is high, the 16 bits are transferred on DB0 to DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/B is low, DB8/HBEN assumes its HBEN functionality and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB. When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ- ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy. Table I. Write Register Addressing ADDR1 ADDR0 Comment 0 0 This combination does not address any register. 0 1 This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register. 1 0 This combination addresses the CALIBRATION REGISTERS. The 14 LSBs of data are written to the selected calibration register. 1 1 This combination addresses the CONTROL REGISTER. The 14 LSBs of data are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading from the calibration registers in byte mode, the low byte must be read first. Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un- til the read selection bits are changed in the control register. Table II. Read Register Addressing RDSLT1 RDSLT0 Comment 0 0 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power- up setting. There is always four leading zeros when reading from the ADC output data register. 0 1 All successive read operations are from the TEST REGISTER. 1 0 All successive read operations are from the CALIBRATION REGISTERS. 1 1 All successive read operations are from the STATUS REGISTER. RDSLT1, RDSLT0 ADDR1, ADDR0 DECODE DECODE 00 01 10 11 01 10 11 ADC OUTPUT TEST CALIBRATION STATUS TEST CALIBRATION CONTROL DATA REGISTER REGISTER REGISTERS REGISTER REGISTER REGISTERS REGISTER GAIN (1) GAIN (1) GAIN (1) GAIN (1) OFFSET (1) GAIN (1) OFFSET (1) GAIN (1) OFFSET (1) OFFSET (1) OFFSET (1) OFFSET (1) DAC (8) DAC (8) 00 01 10 11 00 01 10 11 CALSLT1, CALSLT0 CALSLT1, CALSLT0 DECODE DECODE Figure 2. Write Register Hierarchy/Address Decoding Figure 3. Read Register Hierarchy/Address Decoding –8– REV. A AD7859/AD7859L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described below. The power-up status of all bits is 0. MSB SGL/DIFF CHSLT2 CHSLT1 CHSLT0 PMGT1 PMGT0 RDSLT1 RDSLT0 AMODE CONVST CALMD CALSLT1 CALSLT0 STCAL LSB CONTROL REGISTER BIT FUNCTION DESCRIPTION Bit Mnemonic Comment 13 SGL/DIFF A 0 in this bit position configures the input channels for pseudo-differential mode. A 1 in this bit posi- tion configures the input channels in single ended mode. Please see Table III for channel selection. 12 CHSLT2 These three bits are used to select the analog input on which the conversion is performed. The analog 11 CHSLT1 inputs can be configured as eight single-ended channels or four pseudo-differential channels. The 10 CHSLT0 default selection is AIN1 for the positive input and AIN2 for the negative input. Please see Table III for channel selection information. 9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8 PMGT0 Power-Down modes (See Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations. Please see Table II. 6 RDSLT0 5 AMODE Analog Mode Bit. This bit has two different functions, depending on the status of the SGL/DIFF bit. When SGL/DIFF is 0, AMODE selects between unipolar and bipolar analog input ranges. A logic 0 in this bit position selects the unipolar range, 0 to V (i.e., AIN(+) – AIN(–) = 0 to V ). A logic 1 in REF REF this bit position selects the bipolar range –V /2 to +V /2 (i.e., AIN(+) – AIN(–) = –V /2 to REF REF REF +V /2). In this case AIN(–) needs to be tied to at least +V /2 to allow AIN(+) to have a full input REF REF swing from 0 V to +V . REF When SGL/DIFF is 1, AMODE selects the source for the AIN(–) channel of the sample and hold cir- cuitry. If AMODE is a 0, AGND is selected. If AMODE is a 1, then AIN8 is selected. Please see Table III for more information. 4 CONVST Conversion Start Bit. A logic 1 in this bit position starts a single conversion, and this bit is automatically reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see calibration section on page 21). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table IV). 2 CALSLT1 Calibration Selection Bits 1 and 0. These bits have two functions, depending on the STCAL bit. 1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits, along with the CALMD bit, deter- mine the type of calibration performed by the part (see Table IV). With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see Table V for more details). 0 STCAL Start Calibration Bit. When STCAL is set to a 1, a calibration is performed, as determined by the CALMD, CALSLT1 and CALSLT0 bits. Please see Table IV. When STCAL is set to a zero, no cali- bration is performed. REV. A –9– AD7859/AD7859L Table IIIa. Channel Selection for AD7859/AD7859L Table IIIb. Channel Selection for AD7859/AD7859L Differential Sampling (SGL/DIFF = 0) Single-Ended Sampling (SGL/DIFF = 1) AMODE CHSLT AIN(+)*AIN(–)* Bipolar or AMODE CHSLT AIN(+)*AIN(–)* Bipolar or 2 1 0 Unipolar 2 1 0 Unipolar 0 0 0 0 AIN1 AIN2 Unipolar 0 0 0 0 AIN1 AGND Unipolar 0 0 0 1 AIN3 AIN4 Unipolar 0 0 0 1 AIN3 AGND Unipolar 0 0 1 0 AIN5 AIN6 Unipolar 0 0 1 0 AIN5 AGND Unipolar 0 0 1 1 AIN7 AIN8 Unipolar 0 0 1 1 AIN7 AGND Unipolar 0 1 x x x x Not Used 0 1 0 0 AIN2 AGND Unipolar 1 0 0 0 AIN1 AIN2 Bipolar 0 1 0 1 AIN4 AGND Unipolar 1 0 0 1 AIN3 AIN4 Bipolar 0 1 1 0 AIN6 AGND Unipolar 1 0 1 0 AIN5 AIN6 Bipolar 0 1 1 1 AIN8 AGND Unipolar 1 0 1 1 AIN7 AIN8 Bipolar 1 0 0 0 AIN1 AIN8 Unipolar 1 1 x x x x Not Used 1 0 0 1 AIN3 AIN8 Unipolar *AIN(+) refers to the positive input seen by the AD7859/AD7859L sample-and- 1 0 1 0 AIN5 AIN8 Unipolar hold circuitry. 1 0 1 1 AIN7 AIN8 Unipolar AIN(–) refers to the negative input seen by the AD7859/AD7859L sample-and- hold circuitry. 1 1 0 0 AIN2 AIN8 Unipolar 1 1 0 1 AIN4 AIN8 Unipolar 1 1 1 0 AIN6 AIN8 Unipolar 1 1 1 1 AIN8 AIN8 Unipolar Table IV. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 00 0 A full internal calibration is initiated. First the internal DAC is calibrated, then the internal gain error and finally the internal offset error are removed. This is the default setting. 0 0 1 First the internal gain error is removed, then the internal offset error is removed. 0 1 0 The internal offset error only is calibrated out. 0 1 1 The internal gain error only is calibrated out. 10 0 A full system calibration is initiated. First the internal DAC is calibrated, followed by the system gain error calibration, and finally the system offset error calibration. 1 0 1 First the system gain error is calibrated out, followed by the system offset error. 1 1 0 The system offset error only is removed. 1 1 1 The system gain error only is removed. –10– REV. A AD7859/AD7859L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 4. Flowchart for Reading the Status Register MSB ZERO ZERO SGL/DIFF CHSLT2 CHSLT1 CHSLT0 PMGT1 PMGT0 ONE ONE AMODE BUSY CALMD CALSLT1 CALSLT0 STCAL LSB STATUS REGISTER BIT FUNCTION DESCRIPTION Bit Mnemonic Comment 15 ZERO These two bits are always 0. 14 ZERO 13 SGL/DIFF Single/Differential Bit. 12 CHSLT2 Channel Selection Bits. These bits, in conjunction with the SGL/DIFF bit, determine which channel has 11 CHSLT1 been selected for conversion. Please refer to Table IIIa and Table IIIb. 10 CHSLT0 9 PMGT1 Power Management Bits. These bits along with the SLEEP pin indicate if the part is in a power-down 8 PMGT0 mode or not. See Table VI in Power-Down Section for description. 7 ONE Both these bits are always 1. 6 ONE 5 AMODE Analog Mode Bit. This bit is used along with SGL/DIFF and CHSLT2 – CHSLT0 to determine the AIN(+) and AIN(–) inputs to the track and hold circuitry and the analog conversion mode (unipolar or bi- polar). Please see Table III for details. 4 BUSY Conversion/Calibration BUSY Bit. When this bit is a 1, there is a conversion or a calibration in progress. When this bit is a zero, there is no conversion or calibration in progress. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see Table IV). 2 CALSLT1 Calibration Selection Bits. The CALSLT1 and CALSLT0 bits indicate which of the calibration 1 CALSLT0 registers are addressed for reading and writing (see section on the Calibration Registers for more details). 0 STCAL Start Calibration Bit. The STCAL bit is a 1 if a calibration is in progress and a 0 if there is no calibration in progress. REV. A –11– AD7859/AD7859L CALIBRATION REGISTERS The AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. Addressing the Calibration Registers The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad- dressed (See Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time. Table V. Calibration Register Addressing CALSLT1 CALSLT0 Comment 0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. 0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total. 1 0 This combination addresses the Offset Register. One register in total. 1 1 This combination addresses the Gain Register. One register in total. Writing to/Reading from the Calibration Registers When reading from the calibration registers there is always two When writing to the calibration registers a write to the control leading zeros for each of the registers. register is required to set the CALSLT0 and CALSLT1 bits. When reading from the calibration registers a write to the con- START trol register is required to set the CALSLT0 and CALSLT1 bits and also to set the RDSLT1 and RDSLT0 bits to 10 (this ad- WRITE TO CONTROL REGISTER SETTING STCAL = 0 dresses the calibration registers for reading). The calibration AND CALSLT1, CALSLT0 = 00, 01, 10, 11 register pointer is reset on writing to the control register setting the CALSLT1 and CALSLT0 bits, or upon completion of all the calibration register write/read operations. When reset it CAL REGISTER POINTER IS AUTOMATICALLY RESET points to the first calibration register in the selected write/read sequence. The calibration register pointer points to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own WRITE TO CAL REGISTER (ADDR1 = 1, ADDR0 = 0) (CALSLT1 = 1, CALSLT0 = 0). Where more than one cali- bration register is being accessed, the calibration register pointer is automatically incremented after each full calibration register CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED write/read operation. The calibration register address pointer is incremented after the high byte read or write operation in byte mode. Therefore when reading (in byte mode) from the calibra- LAST tion registers, the low byte must always be read first, i.e., HBEN REGISTER = logic zero. The order in which the 10 calibration registers are NO WRITE OPERATION arranged is shown in Figure 5. Read/Write operations may be OR aborted at any time before all the calibration registers have been ABORT ? accessed, and the next control register write operation resets the YES calibration register pointer. The flowchart in Figure 6 shows the sequence for writing to the calibration registers. Figure 7 shows FINISHED the sequence for reading from the calibration registers. Figure 6. Flowchart for Writing to the Calibration Registers CALIBRATION REGISTERS CAL REGISTER GAIN REGISTER (1) ADDRESS POINTER (2) OFFSET REGISTER (3) DAC 1st MSB REGISTER (10) DAC 8th MSB REGISTER CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS. Figure 5. Calibration Register Arrangement –12– REV. A AD7859/AD7859L ence voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 START has a weighting of 1.25%, and so on down to the LSB which has a weighting of 0.0006%. This gives a resolution of ±0.0006% of WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, V approximately. The resolution can also be expressed as REF RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 13 ±(0.05 × V )/2 volts. This equals ±0.015 mV, with a 2.5 V REF reference. The maximum offset that can be compensated for is CAL REGISTER POINTER IS ±5% of the reference voltage, which equates to ±125 mV with a AUTOMATICALLY RESET 2.5 V reference and ±250 mV with a 5 V reference. Q. If a +20 mV offset is present in the analog input signal and the READ CAL REGISTER reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset ? A. 2.5 V reference implies that the resolution in the offset reg- CAL REGISTER POINTER IS 13 AUTOMATICALLY INCREMENTED ister is 5% × 2.5 V/2 = 0.015 mV. +20 mV/0.015 mV = 1310.72; rounding to the nearest number gives 1311. In binary terms this is 00 0101 0001 1111, therefore increase LAST the offset register by 00 0101 0001 1111. REGISTER NO WRITE This method of compensating for offset in the analog input sig- OPERATION nal allows for fine tuning the offset compensation. If the offset OR on the analog input signal is known, there is no need to apply ABORT ? the offset voltage to the analog input pins and do a system cali- YES bration. The offset compensation can take place in software. FINISHED Adjusting the Gain Calibration Register The gain calibration register contains 16 bits. The two MSBs Figure 7. Flowchart for Reading from the Calibration are zero and the 14 LSBs contain gain data. As in the offset cali- Registers brating register the data bits in the gain calibration register are binary weighted, with the MSB having a weighting of 2.5% of Adjusting the Offset Calibration Register the reference voltage. The gain register value is effectively multi- The offset calibration register contains 16 bits. The two MSBs plied by the analog input to scale the conversion result over the are zero and the 14 LSBs contain offset data. By changing the full range. Increasing the gain register compensates for a contents of the offset register, different amounts of offset on the smaller analog input range and decreasing the gain register com- analog input signal can be compensated for. Decreasing the pensates for a larger input range. The maximum analog input number in the offset calibration register compensates for nega- range that the gain register can compensate for is 1.025 times tive offset on the analog input signal, and increasing the number the reference voltage, and the minimum input range is 0.975 in the offset calibration register compensates for positive offset times the reference voltage. on the analog input signal. The default value of the offset cali- bration register is 0010 0000 0000 0000 approximately. This is not the exact value, but the value in the offset register should be close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the refer- REV. A –13– AD7859/AD7859L CIRCUIT INFORMATION and 1.5 CLKIN periods are allowed for the acquisition time. The AD7859/AD7859L is a fast, 8-channel, 12-bit, single sup- With a 1.8 MHz clock, this gives a full cycle time of 10 μs, ply A/D converter. The part requires an external 4 MHz/1.8 which equates to a throughput rate of 100 kSPS. MHz master clock (CLKIN), two C capacitors, a CONVST REF When using the software conversion start for maximum signal to start conversion and power supply decoupling capaci- throughput, the user must ensure the control register write op- tors. The part provides the user with track/hold, on-chip refer- eration extends beyond the falling edge of BUSY. The falling ence, calibration features, A/D converter and parallel interface edge of BUSY resets the CONVST bit to 0 and allows it to be logic functions on a single chip. The A/D converter section of reprogrammed to 1 to start the next conversion. the AD7859/AD7859L consists of a conventional successive-ap- proximation converter based around a capacitor DAC. The TYPICAL CONNECTION DIAGRAM AD7859/AD7859L accepts an analog input range of 0 to +V REF. Figure 8 shows a typical connection diagram for the AD7859/ V can be tied to V . The reference input to the part con- REF DD AD7859L. The AGND and the DGND pins are connected nected via a 150 kΩ resistor to the internal 2.5 V reference and together at the device for good noise suppression. The first to the on-chip buffer. CONVST applied after power-up starts a self-calibration A major advantage of the AD7859/AD7859L is that a conver- sequence. This is explained in the calibration section of this data sion can be initiated in software, as well as by applying a signal sheet. Note that after power is applied to AV and DV and DD DD to the CONVST pin. The part is available in a 44-pin PLCC or a the CONVST signal is applied, the part requires (70 ms + 1/ 44-pin PQFP package, and this offers the user considerable sample rate) for the internal reference to settle and for the self- spacing saving advantages over alternative solutions. The calibration on power-up to be completed. AD7859L version typically consumes only 5.5 mW making it 4MHz/1.8MHz OSCILLATOR ideal for battery-powered applications. ANALOG SUPPLY CONVERTER DETAILS +3V TO +5V 10µF 0.1µF 0.1µF The master clock for the part is applied to the CLKIN pin. CONVERSION START SIGNAL Conversion is initiated on the AD7859/AD7859L by pulsing the DV W/B AV DD DD CONVST input or by writing to the control register and setting 0V TO 2.5V AIN(+) CLKIN INPUT the CONVST bit to 1. On the rising edge of CONVST (or at AIN(–) CONVST the end of the control register write operation), the on-chip C REF1 track/hold goes from track to hold mode. The falling edge of the 0.1µF CS CLKIN signal which follows the rising edge of CONVST ini- AD7859/ RD C tiates the conversion, provided the rising edge of CONVST (or REF2 AD7859L 0.01µF WR WR when converting via the control register) occurs typically at µC/µP BUSY least 10 ns before this CLKIN edge. The conversion takes 16.5 DV SLEEP DD CAL CLKIN periods from this CLKIN falling edge. If the 10 ns set- DB0 AGND up time is not met, the conversion takes 17.5 CLKIN periods. DB15 DGND The time required by the AD7859/AD7859L to acquire a signal REF /REF IN OUT depends upon the source resistance connected to the AIN(+) in- put. Please refer to the acquisition time section for more details. 0.1nF EXTERNAL REF 0.1µF INTERNAL REF When a conversion is completed, the BUSY output goes low, OPTIONAL AD780/ EXTERNAL and the result of the conversion can be read by accessing the REF192 REFERENCE data through the data bus. To obtain optimum performance from the part, read or write operations should not occur during Figure 8. Typical Circuit the conversion or less than 200 ns prior to the next CONVST For applications where power consumption is a major concern, rising edge. Reading/writing during conversion typically de- the power-down options can be exercised by writing to the part grades the Signal-to-(Noise + Distortion) by less than 0.5 dBs. and using the SLEEP pin. See the Power-Down section for more The AD7859 can operate at throughput rates of over 200 kSPS details on low power applications. (up to 100 kSPS for the AD7859L). With the AD7859L, 100 kSPS throughput can be obtained as follows: the CLKIN and CONVST signals are arranged to give a conversion time of 16.5 CLKIN periods as described above –14– REV. A AD7859/AD7859L ANALOG INPUT DC/AC Applications The equivalent analog input circuit is shown in Figure 9. AIN(+) For dc applications, high source impedances are acceptable, is the channel connected to the positive input of the track/hold provided there is enough acquisition time between conversions circuitry and AIN(–) is the channel connected to the negative to charge the 20 pF capacitor. For example with R = 5 kΩ, IN input. Please refer to Table IIIa and Table IIIb for channel the required acquisition time is 922 ns. configuration. For ac applications, removing high frequency components During the acquisition interval the switches are both in the track greater than the Nyquist frequency from the analog input signal position and the AIN(+) charges the 20 pF capacitor through is recommended by use of a low- pass filter on the AIN(+) pin, the 125 Ω resistance. The rising edge of CONVST switches as shown in Figure 11. In applications where harmonic distor- SW1 and SW2 go into the hold position retaining charge on the tion and signal to noise ratio are critical, the analog input should 20 pF capacitor as a sample of the signal on AIN(+). The AIN(–) be driven from a low impedance source. Large source imped- is connected to the 20 pF capacitor, and this unbalances the ances significantly affect the ac performance of the ADC. They voltage at node A at the input of the comparator. The capacitor may require the use of an input buffer amplifier. The choice of DAC adjusts during the remainder of the conversion cycle to the amplifier is a function of the particular application. restore the voltage at node A to the correct value. This action The maximum source impedance depends on the amount of to- transfers a charge, representing the analog input signal, to the tal harmonic distortion (THD) that can be tolerated. The THD capacitor DAC which in turn forms a digital representation of increases as the source impedance increases. Figure 10 shows a the analog input signal. The voltage on the AIN(–) pin directly graph of the Total Harmonic Distortion vs. analog input signal influences the charge transferred to the capacitor DAC at the frequency for different source impedances. With the setup as in hold instant. If this voltage changes during the conversion Figure 11, the THD is at the –90 dB level. With a source im- period, the DAC representation of the analog input voltage is pedance of 1 kΩ and no capacitor on the AIN(+) pin, the THD altered. Therefore it is most important that the voltage on the increases with frequency. AIN(–) pin remains constant during the conversion period. Furthermore, it is recommended that the AIN(–) pin is always –72 THD VS. FREQUENCY FOR DIFFERENT connected to AGND or to a fixed dc voltage. SOURCE IMPEDANCES –76 125Ω TRACK AIN(+) CAPACITOR AIN(–) SW1 DAC –80 125Ω HOLD 20pF R = 1kΩ IN NODE A –84 SW2 COMPARATOR HOLD TRACK –88 R = 50kΩ, 10nF IN AS IN FIGURE 13 AGND –92 0 20 40 60 80 100 Figure 9. Analog Input Equivalent Circuit INPUT FREQUENCY – kHz Acquisition Time The track-and-hold amplifier enters its tracking mode on the Figure 10. THD vs. Analog Input Frequency falling edge of the BUSY signal. The time required for the In a single supply application (both 3 V and 5 V), the V+ and track-and-hold amplifier to acquire an input signal will depend V– of the op amp can be taken directly from the supplies to the on how quickly the 20 pF input capacitance is charged. There is AD7859/AD7859L which eliminates the need for extra external a minimum acquisition time of 400 ns. This includes the time power supplies. When operating with rail-to-rail inputs and out- required to change channels. For large source impedances, >2 kΩ, puts at frequencies greater than 10 kHz, care must be taken in the acquisition time is calculated using the formula: selecting the particular op amp for the application. In particular, t = 9 × (R + 125 Ω) × 20 pF ACQ IN for single supply applications the input amplifiers should be where R is the source impedance of the input signal, and IN connected in a gain of –1 arrangement to get the optimum per- 125 Ω, 20 pF is the input R, C. formance. Figure 11 shows the arrangement for a single supply application with a 50 Ω and 10 nF low-pass filter (cutoff fre- quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a capacitor with good linearity to ensure good ac performance. Recommended single supply op amps are the AD820 and the AD820-3V. REV. A –15– THD – dB AD7859/AD7859L +3V TO +5V Transfer Functions 0.1µF 10µF For the unipolar range the designed code transitions occur mid- 10kΩ way between successive integer LSB values (i.e., 1/2 LSB, V 10kΩ IN V+ 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is 50Ω (–V /2 TO +V /2) REF REF TO AIN(+) OF straight binary for the unipolar range with 1 LSB = FS/4096 = IC1 10kΩ AD7854/AD7854L V /2 10nF REF 3.3 V/4096 = 0.8 mV when V = 3.3 V. Figure 12 shows the AD820 REF V– (NPO) AD820-3V 10kΩ unipolar analog input configuration. The ideal input/output transfer characteristic for the unipolar range is shown in Figure 14. Figure 11. Analog Input Buffering OUTPUT CODE Input Ranges The analog input range for the AD7859/AD7859L is 0 V to 111...111 V in both the unipolar and bipolar ranges. REF 111...110 111...101 The difference between the unipolar range and the bipolar range 111...100 is that in the bipolar range the AIN(–) should be biased up to at least +V /2 and the output coding is 2s complement (See REF Table VI and Figures 14 and 15). 000...011 FS Table VI. Analog Input Connections 1LSB = 4096 000...010 Analog Input Input Connections Connection 000...001 Range AIN(+) AIN(–) Diagram 000...000 0V 1LSB +FS –1LSB 1 V = (AIN(+) – AIN(–)), INPUT VOLTAGE 0 V to V V AGND Figure 12 IN REF IN 2 ±V /2 V V /2 Figure 13 REF IN REF Figure 14. AD7859/AD7859L Unipolar Transfer NOTES Characteristic 1 Output code format is straight binary. 2 Range is ±V /2 biased about V /2. Output code format is 2s complement. REF REF Figure 13 shows the AD7859/AD7859L’s ±V /2 bipolar ana- REF log input configuration. AIN(+) cannot go below 0 ,V so for Note that the AIN(–) channel on the AD7859/AD7859L can be the full bipolar range, AIN(–) should be biased to at least biased up above AGND in the unipolar mode, or above V /2 REF +V /2. Once again the designed code transitions occur mid- REF in bipolar mode if required. The advantage of biasing the lower way between successive integer LSB values. The output coding end of the analog input range away from AGND is that the ana- is 2s complement with 1 LSB = 4096 = 3.3 V/4096 = 0.8 mV. log input does not have to swing all the way down to AGND. The ideal input/output transfer characteristic is shown in Fig- Thus, in single supply applications the input amplifier does not ure 15. have to swing all the way down to AGND. The upper end of the analog input range is shifted up by the same amount. Care must OUTPUT be taken so that the bias applied does not shift the upper end of CODE the analog input above the AV supply. In the case where the DD 011...111 reference is the supply, AV , the AIN(–) should be tied to DD 011...110 AGND in unipolar mode or to AV /2 in bipolar mode. DD (V /2) –1LSB REF TRACK AND HOLD 000...001 0V AMPLIFIER AIN(+) 000...000 DB0 V = 0 TO V STRAIGHT IN REF +FS –1LSB BINARY 111...111 AIN(–) FORMAT (V /2) +1LSB DB15 REF 000...010 FS = V V REF AD7859/AD7859L FS 000...001 1LSB = 4096 000...000 Figure 12. 0 to V Unipolar Input Configuration V /2 REF REF V = (AIN(+) –AIN(–)), INPUT VOLTAGE IN TRACK AND HOLD Figure 15. AD7859/AD7859L Bipolar Transfer Characteristic AMPLIFIER AIN(+) V = 0 TO V DB0 IN REF 2'S COMPLEMENT AIN(–) V /2 FORMAT REF DB15 AD7859/AD7859L Figure 13. ±V /2 about V /2 Bipolar Input Configuration REF REF –16– REV. A AD7859/AD7859L REFERENCE SECTION AD7859/AD7859L PERFORMANCE CURVES For specified performance, it is recommended that when using Figure 18 shows a typical FFT plot for the AD7859 at 200 kHz an external reference, this reference should be between 2.3 V sample rate and 10 kHz input frequency. and the analog supply AV . The connections for the reference DD 0 pins are shown below. If the internal reference is being used, AV = DV = 3.3V DD DD the REF /REF pin should be decoupled with a 100 nF IN OUT F = 200kHz SAMPLE –20 capacitor to AGND very close to the REF /REF pin. These IN OUT F = 10kHz IN connections are shown in Figure 16. SNR = 72.04dB –40 THD = –88.43dB If the internal reference is required for use external to the ADC, it should be buffered at the REF /REF pin and a 100 nF IN OUT –60 capacitor should be connected from this pin to AGND. The typical noise performance for the internal reference, with 5 V supplies is –80 150 nV/√Hz @ 1 kHz and dc noise is 100 μV p-p. ANALOG SUPPLY –100 +3V TO +5V 10µF 0.1µF 0.1µF –120 20 40 60 80 100 0 FREQUENCY – kHz AV DV DD DD C REF1 0.1µF Figure 18. FFT Plot AD7859/AD7859L Figure 19 shows the SNR versus Frequency for different sup- C REF2 0.01µF plies and different external references. 74 REF /REF IN OUT AV = DV WITH 2.5V REFERENCE DD DD 0.1µF UNLESS STATED OTHERWISE 73 5.0V SUPPLIES, WITH 5V REFERENCE Figure 16. Relevant Connections Using Internal Reference 5.0V SUPPLIES 72 The REF /REF pin may be overdriven by connecting it to IN OUT an external reference. This is possible due to the series resis- 5.0V SUPPLIES, tance from the REF /REF pin to the internal reference. IN OUT 71 L VERSION This external reference can be in the range 2.3 V to AV . DD 3.3V SUPPLIES When using AV as the reference source, the 10 nF capacitor DD 70 from the REF /REF pin to AGND should be as close as IN OUT possible to the REF /REF pin, and also the C pin IN OUT REF1 should be connected to AV to keep this pin at the same volt- DD 69 0 20 40 60 80 100 age as the reference. The connections for this arrangement are INPUT FREQUENCY – kHz shown in Figure 17. When using AV it may be necessary to DD add a resistor in series with the AV supply. This has the effect DD Figure 19. SNR vs. Frequency of filtering the noise associated with the AV supply. DD Figure 20 shows the Power Supply Rejection Ratio versus Fre- Note that when using an external reference, the voltage present quency for the part. The Power Supply Rejection Ratio is de- at the REF /REF pin is determined by the external refer- IN OUT fined as the ratio of the power in ADC output at frequency f to ence source resistance and the series resistance of 150 kΩ from the power of a full-scale sine wave. the REF /REF pin to the internal 2.5 V reference. Thus, a IN OUT PSRR (dB) = 10 log (Pf/Pfs) low source impedance external reference is recommended. Pf = Power at frequency f in ADC output, Pfs = power of a full- ANALOG SUPPLY scale sine wave. Here a 100 mV peak-to-peak sine wave is +3V TO +5V 0.1µF 10µF 0.1µF coupled onto the AV supply while the digital supply is left DD unaltered. Both the 3.3 V and 5.0 V supply performances are shown. AV DV DD DD C REF1 0.1µF AD7859/AD7859L C REF2 0.01µF REF /REF IN OUT 0.01µF Figure 17. Relevant Connections, AV as the Reference DD REV. A –17– SNR – dB S(N+D) RATIO – dB AD7859/AD7859L Table VII. Power Management Options –78 AV = DV = 3.3V/5.0V DD DD 100mV pk-pk SINEWAVE ON AV DD PMGT1 PMGT0 SLEEP –80 3.3V Bit Bit Pin Comment –82 0 0 0 Full Power-Down Between Conversions (HW / SW) –84 0 0 1 Full Power-Up (HW / SW) 0 1 X Full Power-Down Between –86 Conversions (SW ) 5.0V –88 1 0 X Full Power-Down (SW) 1 1 X Partial Power-Down Between –90 Conversions (SW) 0 20 40 60 80 100 INPUT FREQUENCY – kHz NOTE SW = Software selection, HW = Hardware selection. Figure 20. PSRR vs. Frequency POWER-UP TIMES POWER-DOWN OPTIONS Using An External Reference The AD7859/AD7859L provides flexible power management to When the AD7859/AD7859L are powered up, the parts are allow the user to achieve the best power performance for a given powered up from one of two conditions. First, when the power throughput rate. The power management options are selected supplies are initially powered up and, secondly, when the parts by programming the power management bits, PMGT1 and are powered up from either a hardware or software power-down PMGT0, in the control register and by use of the SLEEP pin. (see last section). Table VII summarizes the power-down options that are avail- When AV and DV are powered up, the AD7859/AD7859L DD DD able and how they can be selected by using either software, enters a mode whereby the CONVST signal initiates a timeout hardware or a combination of both. The AD7859/AD7859L can followed by a self-calibration. The total time taken for this time- be fully or partially powered down. When fully powered down, out and calibration is approximately 70 ms—see Calibration on all the on-chip circuitry is powered down and I is 10 μA typ. DD Power-Up in the calibration section of this data sheet. During If a partial power-down is selected, then all the on-chip circuitry power-up the functionality of the SLEEP pin is disabled, i.e., except the reference is powered down and I is 400 μA typ. DD the part will not power down until the end of the calibration if The choice of full or partial power-down does not give any sig- SLEEP is tied logic low. The power-up calibration mode can be nificant improvement in throughput with a power-down between disabled if the user writes to the control register before a conversions. This is discussed in the next section—Power-Up CONVST signal is applied. If the time out and self-calibration Times. But a partial power-down does allow the on-chip refer- are disabled, then the user must take into account the time ence to be used externally even though the rest of the AD7859/ required by the AD7859/AD7859L to power up before a self- AD7859L circuitry is powered down. It also allows the calibration is carried out. This power-up time is the time taken AD7859/AD7859L to be powered up faster after a long power- for the AD7859/AD7859L to power up when power is first down period when using the on-chip reference (See Power-Up applied (300 μs typ) or the time it takes the external reference to Times—Using On-Chip Reference). settle to the 12-bit level—whichever is the longer. When using the SLEEP pin, the power management bits The AD7859/AD7859L powers up from a full hardware or soft- PMGT1 and PMGT0 should be set to zero. Bringing the ware power-down in 5 μs typ. This limits the throughput which SLEEP pin logic high ensures normal operation, and the part the part is capable of to 100 kSPS for the AD7859 and 60 kSPS does not power down at any stage. This may be necessary if the for the AD7859L when powering down between conversions. part is being used at high throughput rates when it is not pos- Figure 21 shows how power-down between conversions is sible to power down between conversions. If the user wishes to implemented using the CONVST pin. The user first selects the power down between conversions at lower throughput rates power-down between conversions option by using the SLEEP (i.e., <100 kSPS for the AD7859 and <60 kSPS for the pin and the power management bits, PMGT1 and PMGT0, in AD7859L) to achieve better power performances, then the the control register. See last section. In this mode the AD7859/ SLEEP pin should be tied logic low. AD7859L automatically enters a full power-down at the end of If the power-down options are to be selected in software only, a conversion, i.e., when BUSY goes low. The falling edge of the then the SLEEP pin should be tied logic high. By setting the next CONVST pulse causes the part to power up. Assuming the power management bits PMGT1 and PMGT0 as shown in external reference is left powered up, the AD7859/AD7859L Table VII, a Full Power-Down, Full Power-Up, Full Power- should be ready for normal operation 5 μs after this falling edge. Down Between Conversions, and a Partial Power-Down Be- The rising edge of CONVST initiates a conversion so the tween Conversions can be selected. CONVST pulse should be at least 5 μs wide. The part automati- cally powers down on completion of the conversion. Where the A combination of hardware and software selection can also be software convert start is used, the part may be powered up in used to achieve the desired effect. software before a conversion is initiated. –18– REV. A PSRR – dB AD7859/AD7859L START CONVERSION ON RISING EDGE POWER VS. THROUGHPUT RATE POWER UP ON FALLING EDGE The main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part 5µs 4.6µs at lower throughput rates. When using this mode of operation, CONVST t CONVERT the AD7859/AD7859L is only powered up for the duration of the conversion. If the power-up time of the AD7859/AD7859L BUSY is taken to be 5 μs and it is assumed that the current during power up is 4.5 mA/1.5 mA typ, then power consumption as a POWER-UP NORMAL FULL POWER-UP function of throughput can easily be calculated. The AD7859 TIME OPERATION POWER-DOWN TIME has a conversion time of 4.6 μs with a 4 MHz external clock and the AD7859L has a conversion time of 9 μs with a 1.8 MHz Figure 21. Using the CONVST Pin to Power Up the AD7859 clock. This means the AD7859/AD7859L consumes 4.5 mA/ for a Conversion 1.5 mA typ for 9.6 μs/14 μs in every conversion cycle if the parts Using The Internal (On-Chip) Reference are powered down at the end of a conversion. The two graphs, As in the case of an external reference, the AD7859/AD7859L Figure 24 and Figure 25, show the power consumption of the can power up from one of two conditions, power-up after the AD7859 and AD7859L for V = 3 V as a function of through- DD supplies are connected or power-up from hardware/software put. Table VIII lists the power consumption for various power-down. throughput rates. When using the on-chip reference and powering up when AV DD and DV are first connected, it is recommended that the DD Table VIII. Power Consumption vs. Throughput power-up calibration mode be disabled as explained above. Power Power When using the on-chip reference, the power-up time is effec- Throughput Rate AD7859 AD7859L tively the time it takes to charge up the external capacitor on the REF /REF pin. This time is given by the equation: IN OUT 1 kSPS 130 μW65μW t = 9 × R × C UP 10 kSPS 1.3 mW 650 μW 20 kSPS 2.6 mW 1.25 mW where R ≈ 150K and C = external capacitor. 50 kSPS 6.48 mW 3.2 mW The recommended value of the external capacitor is 100 nF; this gives a power-up time of approximately 135 ms before a 1.8MHz CURRENT, calibration is initiated and normal operation should commence. OSCILLATOR I = 1.5mA TYP ANALOG When C is fully charged, the power-up time from a hardware REF SUPPLY 10µF 0.1µF 0.1µF +3V or software power-down reduces to 5 μs. This is because an in- ternal switch opens to provide a high impedance discharge path CONVERSION START SIGNAL for the reference capacitor during power-down—see Figure 22. W/B AV DV DD DD An added advantage of the low charge leakage from the refer- 0V TO 2.5V CLKIN AIN(+) INPUT ence capacitor during power-down is that even though the refer- AIN(–) CONVST ence is being powered down between conversions, the reference C REF1 capacitor holds the reference voltage to within 0.5 LSBs with 0.1µF CS throughput rates of 100 samples/second and over with a full AD7859L RD C power-down between conversions. A high input impedance op REF2 0.01µF WR amp like the AD707 should be used to buffer this reference LOW POWER BUSY capacitor if it is being used externally. Note, if the AD7859/ SLEEP µC/µP AD7859L is left in its powered-down state for more than DB0 DV CAL DD 100 ms, the charge on C will start to leak away and the REF AGND DB15 power-up time will increase. If this long power-up time is a DGND problem, the user can use a partial power-down for the last con- REF /REF IN OUT version so the reference remains powered up. 0.1µF SWITCH OPENS OPTIONAL DURING POWER-DOWN REF192 EXTERNAL REFERENCE REF IN/OUT ON-CHIP REFERENCE EXTERNAL Figure 23. Typical Low Power Circuit CAPACITOR TO OTHER CIRCUITRY BUF Figure 22. On-Chip Reference During Power-Down REV. A –19– AD7859/AD7859L 10 AD7859 FULL POWER-DOWN AD7859 FULL POWER-DOWN V = 3V CLKIN = 4MHz V = 3V CLKIN = 4MHz DD DD 1 ON-CHIP REFERENCE ON-CHIP REFERENCE 1 0.1 0.1 0.01 0.01 01 24680 05 10 20 30 400 THROUGHPUT RATE – kSPS THROUGHPUT RATE – kSPS Figure 24. Power vs. Throughput AD7859 Figure 26. Power vs. Throughput AD7859 10 AD7859L FULL POWER-DOWN AD7859L FULL POWER-DOWN V = 3V CLKIN = 1.8MHz V = 3V CLKIN = 1.8MHz DD DD 1 ON-CHIP REFERENCE ON-CHIP REFERENCE 1 0.1 0.1 0.01 0.01 02 4 8 12 160 05 10 20 30 400 THROUGHPUT RATE – kSPS THROUGHPUT RATE – kSPS Figure 25. Power vs. Throughput AD7859L Figure 27. Power vs. Throughput AD7859L –20– REV. A POWER – mW POWER – mW POWER – mW POWER – mW AD7859/AD7859L CALIBRATION SECTION AV = DV CONVERSION IS INITIATED DD DD POWER-ON ON THIS EDGE Calibration Overview The automatic calibration that is performed on power-up CONVST ensures that the calibration options covered in this section are not required in a significant number of applications. A calibra- BUSY tion does not have to be initiated unless the operating condi- 32/72ms 32/72ms tions change (CLKIN frequency, analog input mode, reference voltage, temperature, and supply voltages). The AD7859/ TIMEOUT PERIOD AUTOMATIC CALIBRATION AD7859L has a number of calibration features that may be DURATION required in some applications, and there are a number of advan- tages in performing these different types of calibration. First, the Figure 28. Timing Arrangement for Autocalibration on internal errors in the ADC can be reduced significantly to give Power-On superior dc performance; and second, system offset and gain er- The CONVST signal is gated with the BUSY internally so that rors can be removed. This allows the user to remove reference as soon as the timeout is initiated by the first CONVST pulse all errors (whether it be internal or external reference) and to make subsequent CONVST pulses are ignored until the BUSY signal use of the full dynamic range of the AD7859/AD7859L by ad- goes low, 32/72 ms later. The CONVST pulse that follows after justing the analog input range of the part for a specific system. the BUSY signal goes low initiates a full self-calibration. This There are two main calibration modes on the AD7859/AD7859L, takes a further 32/72 ms. After calibration, the part is accurate self-calibration and system calibration. There are various op- to the 12-bit level and the specifications quoted on the data tions in both self-calibration and system calibration as outlined sheet apply; all subsequent CONVST pulses initiate conver- previously in Table IV. All the calibration functions are initi- sions. There is no need to perform another calibration unless ated by writing to the control register and setting the STCAL the operating conditions change or unless a system calibration is bit to 1. required. The duration of each of the different types of calibration is given This autocalibration at power-on is disabled if the user writes to in Table IX for the AD7859 with a 4 MHz master clock. These the control register before the autocalibration is initiated. If the calibration times are master clock dependent. Therefore the control register write operation occurs during the first 32/72 ms calibration times for the AD7859L (CLKIN = 1.8 MHz) are timeout period, then the BUSY signal stays high for the 32/72 larger than those quoted in Table IX. ms and the CONVST pulse that follows the BUSY going low does not initiate a full self-calibration. It initiates a conversion Table IX. Calibration Times (AD7859 with 4 MHz CLKIN) and all subsequent CONVST pulses initiate conversions as well. If the control register write operation occurs when the automatic Type of Self-Calibration or System Calibration Time full self-calibration is in progress, then the calibration is not be aborted; the BUSY signal remains high until the automatic full Full 31.25 ms self-calibration is complete. Gain + Offset 6.94 ms Offset 3.47 ms Self-Calibration Description Gain 3.47 ms There are four different calibration options within the self- calibration mode. There is a full self-calibration where the Calibration on Power-On DAC, internal offset, and internal gain errors are removed. The calibration on power-on is initiated by the first CONVST There is the (Gain + Offset) self-calibration which removes the pulse after the AV and DV power on. From the CONVST DD DD internal gain error and then the internal offset errors. The inter- pulse the part internally sets a 32/72 ms (4 MHz/1.8 MHz nal DAC is not calibrated here. Finally, there are the self-offset CLKIN) timeout. This time is large enough to ensure that the and self-gain calibrations which remove the internal offset errors internal reference has settled before the calibration is performed. and the internal gain errors respectively. However, if an external reference is being used, this reference The internal capacitor DAC is calibrated by trimming each of must have stabilized before the automatic calibration is initiated. the capacitors in the DAC. It is the ratio of these capacitors to This first CONVST pulse also triggers the BUSY signal high, each other that is critical, and so the calibration algorithm en- and once the 32/72 ms has elapsed, the BUSY signal goes low. sures that this ratio is at a specific value by the end of the cali- At this point the next CONVST pulse that is applied initiates bration routine. For the offset and gain there are two separate the automatic full self-calibration. This CONVST pulse again capacitors, one of which is trimmed during offset calibration triggers the BUSY signal high, and after 32/72 ms (4 MHz/ and one of which is trimmed during gain calibration. 1.8 MHz CLKIN), the calibration is completed and the BUSY In Bipolar Mode the midscale error is adjusted by an offset cali- signal goes low. This timing arrangement is shown in Figure 28. bration and the positive full-scale error is adjusted by the gain The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN signal. calibration. In Unipolar Mode the zero-scale error is adjusted by the offset calibration and the positive full-scale error is ad- justed by the gain calibration. REV. A –21– AD7859/AD7859L Self-Calibration Timing Figure 31 shows a system gain calibration (assuming a system Figure 29 shows the timing for a software full self-calibration. full scale greater than the reference voltage) where the analog Here the BUSY line stays high for the full length of the self- input range has been increased after the system gain calibration calibration. A self-calibration is initiated by writing to the is completed. A system full-scale voltage less than the reference control register and setting the STCAL bit to 1. The BUSY line voltage may also be accounted for a by a system gain calibration. goes high at the end of the write to the control register, and BUSY goes low when the full self-calibration is complete after a MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE IS ±2.5% FROM V IS ±2.5% FROM V REF REF time t as show in Figure 29. CAL SYS FULL S. SYS FULL S. t 19 V – 1LSB V – 1LSB REF REF CS DATA LATCHED INTO SYSTEM GAIN ANALOG CONTROL REGISTER ANALOG INPUT INPUT RANGE RANGE WR CALIBRATION AGND AGND HI-Z HI-Z DATA DATA VALID Figure 31. System Gain Calibration Finally in Figure 32 both the system offset error and gain error BUSY are removed by the system offset followed by a system gain cali- t CAL bration. First the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at Figure 29. Timing Diagram for Full Self-Calibration the top end to account for the system full scale. For the self-(gain + offset), self-offset and self-gain calibrations, the BUSY line is triggered high at the end of the write to the MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE control register and stays high for the full duration of the self- IS ±2.5% FROM V IS ±2.5% FROM V REF REF calibration. The length of time for which BUSY is high depends SYS F.S. V + SYS OFFSET REF on the type of self-calibration that is initiated. Typical values are SYS F.S. V – 1LSB REF V – 1LSB REF given in Table IX. The timing diagram for the other self-calibration SYSTEM OFFSET CALIBRATION options is similar to that outlined in Figure 29. ANALOG FOLLOWED BY ANALOG INPUT INPUT System Calibration Description RANGE RANGE SYSTEM GAIN System calibration allows the user to remove system errors ex- CALIBRATION SYS OFFSET ternal to the AD7859/AD7859L, as well as remove the errors of SYS OFFSET AGND AGND the AD7859/AD7859L itself. The maximum calibration range MAX SYSTEM OFFSET MAX SYSTEM OFFSET for the system offset errors is ±5% of V and for the system REF IS ±5% OF V IS ±5% OF V REF REF gain errors, it is ±2.5% of V . If the system offset or system REF gain errors are outside these ranges, the system calibration algo- Figure 32. System (Gain + Offset) Calibration rithm reduces the errors as much as the trim range allows. Figures 30 through 32 illustrate why a specific type of system calibration might be used. Figure 30 shows a system offset cali- bration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. A negative offset may also be removed by a system offset calibration. MAX SYSTEM FULL SCALE IS ±2.5% FROM V REF V + SYS OFFSET REF V – 1LSB V – 1LSB REF REF ANALOG SYSTEM OFFSET ANALOG INPUT INPUT RANGE RANGE CALIBRATION SYS OFFSET SYS OFFSET AGND AGND MAX SYSTEM OFFSET MAX SYSTEM OFFSET IS ±5% OF V IS ±5% OF V REF REF Figure 30. System Offset Calibration –22– REV. A AD7859/AD7859L System Gain and Offset Interaction The timing for a system (gain + offset) calibration is very similar The architecture of the AD7859/AD7859L leads to an interac- to that of Figure 33, the only difference being that the time tion between the system offset and gain errors when a system t is replaced by a shorter time of the order of t as the in- CAL1 CAL2 calibration is performed. Therefore, it is recommended to per- ternal DAC is not calibrated. The BUSY signal signifies when form the cycle of a system offset calibration followed by a sys- the gain calibration is finished and when the part is ready for the tem gain calibration twice. When a system offset calibration is offset calibration. performed, the system offset error is reduced to zero. If this is DATA LATCHED INTO followed by a system gain calibration, then the system gain error CONTROL REGISTER is now zero, but the system offset error is no longer zero. A sec- t 19 ond sequence of system offset error calibration followed by a CS system gain calibration is necessary to reduce system offset error to below the 12-bit level. The advantage of doing separate WR CONVST BIT SET TO 1 IN system offset and system gain calibrations is that the user has CONTROL REGISTER more control over when the analog inputs need to be at the HI-Z HI-Z HI-Z DATA DATA DATA VALID VALID required levels, and the CONVST signal does not have to be used. Alternatively, a system (gain + offset) calibration can be per- BUSY t CAL2 t CAL1 t 19 formed. At the end of one system (gain + offset) calibration, the t SETUP system offset error is zero, while the system gain error is reduced V AIN V SYSTEM FULL SCALE OFFSET from its initial value. Three system (gain + offset) calibrations are required to reduce the system gain error to below the 12-bit Figure 33. Timing Diagram for Full System Calibration error level. There is never any need to perform more than three system (gain + offset) calibrations. The timing diagram for a system offset or system gain calibra- tion is shown in Figure 34. Here again a write to the control reg- In bipolar mode the midscale error is adjusted for an offset cali- ister initiates the calibration sequence. At the end of the control bration and the positive full-scale error is adjusted for the gain register write operation the BUSY line goes high and it stays calibration; in unipolar mode the zero-scale error is adjusted for high until the calibration sequence is finished. The analog input an offset calibration and the positive full-scale error is adjusted should be set at the correct level for a minimum setup time for a gain calibration. (t ) of 100 ns before the CS rising edge and stay at the cor- SETUP System Calibration Timing rect level until the BUSY signal goes low. The timing diagram in Figure 33 is for a software full system calibration. It may be easier in some applications to perform t 19 separate gain and offset calibrations so that the CONVST bit in the control register does not have to be programmed in the CS DATA LATCHED INTO CONTROL REGISTER middle of the system calibration sequence. Once the write to the control register setting the bits for a full system calibration is WR completed, calibration of the internal DAC is initiated and the HI-Z HI-Z BUSY line goes high. The full-scale system voltage should be DATA DATA VALID applied to the analog input pins, AIN(+) and AIN(–) at the start of calibration. The BUSY line goes low once the DAC and sys- BUSY tem gain calibration are complete. Next the system offset volt- t CAL2 age should be applied across the AIN(+) and AIN(–) pins for a t SETUP minimum setup time (t ) of 100 ns before the rising edge of SETUP AIN V OR V SYSTEM FULL SCALE OFFSET CS. This second write to the control register sets the CONVST bit to 1 and at the end of this write operation the BUSY signal is triggered high (note that a CONVST pulse can be applied in- Figure 34. Timing Diagram for System Gain or stead of this second write to the control register). The BUSY System Offset Calibration signal is low after a time t when the system offset calibration CAL2 section is complete. The full system calibration is now complete. REV. A –23– AD7859/AD7859L t 1 CONVST t CONVERT BUSY t 18 CS t t 13 14 WR t 15 t t 5 6 RD t 7 t 17 t t 16 t 9 8 DATA DATA DB0 – DB15 VALID VALID INTERNAL OLD DATA NEW DATA DATA LATCH *W/B PIN LOGIC HIGH Figure 35. Read and Write Cycle Timing Diagram for 16-Bit Transfers PARALLEL INTERFACE Figure 35 shows the read cycle timing diagram for 16-bit trans- The AD7859 provides a flexible, high speed, parallel interface. fers for the AD7859. When operated in word mode, the HBEN This interface is capable of operating in either word (with the input does not exist, and only the first read operation is required W/B pin tied high) or byte (with W/B tied low) mode. A detailed to access data from the AD7859. Valid data, in this case, is pro- description of the different interface arrangements follows. vided on DB0–DB15. When operated in byte mode, the two read cycles shown in Figure 36 are required to access the full data Reading word from the AD7859. Note that in byte mode, the order of With the W/B pin at a logic high, the AD7859 interface operates successive read operations is important when reading the cali- in word mode. In this case, a single read operation from the bration registers. This is because the register file address pointer device accesses the word on pins DB0 to DB15 (for a data read, is incremented on a high byte read as explained in the calibra- the 12-bit conversion result appears on DB0–DB11). DB0 is tion register section of this data sheet. In this case the order of the LSB of the word. The DB8/HBEN pin assumes its DB8 the read should always be Low Byte–High Byte. In Figure 36, function. With the W/B pin at a logic low, the AD7859 interface the first read places the lower 8 bits of the full data word on operates in byte mode. In this case, the DB8/HBEN pin as- DB0–DB7 and the second read places the upper 8 bits of the sumes its HBEN function. Data to be accessed from the data word on DB0–DB7. AD7859 must be accessed in two read operations with 8 bits of data provided by the AD7859 on DB0–DB7 for each of the The CS and RD signals are gated internally and level-triggered read operations. The HBEN pin determines whether the read active low. In either word or byte mode, CS and RD may be operation accesses the high byte or low byte of the 16-bit word. tied together as the timing specification for t and t is 0 ns min. 5 6 For a low byte read, DB0 provides the LSB of the 16-bit word. The data is output a time t after both CS and RD go low. The 8 For a high byte read DB0 provides data bit 8 of the 16-bit word RD rising should be used to latch data by the user and after a with DB7 providing the MSB of the 16-bit word. time t the data lines will become three-stated. 9 HBEN t 3 t t t 3 4 4 CS t t 5 10 t 6 t 7 RD t t 9 8 DB0 – DB7 LOW BYTE HIGH BYTE *W/B PIN LOGIC LOW Figure 36. Read Cycle Timing for Byte Mode Operation –24– REV. A AD7859/AD7859L HBEN t 11 t t t 11 12 12 CS t 13 t 14 t 15 WR t t 17 16 DB0 – DB7 LOW BYTE HIGH BYTE *W/B PIN LOGIC LOW Figure 37. Write Cycle Timing for Byte Mode Operation Writing AD7859/AD7859L to ADSP-21xx With W/B at a logic high, a single write operation transfers the Figure 38 shows the AD7859/AD7859L interfaced to the ADSP-21xx series of DSPs as a memory mapped device. A full data word to the AD7859. The DB8/HBEN pin assumes its DB8 function. Data to be written to the AD7859 should be pro- single wait state may be necessary to interface the AD7859/ vided on the DB0–DB15 inputs with DB0 the LSB of the data AD7859L to the ADSP-21xx depending on the clock speed of the DSP. This wait state can be programmed via the Data word. With W/B at a logic low, the AD7859 requires two write operations to transfer a full 16-bit word. DB8/HBEN assumes Memory Waitstate Control Register of the ADSP-21xx (please its HBEN function. Data to be written to the AD7859 should see ADSP-2100 Family Users Manual for details). The following instruction reads data from the AD7859/AD7859L: be provided on the DB0–DB7 inputs. HBEN determines whether the byte which is to be written is high byte or low byte MR = DM(ADC) data. The low byte of the data word should be written first with where ADC is the address of the AD7859/AD7859L. DB0 the LSB of the full data word. For the high byte write, HBEN should be high and the data on the DB0 input should be A13–A0 ADDRESS BUS data bit 8 of the 16-bit word with the data on DB7 the MSB of ADSP-21xx* the 16-bit word. ADDR DMS EN CS DECODE Figure 35 shows the write cycle timing diagram for the AD7859. AD7859/ AD7859L* When operated in word mode, the HBEN input does not exist WR WR and only the first write operation is required to write data to the RD RD AD7859. Data should be provided on DB0–DB15. When oper- IRQ2 BUSY ated in byte mode, the two write cycles shown in Figure 37 are required to write the full data word to the AD7859. In Figure 37, D23–D8 DATA BUS DB15–DB0 the first write transfers the lower 8 bits of the full data from DB0–DB7 and the second write transfers the upper 8 bits of the *ADDITIONAL PINS OMITTED FOR CLARITY data word from DB0-DB7. Figure 38. AD7859/AD7859L to ADSP-21xx Parallel The CS and WR signals are gated internally. CS and WR may Interface be tied together as the timing specification for t and t is 0 ns 13 14 min. The data is latched on the rising edge of WR. The data AD7859/AD7859L to TMS32020, TMS320C25 and TMS320C5x needs to be set up a time t before the WR rising edge and held 16 Parallel interfaces between the AD7859/AD7859L and the for a time t after the WR rising edge. 17 TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 39. The memory mapped address chosen for Resetting the Parallel Interface the AD7859/AD7859L should be chosen to fall in the I/O In the case where incorrect data is inadvertently written to the memory space of the DSPs. AD7859, there is a possibility that the Test Register contents may have been altered. If there is a suspicion that this may have happened and the part is not operating as expected, a 16-bit A15–A0 ADDRESS BUS word 0000 0000 0000 0010 should be written to the AD7859 to TMS32020/ restore the Test Register contents to the default value. TMS320C25/ ADDR IS CS EN TMS320C50* DECODE AD7859/ AD7859L* MICROPROCESSOR INTERFACING READY TMS320C25 Interfacing the AD7859/AD7859L to a 16-Bit Data Bus MSC ONLY STRB WR The parallel port on the AD7859 allows the device to be inter- R/W faced to microprocessors or DSP processors as a memory- RD mapped or I/O-mapped device. The CS and RD inputs are BUSY INTx common to all memory peripheral interfacing. Typical inter- D23–D0 DATA BUS DB15–DB0 faces to different processors are shown in Figures 38 to 42. In all the interfaces shown, an external timer controls the CONVST *ADDITIONAL PINS OMITTED FOR CLARITY input of the AD7859/AD7859L, the BUSY output interrupts the host DSP and the W/B input is logic high. Figure 39. AD7859/AD7859L to TMS32020/C25/C5x Parallel Interface REV. A –25– AD7859/AD7859L The parallel interface on the AD7859/AD7859L is fast enough A15–A0 ADDRESS BUS to interface to the TMS32020 with no extra wait states. If high DSP56000/ speed glue logic such as 74AS devices are used to drive the WR X/Y ADDR DSP56002* CS DECODE and RD lines when interfacing to the TMS320C25, then again DS AD7859/ no wait states are necessary. However, if slower logic is used, AD7859L* data accesses may be slowed sufficiently when reading from and WR WR RD RD writing to the part to require the insertion of one wait state. In BUSY IRQ such a case, this wait state can be generated using the single OR gate to combine the CS and MSC signals to drive the READY line of the TMS320C25, as shown in Figure 39. Extra wait D23–D0 DATA BUS DB15–DB0 states will be necessary when using the TMS320C5x at their fastest clock speeds. Wait states can be programmed via the *ADDITIONAL PINS OMITTED FOR CLARITY IOWSR and CWSR registers (please see TMS320C5x User Figure 41. AD7859/AD7859L to DSP5600x Parallel Interface Guide for details). Interfacing the AD7859/AD7859L to an 8-Bit Data Bus Data is read from the ADC using the following instruction: AD7859/AD7859L to 8051 IN D,ADC This mode of operation allows the AD7859/AD7859L to be in- where D is the memory location where the data is to be stored terfaced directly to microcontrollors with an 8-bit data bus. The and ADC is the I/O address of the AD7859/AD7859L. AD7859/AD7859L is placed in byte mode by placing a logic low signal on the W/B pin. AD7859/AD7859L to TMS320C30 Figure 40 shows a parallel interface between the AD7859/ Figure 42 shows a parallel interface between the AD7859/ AD7859L and the TMS320C3x family of DSPs. The AD7859/ AD7859L and the 8051 microcontroller. Here the W/B pin is AD7859L is interfaced to the Expansion Bus of the TMS320C3x. tied logic low and the DB8/HBEN pin connected to line 1 of A single wait state is required in this interface. This can be pro- Port 2. Port 0 serves as a multiplexed address/data bus to the grammed using the WTCNT bits of the Expansion Bus Control AD7859/AD7859L. Alternatively if the 8051 is not using exter- register (see TMS320C3x Users Guide for details). Data from nal memory or other memory mapped peripheral devices, line 2 the AD7859/AD7859L can be read using the following instruction: of Port 2 (or any other line) could be used as the CS signal. LDI *ARn,Rx where ARn is an auxiliary register containing the lower 16 bits DB7–DB0 P0 of the address of the AD7859/AD7859L in the TMS320C3x ALE LATCH AD7859/ memory space and Rx is the register into which the ADC data is AD7859L* loaded. 8051* ADDR CS DECODE XA12–XA0 EXPANSION ADDRESS BUS P2.1 DB8/HBEN WR WR TMS320C30* ADDR CS RD RD DECODE AD7859/ BUSY INT0 AD7859L* IOSTRB WR W/B XR/W DGND RD *ADDITIONAL PINS OMITTED FOR CLARITY BUSY INTx Figure 42. AD7859/AD7859L to 8051 Parallel Interface XD23–XD0 EXPANSION DATA BUS DB15–DB0 APPLICATION HINTS *ADDITIONAL PINS OMITTED FOR CLARITY Grounding and Layout Figure 40. AD7859/AD7859L to TMS320C30 Parallel Interface The analog and digital supplies of the AD7859/AD7859L are independent and separately pinned out to minimize coupling AD7859/AD7859L to DSP5600x between the analog and digital sections of the device. The part Figure 41 shows a parallel interface between the AD7859/ has very good immunity to noise on the power supplies as can AD7859L and the DSP5600x series of DSPs. The AD7859/ be seen by the PSRR versus Frequency graph. However, care AD7859L should be mapped into the top 64 locations of Y data should still be taken with regard to grounding and layout. memory. If extra wait states are needed in this interface, they can be programmed using the Port A Bus Control Register The printed circuit board on which the AD7859/AD7859L is (please see DSP5600x Users Manual for details). Data can be mounted should be designed such that the analog and digital read from the AD7859/AD7859L using the following instruction: sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be eas- MOVEO Y:ADC,X0 ily separated. A minimum etch technique is generally best for where ADC is the address in the DSP5600x address space ground planes as it gives the best shielding. Digital and analog which the AD7859/AD7859L has been mapped to. ground planes should only be joined in one place. If the AD7859/AD7859L is the only device requiring an AGND to –26– REV. A AD7859/AD7859L DGND connection, then the ground planes should be con- The software allows the user to perform ac (fast Fourier trans- nected at the AGND and DGND pins of the AD7859/ form) and dc (histogram of codes) tests on the AD7859/ AD7859L. If the AD7859/AD7859L is in a system where mul- AD7859L. It also gives full access to all the AD7859/AD7859L tiple devices require AGND to DGND connections, the con- on-chip registers allowing for various calibration and power- nection should still be made at one point only, a star ground down options to be programmed. point which should be established as close as possible to the AD785x Family AD7859/AD7859L. All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V. Avoid running digital lines under the device as these couple AD7853 – Single-Channel Serial noise onto the die. The analog ground plane should be allowed AD7854 – Single-Channel Parallel to run under the AD7859/AD7859L to avoid noise coupling. The power supply lines to the AD7859/AD7859L should use as AD7858 – Eight-Channel Serial large a trace as possible to provide low impedance paths and AD7859 – Eight-Channel Parallel reduce the effects of glitches on the power supply line. Fast switching signals like clocks and the data inputs should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not al- ways possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with a 10 μF tantalum capacitor in parallel with 0.1 μF disc ceramic capacitor to AGND. All digital supplies should have a 0.1 μF disc ceramic capacitor to DGND. To achieve the best performance from these decoupling compo- nents, they must be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AV and DV of the DD DD AD7859/AD7859L, it is recommended that the system’s AV DD supply is used. In this case an optional 10 Ω resistor between the AV pin and DV pin can help to filter noise from digital DD DD circuitry. This supply should have the recommended analog supply decoupling capacitors between the AV pin of the DD AD7859/AD7859L and AGND and the recommended digital supply decoupling capacitor between the DV pin of the DD AD7859/AD7859L and DGND. Evaluating the AD7859/AD7859L Performance The recommended layout for the AD7859/AD7859L is outlined in the evaluation board for the AD7859/AD7859L. The evalua- tion board package includes a fully assembled and tested evalua- tion board, documentation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7859/AD7859L Evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7859/AD7859L. REV. A –27– PAGE INDEX OUTLINE DIMENSIONS Topic Page Dimensions shown in inches and (mm). FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44-Lead PLCC (P-44A) PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0.056 (1.42) 0.025 (0.63) 0.042 (1.07) 0.042 (1.07) 0.015 (0.38) ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 5 6 40 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 39 PIN 1 0.021 (0.53) 0.048 (1.21) IDENTIFIER PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0.013 (0.33) 0.042 (1.07) TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0.63 (16.00) 0.59 (14.99) PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 7 0.032 (0.81) TOP VIEW AD7859/AD7859L ON-CHIP REGISTERS . . . . . . . . . . . . . . . 8 0.026 (0.66) Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . . . . 8 0.050 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 (1.27) BSC CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 29 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 18 28 0.020 0.040 (1.01) 0.656 (16.66) CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 12 (0.50) 0.025 (0.64) SQ R 0.650 (16.51) 0.110 (2.79) Addressing the Calibration Registers . . . . . . . . . . . . . . . . . . . 12 0.695 (17.65) SQ 0.085 (2.16) 0.685 (17.40) Writing to/Reading from the Calibration Registers . . . . . . . . 12 Adjusting the Offset Calibration Register . . . . . . . . . . . . . . . . 13 Adjusting the Gain Calibration Registers . . . . . . . . . . . . . . . . 13 CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14 44-Pin PQFP CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 (S-44) TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . 14 0.557 (14.15) ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0.537 (13.65) 0.096 (2.45) Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0.397 (10.1) MAX 0.390 (9.9) DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0.037 (0.95) 8° 0.026 (0.65) Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 0° 33 23 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 34 22 REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AD7859/AD7859L PERFORMANCE CURVES . . . . . . . . . . 17 POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18 0.398 (10.1) TOP VIEW POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 0.390 (9.9) POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . . . 19 CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PIN 1 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 44 12 1 Calibration on Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11 0.040 (1.02) Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . . . 21 0.032 (0.82) 0.040 (1.02) Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 0.032 (0.82) 0.016 (0.4) 0.033 (0.85) System Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 22 0.083 (2.1) 0.029 (0.75) 0.012 (0.3) 0.077 (1.95) System Gain and Offset Interaction . . . . . . . . . . . . . . . . . . . . 23 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . 25 APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Evaluating the AD7859/AD7859L Performance . . . . . . . . . . 27 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 –28– PRINTED IN U.S.A. C2109–7–1/96