ANALOG DEVICES AD7854

3 V to 5 V Single Supply, 200 kSPS a 12-Bit Sampling ADCs AD7854/AD7854L FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for V of 3 V to 5.5 V AV AGND DD DD Read-Only Operation AD7854–200 kSPS; AD7854L–100 kSPS AIN(+) AD7854/AD7854L T/H System and Self-Calibration AIN(–) Low Power DV 2.5V DD Normal Operation REFERENCE AD7854: 15 mW (V = 3 V) DD COMP REF / IN AD7854L: 5.5 mW (V = 3 V) BUF DD REF OUT Automatic Power-Down After Conversion (25�W) DGND AD7854: 1.3 mW 10 kSPS C REF1 CHARGE AD7854L: 650 �W 10 kSPS REDISTRIBUTION DAC Flexible Parallel Interface CLKIN 12-Bit Parallel/8-Bit Parallel (AD7854) SAR + ADC CONVST C 28-Lead DIP, SOIC and SSOP Packages (AD7854) REF2 CONTROL CALIBRATION BUSY MEMORY APPLICATIONS AND CONTROLLER Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) Pen Computers PARALLEL INTERFACE/CONTROL REGISTER Instrumentation and Control Systems High Speed Modems HBEN DB11–DB0 CS RD WR GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7854/AD7854L is a high speed, low power, 12-bit ADC 1. Operation with either 3 V or 5 V power supplies. that operates from a single 3 V or 5 V power supply, the 2. Flexible power management options including automatic AD7854 being optimized for speed and the AD7854L for low power-down after conversion. By using the power manage- power. The ADC powers up with a set of default conditions at ment options a superior power performance at slower which time it can be operated as a read-only ADC. The ADC throughput rates can be achieved: contains self-calibration and system calibration options to en- AD7854: 1 mW typ @ 10 kSPS sure accurate operation over time and temperature and has a AD7854L: 1 mW typ @ 20 kSPS number of power-down options for low power applications. 3. Operates with reference voltages from 1.2 V to AV . DD The AD7854 is capable of 200 kHz throughput rate while the 4. Analog input ranges from 0 V to AV . DD AD7854L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- 5. Self-calibration and system calibration. differential sampling scheme. The AD7854 and AD7854L input 6. Versatile parallel I/O port. voltage range is 0 to V (unipolar) and –V /2 to +V /2, REF REF REF 7. Lower power version AD7854L. centered at V /2 (bipolar). The coding is straight binary in REF unipolar mode and twos complement in bipolar mode. Input signal range is to the supply and the part is capable of convert- ing full-power signals to 100 kHz. CMOS construction ensures low power dissipation of typically 5.4 mW for normal operation and 3.6 µW in power-down mode. The part is available in 28-lead, 0.6 inch wide dual-in-line pack- age (DIP), 28-lead small outline (SOIC) and 28-lead small shrink outline (SSOP) packages. See Page 27 for data sheet index. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 1, 2 (AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V AD7854/AD7854L–SPECIFICATIONS DD DD IN OUT External Reference, f = 4 MHz (for L Version: 1.8 MHz (0�C to +70�C) and 1 MHz (–40�C to +85�C)); f = 200 kHz (AD7854), 100 kHz CLKIN SAMPLE (AD7854L); T = T to T , unless otherwise noted.) Specifications in () apply to the AD7854L. A MIN MAX 1 1 1 Parameter A Version B Version S Version Units Test Conditions/Comments DYNAMIC PERFORMANCE 3 Signal to Noise + Distortion Ratio 70 71 70 dB min Typically SNR is 72 dB (SNR) V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Total Harmonic Distortion (THD) –78 –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Peak Harmonic or Spurious Noise –78 –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz IN SAMPLE (L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Intermodulation Distortion (IMD) Second Order Terms –78 –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 200 kHz SAMPLE (L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN Third Order Terms –78 –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 200 kHz SAMPLE (L Version: f = 100 kHz @ f = 2 MHz) SAMPLE CLKIN DC ACCURACY Resolution 12 12 12 Bits Integral Nonlinearity ±1 ±0.5 ±1 LSB max 5 V Reference V = 5 V DD Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits Unipolar Offset Error ±3 ±3 ±4 LSB max ±2 ±2 ±2 LSB typ Unipolar Gain Error ±4 ±4 ±4 LSB max ±2 ±2 ±2 LSB typ Bipolar Positive Full-Scale Error ±4 ±4 ±5 LSB max ±2 ±2 ±2 LSB typ Negative Full-Scale Error ±4 ±4 ±5 LSB max ±2 ±2 ±2 LSB typ Bipolar Zero Error ±4 ±4 ±5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V 0 to V Volts i.e., AIN(+) – AIN(–) = 0 to V , AIN(–) can be REF REF REF REF biased up but AIN(+) cannot go below AIN(–). ±V /2 ±V /2 ±V /2 Volts i.e., AIN(+) – AIN(–) = –V /2 to +V /2, AIN(–) REF REF REF REF REF should be biased to +V /2 and AIN(+) can go below REF AIN(–) but cannot go below 0 V. Leakage Current ±1 ±1 ±1 µA max Input Capacitance 20 20 20 pF typ REFERENCE INPUT/OUTPUT REF Input Voltage Range 2.3/V 2.3/V 2.3/V V min/max Functional from 1.2 V IN DD DD DD Input Impedance 150 150 150 kΩ typ REF Output Voltage 2.3/2.75 2.3/2.7 2.3/2.7 V min/max OUT REF Tempco 20 20 20 ppm/°C typ OUT LOGIC INPUTS Input High Voltage, V 3 3 3 V min AV = DV = 4.5 V to 5.5 V INH DD DD 2.1 2.1 2.1 V min AV = DV = 3.0 V to 3.6 V DD DD Input Low Voltage, V 0.4 0.4 0.4 V max AV = DV = 4.5 V to 5.5 V INL DD DD 0.6 0.6 0.6 V max AV = DV = 3.0 V to 3.6 V DD DD Input Current, I ±10 ±10 ±10 µA max Typically 10 nA, V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V I = 200 µA OH SOURCE 4 4 4 V min AV = DV = 4.5 V to 5.5 V DD DD 2.4 2.4 2.4 V min AV = DV = 3.0 V to 3.6 V DD DD Output Low Voltage, V 0.4 0.4 0.4 V max I = 0.8 mA OL SINK Floating-State Leakage Current ±10 ±10 ±10 µA max 4 Floating-State Output Capacitance 10 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range Twos Complement Bipolar Input Range CONVERSION RATE t × 18 CLKIN Conversion Time 4.6 (10) 4.6 (9) 4.6 (9) µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN) Track/Hold Acquisition Time 0.5 (1) 0.5 (1) 0.5 (1) µs min (L Versions Only, –40°C to +85°C, 1 MHz CLKIN) –2– REV. B AD7854/AD7854L 1 1 1 Parameter A Version B Version S Version Units Test Conditions/Comments POWER REQUIREMENTS AV DV +3.0/+5.5 +3.0/+5.5 +3.0/+5.5 V min/max DD, DD I DD 5 Normal Mode 5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV = DV = 4.5 V to 5.5 V. Typically 4.5 mA DD DD (1.5 mA); 5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV = DV = 3.0 V to 3.6 V. Typically 4.0 mA DD DD (1.5 mA). 6 Sleep Mode With External Clock On 10 10 10 µA typ Full power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 400 400 400 µA typ Partial power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 5 5 5 µA max Typically 1 µA. Full power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 200 200 200 µA typ Partial power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 30 (10) 30 (10) 30 (10) mW max V = 5.5 V: Typically 25 mW (8) DD 20 (6.5) 20 (6.5) 20 (6.5) mW max V = 3.6 V: Typically 15 mW (5.4) DD Sleep Mode Power Dissipation With External Clock On 55 55 55 µW typ V = 5.5 V DD 36 36 36 µW typ V = 3.6 V DD With External Clock Off 27.5 27.5 27.5 µW max V = 5.5 V: Typically 5.5 µW DD 18 18 18 µW max V = 3.6 V: Typically 3.6 µW DD SYSTEM CALIBRATION 7 Offset Calibration Span +0.05 × V /–0.05 × V V max/min Allowable Offset Voltage Span for Calibration REF REF 7 Gain Calibration Span +0.025 × V /–0.025 × V V max/min Allowable Full-Scale Voltage Span for Calibration REF REF NOTES 1 Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C. 2 Specifications apply after calibration. 3 Not production tested. Guaranteed by characterization at initial product release. 4 Sample tested @ +25°C to ensure compliance. 5 All digital inputs @ DGND except for CONVST @ DV . No load on the digital outputs. Analog inputs @ AGND. DD 6 CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DV . No load on the digital outputs. Analog inputs @ AGND. DD 7 The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V , REF and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V ± 0.025 × V REF REF (unipolar mode) and V /2 ± 0.025 × V (bipolar mode)). This is explained in more detail in the calibration section of the data sheet. REF REF Specifications subject to change without notice. REV. B –3– AD7854/AD7854L (AV = DV = +3.0 V to +5.5 V; f = 4 MHz for AD7854 and 1.8 MHz for AD7854L; DD DD CLKIN 1 T = T to T , unless otherwise noted) TIMING SPECIFICATIONS A MIN MAX Limit at T , T MIN MAX (A, B, S Versions) Parameter 5 V 3 V Units Description 2 f 500 500 kHz min Master Clock Frequency CLKIN 4 4 MHz max 1.8 1.8 MHz max L Version 3 t 100 100 ns min CONVST Pulsewidth 1 t 50 90 ns max CONVST to BUSY ↑ Propagation Delay 2 t 4.5 4.5 µs max Conversion Time = 18 t CONVERT CLKIN 10 10 µs max L Version 1.8 MHz CLKIN. Conversion Time = 18 t CLKIN t 15 15 ns min HBEN to RD Setup Time 3 t 5 5 ns min HBEN to RD Hold Time 4 t 0 0 ns min CS to RD to Setup Time 5 t 0 0 ns min CS to RD Hold Time 6 t 55 70 ns min RD Pulsewidth 7 4 t 50 50 ns max Data Access Time After RD 8 5 t 5 5 ns min Bus Relinquish Time After RD 9 40 40 ns max t 60 70 ns min Minimum Time Between Reads 10 t 0 0 ns min HBEN to WR Setup Time 11 t 5 5 ns max HBEN to WR Hold Time 12 t 0 0 ns min CS to WR Setup Time 13 t 0 0 ns max CS to WR Hold Time 14 t 55 70 ns min WR Pulsewidth 15 t 10 10 ns min Data Setup Time Before WR 16 t 5 5 ns min Data Hold Time After WR 17 4 t 1/2 t 1/2 t ns min New Data Valid Before Falling Edge of BUSY 18 CLKIN CLKIN t 50 70 ns min HBEN High Pulse Duration 19 t 50 70 ns min HBEN Low Pulse Duration 20 t 40 60 ns min Propagation Delay from HBEN Rising Edge to Data Valid 21 t 40 60 ns min Propagation Delay from HBEN Falling Edge to Data Valid 22 t 2.5 t 2.5 t ns max CS↑ to BUSY ↑ in Calibration Sequence 23 CLKIN CLKIN 6 t 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013 CAL t ) CLKIN 6 t 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock CAL1 Dependent (111124 t ) CLKIN 6 t 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent CAL2 (13889 t ) CLKIN NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD 2 Mark/Space ratio for the master clock input is 40/60 to 60/40. 3 The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down section). 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated 9 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 9 time of the part and is independent of the bus loading. 6 The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice. REV. B –4– AD7854/AD7854L 1 ABSOLUTE MAXIMUM RATINGS 1.6mA I OL (T = +25°C unless otherwise noted) A AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD TO DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD OUTPUT +2.1V PIN C AV to DV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DD DD L 50pF Analog Input Voltage to AGND . . . . –0.3 V to AV + 0.3 V DD Digital Input Voltage to DGND . . . . –0.3 V to DV + 0.3 V DD 200µA I OH Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V DD REF /REF to AGND . . . . . . . . . –0.3 V to AV + 0.3 V IN OUT DD Figure 1. Load Circuit for Digital Output Timing 2 Input Current to Any Pin Except Supplies . . . . . . . . . ±10 mA Specifications Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C PIN CONFIGURATION Storage Temperature Range . . . . . . . . . . . –65°C to +150°C FOR DIP, SOIC AND SSOP Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C 1 28 Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW CONVST BUSY 2 27 θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W WR CLKIN JA 3 26 Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +300°C RD DB11 4 SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW CS 25 DB10 5 θ Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP) 24 DB9 JA REF /REF IN OUT AD7854 6 θ Thermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP) AV 23 JC TOP VIEW DGND DD (Not to Scale) 7 Lead Temperature, Soldering AGND 22 DV DD 8 Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C 21 C DB8 REF1 9 20 Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C C DB7 REF2 10 19 AIN(+) DB6 NOTES 1 11 18 AIN(–) DB5 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the 12 17 HBEN DB4 device at these or any other conditions above those listed in the operational 13 16 DB0 DB3 sections of this specification is not implied. Exposure to absolute maximum rating 14 15 DB1 DB2 conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latchup. ORDERING GUIDE Linearity Power Temperature Error Dissipation Package 1 2 Model Range (LSB) (mW) Option AD7854AQ –40°C to +85°C 1 15 Q-28 AD7854SQ –55°C to +125°C 1 15 Q-28 AD7854AR –40°C to +85°C 1 15 R-28 AD7854BR –40°C to +85°C 1/2 15 R-28 AD7854ARS –40°C to +85°C 1 15 RS-28 3 AD7854LAQ –40°C to +85°C 1 5.5 Q-28 3 AD7854LAR –40°C to +85°C 1 5.5 R-28 3 AD7854LARS –40°C to +85°C 1 5.5 RS-28 4 EVAL-AD7854CB 5 EVAL-CONTROL BOARD NOTES 1 Linearity error refers to the integral linearity error. 2 Q = Cerdip; R = SOIC; RS = SSOP. 3 L signifies the low power version. 4 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. For more information on Analog Devices products and evaluation boards visit our World Wide Web home page at http://www.analog.com. REV. B –5– AD7854/AD7854L PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV . DD 2 WR Write Input. Active low logic input. Used in conjunction with CS and HBEN to write to internal registers. 3 RD Read Input. Active low logic input. Used in conjunction with CS and HBEN to read from internal registers. 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 REF / Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the IN REF reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears OUT at the pin. This pin can be overdriven by an external reference and can be taken as high as AV . When DD this pin is tied to AV , then the C pin should also be tied to AV . DD REF1 DD 6AV Analog Positive Supply Voltage, +3.0 V to +5.5 V. DD 7 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 8C Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the REF1 internal DAC. The capacitor should be tied between the pin and AGND. 9C Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip REF2 reference. The capacitor should be tied between the pin and AGND. 10 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time, and cannot go below AIN(–) when the unipolar input range is selected. DD 11 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time. DD 12 HBEN High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a read cycle with HBEN low. When HBEN is high, then the high byte of data that is written to or read from the part is on DB0 to DB7. When HBEN is low, then the lowest byte of data being written to the part is on DB0 to DB7. If reading from the part with HBEN low, then the lowest 12 bits of data appear on pins DB0 to DB11. This allows a single read from the ADC or from the control register in a 16-bit bus system. However, two reads are needed to access the calibration registers. Also, two writes are necessary to write to any of the registers. 13–21 DB0–DB8 Data Bits 0 to 8. Three state data I/O pins that are controlled by CS, RD, WR and HBEN. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). 22 DV Digital Supply Voltage, +3.0 V to +5.5 V. DD 23 DGND Digital Ground. Ground reference point for digital circuitry. 24–26 DB9–DB11 Data Bits 9 to 11. Three state data output pins that are controlled by CS, RD and HBEN. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). These output pins should be tied to via 100 kΩ resistors when the AD7854/AD7854L is being interfaced to an 8-bit data bus. DV DD 27 CLKIN Master Clock Signal for the device (4 MHz for AD7854, 1.8 MHz for AD7854L). Sets the conversion and calibration times. 28 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. BUSY is also used to indicate when the AD7854/AD7854L has completed its on- chip calibration sequence. REV. B –6– AD7854/AD7854L TERMINOLOGY Total Harmonic Distortion Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum of This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7854/AD7854L, it is through the endpoints of the ADC transfer function. The end- defined as: points of the transfer function are zero scale, a point 1/2 LSB 2 2 2 2 2 below the first code transition, and full scale, a point 1/2 LSB (V +V +V +V +V ) 2 3 4 5 6 above the last code transition. THD (dB) = 20log V 1 Differential Nonlinearity where V is the rms amplitude of the fundamental and V , V , This is the difference between the measured and the ideal 1 LSB 1 2 3 V , V and V are the rms amplitudes of the second through the change between any two adjacent codes in the ADC. 4 5 6 sixth harmonics. Unipolar Offset Error Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000 to Peak harmonic or spurious noise is defined as the ratio of the 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) rms value of the next largest component in the ADC output when operating in the unipolar mode. spectrum (up to f /2 and excluding dc) to the rms value of the S Unipolar Gain Error fundamental. Normally, the value of this specification is deter- This is the deviation of the last code transition (111 . . . 110 to mined by the largest harmonic in the spectrum, but for ADCs 111 . . . 111) from the ideal, i.e., AIN(–) +V /2 – 1.5 LSB, REF where the harmonics are buried in the noise floor, it will be a after the unipolar offset error has been adjusted out. noise peak. Bipolar Positive Full-Scale Error Intermodulation Distortion This applies to the bipolar modes only and is the deviation of the With inputs consisting of sine waves at two frequencies, fa and last code transition from the ideal AIN(+) voltage. For bipolar fb, any active device with nonlinearities will create distortion mode, the ideal AIN(+) voltage is (AIN(–) +V /2 – 1.5 LSB). REF products at sum and difference frequencies of mfa ± nfb where Negative Full-Scale Error m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are This applies to the bipolar mode only and is the deviation of the those for which neither m nor n are equal to zero. For example, first code transition (10 . . . 000 to 10 . . . 001) from the ideal the second order terms include (fa + fb) and (fa – fb), while the AIN(+) voltage (AIN(–) – V /2 + 0.5 LSB). REF third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Bipolar Zero Error This is the deviation of the midscale transition (all 0s to all 1s) Testing is performed using the CCIF standard where two input from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in fre- Track/Hold Acquisition Time quency from the original sine waves while the third order terms The track/hold amplifier returns into track mode and the end of are usually at a frequency close to the input frequencies. As a conversion. Track/Hold acquisition time is the time required for result, the second and third order terms are specified separately. the output of the track/hold amplifier to reach its final value, The calculation of the intermodulation distortion is as per the within ±1/2 LSB, after the end of conversion. THD specification where it is the ratio of the rms sum of the Signal to (Noise + Distortion) Ratio individual distortion products to the rms amplitude of the sum This is the measured ratio of signal to (noise + distortion) at the of the fundamentals expressed in dBs. output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f /2), excluding dc. The S ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. REV. B –7– AD7854/AD7854L AD7854/AD7854L ON-CHIP REGISTERS The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DV for operating the AD7854/AD7854L as a DD read-only ADC. Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali- bration, and software conversion start can be selected by writing to the part. The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra- tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to. Addressing the On-Chip Registers Writing To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first 8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the 8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy. Table I. Write Register Addressing ADDR1 ADDR0 Comment 0 0 This combination does not address any register. 0 1 This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register. 1 0 This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are writ- ten to the selected calibration register. 1 1 This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first. Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register until the read selection bits are changed in the control register. Table II. Read Register Addressing RDSLT1 RDSLT0 Comment 0 0 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power- up setting. There is always four leading zeros when reading from the ADC output data register. 0 1 All successive read operations are from the TEST REGISTER. 1 0 All successive read operations are from the CALIBRATION REGISTERS. 1 1 All successive read operations are from the STATUS REGISTER. ADDR1, ADDR0 RDSLT1, RDSLT0 DECODE DECODE 01 10 11 00 01 10 11 TEST CALIBRATION CONTROL ADC OUTPUT TEST CALIBRATION CONTROL REGISTERS REGISTER REGISTERS REGISTER DATA REGISTER REGISTER REGISTER GAIN(1) GAIN(1) GAIN(1) GAIN(1) OFFSET(1) GAIN(1) OFFSET(1) GAIN(1) OFFSET(1) OFFSET(1) OFFSET(1) OFFSET(1) DAC(8) DAC(8) 00 01 10 11 00 01 10 11 CALSLT1, CALSLT0 CALSLT1, CALSLT0 DECODE DECODE Figure 3. Read Register Hierarchy/Address Decoding Figure 2. Write Register Hierarchy/Address Decoding REV. B –8– AD7854/AD7854L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described below. The power-up status of all bits is 0. MSB ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 AMODE CONVST CALMD CALSLT1 CALSLT0 STCAL LSB Control Register Bit Function Description Bit Mnemonic Comment 13 ZERO These four bits must be set to 0 when writing to the control register. 12 ZERO 11 ZERO 10 ZERO 9 PMGT1 Power Management Bits. These two bits are used for putting the part into various power-down modes 8 PMGT0 (See Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II. 6 RDSLT0 5 AMODE Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit position selects range 0 to V (i.e., AIN(+) – AIN(–) = 0 to V ). In this range AIN(+) cannot go REF REF below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this bit position selects range –V /2 to +V /2 (i.e., AIN(+) – AIN(–) = –V /2 to +V /2). AIN(+) REF REF REF REF cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +V /2 to allow REF AIN(+) to go as low as AIN(–) –V /2 V. Data coding is twos complement for this range. REF 4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration (see Calibration section). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions. 1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per- 0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details). Table III. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 00 0 A full internal calibration is initiated. First the internal DAC is calibrated, then the internal gain error and finally the internal offset error are removed. This is the default setting. 0 0 1 First the internal gain error is removed, then the internal offset error is removed. 0 1 0 The internal offset error only is calibrated out. 0 1 1 The internal gain error only is calibrated out. 10 0 A full system calibration is initiated. First the internal DAC is calibrated, followed by the system gain error calibration, and finally the system offset error calibration. 1 0 1 First the system gain error is calibrated out followed by the system offset error. 1 1 0 The system offset error only is removed. 1 1 1 The system gain error only is removed. REV. B –9– AD7854/AD7854L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 4. Flowchart for Reading the Status Register MSB ZERO ZERO ZERO ZERO ZERO ZERO PMGT1 PMGT0 ONE ONE AMODE BUSY CALMD CALSLT1 CALSLT0 STCAL LSB Status Register Bit Function Description Bit Mnemonic Comment 15 ZERO These six bits are always 0. 14 ZERO 13 ZERO 12 ZERO 11 ZERO 10 ZERO 9 PMGT1 Power Management Bits. These bits will indicate if the part is in a power-down mode or not. See Table VI 8 PMGT0 in Power-Down Section for description. 7 ONE Both these bits are always 1. 6 ONE 5 AMODE Analog Mode Bit. When this bit is a 0, the device is set up for the unipolar analog input range. When this bit is a 1, the device is set up for the bipolar analog input range. 4 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration in progress. When this bit is 0, there is no conversion or calibration in progress. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in 1 CALSLT0 progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate 0 STCAL which of the calibration registers are addressed for reading and writing (see section on the Calibration Registers for more details). REV. B –10– AD7854/AD7854L CALIBRATION REGISTERS The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. Addressing the Calibration Registers The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are addressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time. Table IV. Calibration Register Addressing CALSLT1 CALSLT0 Comment 0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. 0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total. 1 0 This combination addresses the Offset Register. One register in total. 1 1 This combination addresses the Gain Register. One register in total. Writing to/Reading from the Calibration Registers When reading from the calibration registers there are always two When writing to the calibration registers a write to the control leading zeros for each of the registers. register is required to set the CALSLT0 and CALSLT1 bits. When reading from the calibration registers a write to the con- START trol register is required to set the CALSLT0 and CALSLT1 bits and also to set the RDSLT1 and RDSLT0 bits to 10 (this WRITE TO CONTROL REGISTER SETTING STCAL = 0 addresses the calibration registers for reading). The calibration AND CALSLT1, CALSLT0 = 00, 01, 10, 11 register pointer is reset on writing to the control register setting the CALSLT1 and CALSLT0 bits, or upon completion of all CAL REGISTER POINTER IS AUTOMATICALLY RESET the calibration register write/read operations. When reset it points to the first calibration register in the selected write/read sequence. The calibration register pointer points to the gain WRITE TO CAL REGISTER (ADDR1 = 1, ADDR0 = 0) calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (CALSLT1 = 1, CALSLT0 = 0). Where more than one cali- CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED bration register is being accessed, the calibration register pointer is automatically incremented after each full calibration register write/read operation. The calibration register address pointer is LAST incremented after the high byte read or write operation in byte REGISTER WRITE NO mode. Therefore when reading from or writing to the calibra- OPERATION OR tion registers, the low byte transfer must be carried out first, i.e., ABORT ? HBEN is at logic zero. The order in which the 10 calibration registers are arranged is shown in Figure 5. Read/Write opera- YES tions may be aborted at any time before all the calibration FINISHED registers have been accessed, and the next control register write operation resets the calibration register pointer. The flowchart Figure 6. Flowchart for Writing to the Calibration Registers in Figure 6 shows the sequence for writing to the calibration registers. Figure 7 shows the sequence for reading from the cali- bration registers. CALIBRATION REGISTERS CAL REGISTER GAIN REGISTER (1) ADDRESS POINTER OFFSET REGISTER (2) DAC 1ST MSB REGISTER (3) DAC 8TH MSB REGISTER (10) CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS. Figure 5. Calibration Register Arrangement REV. B –11– AD7854/AD7854L has a weighting of 1.25%, and so on down to the LSB which has START a weighting of 0.0006%. This gives a resolution of ±0.0006% of V approximately. The resolution can also be expressed as REF WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, 13 ±(0.05 × V )/2 volts. This equals ±0.015 mV, with a 2.5 V REF RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 reference. The maximum offset that can be compensated for is ±5% of the reference voltage, which equates to ±125 mV with a CAL REGISTER POINTER IS AUTOMATICALLY RESET 2.5 V reference and ±250 mV with a 5 V reference. Q. If a +20 mV offset is present in the analog input signal and the READ CAL REGISTER reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset ? CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED A. 2.5 V reference implies that the resolution in the offset reg- 13 ister is 5% × 2.5 V/2 = 0.015 mV. +20 mV/0.015 mV = 1310.72; rounding to the nearest number gives 1311. In LAST REGISTER binary terms this is 00 0101 0001 1111, therefore increase NO READ the offset register by 00 0101 0001 1111. OPERATION OR ABORT This method of compensating for offset in the analog input sig- ? nal allows for fine tuning the offset compensation. If the offset YES on the analog input signal is known, there is no need to apply FINISHED the offset voltage to the analog input pins and do a system cali- bration. The offset compensation can take place in software. Figure 7. Flowchart for Reading from the Calibration Adjusting the Gain Calibration Register Registers The gain calibration register contains 16 bits. The two MSBs Adjusting the Offset Calibration Register are zero and the 14 LSBs contain gain data. As in the offset cali- The offset calibration register contains 16 bits. The two MSBs bration register the data bits in the gain calibration register are are zero and the 14 LSBs contain offset data. By changing the binary weighted, with the MSB having a weighting of 2.5% of contents of the offset register, different amounts of offset on the the reference voltage. The gain register value is effectively multi- analog input signal can be compensated for. Decreasing the plied by the analog input to scale the conversion result over the number in the offset calibration register compensates for nega- full range. Increasing the gain register compensates for a tive offset on the analog input signal, and increasing the number smaller analog input range and decreasing the gain register com- in the offset calibration register compensates for positive offset pensates for a larger input range. The maximum analog input on the analog input signal. The default value of the offset cali- range that the gain register can compensate for is 1.025 times bration register is 0010 0000 0000 0000 approximately. This is the reference voltage, and the minimum input range is 0.975 not the exact value, but the value in the offset register should be times the reference voltage. close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the refer- ence voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 REV. B –12– AD7854/AD7854L CIRCUIT INFORMATION When using the software conversion start for maximum The AD7854/AD7854L is a fast, 12-bit single supply A/D con- throughput, the user must ensure the control register write verter. The part requires an external 4 MHz/1.8 MHz master operation extends beyond the falling edge of BUSY. The falling clock (CLKIN), two C capacitors, a CONVST signal to start edge of BUSY resets the CONVST bit to 0 and allows it to be REF conversion and power supply decoupling capacitors. The part reprogrammed to 1 to start the next conversion. provides the user with track/hold, on-chip reference, calibration features, A/D converter and parallel interface logic functions on TYPICAL CONNECTION DIAGRAM a single chip. The A/D converter section of the AD7854/ Figure 8 shows a typical connection diagram for the AD7854/ AD7854L consists of a conventional successive-approximation AD7854L. The AGND and the DGND pins are connected converter based around a capacitor DAC. The AD7854/ together at the device for good noise suppression. The first AD7854L accepts an analog input range of 0 to +V V CONVST applied after power-up starts a self-calibration REF. REF can be tied to V . The reference input to the part connected sequence. This is explained in the calibration section of the data DD via a 150 kΩ resistor to the internal 2.5 V reference and to the sheet. Applying the RD and CS signals causes the conversion on-chip buffer. result to be output on the 12 data pins. Note that after power is applied to AV and DV , and the CONVST signal is applied, DD DD A major advantage of the AD7854/AD7854L is that a conver- the part requires (70 ms + 1/sample rate) for the internal refer- sion can be initiated in software as well as applying a signal to ence to settle and for the self-calibration to be completed. the CONVST pin. The part is available in a 28-Lead SSOP package, and this offers the user considerable space saving advan- 4MHz/1.8MHz tages over alternative solutions. The AD7854L version typically OSCILLATOR consumes only 5.5 mW making it ideal for battery-powered ANALOG applications. SUPPLY +3V TO +5V 10�F 0.1�F 0.1�F CONVERSION CONVERTER DETAILS START SIGNAL The master clock for the part is applied to the CLKIN pin. AV DV DD DD CLKIN Conversion is initiated on the AD7854/AD7854L by pulsing the 0V TO 2.5V AIN(+) INPUT CONVST input or by writing to the control register and setting CONVST AIN(–) the CONVST bit to 1. On the rising edge of CONVST (or at the HBEN end of the control register write operation), the on-chip track/ C REF1 hold goes from track to hold mode. The falling edge of the CLKIN 0.1�F AD7854/ CS AD7854L signal which follows the rising edge of CONVST initates the RD C REF2 conversion, provided the rising edge of CONVST (or WR when 0.01�F WR �C/�P converting via the control register) occurs typically at least 10 ns BUSY before this CLKIN edge. The conversion takes 16.5 CLKIN AGND periods from this CLKIN falling edge. If the 10 ns setup time is DB0 not met, the conversion takes 17.5 CLKIN periods. DGND DB11 REF /REF IN OUT The time required by the AD7854/AD7854L to acquire a signal depends upon the source resistance connected to the AIN(+) 0.1nF EXTERNAL REFERENCE input. Please refer to the Acquisition Time section for more OPTIONAL AD780/ 0.1�F ON-CHIP REFERENCE EXTERNAL details. REF192 REFERENCE When a conversion is completed, the BUSY output goes low, Figure 8. Typical Circuit and the result of the conversion can be read by accessing the For applications where power consumption is a major concern, data through the data bus. To obtain optimum performance the power-down options can be programmed by writing to the from the part, read or write operations should not occur during part. See Power-Down section for more detail on low power the conversion or less than 200 ns prior to the next CONVST applications. rising edge. Reading/writing during conversion typically de- grades the Signal to (Noise + Distortion) by less than 0.5 dBs. The AD7854 can operate at throughput rates of over 200 kSPS (up to 100 kSPS for the AD7854L). With the AD7854L, 100 kSPS throughput can be obtained as follows: the CLKIN and CONVST signals are arranged to give a conversion time of 16.5 CLKIN periods as described above and 1.5 CLKIN periods are allowed for the acquisition time. With a 1.8 MHz clock, this gives a full cycle time of 10 µs, which equates to a throughput rate of 100 kSPS. REV. B –13– AD7854/AD7854L –72 ANALOG INPUT THD VS. FREQUENCY FOR DIFFERENT The equivalent analog input circuit is shown in Figure 9. Dur- SOURCE IMPEDANCES ing the acquisition interval the switches are both in the track –76 position and the AIN(+) charges the 20 pF capacitor through the 125 Ω resistance. On the rising edge of CONVST switches –80 SW1 and SW2 go into the hold position retaining charge on the R = 1k� IN 20 pF capacitor as a sample of the signal on AIN(+). The AIN(–) is connected to the 20 pF capacitor, and this unbalances –84 the voltage at Node A at the input of the comparator. The capacitor DAC adjusts during the remainder of the conversion –88 R = 50�, 10nF cycle to restore the voltage at Node A to the correct value. This IN AS IN FIGURE 13 action transfers a charge, representing the analog input signal, to the capacitor DAC which in turn forms a digital representation –92 0 20 40 60 80 100 of the analog input signal. The voltage on the AIN(–) pin directly INPUT FREQUENCY – kHz influences the charge transferred to the capacitor DAC at the hold instant. If this voltage changes during the conversion period, Figure 10. THD vs. Analog Input Frequency the DAC representation of the analog input voltage is altered. The maximum source impedance depends on the amount of Therefore it is most important that the voltage on the AIN(–) total harmonic distortion (THD) that can be tolerated. The pin remains constant during the conversion period. Further- THD increases as the source impedance increases. Figure 10 more, it is recommended that the AIN(–) pin is always connected shows a graph of the total harmonic distortion vs. analog input to AGND or to a fixed dc voltage. signal frequency for different source impedances. With the setup as in Figure 11, the THD is at the –90 dB level. With a 125� TRACK source impedance of 1 kΩ and no capacitor on the AIN(+) pin, AIN(+) CAPACITOR the THD increases with frequency. 125� DAC SW1 AIN(–) 20pF In a single supply application (both 3 V and 5 V), the V+ and HOLD NODE A V– of the op amp can be taken directly from the supplies to the SW2 AD7854/AD7854L which eliminates the need for extra external COMPARATOR power supplies. When operating with rail-to-rail inputs and out- TRACK HOLD puts at frequencies greater than 10 kHz, care must be taken in AGND selecting the particular op amp for the application. In particular, Figure 9. Analog Input Equivalent Circuit for single supply applications the input amplifiers should be connected in a gain of –1 arrangement to get the optimum per- Acquisition Time formance. Figure 11 shows the arrangement for a single supply The track-and-hold amplifier enters its tracking mode on the application with a 50 Ω and 10 nF low-pass filter (cutoff fre- falling edge of the BUSY signal. The time required for the quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a track-and-hold amplifier to acquire an input signal depends on capacitor with good linearity to ensure good ac performance. how quickly the 20 pF input capacitance is charged. There is a Recommended single supply op amps are the AD820 and the minimum acquisition time of 400 ns. For large source imped- AD820-3V. ances, >2 kΩ, the acquisition time is calculated using the formula: t = 9 × (R + 125 Ω) × 20 pF ACQ IN +3V TO +5V 0.1�F 10�F where R is the source impedance of the input signal, and IN 10k� 125 Ω, 20 pF is the input R, C. 10k� V V+ IN 50� DC/AC Applications (–V /2 TO +V /2) TO AIN(+) OF REF REF IC1 10k� AD7854/AD7854L V /2 For dc applications, high source impedances are acceptable, 10nF REF AD820 V– (NPO) AD820-3V 10k� provided there is enough acquisition time between conversions to charge the 20 pF capacitor. For example with R = 5 kΩ, IN the required acquisition time is 922 ns. Figure 11. Analog Input Buffering For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low- pass filter on the AIN(+) pin, as shown in Figure 11. In applica- tions where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac per- formance of the ADC. They may require the use of an input buffer amplifier. The choice of the amplifier is a function of the particular application. REV. B –14– THD – dB AD7854/AD7854L Transfer Functions Input Ranges For the unipolar range the designed code transitions occur The analog input range for the AD7854/AD7854L is 0 V to midway between successive integer LSB values (i.e., 1/2 LSB, V in both the unipolar and bipolar ranges. REF 3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The output coding is The only difference between the unipolar range and the bipolar straight binary for the unipolar range with 1 LSB = FS/4096 = range is that in the bipolar range the AIN(–) should be biased 3.3 V/4096 = 0.8 mV when V = 3.3 V. The ideal input/ REF up to at least +V /2 and the output coding is twos comple- REF output transfer characteristic for the unipolar range is shown in ment (see Table V and Figures 14 and 15). Figure 14. Table V. Analog Input Connections OUTPUT CODE Analog Input Input Connections Connection 111...111 Range AIN(+) AIN(–) Diagram 111...110 1 111...101 0 V to V V AGND Figure 12 REF IN 2 111...100 ±V /2 V V /2 Figure 13 REF IN REF NOTES 1 Output code format is straight binary. 2 Range is ±V /2 biased about V /2. Output code format is twos complement. REF REF FS 000...011 1LSB = Note that the AIN(–) pin on the AD7854/AD7854L can be 4096 000...010 biased up above AGND in the unipolar mode, or above V /2 REF in bipolar mode if required. The advantage of biasing the lower 000...001 end of the analog input range away from AGND is that the analog 000...000 0V 1LSB +FS –1LSB input does not have to swing all the way down to AGND. Thus, V = (AIN(+) – AIN(–)), INPUT VOLTAGE IN in single supply applications the input amplifier does not have to Figure 14. AD7854/AD7854L Unipolar Transfer swing all the way down to AGND. The upper end of the analog Characteristic input range is shifted up by the same amount. Care must be taken so that the bias applied does not shift the upper end of the Figure 13 shows the AD7854/AD7854L’s ±V /2 bipolar ana- REF analog input above the AV supply. In the case where the ref- DD log input configuration. AIN(+) cannot go below 0 V, so for the erence is the supply, AV , the AIN(–) should be tied to AGND DD full bipolar range, AIN(–) should be biased to at least +V /2. REF in unipolar mode or to AV /2 in bipolar mode. DD Once again the designed code transitions occur midway between successive integer LSB values. The output coding is twos complement with 1 LSB = 4096 = 3.3 V/4096 = 0.8 mV. The TRACK AND HOLD AMPLIFIER ideal input/output transfer characteristic is shown in Figure 15. AIN(+) DB0 V = 0 TO V STRAIGHT IN REF . . . BINARY AIN(–) OUTPUT FORMAT DB11 CODE 011...111 AD7854/AD7854L 011...110 (V /2) – 1LSB REF Figure 12. 0 to V Unipolar Input Configuration REF 000...001 0V 000...000 + FS – 1LSB 111...111 (V /2) + 1 LSB REF TRACK AND HOLD FS = V V REF AIN(+) AMPLIFIER 000...010 V = 0 TO V DB0 2’S IN REF FS . . . 1LSB = COMPLEMENT 000...001 AIN(–) 4096 DB11 FORMAT V /2 REF 000...000 AD7854/AD7854L V /2 REF V = (AIN(+) – AIN(–)), INPUT VOLTAGE IN Figure 15. AD7854/AD7854L Bipolar Transfer Characteristic Figure 13. ±V /2 about V /2 Bipolar Input Configuration REF REF REV. B –15– AD7854/AD7854L REFERENCE SECTION AD7854/AD7854L PERFORMANCE CURVES For specified performance, it is recommended that when using Figure 18 shows a typical FFT plot for the AD7854 at 200 kHz an external reference, this reference should be between 2.3 V sample rate and 10 kHz input frequency. and the analog supply AV . The connections for the reference DD 0 pins are shown below. If the internal reference is being used, the REF /REF pin should be decoupled with a 100 nF IN OUT AV = DV = 3.3V DD DD capacitor to AGND very close to the REF /REF pin. These –20 IN OUT F = 200kHz SAMPLE F = 10kHz connections are shown in Figure 16. IN SNR = 72.04dB –40 THD = –88.43dB If the internal reference is required for use external to the ADC, it should be buffered at the REF /REF pin and a 100 nF IN OUT –60 capacitor should be connected from this pin to AGND. The typical noise performance for the internal reference, with 5 V supplies is –80 150 nV/√Hz @ 1 kHz and dc noise is 100 µV p-p. ANALOG –100 SUPPLY +3V TO +5V 10�F 0.1�F 0.1�F –120 0 20 40 60 80 100 FREQUENCY – kHz AV DV DD DD C REF1 Figure 18. FFT Plot 0.1�F Figure 19 shows the SNR versus frequency for different supplies AD7854/ C REF2 and different external references. 0.01�F AD7854L 74 REF /REF IN OUT AV = DV WITH 2.5V REFERENCE DD DD 0.1�F UNLESS STATED OTHERWISE 73 Figure 16. Relevant Connections Using Internal Reference 5.0V SUPPLIES, WITH 5V REFERENCE The REF /REF pin may be overdriven by connecting it to IN OUT 72 5.0V SUPPLIES an external reference. This is possible due to the series resis- tance from the REF /REF pin to the internal reference. IN OUT 5.0V SUPPLIES, L VERSION 71 This external reference can be in the range 2.3 V to AV . DD When using AV as the reference source, the 10 nF capacitor DD from the REF /REF pin to AGND should be as close as IN OUT 70 possible to the REF /REF pin, and also the C pin IN OUT REF1 3.3V SUPPLIES should be connected to AV to keep this pin at the same volt- DD 69 age as the reference. The connections for this arrangement are 0 20 40 60 80 100 shown in Figure 17. When using AV it may be necessary to INPUT FREQUENCY – kHz DD add a resistor in series with the AV supply. This has the effect DD Figure 19. SNR vs. Frequency of filtering the noise associated with the AV supply. DD Figure 20 shows the power supply rejection ratio versus fre- Note that when using an external reference, the voltage present quency for the part. The power supply rejection ratio is defined at the REF /REF pin is determined by the external refer- IN OUT as the ratio of the power in ADC output at frequency f to the ence source resistance and the series resistance of 150 kΩ from power of a full-scale sine wave: the REF /REF pin to the internal 2.5 V reference. Thus, a IN OUT PSRR (dB) = 10 log (Pf/Pfs) low source impedance external reference is recommended. Pf = Power at frequency f in ADC output, Pfs = power of a full- ANALOG scale sine wave. Here a 100 mV peak-to-peak sine wave is SUPPLY +3V TO +5V 10�F 0.1�F 0.1�F coupled onto the AV supply while the digital supply is left DD unaltered. Both the 3.3 V and 5.0 V supply performances are shown. AV DV DD DD C REF1 0.1�F AD7854/ C REF2 AD7854L 0.01�F REF /REF IN OUT 0.01�F Figure 17. Relevant Connections, AV as the Reference DD REV. B –16– SNR – dB S(N+D) RATIO – dB AD7854/AD7854L POWER-UP TIMES –78 AV = DV = 3.3V/5.0V, DD DD Using an External Reference 100mV pk-pk SINE WAVE ON AV DD When the AD7854/AD7854L are powered up, the parts are –80 powered up from one of two conditions. First, when the power supplies are initially powered up and, secondly, when the parts –82 are powered up from a software power-down (see last section). 3.3V –84 When AV and DV are powered up, the AD7854/AD7854L DD DD enters a mode whereby the CONVST signal initiates a timeout 5.0V followed by a self-calibration. The total time taken for this time- –86 out and calibration is approximately 70 ms—see Calibration on Power-Up in the calibration section of this data sheet. The power- –88 up calibration mode can be disabled if the user writes to the control register before a CONVST signal is applied. If the timeout and –90 0 20 40 60 80 100 self-calibration are disabled, then the user must take into account INPUT FREQUENCY – kHz the time required by the AD7854/AD7854L to power up before Figure 20. PSRR vs. Frequency a self-calibration is carried out. This power-up time is the time taken for the AD7854/AD7854L to power up when power is POWER-DOWN OPTIONS first applied (300 µs typ) or the time it takes the external refer- The AD7854/AD7854L provides flexible power management to ence to settle to the 12-bit level—whichever is the longer. allow the user to achieve the best power performance for a given The AD7854/AD7854L powers up from a full software power- throughput rate. The power management options are selected down in 5 µs typ. This limits the throughput which the part is by programming the power management bits, PMGT1 and capable of to 100 kSPS for the AD7854 and 60 kSPS for the PMGT0, in the control register. Table VI summarizes the power- AD7854L when powering down between conversions. Figure 21 down options that are available and how they can be selected by shows how a full power-down between conversions is implemented programming the power management bits in the control register. using the CONVST pin. The user first selects the power-down The AD7854/AD7854L can be fully or partially powered down. between conversions option by setting the power management When fully powered down, all the on-chip circuitry is powered bits, PMGT1 and PMGT0, to 0 and 1 respectively in the control down and I is 10 µA typ. If a partial power-down is selected, DD register (see last section). In this mode the AD7854/AD7854L then all the on-chip circuitry except the reference is powered automatically enters a full power-down at the end of a conver- down and I is 400 µA typ with the external clock running. DD sion, i.e., when BUSY goes low. The falling edge of the next Additional power savings may be made if the external clock is off. CONVST pulse causes the part to power up. Assuming the external reference is left powered up, the AD7854/AD7854L The choice of full or partial power-down does not give any should be ready for normal operation 5 µs after this falling edge. significant improvement in the throughput rate which can be The rising edge of CONVST initiates a conversion so the achieved with a power-down between conversions. This is dis- CONVST pulse should be at least 5 µs wide. The part auto- cussed in the next section—Power-Up Times. But a partial matically powers down on completion of the conversion. Where power-down does allow the on-chip reference to be used exter- the software convert start is used, the part may be powered up in nally even though the rest of the AD7854/AD7854L circuitry is software before a conversion is initiated. powered down. It also allows the AD7854/AD7854L to be pow- ered up faster after a long power-down period when using the START CONVERSION ON RISING EDGE on-chip reference (See Power-Up Times section—Using the POWER-UP ON FALLING EDGE Internal (On-Chip) Reference). 5�s 4.6�s As can be seen from Table VI, the AD7854/AD7854L can be CONVST programmed for normal operation, a full power-down at the end t CONVERT of a conversion, a partial power-down at the end of a conversion and finally a full power-down whether converting or not. The BUSY full and partial power-down at the end of a conversion can be used to achieve a superior power performance at slower through- POWER-UP NORMAL FULL POWER-UP TIME OPERATION POWER-DOWN TIME put rates, in the order of 50 kSPS (see Power vs. Throughput Rate section of this data sheet). Figure 21. Using the CONVST Pin to Power Up the AD7854 for a Conversion Table VI. Power Management Options PMGT1 PMGT0 Bit Bit Comment 0 0 Normal Operation 0 1 Full Power-Down After a Conversion 1 0 Full Power-Down 1 1 Partial Power-Down After a Conversion REV. B –17– PSRR – dB AD7854/AD7854L Using The Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE As in the case of an external reference the AD7854/AD7854L can The main advantage of a full power-down after a conversion is power up from one of two conditions, power-up after the sup- that it significantly reduces the power consumption of the part plies are connected or power-up from a software power-down. at lower throughput rates. When using this mode of operation, the AD7854/AD7854L is only powered up for the duration of When using the on-chip reference and powering up when AV DD the conversion. If the power-up time of the AD7854/AD7854L and DV are first connected, it is recommended that the power- DD is taken to be 5 µs and it is assumed that the current during up calibration mode be disabled as explained above. When using power-up is 4.5 mA/1.5 mA typ, then power consumption as a the on-chip reference, the power-up time is effectively the time function of throughput can easily be calculated. The AD7854 it takes to charge up the external capacitor on the REF / IN has a conversion time of 4.6 µs with a 4 MHz external clock, REF pin. This time is given by the equation: OUT and the AD7854L has a conversion time of 9 µs with a 1.8 MHz t = 9 × R × C UP clock. This means the AD7854/AD7854L consumes 4.5 mA/ 1.5 mA typ for 9.6 µs/14 µs in every conversion cycle if the parts where R ≈ 150K and C = external capacitor. are powered down at the end of a conversion. The four graphs, The recommended value of the external capacitor is 100 nF; Figures 24, 25, 26 and 27, show the power consumption of the this gives a power-up time of approximately 135 ms before a AD7854 and AD7854L for V = 3 V as a function of through- DD calibration is initiated and normal operation should commence. put. Table VII lists the power consumption for various throughput When C is fully charged, the power-up time from a software REF rates. power-down reduces to 5 µs. This is because an internal switch opens to provide a high impedance discharge path for the refer- Table VII. Power Consumption vs. Throughput ence capacitor during power-down—see Figure 22. An added Power Power advantage of the low charge leakage from the reference capacitor Throughput Rate AD7854 AD7854L during power-down is that even though the reference is being powered down between conversions, the reference capacitor 1 kSPS 130 µW65 µW holds the reference voltage to within 0.5 LSBs with throughput 10 kSPS 1.3 mW 650 µW rates of 100 samples/second and over with a full power-down 20 kSPS 2.6 mW 1.25 mW between conversions. A high input impedance op amp like the 50 kSPS 6.48 mW 3.2 mW AD707 should be used to buffer this reference capacitor if it is being used externally. Note, if the AD7854/AD7854L is left in 4MHz/1.8MHz its powered-down state for more than 100 ms, the charge on OSCILLATOR C will start to leak away and the power-up time will increase. REF ANALOG If this longer power-up time is a problem, the user can use a SUPPLY partial power-down for the last conversion so the reference +3V TO +5V 10�F 0.1�F 0.1�F remains powered up. CONVERSION START SIGNAL AV DV DD DD CLKIN 0V TO 2.5V AIN(+) SWITCH OPENS AD7854/ INPUT DURING POWER-DOWN AD7854L CONVST AIN(–) REF IN/OUT ON-CHIP HBEN REFERENCE C REF1 EXTERNAL 0.1�F AD7854/ CS CAPACITOR AD7854L RD TO OTHER CIRCUITRY C REF2 BUF 0.01�F WR �C/�P BUSY AGND Figure 22. On-Chip Reference During Power-Down DB0 DGND DB11 REF /REF IN OUT 0.1nF EXTERNAL REFERENCE 0.1�F ON-CHIP REFERENCE OPTIONAL AD780/ EXTERNAL FULL POWER-DOWN REF192 AFTER A CONVERSION REFERENCE PMGT1 = 0 PMGT0 = 1 Figure 23. Typical Low Power Circuit REV. B –18– AD7854/AD7854L 10 AD7854 FULL POWER-DOWN AD7854 FULL POWER-DOWN V = 3V CLKIN = 4MHz DD V = 3V CLKIN = 4MHz DD 1 ON-CHIP REFERENCE ON-CHIP REFERENCE 1 0.1 0.1 0.01 0.01 0 24 68 10 05 10 20 30 400 THROUGHPUT RATE – kSPS THROUGHPUT RATE – kSPS Figure 24. Power vs. Throughput AD7854 Figure 26. Power vs. Throughput AD7854 10 AD7854L FULL POWER-DOWN AD7854L FULL POWER-DOWN V = 3V CLKIN = 1.8MHz DD V = 3V CLKIN = 1.8MHz DD 1 ON-CHIP REFERENCE ON-CHIP REFERENCE 1 0.1 0.1 0.01 0.01 4 8 12 16 20 05 10 20 30 400 0 THROUGHPUT RATE – kSPS THROUGHPUT RATE – kSPS Figure 27. Power vs. Throughput AD7854L Figure 25. Power vs. Throughput AD7854L REV. B –19– POWER – mW POWER – mW POWER – mW POWER – mW AD7854/AD7854L CALIBRATION SECTION AV = DV DD DD CONVERSION IS INITIATED POWER ON Calibration Overview ON THIS EDGE The automatic calibration that is performed on power-up CONVST ensures that the calibration options covered in this section are not required in a significant number of applications. A calibration BUSY does not have to be initiated unless the operating conditions change (CLKIN frequency, analog input mode, reference volt- 32/72 ms 32/72 ms age, temperature, and supply voltages). The AD7854/AD7854L TIMEOUT PERIOD AUTOMATIC has a number of calibration features that may be required in CALIBRATION DURATION some applications, and there are a number of advantages in per- forming these different types of calibration. First, the internal Figure 28. Timing Arrangement for Autocalibration on errors in the ADC can be reduced significantly to give superior Power-On dc performance; and second, system offset and gain errors can The CONVST signal is gated with the BUSY internally so that be removed. This allows the user to remove reference errors as soon as the timeout is initiated by the first CONVST pulse all (whether it be internal or external reference) and to make use of subsequent CONVST pulses are ignored until the BUSY signal the full dynamic range of the AD7854/AD7854L by adjusting goes low, 32/72 ms later. The CONVST pulse that follows after the analog input range of the part for a specific system. the BUSY signal goes low initiates an automatic full self- There are two main calibration modes on the AD7854/AD7854L, calibration. This takes a further 32/72 ms. After calibration, self-calibration and system calibration. There are various op- the part is accurate to the 12-bit level and the specifications tions in both self-calibration and system calibration as outlined quoted on the data sheet apply, and all subsequent CONVST previously in Table III. All the calibration functions are initi- pulses initiate conversions. There is no need to perform another ated by writing to the control register and setting the STCAL calibration unless the operating conditions change or unless a bit to 1. system calibration is required. The duration of each of the different types of calibration is given This autocalibration at power-on is disabled if the user writes to in Table IX for the AD7854 with a 4 MHz master clock. These the control register before the autocalibration is initiated. If the calibration times are master clock dependent. Therefore the control register write operation occurs during the first 32/72 ms calibration times for the AD7854L (CLKIN = 1.8 MHz) are timeout period, then the BUSY signal stays high for the 32/72 ms larger than those quoted in Table VIII. and the CONVST pulse that follows the BUSY going low does not initiate an automatic full self-calibration. It initiates a con- Table VIII. Calibration Times (AD7854 with 4 MHz CLKIN) version and all subsequent CONVST pulses initiate conversions as well. If the control register write operation occurs when the Type of Self-Calibration or System Calibration Time automatic full self-calibration is in progress, then the calibration Full 31.25 ms is not be aborted; the BUSY signal remains high until the auto- Gain + Offset 6.94 ms matic full self-calibration is complete. Offset 3.47 ms Self-Calibration Description Gain 3.47 ms There are four different calibration options within the self- calibration mode. There is a full self-calibration where the Automatic Calibration on Power-On DAC, internal offset, and internal gain errors are removed. The automatic calibration on power-on is initiated by the first There is the (Gain + Offset) self-calibration which removes the CONVST pulse after the AV and DV power on. From the DD DD internal gain error and then the internal offset errors. The inter- CONVST pulse the part internally sets a 32/72 ms (4 MHz/ nal DAC is not calibrated here. Finally, there are the self-offset 1.8 MHz CLKIN) timeout. This time is large enough to ensure and self-gain calibrations which remove the internal offset errors that the internal reference has settled before the calibration is and the internal gain errors respectively. performed. However, if an external reference is being used, this reference must have stabilized before the automatic calibration The internal capacitor DAC is calibrated by trimming each of is initiated. This first CONVST pulse also triggers the BUSY the capacitors in the DAC. It is the ratio of these capacitors to signal high, and once the 32/72 ms has elapsed, the BUSY signal each other that is critical, and so the calibration algorithm goes low. At this point the next CONVST pulse that is applied ensures that this ratio is at a specific value by the end of the initiates the automatic full self-calibration. This CONVST pulse calibration routine. For the offset and gain there are two again triggers the BUSY signal high, and after 32/72 ms (4 MHz/ separate capacitors, one of which is trimmed during offset 1.8 MHz CLKIN), the calibration is completed and the BUSY calibration and one of which is trimmed during gain calibration. signal goes low. This timing arrangement is shown in Figure 28. In bipolar mode the midscale error is adjusted by an offset cali- The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN bration and the positive full-scale error is adjusted by the gain signal. calibration. In unipolar mode the zero-scale error is adjusted by the offset calibration and the positive full-scale error is adjusted by the gain calibration. REV. B –20– AD7854/AD7854L Self-Calibration Timing MAX SYSTEM FULL SCALE IS ±2.5% FROM V Figure 29 shows the timing for a software full self-calibration. REF Here the BUSY line stays high for the full length of the self- V + SYS OFFSET REF V – 1LSB calibration. A self-calibration is initiated by writing to the con- V – 1LSB REF REF trol register and setting the STCAL bit to 1. The BUSY line SYSTEM OFFSET ANALOG ANALOG goes high at the end of the write to the control register, and INPUT INPUT RANGE RANGE BUSY goes low when the full self-calibration is complete after a CALIBRATION time t as show in Figure 29. CAL SYS OFFSET SYS OFFSET AGND AGND t 23 MAX SYSTEM OFFSET MAX SYSTEM OFFSET IS ±5% OF V IS ±5% OF V CS REF REF DATA LATCHED INTO CONTROL REGISTER Figure 30. System Offset Calibration WR Figure 31 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog Hi-Z Hi-Z DATA input range has been increased after the system gain calibration DATA VALID is completed. A system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. BUSY t CAL MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE IS ±2.5% FROM V IS ±2.5% FROM V REF REF Figure 29. Timing Diagram for Full Self-Calibration SYS FULL S. SYS FULL S. For the self-(gain + offset), self-offset and self-gain calibrations, V – 1LSB V – 1LSB REF REF the BUSY line is triggered high at the end of the write to the SYSTEM OFFSET ANALOG ANALOG control register and stays high for the full duration of the self- INPUT INPUT calibration. The length of time for which BUSY is high depends RANGE RANGE CALIBRATION on the type of self-calibration that is initiated. Typical values are given in Table VIII. The timing diagram for the other self- AGND AGND calibration options is similar to that outlined in Figure 29. Figure 31. System Gain Calibration System Calibration Description Finally in Figure 32 both the system offset error and gain error System calibration allows the user to remove system errors are removed by the system offset followed by a system gain cali- external to the AD7854/AD7854L, as well as remove the errors bration. First the analog input range is shifted upwards by the of the AD7854/AD7854L itself. The maximum calibration positive system offset and then the analog input range is range for the system offset errors is ±5% of V , and for the REF adjusted at the top end to account for the system full scale. system gain errors it is ±2.5% of V . If the system offset or REF system gain errors are outside these ranges, the system calibration MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE algorithm reduces the errors as much as the trim range allows. IS ±2.5% FROM V IS ±2.5% FROM V REF REF Figures 30 through 32 illustrate why a specific type of system V + SYS OFFSET SYS F.S. REF SYS F.S. calibration might be used. Figure 30 shows a system offset cali- V – 1LSB REF V – 1LSB REF bration (assuming a positive offset) where the analog input SYSTEM OFFSET CALIBRATION range has been shifted upwards by the system offset after the ANALOG ANALOG FOLLOWED BY INPUT INPUT system offset calibration is completed. A negative offset may RANGE RANGE also be removed by a system offset calibration. SYSTEM GAIN CALIBRATION SYS OFFSET SYS OFFSET AGND AGND MAX SYSTEM OFFSET MAX SYSTEM OFFSET IS ±5% OF V IS ±5% OF V REF REF Figure 32. System (Gain + Offset) Calibration REV. B –21– AD7854/AD7854L System Gain and Offset Interaction The timing for a system (gain + offset) calibration is very similar The architecture of the AD7854/AD7854L leads to an interac- to that of Figure 33, the only difference being that the time t is CAL1 tion between the system offset and gain errors when a system replaced by a shorter time of the order of t as the internal CAL2 calibration is performed. Therefore it is recommended to perform DAC is not calibrated. The BUSY signal signifies when the gain the cycle of a system offset calibration followed by a system gain calibration is finished and when the part is ready for the offset calibration twice. When a system offset calibration is performed, calibration. the system offset error is reduced to zero. If this is followed by a system gain calibration, then the system gain error is now zero, DATA LATCHED INTO CONTROL REGISTER but the system offset error is no longer zero. A second sequence t 23 of system offset error calibration followed by a system gain cali- bration is necessary to reduce system offset error to below the CS 12-bit level. The advantage of doing separate system offset and system gain calibrations is that the user has more control over WR CONVST BIT SET TO 1 IN CONTROL when the analog inputs need to be at the required levels, and the REGISTER Hi-Z Hi-Z Hi-Z CONVST signal does not have to be used. DATA DATA DATA VALID VALID Alternatively, a system (gain + offset) calibration can be per- BUSY formed. At the end of one system (gain + offset) calibration, the t t CAL1 CAL2 system offset error is zero, while the system gain error is reduced t 23 from its initial value. Three system (gain + offset) calibrations t SETUP are required to reduce the system gain error to below the 12-bit AIN V V SYSTEM FULL SCALE OFFSET error level. There is never any need to perform more than three Figure 33. Timing Diagram for Full System Calibration system (gain + offset) calibrations. The timing diagram for a system offset or system gain calibra- In bipolar mode the midscale error is adjusted for an offset cali- tion is shown in Figure 34. Here again a write to the control bration and the positive full-scale error is adjusted for the gain register initiates the calibration sequence. At the end of the con- calibration; in unipolar mode the zero-scale error is adjusted for trol register write operation the BUSY line goes high and it stays an offset calibration and the positive full-scale error is adjusted high until the calibration sequence is finished. The analog input for a gain calibration. should be set at the correct level for a minimum setup time System Calibration Timing (t ) of 100 ns before the CS rising edge and stay at the cor- SETUP The timing diagram in Figure 33 is for a software full system rect level until the BUSY signal goes low. calibration. It may be easier in some applications to perform separate gain and offset calibrations so that the CONVST bit in t 23 the control register does not have to be programmed in the CS DATA LATCHED INTO middle of the system calibration sequence. Once the write to the CONTROL REGISTER control register setting the bits for a full system calibration is completed, calibration of the internal DAC is initiated and the WR BUSY line goes high. The full-scale system voltage should be applied to the analog input pins, AIN(+) and AIN(–) at the start Hi-Z Hi-Z DATA DATA VALID of calibration. The BUSY line goes low once the DAC and system gain calibration are complete. Next the system offset voltage should be applied across the AIN(+) and AIN(–) pins BUSY for a minimum setup time (t ) of 100 ns before the rising SETUP t CAL2 edge of CS. This second write to the control register sets the t SETUP CONVST bit to 1 and at the end of this write operation the AIN V OR V SYSTEM FULL SCALE OFFSET BUSY signal is triggered high (note that a CONVST pulse can Figure 34. Timing Diagram for System Gain or System be applied instead of this second write to the control register). Offset Calibration The BUSY signal is low after a time t when the system offset CAL2 calibration section is complete. The full system calibration is now complete. REV. B –22– AD7854/AD7854L PARALLEL INTERFACE to DB11. Bringing HBEN high causes the 8 MSBs of the 16-bit Reading word to be output on pins DB0 to DB7. Note that with this The timing diagram for a read cycle is shown in Figure 35. The arrangement the data lines are always active. CONVST and BUSY signals are not shown here as the read cycle may occur while a conversion is in progress or after the t = 100ns MIN, t = 70ns MIN, 1 20 t = t = 70ns MIN, t = t = 60ns MAX conversion is complete. 19 20 21 22 t 1 The HBEN signal is low for the first read and high for the sec- CONVST CONVERSION IS INITIATED ON THIS EDGE ond read. This ensures that it is the lower 12 bits of the 16-bit t CONVERT t word are output in the first read and the 8 MSBs of the 16-bit 2 word are output in the second read. If required, the HBEN BUSY signal may be high for the first read and low for the second t t 19 20 read to ensure that the high byte is output in the first read HBEN and the lower byte in the second read. The CS and RD sig- t 21 t t 18 22 nals are gated together internally and level triggered active NEW DATA NEW DATA NEW DATA NEW DATA VALID VALID VALID VALID DATA OLD DATA VALID low. Both CS and RD may be tied together as the timing speci- (DB0–DB11) (DB8–DB11) (DB0–DB11) (DB8–DB11) fication for t and t are both 0 ns min. The data is output a time t 5 6 8 ON PINS DB0 TO DB11 after both CS and RD go low. The RD rising edge should be ON PINS DB0 TO DB7 used to latch the data by the user and after a time t the data 9 lines will go into their high impedance state. Figure 36. Read Cycle Timing Diagram with CS and RD Tied Low In Figure 35, the first read outputs the 12 LSBs of the 16-bit word on pins DB0 to DB11 (DB0 being the LSB of the 12-bit Writing read). The second read outputs the 8 MSBs of the 16-bit word The timing diagram for a write cycle is shown in Figure 37. The on pins DB0 to DB7 (DB0 being the LSB of the 8-bit read). If the CONVST and BUSY signals are not shown here as the write system has a 12-bit or a 16-bit data bus, only one read operation cycle may occur while a conversion is in progress or after the is necessary to obtain the 12-bit conversion result (12 bits are conversion is complete. output in the first read). A second read operation is not required. To write a 16-bit word to the AD7854/AD7854L, two 8-bit If the system has an 8-bit data bus then two reads are needed. writes are required. The HBEN signal must be low for the first Pins DB0 to DB7 should be connected the 8-bit data bus. Pins write and high for the second write. This ensures that it is the DB8 to DB11 should be tied to DGND or DV via 10 kΩ lower 8 bits of the 16-bit word are latched in the first write and DD resistors. With this arrangement, HBEN is pulled low for the the 8 MSBs of the 16-bit word are latched in the second write. first read and the 8 LSBs of the 16-bit word are output on pins For both write operations the 8 bits of data should be present on DB0 to DB7 (data on pins DB8 to DB11 will be ignored). pins DB0 to DB7 (DB0 being the LSB of the 8-bit write). Any HBEN is pulled high for the second read and now the 8 MSBs data on pins DB8 to DB11 is ignored when writing to the device. of the 16-bit word are output on pins DB0 to DB7. The CS and WR signals are gated together internally. Both CS and WR may be tied together as the timing specification for t 13 and t are both 0 ns min. The data is latched on the rising edge 14 t = 15ns MIN, t = 5ns MIN, t = t = 0ns MIN, 3 4 5 6 t = 50ns MAX, t = 5/40ns MIN/MAX, t = 70ns MIN 8 9 10 of WR. The data needs to be set up a time t before the WR 16 rising edge and held for a time t after the WR rising edge. 17 HBEN t = 0ns MIN, t = 5ns MIN, t = t = 0ns MIN, 11 12 13 14 t t t t 4 t = 70ns MIN, t = 10ns MIN, t = 5ns MIN 3 4 3 15 16 17 CS HBEN t 10 t 5 t 6 t t t t 11 12 11 12 t RD 7 CS t 10 t 9 t t 13 8 t 14 DATA DATA DATA VALID VALID t WR 15 t 17 Figure 35. Read Cycle Timing Diagram Using CS and RD t 16 DATA DATA DATA In the case where the AD7854/AD7854L is operated as a read- VALID VALID only ADC, the WR pin can be tied permanently high. The read Figure 37. Write Cycle Timing Diagram operation need only consist of one read if the system has a 12- bit or a 16-bit data bus. Resetting the Parallel Interface If random data has been inadvertently written to the test regis- When both the CS and RD signals are tied permanently low a ter, it is necessary to write the 16-bit word 0100 0000 0000 different timing arrangement results, as shown in Figure 36. 0010 (in two 8-bit bytes) to restore the test register to its Here the data is output a time t before the falling edge of the 20 default value. BUSY signal. This allows the falling edge of BUSY to be used for latching the data. Again if HBEN is low during the conver- sion the 12 LSBs of the 16-bit word will be output on pins DB0 REV. B –23– AD7854/AD7854L MICROPROCESSOR INTERFACING AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x The parallel port on the AD7854/AD7854L allows the device to A parallel interface between the AD7854/AD7854L and the be interfaced to microprocessors or DSP processors as a memory TMS32020, TMS320C25 and TMS320C5x family of DSPs are mapped or I/O mapped device. The CS and RD inputs are shown in Figure 39. The memory mapped addresses chosen for common to all memory peripheral interfacing. Typical inter- the AD7854/AD7854L should be chosen to fall in the I/O faces to different processors are shown in Figures 38 to 41. memory space of the DSPs. In all the interfaces shown, an external timer controls the The parallel interface on the AD7854/AD7854L is fast enough CONVST input of the AD7854/AD7854L and the BUSY out- to interface to the TMS32020 with no extra wait states. In the put interrupts the host DSP. Also, the HBEN pin is connected TMS320C25 interface, data accesses may be slowed sufficiently to address line A0 (XA0 in the case of the TMS320C30). This when reading from and writing to the part to require the inser- maps the AD7854/AD7854L to two locations in the processor tion of one wait state. In such a case, this wait state can be memory space, ADCaddr and ADCaddr+1. Thus when writing generated using the single OR gate to combine the CS and to the ADC, first the 8 LSBs of the 16-bit are written to address MSC signals to drive the READY line of the TMS320C25, as location ADCaddr and then the 8 MSBs to location ADCaddr+1. shown in Figure 39. Extra wait states are necessary when using All the interfaces use a 12-bit data bus, so only one read is needed the TMS320C5x at their fastest clock speeds. Wait states can from location ADCaddr to access the ADC output data register be programmed via the IOWSR and CWSR registers (please see or the status register. To read from the other registers, the TMS320C5x User Guide for details). 8 MSBs must be read from location ADCaddr+1. Interfacing Data is read from the ADC using the following instruction: to 8-bit bus systems is similar, except that two reads are IN D,ADCaddr required to obtain data from all the registers. where D is the memory location where the data is to be stored AD7854/AD7854L to ADSP-21xx and ADCaddr is the I/O address of the AD7854/AD7854L. Figure 38 shows the AD7854/AD7854L interfaced to the ADSP-21xx series of DSPs as a memory mapped device. A Data is written to the ADC using the following two instructions: single wait state may be necessary to interface the AD7854/ OUT D8LSB, ADCaddr AD7854L to the ADSP-21xx depending on the clock speed of OUT D8MSB, ADCaddr+1 the DSP. This wait state can be programmed via the data memory waitstate control register of the ADSP-21xx (please see where D8LSB is the memory location where the 8 LSBs of data ADSP-2100 Family Users Manual for details). The following are stored, D8MSB is the location where the 8 MSBs of data are instruction reads data from the AD7854/AD7854L: stored and ADCaddr and ADCaddr+1 are the I/O memory spaces that the AD7854/AD7854L is mapped into. AX0 = DM(ADCaddr) Data can be written to the AD7854/AD7854L using the instructions: A15–A1 ADDRESS BUS DM (ADCaddr) = AY0 TMS32020/ TMS320C25/ ADDR CS IS EN DM (ADCaddr+1) = AY1 TMS320C50* DECODE AD7854/ where ADCaddr is the address of the AD7854/AD7854L in READY AD7854L* ADSP-21xx data memory, AX0 contains the data read from the TMS320C25 MSC ONLY ADC, and AY0 contains the 8 LSBs and AY1 the 8 MSBs of A0 HBEN STRB data written to the AD7854/AD7854L. WR R/W RD A13–A1 ADDRESS BUS INTx BUSY ADSP-21xx* DB11–DB0 D23–D0 DATA BUS ADDR DMS EN CS DECODE AD7854/ *ADDITIONAL PINS OMITTED FOR CLARITY AD7854L* A0 HBEN Figure 39. AD7854/AD7854L to TMS32020/C25/C5x WR WR Parallel Interface RD RD IRQ2 BUSY D23–D8 DB11–DB0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. AD7854/AD7854L to ADSP-21xx Parallel Interface REV. B –24– AD7854/AD7854L AD7854/AD7854L to TMS320C30 AD7854/AD7854L to DSP5600x Figure 40 shows a parallel interface between the AD7854/ Figure 41 shows a parallel interface between the AD7854/ AD7854L and the TMS320C3x family of DSPs. The AD7854L and the DSP5600x series of DSPs. The AD7854/ AD7854/AD7854L is interfaced to the Expansion Bus of the AD7854L should be mapped into the top 64 locations of Y data TMS320C3x. Two wait states are required in this interface. memory. If extra wait states are needed in this interface, they These can be programmed using the WTCNT bits of the can be programmed using the Port A bus control register (please Expansion Bus Control register (see TMS320C3x Users Guide see DSP5600x User’s Manual for details). Data can be read for details). Data from the AD7854/AD7854L can be read from the DSP5600x using the following instruction: using the following instruction: MOVE Y:ADCaddr, X0 LDI *ARn,Rx Data can be written to the AD7854/AD7854L using the follow- Data can be loaded into the AD7854/AD7854L using the ing two instructions: instructions: MOVE X0, Y:ADCaddr STI Ry,*ARn++ MOVE X1, Y:ADCaddr+1 STI Rz,*ARn-- Where ADCaddr is the address in the DSP5600x address space where ARn is an auxiliary register containing the lower 16 bits to which the AD7854/AD7854L has been mapped. of the address of the AD7854/AD7854L in the TMS320C3x memory space, Rx is the register into which the ADC data is A15–A1 ADDRESS BUS loaded during a load operation, Ry contains the 8 LSBs of DSP56000/ data and Rz contains the 8 MSBs of data to be written to the DSP56002* X/Y AD7854/AD7854L. ADDR CS DECODE DS AD7854/ AD7854L* A0 HBEN XA12–XA1 EXPANSION ADDRESS BUS WR WR RD RD TMS320C30* ADDR CS IRQ BUSY DECODE AD7854/ AD7854L* DATA BUS DB11–DB0 D23–D0 XA0 HBEN IOSTRB WR XR/W *ADDITIONAL PINS OMITTED FOR CLARITY RD BUSY INTx Figure 41. AD7854/AD7854L to DSP5600x Parallel Interface DB11–DB0 XD23–XD0 EXPANSION DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 40. AD7854/AD7854L to TMS320C30 Parallel Interface REV. B –25– AD7854/AD7854L Good decoupling is also important. All analog supplies should APPLICATION HINTS be decoupled with a 10 µF tantalum capacitor in parallel with Grounding and Layout 0.1 µF disc ceramic capacitor to AGND. All digital supplies The analog and digital supplies of the AD7854/AD7854L are should have a 0.1 µF disc ceramic capacitor to DGND. To independent and separately pinned out to minimize coupling achieve the best performance from these decoupling compo- between the analog and digital sections of the device. The part nents, they must be placed as close as possible to the device, has very good immunity to noise on the power supplies as can ideally right up against the device. In systems where a common be seen by the PSRR versus frequency graph. However, care supply voltage is used to drive both the AV and DV of the should still be taken with regard to grounding and layout. DD DD AD7854/AD7854L, it is recommended that the system’s AV DD The printed circuit board on which the AD7854/AD7854L is supply is used. In this case an optional 10 Ω resistor between mounted should be designed such that the analog and digital the AV pin and DV pin can help to filter noise from digital DD DD sections are separated and confined to certain areas of the circuitry. This supply should have the recommended analog board. This facilitates the use of ground planes that can be supply decoupling capacitors between the AV pin of the DD easily separated. A minimum etch technique is generally best AD7854/AD7854L and AGND and the recommended digital for ground planes as it gives the best shielding. Digital and supply decoupling capacitor between the DV pin of the DD analog ground planes should only be joined in one place. If AD7854/AD7854L and DGND. the AD7854/AD7854L is the only device requiring an AGND Evaluating the AD7854/AD7854L Performance to DGND connection, then the ground planes should be The recommended layout for the AD7854/AD7854L is outlined connected at the AGND and DGND pins of the AD7854/ in the evaluation board for the AD7854/AD7854L. The evalua- AD7854L. If the AD7854/AD7854L is in a system where tion board package includes a fully assembled and tested multiple devices require AGND to DGND connections, the evaluation board, documentation, and software for controlling connection should still be made at one point only, a star ground the board from the PC via the EVAL-CONTROL BOARD. point which should be established as close as possible to the The EVAL-CONTROL BOARD can be used in conjunction AD7854/AD7854L. with the AD7854/AD7854L Evaluation board, as well as many Avoid running digital lines under the device as these couple other Analog Devices evaluation boards ending in the CB desig- noise onto the die. The analog ground plane should be allowed nator, to demonstrate/evaluate the ac and dc performance of the to run under the AD7854/AD7854L to avoid noise coupling. AD7854/AD7854L. The power supply lines to the AD7854/AD7854L should use as The software allows the user to perform ac (fast Fourier trans- large a trace as possible to provide low impedance paths and form) and dc (histogram of codes) tests on the AD7854/ reduce the effects of glitches on the power supply line. Fast AD7854L. It also gives full access to all the AD7854/AD7854L switching signals like clocks and the data inputs should be on-chip registers allowing for various calibration and power- shielded with digital ground to avoid radiating noise to other down options to be programmed. sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. AD785x Family Traces on opposite sides of the board should run at right angles All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V. to each other. This reduces the effects of feedthrough through AD7853 – Single Channel Serial the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, AD7854 – Single Channel Parallel the component side of the board is dedicated to ground planes AD7858 – Eight Channel Serial while signals are placed on the solder side. AD7859 – Eight Channel Parallel REV. B –26– AD7854/AD7854L PAGE INDEX Topic Page Topic Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 System Calibration Description . . . . . . . . . . . . . . . . . . . . 21 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 23 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AD7854/AD7854L ON-CHIP REGISTERS . . . . . . . . . . . . 8 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 8 Resetting the Parallel Interface . . . . . . . . . . . . . . . . . . . . . 23 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 24 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AD7854/AD7854L to ADSP-21xx . . . . . . . . . . . . . . . . . . 24 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 11 AD7854/AD7854L to TMS320C30 . . . . . . . . . . . . . . . . 25 Addressing the Calibration Registers . . . . . . . . . . . . . . . . 11 AD7854/AD7854L to DSP5600x . . . . . . . . . . . . . . . . . . 25 Writing to/Reading from the Calibration Registers . . . . . . 11 APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Adjusting the Offset Calibration Register . . . . . . . . . . . . . 12 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 12 Evaluating the AD7854/AD7854L Performance . . . . . . . 26 CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 13 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 28 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 13 ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE INDEX Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 # Title Page DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8 Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 II Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 III Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IV Calibrating Register Addressing . . . . . . . . . . . . . . . . . 11 AD7854/AD7854L PERFORMANCE CURVES . . . . . . . . 16 V Analog Input Connections . . . . . . . . . . . . . . . . . . . . . 15 POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 17 VI Power Management Options . . . . . . . . . . . . . . . . . . . . 17 POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VII Power Consumption vs. Throughput . . . . . . . . . . . . . 18 Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 17 VIII Calibration Times (AD7854 with 4 MHz CLKIN) . . . 20 Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 18 POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 18 REV. B –27– AD7854/AD7854L OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Q-28) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 114 0.620 (15.75) PIN 1 0.015 0.590 (14.99) 1.490 (37.85) MAX (0.38) 0.225 MIN (5.72) 0.150 MAX 0.018 (0.46) (3.81) 0.008 (0.20) MIN 0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) 15° SEATING 0.125 (3.18) 0° PLANE 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) 28-Lead Small Outline Package (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) � 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) 0.0040 (0.10) PLANE BSC 0.0091 (0.23) 28-Lead Shrink Small Outline Package (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.078 (1.98) 0.07 (1.79) PIN 1 0.066 (1.67) 0.068 (1.73) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.008 (0.203) 0.022 (0.558) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) 0.002 (0.050) PLANE BSC 0.005 (0.127) REV. B –28– 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.2992 (7.60) 0.205 (5.21) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. C2117–0–3/00 (rev. B)