ANALOG DEVICES AD7853

3 V to 5 V Single Supply, 200 kSPS a 12-Bit Sampling ADCs AD7853/AD7853L* FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for V of 3 V to 5.5 V DD AV AGND AGND DD Read-Only Operation AD7853–200 kSPS; AD7853L–100 kSPS DV DD AIN(+) System and Self-Calibration with Autocalibration on AD7853/AD7853L T/H Power-Up AIN(–) DGND Low Power: 2.5V AD7853: 12 mW (V = 3 V) REFERENCE DD AD7853L: 4.5 mW (V = 3 V) COMP DD Automatic Power Down After Conversion (25 mW) REF / BUF IN Flexible Serial Interface: REF OUT 8051/SPI™/QSPI™/mP Compatible C REF1 24-Lead DIP, SOIC and SSOP Packages AMODE CHARGE REDISTRIBUTION APPLICATIONS DAC CLKIN Battery-Powered Systems (Personal Digital Assistants, C REF2 SAR + ADC CONVST Medical Instruments, Mobile Communications) CONTROL Pen Computers CALIBRATION BUSY CAL MEMORY Instrumentation and Control Systems AND CONTROLLER SLEEP High Speed Modems SERIAL INTERFACE / CONTROL REGISTER GENERAL DESCRIPTION SM1 SM2 SYNC DIN DOUT SCLK POLARITY The AD7853/AD7853L are high speed, low power, 12-bit ADCs that operate from a single 3 V or 5 V power supply, the AD7853 being optimized for speed and the AD7853L for low power. The ADC powers up with a set of default conditions at PRODUCT HIGHLIGHTS which time it can be operated as a read-only ADC. The ADC 1. Specified for 3 V and 5 V supplies. contains self-calibration and system-calibration options to en- sure accurate operation over time and temperature and have a 2. Automatic calibration on power-up. number of power-down options for low power applications. 3. Flexible power management options including automatic The part powers up with a set of default conditions and can power-down after conversion. operate as a read only ADC. 4. Operates with reference voltages from 1.2 V to V . DD The AD7853 is capable of 200 kHz throughput rate while the 5. Analog input ranges from 0 V to V . DD AD7853L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- 6. Self- and system calibration. differential sampling scheme. The AD7853/AD7853L voltage 7. Versatile serial I/O port (SPI/QSPI/8051/mP). range is 0 to V with both straight binary and twos comple- REF 8. Lower power version AD7853L. ment output coding. Input signal range is to the supply, and the part is capable of converting full power signals to 100 kHz. CMOS construction ensures low power dissipation of typically 4.5 mW for normal operation and 1.15 mW in power-down mode, with a throughput rate of 10 kSPS (V = 3 V). The part DD is available in 24-lead, 0.3 inch wide dual-in-line package (DIP), 24-lead small outline (SOIC) and 24-lead small shrink outline (SSOP) packages. *Patent pending. SPI and QSPI are trademarks of Motorola, Incorporated. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 1, 2 (AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V AD7853/AD7853L–SPECIFICATIONS DD DD IN OUT External Reference, f = 4 MHz (1.8 MHz B Grade (08C to +708C), 1 MHz A and B Grades (–408C to +858C) for L Version); f = 200 kHz CLKIN SAMPLE (AD7853) 100 kHz (AD7853L); SLEEP = Logic High; T = T to T , unless otherwise noted.) Specifications in () apply to the AD7853L. A MIN MAX 1 1 Parameter A Version B Version Units Test Conditions/Comments DYNAMIC PERFORMANCE 3 Signal to Noise + Distortion Ratio 70 71 dB min Typically SNR Is 72 dB (SNR) V = 10 kHz Sine Wave, f = 200 kHz (100 kHz) IN SAMPLE Total Harmonic Distortion (THD) –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz (100 kHz) IN SAMPLE Peak Harmonic or Spurious Noise –78 –78 dB max V = 10 kHz Sine Wave, f = 200 kHz (100 kHz) IN SAMPLE Intermodulation Distortion (IMD) Second Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 200 kHz (100 kHz) SAMPLE Third Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 200 kHz (100 kHz) SAMPLE DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity–1–1 LSB max 2.5 V External Reference V = 3 V, V = 5 V (B Grade Only) DD DD –1–0.5 LSB max 5 V External Reference V = 5 V DD (–1) LSB max (L Version, 5 V External Reference, V = 5 V) DD (–1) LSB max (L Version) Differential Nonlinearity–1–1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V External Reference V = 3 V, 5 V External Reference V = 5 V DD DD Total Unadjusted Error–1–1 LSB typ Unipolar Offset Error–1–1 LSB max 2.5 V External Reference V = 3 V, 5 V External Reference V = 5 V DD DD Unipolar Offset Error (–2.5) (–2.5) LSB max (L Versions, 2.5 V External Reference V = 3 V, 5 V External DD Reference V = 5 V) DD Positive Full-Scale Error–2.5–2.5 LSB max 2.5 V External Reference V = 3 V, 5 V External Reference V = 5 V DD DD Positive Full-Scale Error (–4) (–4) LSB max (L Versions, 2.5 V External Reference V = 3 V, 5 V External DD Reference V = 5 V) DD Negative Full-Scale Error–2.5–2.5 LSB max 2.5 V External Reference V = 3 V, 5 V External Reference V = 5 V DD DD Negative Full-Scale Error (–4) (–4) LSB max (L Versions, 2.5 V External Reference V = 3 V, 5 V External DD Reference V = 5 V) DD Bipolar Zero Error–2–2 LSB max 2.5 V External Reference V = 3 V, 5 V External Reference V = 5 V DD DD Bipolar Zero Error (–2.5) (–2.5) LSB max (L Versions, 2.5 V External Reference V = 3 V, 5 V External DD Reference V = 5 V) DD ANALOG INPUT Input Voltage Ranges 0 to V 0 to V Volts i.e., AIN(+) – AIN(–) = 0 to V , AIN(–) Can Be Biased REF REF REF Up But AIN(+) Cannot Go Below AIN(–) –V /2–V /2 Volts i.e., AIN(+) – AIN(–) = –V /2 to +V /2, AIN(–) Should REF REF REF REF Be Biased to +V /2 and AIN(+) Can Go Below AIN(–) But REF Cannot Go Below 0 V Leakage Current–1–1mA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REF Input Voltage Range 2.3/V 2.3/V V min/max Functional from 1.2 V IN DD DD Input Impedance 150 150 kW typ REF Output Voltage 2.3/2.7 2.3/2.7 V min/max OUT REF Tempco 20 20 ppm/°C typ OUT LOGIC INPUTS Input High Voltage, V INH 2.4 2.4 V min AV = DV = 4.5 V to 5.5 V DD DD 2.1 2.1 V min AV = DV = 3.0 V to 3.6 V DD DD Input Low Voltage, V INL 0.8 0.8 V max AV = DV = 4.5 V to 5.5 V DD DD 0.6 0.6 V max AV = DV = 3.0 V to 3.6 V DD DD Input Current, I–10–10mA max Typically 10 nA, V = 0 V or V IN IN DD 4 Input Capacitance, C 10 10 pF max IN –2– REV. B AD7853/AD7853L 1 1 Parameter A Version B Version Units Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V I = 200 mA OH SOURCE 4 4 V min AV = DV = 4.5 V to 5.5 V DD DD 2.4 2.4 V min AV = DV = 3.0 V to 3.6 V DD DD Output Low Voltage, V 0.4 0.4 V max I = 0.8 mA OL SINK Floating-State Leakage Current–10–10mA max 4 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range Twos Complement Bipolar Input Range CONVERSION RATE Conversion Time 4.6 (18) 4.6 (18)ms max (L Versions Only, –40°C to +85°C, 1 MHz CLKIN) (10)ms max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN) Track/Hold Acquisition Time 0.4 (1) 0.4 (1)ms min (L Versions Only) POWER REQUIREMENTS AV DV +3.0/+5.5 +3.0/+5.5 V min/max DD, DD I DD 5 Normal Mode 6 (1.9) 6 (1.9) mA max AV = DV = 4.5 V to 5.5 V. Typically 4.5 mA (1.5); DD DD 5.5 (1.9) 5.5 (1.9) mA max AV = DV = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA) DD DD 6 Sleep Mode With External Clock On 10 10mA typ Full Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0 400 400mA typ Partial Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 1 With External Clock Off 5 5mA max Typically 1mA. Full-Power Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0 200 200mA typ Partial Power-Down. Power Management Bits in Control Register Set as PMGT1 = 1, PMGT0 = 1 Normal Mode Power Dissipation 33 (10.5) 33 (10.5) mW max V = 5.5 V: Typically 25 mW (8); SLEEP = V DD DD 20 (6.85) 20 (6.85) mW max V = 3.6 V: Typically 15 mW (5.4); SLEEP = V DD DD Sleep Mode Power Dissipation With External Clock On 55 55mW typ V = 5.5 V; SLEEP = 0 V DD 36 36mW typ V = 3.6 V; SLEEP = 0 V DD With External Clock Off 27.5 27.5mW max V = 5.5 V: Typically 5.5 mW; SLEEP = 0 V DD 18 18mW max V = 3.6 V: Typically 3.6 mW; SLEEP = 0 V DD SYSTEM CALIBRATION 7 Offset Calibration Span +0.05 · V /–0.05 · V V max/min Allowable Offset Voltage Span for Calibration REF REF 7 Gain Calibration Span +1.025 · V /–0.975 · V V max/min Allowable Full-Scale Voltage Span for Calibration REF REF NOTES 1 Temperature ranges as follows: A, B Versions, –40°C to +85°C. For L Versions, A and B Versions f = 1 MHz over –40°C to +85°C temperature range, CLKIN B Version f = 1.8 MHz over 0°C to +70°C temperature range. CLKIN 2 Specifications apply after calibration. 3 SNR calculation includes distortion and noise components. 4 Sample tested @ +25°C to ensure compliance. 5 All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV . No load on the digital outputs. Analog inputs @ AGND. DD 6 CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV . No load on the digital outputs. DD Analog inputs @ AGND. 7 The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) –0.05 · V , REF and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V – 0.025 · V ). REF REF This is explained in more detail in the calibration section of the data sheet. Specifications subject to change without notice. REV. B –3– AD7853/AD7853L (AV = DV = +3.0 V to +5.5 V; f = 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; T = T to DD DD CLKIN A MIN 1 T , unless otherwise noted) TIMING SPECIFICATIONS MAX Limit at T , T MIN MAX (A, B Versions) Parameter 5 V 3 V Units Description 2 f 500 500 kHz min Master Clock Frequency CLKIN 4 4 MHz max 1.8 1.8 MHz max L Version, 0°C to +70°C, B Grade Only 1 1 MHz max L Version, –40°C to +85°C 3 f 4 4 MHz max Interface Modes 1, 2, 3 (External Serial Clock) SCLK f f MHz max Interface Modes 4, 5 (Internal Serial Clock) CLKIN CLKIN 4 t 100 100 ns min CONVST Pulsewidth 1 t 50 90 ns max CONVSTfl to BUSY› Propagation Delay 2 t 4.6 4.6ms max Conversion Time = 18 t CONVERT CLKIN 10 (18) 10 (18)ms max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t CLKIN t –0.4 t –0.4 t ns min SYNCfl to SCLKfl Setup Time (Noncontinuous SCLK Input) 3 SCLK SCLK 70.4 t 70.4 t ns min/max SYNCfl to SCLKfl Setup Time (Continuous SCLK Input) SCLK SCLK t 0.6 t 0.6 t ns min SYNCfl to SCLKfl Setup Time. Interface Mode 4 Only 4 SCLK SCLK 5 t 50 90 ns max Delay from SYNCfl until DOUT 3-State Disabled 5 5 t 50 90 ns max Delay from SYNCfl until DIN 3-State Disabled 5A 5 t 75 115 ns max Data Access Time After SCLKfl6 t 40 60 ns min Data Setup Time Prior to SCLK›7 t 20 30 ns min Data Valid to SCLK Hold Time 8 6 t 0.4 t 0.4 t ns min SCLK High Pulsewidth (Interface Modes 4 and 5) 9 SCLK SCLK 6 t 0.4 t 0.4 t ns min SCLK Low Pulsewidth (Interface Modes 4 and 5) 10 SCLK SCLK t 30 50 ns min SCLK› to SYNC› Hold Time (Noncontinuous SCLK) 11 30/0.4 t 50/0.4 t ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 SCLK SCLK t 50 50 ns max SCLK› to SYNC› Hold Time 11A 7 t 50 50 ns max Delay from SYNC› until DOUT 3-State Enabled 12 t 90 130 ns max Delay from SCLK› to DIN Being Configured as Output 13 8 t 50 90 ns max Delay from SCLK› to DIN Being Configured as Input 14 t 2.5 t 2.5 t ns max CAL› to BUSY› Delay 15 CLKIN CLKIN t 2.5 t 2.5 t ns max CONVSTfl to BUSY› Delay in Calibration Sequence 16 CLKIN CLKIN 9 t 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent CAL (125013 t ) CLKIN 9 t 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock CAL1 Dependent (111114 t ) CLKIN 9 t 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent CAL2 (13899 t ) CLKIN NOTES Descriptions that refer to SCLK› (rising) or SCLKfl (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of SCLK will apply. 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. See DD Table X and timing diagrams for different interface modes and calibration. 2 Mark/Space ratio for the master clock input is 40/60 to 60/40. 3 For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f . CLKIN 4 The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power- Down section). 5 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6 For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t = 0.5 t . SCLK CLKIN 7 t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated 12 back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relin- 12 quish time of the part and is independent of the bus loading. 8 t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated 14 back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will not occur. 9 The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8/1 MHz master clock. Specifications subject to change without notice. –4– REV. B AD7853/AD7853L TYPICAL TIMING DIAGRAMS I 1.6mA OL Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in In- terface Modes 2 and 3. To attain the maximum sample rate of 100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes TO OUTPUT +2.1V PIN 2 and 3, reading and writing must be performed during conver- C L sion. Figure 3 shows the timing diagram for Interface Modes 4 100pF and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz (AD7853). At least 400 ns acquisition time must be allowed 200mA I OH (the time from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion begins to ensure that Figure 1. Load Circuit for Digital Output Timing the part is settled to the 12-bit level. If the user does not want to Specifications provide the CONVST signal, the conversion can be initiated in software by writing to the control register. t = 4.6ms MAX, 10ms FOR L VERSION POLARITY PIN LOGIC HIGH CONVERT t = 100 ns MIN, t = 50/90 ns MAX 5V/3V, t = 40/60 ns MIN 5V/3V 1 5 7 t 1 CONVST (I/P) t CONVERT t 2 BUSY (O/P) SYNC (I/P) t t 11 3 t 9 15616 SCLK (I/P) t 10 t 5 t 12 t t 6 6 THREE- THREE- DOUT (O/P) DB15 DB11 DB0 STATE STATE t 7 t 8 DB15 DB11 DB0 Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3) POLARITY PIN LOGIC HIGH t = 4.6ms MAX, 10ms FOR L VERSION CONVERT t = 100 ns MIN, t = 50/90 ns MAX 5V/3V, t = 40/60 ns MIN 5V/3V 1 5 7 t 1 CONVST (I/P) t CONVERT t 2 BUSY (O/P) SYNC (O/P) t t t 4 11 9 15616 SCLK (O/P) t 10 t t 5 t 12 6 THREE- THREE- DOUT (O/P) DB15 DB11 DB0 STATE STATE t 7 t 8 DIN (I/P) DB15 DB11 DB0 Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5) REV. B –5– AD7853/AD7853L 1 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE (T = +25°C unless otherwise noted) A Linearity Power AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Error Dissipation Package DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD 1 2 Model (LSB) (mW) Options AV to DV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DD DD Analog Input Voltage to AGND . . . . –0.3 V to AV + 0.3 V DD AD7853AN–1 20 N-24 Digital Input Voltage to DGND . . . . –0.3 V to DV + 0.3 V DD AD7853BN–1/2 20 N-24 3 Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V DD AD7853LAN–1 6.85 N-24 3 REF /REF to AGND . . . . . . . . . –0.3 V to AV + 0.3 V IN OUT DD AD7853LBN–1 6.85 N-24 2 Input Current to Any Pin Except Supplies . . . . . . . . –10 mA AD7853AR–1 20 R-24 Operating Temperature Range AD7853BR–1/2 20 R-24 3 Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C AD7853LAR–1 6.85 R-24 3 Storage Temperature Range . . . . . . . . . . . –65°C to +150°C AD7853LBR–1 6.85 R-24 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C AD7853ARS–1 6.85 RS-24 3 Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW AD7853LARS–1 6.85 RS-24 4q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W JA EVAL-AD7853CB 5q Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W JC EVAL-CONTROL BOARD Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C NOTES SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW 1 Linearity error refers to the integral linearity error. 2q Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP) JA N = Plastic DIP; R = SOIC; RS = SSOP. 3 q Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP) L signifies the low power version. JC 4 This can be used as a stand-alone evaluation board or in conjunction with the Lead Temperature, Soldering EVAL-CONTROL BOARD for evaluation/demonstration purposes. Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C 5 This board is a complete unit allowing a PC to control and communicate with Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C all Analog Devices, Inc. evaluation boards ending in the CB designators. ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >3 kV NOTES 1 PIN CONFIGURATIONS Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the DIP, SOIC AND SSOP device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 24 CONVST SYNC 2 Transient currents of up to 100 mA will not cause SCR latch-up. 2 23 BUSY SCLK SLEEP 3 22 CLKIN REF /REF 4 21 DIN IN OUT 5 20 AV DOUT DD AD7853/53L TOP VIEW AGND 6 19 DGND (Not to Scale) CREF1 7 18 DV DD 8 CAL CREF2 17 AIN(+) 9 16 SM2 10 AIN(–) 15 SM1 11 14 NC POLARITY 12 13 AGND AMODE NC = NO CONNECT –6– REV. B AD7853/AD7853L PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV . DD 2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and remains high until conversion is completed. BUSY is also used to indicate when the AD7853/AD7853L has completed its on-chip calibration sequence. 3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down including the internal voltage reference provided there is no conversion or calibration being performed. Calibration data is retained. A Logic 1 results in normal operation. See Power-Down section for more details. 4 REF / Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the IN REF reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears OUT at the pin. This pin can be overdriven by an external reference or can be taken as high as AV . When this DD pin is tied to AV , or when an externally applied reference approaches AV , the C pin should also be DD DD REF1 tied to AV . DD 5AV Analog Positive Supply Voltage, +3.0 V to +5.5 V. DD 6, 12 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 7C Reference Capacitor (0.1 mF multilayer ceramic). This external capacitor is used as a charge source for the REF1 internal DAC. The capacitor should be tied between the pin and AGND. 8C Reference Capacitor (0.01 mF ceramic disc). This external capacitor is used in conjunction with the on-chip REF2 reference. The capacitor should be tied between the pin and AGND. 9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time, and cannot go below AIN(–) when the unipolar input range is selected. DD 10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time. DD 11 NC No Connect Pin. 13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range 0 to V (i.e., AIN(+) – AIN(–) = 0 to V ). In this case AIN(+) cannot go below AIN(–) and REF REF AIN(–) cannot go below AGND. A Logic 1 selects range –V /2 to +V /2 (i.e., AIN(+) – AIN(–) = REF REF –V /2 to +V /2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to REF REF +V /2 to allow AIN(+) to go from 0 V to +V V. REF REF 14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and Table IX for the SCLK active edges. 15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera- tion as described in Table X. 16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera- tion as described in Table X. 17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 mA. A Logic 0 on this pin resets all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides all other internal operations. If the autocalibration is not required, this pin should be tied to a logic high. 18 DV Digital Supply Voltage, +3.0 V to +5.5 V. DD 19 DGND Digital Ground. Ground reference point for digital circuitry. 20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word. 21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X). 22 CLKIN Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and calibration times. 23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin. 24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X). REV. B –7– AD7853/AD7853L TERMINOLOGY Total Harmonic Distortion Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum of This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7853/AD7853L, it is through the endpoints of the ADC transfer function. The end- defined as: points of the transfer function are zero scale, a point 1/2 LSB 2 2 2 2 2 below the first code transition, and full scale, a point 1/2 LSB (V +V +V +V +V ) 2 3 4 5 6 above the last code transition. THD (dB) = 20log V 1 Differential Nonlinearity where V is the rms amplitude of the fundamental and V , V , This is the difference between the measured and the ideal 1 LSB 1 2 3 V , V and V are the rms amplitudes of the second through the change between any two adjacent codes in the ADC. 4 5 6 sixth harmonics. Total Unadjusted Error Peak Harmonic or Spurious Noise This is the deviation of the actual code from the ideal code Peak harmonic or spurious noise is defined as the ratio of the taking all errors into account (Gain, Offset, Integral Nonlinearity, rms value of the next largest component in the ADC output and other errors) at any point along the transfer function. spectrum (up to f /2 and excluding dc) to the rms value of the S Unipolar Offset Error fundamental. Normally, the value of this specification is deter- This is the deviation of the first code transition (00 . . . 000 to mined by the largest harmonic in the spectrum, but for parts 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) where the harmonics are buried in the noise floor, it will be a when operating in the unipolar mode. noise peak. Positive Full-Scale Error Intermodulation Distortion This applies to the unipolar and bipolar modes and is the devia- With inputs consisting of sine waves at two frequencies, fa and tion of the last code transition from the ideal AIN(+) voltage fb, any active device with nonlinearities will create distortion (AIN(–) + Full Scale – 1.5 LSB) after the offset error has been products at sum and difference frequencies of mfa – nfb where adjusted out. m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are Negative Full-Scale Error those for which neither m nor n are equal to zero. For example, This applies to the bipolar mode only and is the deviation of the the second order terms include (fa + fb) and (fa – fb), while the first code transition (10 . . . 000 to 10 . . . 001) from the ideal third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and AIN(+) voltage (AIN(–) – V /2 + 0.5 LSB). REF (fa – 2fb). Bipolar Zero Error Testing is performed using the CCIF standard where two input This is the deviation of the midscale transition (all 1s to all 0s) frequencies near the top end of the input bandwidth are used. In from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). this case, the second order terms are usually distanced in fre- quency from the original sine waves while the third order terms Track/Hold Acquisition Time are usually at a frequency close to the input frequencies. As a The track/hold amplifier returns into track mode and the end of result, the second and third order terms are specified separately. conversion. Track/Hold acquisition time is the time required for The calculation of the intermodulation distortion is as per the the output of the track/hold amplifier to reach its final value, THD specification where it is the ratio of the rms sum of the within –1/2 LSB, after the end of conversion. individual distortion products to the rms amplitude of the sum Signal to (Noise + Distortion) Ratio of the fundamentals expressed in dBs. This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f /2), excluding dc. The S ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N +1.76) dB Thus for a 12-bit converter, this is 74 dB. –8– REV. B AD7853/AD7853L ON-CHIP REGISTERS The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power- down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read- Only ADC. Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali- bration, and software conversion start can be selected by writing to the part. The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra- tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to. Addressing the On-Chip Registers Writing A write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ- ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over- all write register hierarchy. Table I. Write Register Addressing ADDR1 ADDR0 Comment 0 0 This combination does not address any register so the subsequent 14 data bits are ignored. 0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register. 1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written to the selected calibration register. 1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register until the read selection bits are changed in the control register. Table II. Read Register Addressing RDSLT1 RDSLT0 Comment 0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default setting. There will always be four leading zeros when reading from the ADC output data register. 0 1 All successive read operations will be from TEST REGISTER. 1 0 All successive read operations will be from CALIBRATION REGISTERS. 1 1 All successive read operations will be from STATUS REGISTER. RDSLT1, RDSLT0 ADDR1, ADDR0 DECODE DECODE 01 00 01 10 11 10 11 ADC OUTPUT TEST CALIBRATION STATUS TEST CALIBRATION CONTROL DATA REGISTER REGISTER REGISTERS REGISTER REGISTER REGISTERS REGISTER GAIN(1) GAIN(1) GAIN(1) GAIN(1) GAIN(1) OFFSET(1) GAIN(1) OFFSET(1) OFFSET(1) OFFSET(1) OFFSET(1) OFFSET(1) DAC(8) DAC(8) 00 01 10 11 00 01 10 11 CALSLT1, CALSLT0 CALSLT1, CALSLT0 DECODE DECODE Figure 4. Write Register Hierarchy/Address Decoding Figure 5. Read Register Hierarchy/Address Decoding REV. B –9– AD7853/AD7853L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0. MSB ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL LSB Control Register Bit Function Descriptions Bit Mnemonic Comment 13 ZERO These four bits must be set to 0 when writing to the control register. 12 ZERO 11 ZERO 10 ZERO 9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8 PMGT0 power-down modes (See Power-Down section for more details). 7 RDSLT1 These two bits determine which register is addressed for the read operations. See Table II. 6 RDSLT0 52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1, Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every write cycle. 4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration (see Calibration Section on page 21). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions. 1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per- 0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details). Table III. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the internal gain error and finally the internal offset error is calibrated out. This is the default setting. 0 0 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated out. 0 1 0 This calibrates out the internal offset error only. 0 1 1 This calibrates out the internal gain error only. 10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol- lowed by the system gain error, and finally the system offset error is calibrated out. 1 0 1 Here the system gain error is calibrated out followed by the system offset error. 1 1 0 This calibrates out the system offset error only. 1 1 1 This calibrates out the system gain error only. –10– REV. B AD7853/AD7853L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 6. Flowchart for Reading the Status Register MSB ZERO BUSY ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE X CALMD CALSLT1 CALSLT0 STCAL LSB Status Register Bit Function Descriptions Bit Mnemonic Comment 15 ZERO This bit is always 0. 14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion or calibration in progress. When this bit is 0, no conversion or calibration is in progress. 13 ZERO These four bits are always 0. 12 ZERO 11 ZERO 10 ZERO 9 PMGT1 Power Management Bits. These bits, along with the SLEEP pin, will indicate whether or not the part is in a 8 PMGT0 power-down mode. See Table VI in Power-Down Section for description. 7 RDSLT1 Both of these bits are always 1, indicating it is the status register that is being read. See Table II. 6 RDSLT0 52/3 MODE Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at 1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle. 4 X Don’t care bit. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected; a 1 in this bit indicates a system calibration is selected (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in 1 CALSLT0 progress and as a 0 if no calibration is in progress. The CALSLT1 and CALSLT0 bits indicate 0 STCAL which of the calibration registers are addressed for reading and writing (see section on the Calibration Registers for more details). REV. B –11– AD7853/AD7853L CALIBRATION REGISTERS The AD7853/AD7853L has ten calibration registers in all, eight for the DAC, one for the offset and one for gain. Data can be writ- ten to or read from all ten calibration registers. In self- and system calibration the part automatically modifies the calibration regis- ters; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. Addressing the Calibration Registers The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad- dressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time. Table IV. Calibration Register Addressing CALSLT1 CALSLT0 Comment 0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. 0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total. 1 0 This combination addresses the Offset Register. One register in total. 1 1 This combination addresses the Gain Register. One register in total. Writing to/Reading from the Calibration Registers When reading from the calibration registers there will always be For writing to the calibration registers a write to the control two leading zeros for each of the registers. When operating in register is required to set the CALSLT0 and CALSLT1 bits. serial Interface Mode 1, the read operations to the calibration For reading from the calibration registers a write to the control registers cannot be aborted. The full number of read operations register is required to set the CALSLT0 and CALSLT1 bits, must be completed (see section on serial Interface Mode 1 tim- but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad- ing for more detail). dresses the calibration registers for reading). The calibration register pointer is reset on writing to the control register setting START the CALSLT1 and CALSLT0 bits, or upon completion of all the calibration register write/read operations. When reset it WRITE TO CONTROL REGISTER SETTING STCAL = 0 points to the first calibration register in the selected write/read AND CALSLT1, CALSLT0 = 00, 01, 10, 11 sequence. The calibration register pointer will point to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own CAL REGISTER POINTER IS (CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra- AUTOMATICALLY RESET tion register is being accessed, the calibration register pointer will be automatically incremented after each calibration register write/read operation. The order in which the ten calibration WRITE TO CAL REGISTER (ADDR1 = 1, ADDR0 = 0) registers are arranged is shown in Figure 7. The user may abort at any time before all the calibration register write/read opera- tions are completed, and the next control register write opera- CAL REGISTER POINTER IS tion will reset the calibration register pointer. The flowchart in AUTOMATICALLY INCREMENTED Figure 8 shows the sequence for writing to the calibration regis- ters and Figure 9 for reading. CALIBRATION REGISTERS LAST REGISTER CAL REGISTER GAIN REGISTER (1) WRITE NO ADDRESS POINTER OPERATION OFFSET REGISTER (2) OR ABORT (3) DAC 1st MSB REGISTER ? YES DAC 8th MSB REGISTER (10) FINISHED CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS Figure 8. Flowchart for Writing to the Calibration Registers ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS. Figure 7. Calibration Register Arrangement –12– REV. B AD7853/AD7853L This gives a resolution of –0.0006% of V approximately. REF START 13 More accurately the resolution is –(0.05 · V )/2 volts = REF –0.015 mV, with a 2.5 V reference. The maximum offset that WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, can be compensated for is –5% of the reference voltage, which RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 equates to –125 mV with a 2.5 V reference and –250 mV with a 5 V reference. Q. If a +20 mV offset is present in the analog input signal and the CAL REGISTER POINTER IS AUTOMATICALLY RESET reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset ? A. 2.5 V reference implies that the resolution in the offset 13 READ CAL REGISTER register is 5% · 2.5 V/2 = 0.015 mV. +20 mV/0.015 mV = 1310.72; rounding to the nearest number gives 1311. In binary terms this is 0101 0001 1111, therefore decrease the CAL REGISTER POINTER IS offset register by 0101 0001 1111. AUTOMATICALLY INCREMENTED This method of compensating for offset in the analog input signal allows for fine tuning the offset compensation. If the offset on the analog input signal is known, there will be no need LAST to apply the offset voltage to the analog input pins and do a REGISTER READ NO system calibration. The offset compensation can take place in OPERATION software. OR ABORT ? Adjusting the Gain Calibration Register The gain calibration register contains 16 bits, two leading 0s YES and 14 data bits. The data bits are binary weighted as in the FINISHED offset calibration register. The gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. Increasing the gain register compensates for Figure 9. Flowchart for Reading from the Calibration a smaller analog input range and decreasing the gain register Registers compensates for a larger input range. The maximum analog Adjusting the Offset Calibration Register input range that the gain register can compensate for is 1.025 The offset calibration register contains 16 bits, two leading zeros times the reference voltage, and the minimum input range is and 14 data bits. By changing the contents of the offset register, 0.975 times the reference voltage. different amounts of offset on the analog input signal can be compensated for. Increasing the number in the offset calibra- tion register compensates for negative offset on the analog input signal, and decreasing the number in the offset calibration regis- ter compensates for positive offset on the analog input signal. The default value of the offset calibration register is 0010 0000 0000 0000 approximately. This is not an exact value, but the value in the offset register should be close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the reference voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so on down to the LSB, which has a weighting of 0.0006%. REV. B –13– AD7853/AD7853L CIRCUIT INFORMATION edge of CONVST occurs at least 10 ns typically before this The AD7853/AD7853L is a fast, 12-bit single supply A/D con- CLKIN edge. The conversion cycle will take 16.5 CLKIN verter. The part requires an external 4 MHz/1.8 MHz master periods from this CLKIN falling edge. If the 10 ns setup time is clock (CLKIN), two C capacitors, a CONVST signal to start not met, the conversion will take 17.5 CLKIN periods. The REF conversion and power supply decoupling capacitors. The part maximum specified conversion time is 4.6 ms for the AD7853 provides the user with track/hold, on-chip reference, calibration (18 t CLKIN = 4 MHz) and 10 ms for the AD7853L (18 CLKIN, features, A/D converter and serial interface logic functions on a t , CLKIN = 1.8 MHz). When a conversion is completed, CLKIN single chip. The A/D converter section of the AD7853/AD7853L the BUSY output goes low, and then the result of the conver- consists of a conventional successive-approximation converter sion can be read by accessing the data through the serial inter- based around a capacitor DAC. The AD7853/AD7853L accepts face. To obtain optimum performance from the part, the read an analog input range of 0 to +V where the reference can be operation should not occur during the conversion or 400␣ ns DD tied to V . The reference input to the part is buffered on-chip. prior to the next CONVST rising edge. However, the maximum DD throughput rates are achieved by reading/writing during conver- A major advantage of the AD7853/AD7853L is that a conver- sion, and reading/writing during conversion is likely to degrade sion can be initiated in software as well as applying a signal to the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7853 the CONVST pin. Another innovative feature of the AD7853/ can operate at throughput rates up to 200 kHz, 100 kHz for AD7853L is self-calibration on power-up, which is initiated the AD7853L. For the AD7853/AD7853L a conversion takes having a capacitor from the CAL pin to AGND, to give superior 18 CLKIN periods, 2 CLKIN periods are needed for the dc accuracy (See Automatic Calibration on Power-Up section). acquisition time giving a full cycle time of 5 ms (= 200 kHz, The part is available in a 24-lead SSOP package, which offers CLKIN = 4 MHz). For the AD7853L 100 kHz throughput can the user considerable space-saving advantages over alternative be obtained as follows: the CLKIN and CONVST signals are solutions. The AD7853L version typically consumes only 5.5 mW, arranged to give a conversion time of 16.5 CLKIN periods as making it ideal for battery-powered applications. described above, 1.5 CLKIN periods are allowed for the acqui- sition time. This gives a full cycle time of 10 ms (= 100 kHz, CONVERTER DETAILS CLKIN = 1.8 MHz). When using the software conversion start The master clock for the part must be applied to the CLKIN for maximum throughput, the user must ensure the control register pin. Conversion is initiated on the AD7853/AD7853L by puls- write operation extends beyond the falling edge of BUSY. The ing the CONVST input or by writing to the control register and falling edge of BUSY resets the CONVST bit to 0 and allows it to setting the CONVST bit to 1. On the rising edge of CONVST be reprogrammed to 1 to start the next conversion. (or at the end of the control register write operation), the on- chip track/hold goes from track to hold mode. The falling edge of the CLKIN signal which follows the rising edge of the edge of CONVST signal initiates the conversion, provided the rising 4MHz/1.8MHz OSCILLATOR 200kHz/100kHz PULSE GENERATOR ANALOG SUPPLY MASTER CLOCK INPUT +3V TO +5V 10mF 0.1mF 0.1mF CONVERSION AV DV START INPUT DD DD 0V TO 2.5V AIN(+) INPUT OSCILLOSCOPE AIN(–) CLKIN UNIPOLAR CH1 AMODE SCLK RANGE SERIAL CLOCK OUTPUT C REF1 CONVST CH2 0.1mF C REF2 SYNC AD7853/53L CH3 0.01mF FRAME SYNC OUTPUT CH4 DOUT SLEEP SERIAL DATA OUTPUT DV POLARITY DIN DD CAL 4 LEADING ZEROS 0.01mF DIN AT DGND FOR ADC DATA SM1 => NO WRITING DV AGND DD TO DEVICE SM2 DGND REF /REF SERIAL MODE IN OUT AUTO CAL ON SELECTION BITS POWER-UP INTERNAL/EXTERNAL 0.1mF REFERENCE OPTIONAL EXTERNAL AD780/REF-192 REFERENCE Figure 10. Typical Circuit –14– REV. B AD7853/AD7853L TYPICAL CONNECTION DIAGRAM DC/AC Applications Figure 10 shows a typical connection diagram for the AD7853/ For dc applications high source impedances are acceptable, AD7853L. The DIN line is tied to DGND so that no data is provided there is enough acquisition time between conversions written to the part. The AGND and the DGND pins are con- to charge the 20 pF capacitor. The acquisition time can be nected together at the device for good noise suppression. The calculated from the above formula for different source imped- CAL pin has a 0.01 mF capacitor to enable an automatic self- ances. For example with R = 5 kW, the required acquisition IN calibration on power-up. The SCLK and SYNC are configured time will be 922 ns. as outputs by having SM1 and SM2 at DV . The conversion DD For ac applications, removing high frequency components from result is output in a 16-bit word with four leading zeros followed the analog input signal is recommended by use of an RC low- by the MSB of the 12-bit result. Note that after the AV and DD pass filter on the AIN(+) pin, as shown in Figure 13. In applica- DV power-up, the part will require approximately 150 ms for DD tions where harmonic distortion and signal to noise ratio are the internal reference to settle and for the automatic calibration critical, the analog input should be driven from a low impedance on power-up to be completed. source. Large source impedances will significantly affect the ac For applications where power consumption is a major concern, performance of the ADC. This may necessitate the use of an the SLEEP pin can be connected to DGND. See Power-Down input buffer amplifier. The choice of the op amp will be a func- section for more detail on low power applications. tion of the particular application. When no amplifier is used to drive the analog input the source ANALOG INPUT impedance should be limited to low values. The maximum The equivalent circuit of the analog input section is shown in source impedance will depend on the amount of total harmonic Figure 11. During the acquisition interval the switches are both distortion (THD) that can be tolerated. The THD will increase in the track position and the AIN(+) charges the 20 pF capaci- as the source impedance increases and performance will degrade. tor through the 125 W resistance. On the rising edge of CONVST Figure 12 shows a graph of the Total Harmonic Distortion vs. switches SW1 and SW2 go into the hold position retaining analog input signal frequency for different source impedances. charge on the 20 pF capacitor as a sample of the signal on With the setup as in Figure 13, the THD is at the –90 dB level. AIN(+). The AIN(–) is connected to the 20 pF capacitor, and With a source impedance of 1 kW and no capacitor on the AIN(+) this unbalances the voltage at Node A at the input of the com- pin, the THD increases with frequency. parator. The capacitor DAC adjusts during the remainder of the conversion cycle to restore the voltage at Node A to the correct –72 value. This action transfers a charge, representing the analog THD VS. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES input signal, to the capacitor DAC which in turn forms a digital –76 representation of the analog input signal. The voltage on the AIN(–) pin directly influences the charge transferred to the capacitor DAC at the hold instant. If this voltage changes dur- –80 R = 1kV ing the conversion period, the DAC representation of the analog IN input voltage will be altered. Therefore it is most important that the voltage on the AIN(–) pin remains constant during the con- –84 version period. Furthermore, it is recommended that the AIN(–) pin is always connected to AGND or to a fixed dc voltage. R = 50V, 10nF IN –88 AS IN FIGURE 13 TRACK 125V AIN(+) –92 CAPACITOR 0 20 40 60 80 100 SW1 AIN(–) DAC INPUT FREQUENCY – kHz 20pF 125V HOLD Figure 12. THD vs. Analog Input Frequency NODE A In a single supply application (both 3 V and 5 V), the V+ and SW2 V– of the op amp can be taken directly from the supplies to the COMPARATOR TRACK HOLD AD7853/AD7853L which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and C REF2 outputs at frequencies greater than 10 kHz, care must be taken Figure 11. Analog Input Equivalent Circuit in selecting the particular op amp for the application. In particu- Acquisition Time lar, for single supply applications the input amplifiers should be The track and hold amplifier enters its tracking mode on the connected in a gain of –1 arrangement to get the optimum per- falling edge of the BUSY signal. The time required for the track formance. Figure 13 shows the arrangement for a single supply and hold amplifier to acquire an input signal will depend on application with a 50 W and 10 nF low-pass filter (cutoff fre- how quickly the 20 pF input capacitance is charged. The acqui- quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a sition time is calculated using the formula: capacitor with good linearity to ensure good ac performance. Recommended single supply op amps are the AD820 and the t = 9 · (R + 125 W) · 20 pF ACQ IN AD820-3 V. where R is the source impedance of the input signal, and 125W, IN 20 pF is the input R, C. REV. B –15– THD – dB AD7853/AD7853L +3V TO +5V 0.1mF 10mF TRACK AND HOLD AIN(+) AMPLIFIER 10kV V = 0 TO V IN REF DOUT 2S AIN(–) V IN 10kV V /2 COMPLEMENT REF V+ –V /2 TO +V /2 REF REF 50V FORMAT TO AIN(+) OF IC1 10kV AD7853/AD7853L 10nF V /2 AD820 REF V– AD7853/AD7853L DV (NPO) AD820-3V DD 10kV BIPOLAR AMODE ANALOG INPUT RANGE Figure 13. Analog Input Buffering SELECTED Input Ranges Figure 15.–V /2 about V /2 Bipolar Input Configuration REF REF The analog input range for the AD7853/AD7853L is 0 V to OUTPUT V in both the unipolar and bipolar ranges. REF CODE The only difference between the unipolar range and the bipolar 111...111 range is that in the bipolar range the AIN(–) has to be biased up 111...110 to +V /2 and the output coding is twos complement (See REF 111...101 Table V and Figures 14 and 15). The unipolar or bipolar mode 111...100 is selected by the AMODE pin (0 for the unipolar range and 1 for the bipolar range). Table V. Analog Input Connections FS 000...011 1LSB = 4096 Analog Input Input Connections Connection 000...010 Range AIN(+) AIN(–) Diagram AMODE 000...001 000...000 1 0 V to V V AGND Figure 14 DGND 0V 1LSB REF IN +FS –1LSB 2 V = (AIN(+) – AIN(–)), INPUT VOLTAGE–V /2 V V /2 Figure 15 DV IN REF IN REF DD NOTES Figure 16. Unipolar Transfer Characteristic 1 Output code format is straight binary. 2 Range is –V /2 biased about V /2. Output code format is twos complement. REF REF Figure 15 shows the AD7853/AD7853L’s –V /2 bipolar ana- REF log input configuration (where AIN(+) cannot go below 0 V so Note that the AIN(–) pin on the AD7853/AD7853L can be for the full bipolar range then the AIN(–) pin should be biased biased up above AGND in the unipolar mode also, if required. to +V /2). Once again the designed code transitions occur The advantage of biasing the lower end of the analog input REF midway between successive integer LSB values. The output range away from AGND is that the user does not have to have coding is twos complement with 1 LSB = 4096 = 3.3 V/4096 = the analog input swing all the way down to AGND. This has the 0.8 mV. The ideal input/output transfer characteristic is shown advantage in true single supply applications that the input am- in Figure 17. plifier does not have to swing all the way down to AGND. The upper end of the analog input range is shifted up by the same OUTPUT amount. Care must be taken so that the bias applied does not CODE shift the upper end of the analog input above the AV supply. 011...111 DD In the case where the reference is the supply, AV , the AIN(–) 011...110 DD must be tied to AGND in unipolar mode. (V /2) –1 LSB REF 000...001 TRACK AND HOLD 0V 000...000 AIN(+) AMPLIFIER + FS – 1 LSB V = 0 TO V IN REF DOUT STRAIGHT 111...111 AIN(–) (V /2) +1 LSB BINARY REF FORMAT 100...010 FS = V V REF FS 1LSB = AD7853/AD7853L 100...001 4096 UNIPOLAR ANALOG 100...000 AMODE INPUT RANGE SELECTED V /2 REF V = (AIN(+) – AIN(–)), INPUT VOLTAGE IN Figure 14. 0 to V Unipolar Input Configuration REF Transfer Functions Figure 17. Bipolar Transfer Characteristic For the unipolar range the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary for the unipolar range with 1 LSB = FS/4096 = 3.3 V/4096 = 0.8 mV when V = 3.3 V. The ideal input/output REF transfer characteristic for the unipolar range is shown in Figure 16. –16– REV. B AD7853/AD7853L REFERENCE SECTION PERFORMANCE CURVES For specified performance, it is recommended that when using Figure 20 shows a typical FFT plot for the AD7853 at 200 kHz an external reference this reference should be between 2.3 V sample rate and 10 kHz input frequency. and the analog supply AV . The connections for the relevant DD 0 reference pins are shown in the typical connection diagrams. If AV = DV = 3.3V DD DD the internal reference is being used, the REF /REF pin IN OUT f = 200kHz SAMPLE should have a 100 nF capacitor connected to AGND very close –20 f = 10kHz IN SNR = 72.04dB to the REF /REF pin. These connections are shown in IN OUT THD = –88.43dB Figure 18. –40 If the internal reference is required for use external to the ADC, it should be buffered at the REF /REF pin and a 100 nF –60 IN OUT connected from this pin to AGND. The typical noise performance for the internal reference, with 5 V supplies is 150 nV/√Hz @ –80 1 kHz and dc noise is 100 mV p-p. –100 ANALOG SUPPLY +3V TO +5V 10mF 0.1mF 0.1mF –120 0 20 40 60 80 100 FREQUENCY – kHz AV DV DD DD Figure 20. FFT Plot C REF1 0.1mF Figure 21 shows the SNR versus Frequency for different sup- plies and different external references. AD7853/AD7853L C REF2 0.01mF 74 AV = DV WITH 2.5V REFERENCE DD DD REF /REF IN OUT UNLESS STATED OTHERWISE 0.1mF 73 5.0V SUPPLIES, WITH 5V REFERENCE 72 5.0V SUPPLIES Figure 18. Relevant Connections When Using Internal Reference 5.0V SUPPLIES, L VERSION 71 The other option is that the REF /REF pin be overdriven IN OUT by connecting it to an external reference. This is possible due to the series resistance from the REF /REF pin to the internal IN OUT 70 reference. This external reference can have a range that includes 3.3V SUPPLIES AV . When using AV as the reference source, the 100 nF DD DD 69 capacitor from the REF /REF pin to AGND should be as IN OUT 0 20 40 60 80 100 INPUT FREQUENCY – kHz close as possible to the REF /REF pin, and also the C IN OUT REF1 pin should be connected to AV to keep this pin at the same Figure 21. SNR vs. Frequency DD level as the reference. The connections for this arrangement are Figure 22 shows the Power Supply Rejection Ratio versus Fre- shown in Figure 19. When using AV it may be necessary to DD quency for the part. The Power Supply Rejection Ratio is de- add a resistor in series with the AV supply. This will have the DD fined as the ratio of the power in ADC output at frequency f to effect of filtering the noise associated with the AV supply. DD the power of a full-scale sine wave. PSRR (dB) = 10 log (Pf/Pfs) ANALOG SUPPLY +3V TO +5V 0.1mF 0.1mF 10mF Pf = Power at frequency f in ADC output, Pfs = power of a full- scale sine wave. Here a 100 mV peak-to-peak sine wave is AV DV coupled onto the AV supply while the digital supply is left DD DD DD unaltered. Both the 3.3 V and 5.0 V supply performances are C REF1 shown. 0.1mF AD7853/AD7853L C REF2 0.01mF REF /REF IN OUT 0.1mF Figure 19. Relevant Connections When Using AV as the DD Reference REV. B –17– SNR – dB S(N+D) RATIO – dB AD7853/AD7853L –78 is powered down and I is 400 mA typ. The choice of full or par- DD AV = DV = 3.3V/5.0V, DD DD tial power-down does not give any significant improvement in 100mV p-p SINE WAVE ON AV DD throughput with a power-down between conversions. This is –80 discussed in the next section–Power-Up Times. However, a 3.3V partial power-down does allow the on-chip reference to be used –82 externally even though the rest of the AD7853 circuitry is pow- ered down. It also allows the AD7853 to be powered up faster –84 after a long power-down period when using the on-chip refer- ence (See Power-Up Times–Using On-Chip Reference). –86 When using the SLEEP pin, the power management bits PMGT1 5.0V and PMGT0 should be set to zero (default status on power-up). –88 Bringing the SLEEP pin logic high ensures normal operation, and the part does not power down at any stage. This may be –90 necessary if the part is being used at high throughput rates when 0 20 40 60 80 100 INPUT FREQUENCY – kHz it is not possible to power down between conversions. If the user Figure 22. PSRR vs. Frequency wishes to power down between conversions at lower throughput rates (i.e. <100 kSPS for the AD7853) to achieve better power POWER-DOWN OPTIONS performances, then the SLEEP pin should be tied logic low. The AD7853 provides flexible power management to allow the If the power-down options are to be selected in software only, user to achieve the best power performance for a given through- then the SLEEP pin should be tied logic high. By setting the put rate. The power management options are selected by power management bits PMGT1 and PMGT0 as shown in programming the power management bits, PMGT1 and PMGT0, Table VI, a Full Power-Down, Full Power-Up, Full Power- in the control register and by use of the SLEEP pin. Table VI Down Between Conversions, and a Partial Power-Down Be- summarizes the power-down options that are available and how tween Conversions can be selected. they can be selected by using either software, hardware or a A typical connection diagram for a low power application is combination of both. The AD7853 can be fully or partially shown in Figure 23 (AD7853L is the low power version of the powered down. When fully powered down, all the on-chip cir- AD7853). cuitry is powered down and I is 1 mA typ. If a partial power- DD down is selected, then all the on-chip circuitry except the reference 1.8MHz OSCILLATOR CURRENT, I = 1.5mA TYP 100kHz PULSE GENERATOR ANALOG SUPPLY MASTER CLOCK INPUT +3V 0.1mF 10mF 0.1mF AV DV DD DD 0V TO 2.5V AIN(+) INPUT AIN(–) CLKIN UNIPOLAR RANGE AMODE SCLK SERIAL CLOCK INPUT C REF1 LOW POWER CONVST 0.1mF mC/mP C CONVERSION REF2 START INPUT AD7853L SYNC 0.01mF AUTO POWER- DOWN AFTER DOUT CONVERSION SLEEP SERIAL DATA OUTPUT DV POLARITY DIN DD CAL DIN AT DGND => NO WRITING 0.01mF SM1 TO DEVICE AGND AUTO CAL ON POWER-UP SM2 SERIAL MODE SELECTION BITS DGND REF /REF IN OUT THREE-WIRE INTERNAL MODE 0.1mF REFERENCE SELECTED OPTIONAL EXTERNAL REF-192 REFERENCE Figure 23. Typical Low Power Circuit –18– REV. B PSRR – dB AD7853/AD7853L Table VI. Power Management Options writes are required. The first initiates the type of calibration required, the second write powers the part down into partial PMGT1 PMGT0 SLEEP power-down mode, while the third write powers the part up Bit Bit Pin Comment again before the next calibration command is issued. 00 0 Full Power-Down if Not Cali- START CONVERSION ON RISING EDGE brating or Converting (Default POWER-UP ON FALLING EDGE Condition After Power-On) 5ms 00 1 Normal Operation CONVST 01 X Normal Operation t CONVERT (Independent of the SLEEP Pin) BUSY 10 X Full Power-Down POWER-UP NORMAL FULL POWER-UP 11 X Partial Power-Down if Not TIME OPERATION POWER-DOWN TIME Converting Figure 24. Power-Up Timing When Using CONVST Pin Using the Internal (On-Chip) Reference POWER-UP TIMES As in the case of an external reference, the AD7853 can power- Using an External Reference up from one of two conditions, power-up after the supplies are When the AD7853 is powered up, the part is powered up from connected or power-up from hardware/software power-down. one of two conditions. First, when the power supplies are ini- When using the on-chip reference and powering up when AV tially powered up and, secondly, when the part is powered up DD and DV are first connected, it is recommended that the power- from either a hardware or software power-down (see last section). DD up calibration mode be disabled as explained above. When using When AV and DV are powered up, the AD7853 should be DD DD the on-chip reference, the power-up time is effectively the time left idle for approximately 32 ms (4 MHz CLK) to allow for the it takes to charge up the external capacitor on the REF /REF IN OUT autocalibration if a 10 nF cap is placed on the CAL pin, (see pin. This time is given by the equation: Calibration section). During power-up the functionality of the t = 9 · R · C SLEEP pin is disabled, i.e., the part will not power down until UP the end of the calibration if SLEEP is tied logic low. The auto- where R @ 150 kW and C = external capacitor. calibration on power-up can be disabled if the CAL pin is tied to The recommended value of the external capacitor is 100 nF; a logic high. If the autocalibration is disabled, then the user must this gives a power-up time of approximately 135 ms before a take into account the time required by the AD7853 to power-up calibration is initiated and normal operation should commence. before a self-calibration is carried out. This power-up time is the time taken for the AD7853 to power up when power is first When C is fully charged, the power-up time from a hardware REF applied (300 ms) typ) or the time it takes the external reference or software power-down reduces to 5 ms. This is because an to settle to the 12-bit level–whichever is the longer. internal switch opens to provide a high impedance discharge path for the reference capacitor during power-down—see Figure The AD7853 powers up from a full hardware or software 23. An added advantage of the low charge leakage from the power-down in 5 ms typ. This limits the throughput which the reference capacitor during power-down is that even though the part is capable of to 104 kSPS for the AD7853 operating with a reference is being powered down between conversions, the 4 MHz CLK and 66 kSPS for the AD7853L with a 1.8 MHz reference capacitor holds the reference voltage to within CLK when powering down between conversions. Figure 24 0.5 LSBs with throughput rates of 100 samples/second and over shows how power-down between conversions is implemented with a full power-down between conversions. A high input im- using the CONVST pin. The user first selects the power-down pedance op amp like the AD707 should be used to buffer this between conversions option by using the SLEEP pin and the reference capacitor if it is being used externally. Note, if the power management bits, PMGT1 and PMGT0, in the control AD7853 is left in its power-down state for more than 100 ms, register, (see last section). In this mode the AD7853 automati- the charge on C will start to leak away and the power-up REF cally enters a full power-down at the end of a conversion, i.e., time will increase. If this long power-up time is a problem, the when BUSY goes low. The falling edge of the next CONVST user can use a partial power-down for the last conversion so the pulse causes the part to power up. Assuming the external refer- reference remains powered up. ence is left powered up, the AD7853 should be ready for normal operation 5 ms after this falling edge. The rising edge of CONVST initiates a conversion so the CONVST pulse should be at least SWITCH OPENS 5 ms wide. The part automatically powers down on completion AD7853 DURING POWER-DOWN of the conversion. REF /REF IN OUT ON-CHIP REFERENCE NOTE: Where the software CONVST is used or automatic EXTERNAL CAPACITOR full power-down, the part must be powered up in software with TO OTHER an extra write setting PMGT1 = 0 and PMGT0 = 1 before a BUF CIRCUITRY conversion is initiated in the next write. Automatic partial power- down after a calibration is not possible; the part must be powered down manually. If software calibrations are to be used when Figure 25. On-Chip Reference During Power-Down operating in the partial power-down mode, then three separate REV. B –19– AD7853/AD7853L POWER VS. THROUGHPUT RATE There are two main calibration modes on the AD7853/AD7853L, The main advantage of a full power-down after a conversion is self-calibration and system calibration. There are various op- that it significantly reduces the power consumption of the part tions in both self-calibration and system calibration as outlined at lower throughput rates. When using this mode of operation, previously in Table III. All the calibration functions can be the AD7853 is only powered up for the duration of the conver- initiated by pulsing the CAL pin or by writing to the control sion. If the power-up time of the AD7853 is taken to be 5 ms register and setting the STCAL bit to 1. The timing diagrams and it is assumed that the current during power-up is 4 mA typ, that follow involve using the CAL pin. then power consumption as a function of throughput can easily The duration of each of the different types of calibrations is be calculated. The AD7853 has a conversion time of 4.6 ms given in Table VIII for the AD7853 with a 4 MHz master clock. with a 4 MHz external clock. This means the AD7853 con- These calibration times are master clock dependent. Therefore sumes 4 mA typ, (or 12 mW typ V = 3 V) for 9.6 ms in every DD the calibration times for the AD7853L (CLKIN = 1.8 MHz) conversion cycle if the device is powered down at the end of a will be larger than those quoted in Table VIII. conversion. If the throughput rate is 1 kSPS, the cycle time is 1000 ms and the average power dissipated during each cycle is Table VIII. Calibration Times (AD7853 with 4 MHz CLKIN) (9.6/1000) · (12 mW) = 115 mW. The graph, Figure 24, shows the power consumption of the AD7853 as a function of through- Type of Self- or System Calibration Time put. Table VII lists the power consumption for various through- Full 31.25 ms put rates. Gain + Offset 6.94 ms Offset 3.47 ms Table VII. Power Consumption vs. Throughput Gain 3.47 ms Throughput Rate Power Automatic Calibration on Power-On 1 kSPS 115 mW The CAL pin has a 0.15 mA pull-up current source connected to 10 kSPS 1.15 mW it internally to allow for an automatic full self-calibration on power-on. A full self-calibration will be initiated on power-on if a capacitor is connected from the CAL pin to DGND. The 10 internal current source connected to the CAL pin charges up the external capacitor and the time required to charge the exter- AD7853 (4MHz CLK) nal capacitor will depend on the size of the capacitor itself. This time should be large enough to ensure that the internal refer- 1 ence is settled before the calibration is performed. A 33 nF capacitor is sufficient to ensure that the internal reference has settled (see Power-Up Times) before a calibration is initiated taking into account trigger level and current source variations on AD7853L (1.8MHz CLK) 0.1 the CAL pin. However, if an external reference is being used, this reference must have stabilized before the automatic calibra- tion is initiated (a larger capacitor on the CAL pin should be used if the external reference has not settled when the autocali- bration is initiated). Once the capacitor on the CAL pin has 0.01 051 105 2025 3035 4045 50 charged, the calibration will be performed which will take 32 ms THROUGHPUT – kSPS (4 MHz CLKIN). Therefore the autocalibration should be Figure 26. Power vs. Throughput Rate complete before operating the part. After calibration, the part is accurate to the 12-bit level and the specifications quoted on the CALIBRATION SECTION data sheet apply. There will be no need to perform another Calibration Overview calibration unless the operating conditions change or unless a The automatic calibration that is performed on power-up en- system calibration is required. sures that the calibration options covered in this section will not Self-Calibration Description be required in a significant amount of applications. The user There are a four different calibration options within the self- will not have to initiate a calibration unless the operating condi- calibration mode. There is a full self-calibration where the DAC, tions change (CLKIN frequency, analog input mode, reference internal offset, and internal gain errors are calibrated out. Then, voltage, temperature, and supply voltages). The AD7853/ there is the (Gain + Offset) self-calibration which calibrates out AD7853L have a number of calibration features that may be the internal gain error and then the internal offset errors. The required in some applications and there are a number of advan- internal DAC is not calibrated here. Finally, there are the self- tages in performing these different types of calibration. First, the offset and self-gain calibrations which calibrate out the internal internal errors in the ADC can be reduced significantly to give offset errors and the internal gain errors respectively. superior dc performance; and second, system offset and gain The internal capacitor DAC is calibrated by trimming each of errors can be removed. This allows the user to remove reference the capacitors in the DAC. It is the ratio of these capacitors to errors (whether it be internal or external reference) and to make each other that is critical, and so the calibration algorithm en- use of the full dynamic range of the AD7853/AD7853L by ad- sures that this ratio is at a specific value by the end of the cali- justing the analog input range of the part for a specific system. bration routine. For the offset and gain there are two separate –20– REV. B POWER – mW AD7853/AD7853L capacitors, one of which is trimmed when an offset or gain cali- errors are outside the ranges mentioned, the system calibration bration is performed. Again it is the ratio of these capacitors to algorithm will reduce the errors as much as the trim range allows. the capacitors in the DAC that is critical and the calibration Figures 33 through 35 illustrate why a specific type of system algorithm ensures that this ratio is at a specified value for both calibration might be used. Figure 33 shows a system offset cali- the offset and gain calibrations. bration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the In Bipolar Mode the midscale error is adjusted for an offset system offset calibration is completed. A negative offset may calibration and the positive full-scale error is adjusted for the also be accounted for by a system offset calibration. gain calibration; in Unipolar Mode the zero-scale error is ad- justed for an offset calibration and the positive full-scale error is adjusted for a gain calibration. MAX SYSTEM FULL SCALE IS 62.5% FROM V REF Self-Calibration Timing V + SYS OFFSET REF The diagram of Figure 27 shows the timing for a full self- V – 1LSB V – 1LSB REF REF calibration. Here the BUSY line stays high for the full length of SYSTEM OFFSET the self-calibration. A self-calibration is initiated by bringing the ANALOG ANALOG INPUT INPUT CAL pin low (which initiates an internal reset) and then high RANGE RANGE CALIBRATION again or by writing to the control register and setting the STCAL bit to 1 (note that if the part is in a power-down mode, the CAL SYS OFFSET SYS OFFSET AGND AGND pulsewidth must take account of the power-up time). The BUSY line MAX SYSTEM OFFSET MAX SYSTEM OFFSET is triggered high from the rising edge of CAL (or the end of the IS 65% OF V IS 65% OF V REF REF write to the control register if calibration is initiated in soft- ware), and BUSY will go low when the full self-calibration is Figure 28. System Offset Calibration complete after a time t as shown in Figure 27. CAL Figure 29 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog t = 100ns MIN, 1 input range has been increased after the system gain calibration t = 2.5 t MAX, 15 CLKIN t = 125013 t is completed. A system full-scale voltage less than the reference CAL CLKIN t voltage may also be accounted for a by a system gain calibration. 1 (I/P) MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE t 15 IS 62.5% FROM V IS 62.5% FROM V REF REF SYS FULL S. BUSY (O/P) SYS FULL S. V – 1LSB V – 1LSB REF REF t CAL SYSTEM GAIN ANALOG ANALOG INPUT INPUT Figure 27. Timing Diagram for Full Self-Calibration RANGE RANGE CALIBRATION For the self-(gain + offset), self-offset and self-gain calibrations, AGND AGND the BUSY line will be triggered high by the rising edge of the CAL signal (or the end of the write to the control register if Figure 29. System Gain Calibration calibration is initiated in software) and will stay high for the full Finally in Figure 30 both the system offset and gain are ac- duration of the self-calibration. The length of time that the counted for by the system offset followed by a system gain cali- BUSY is high for will depend on the type of self-calibration that bration. First the analog input range is shifted upwards by the is initiated. Typical figures are given in Table IX. The timing positive system offset and then the analog input range is ad- diagrams for the other self-calibration options will be similar to justed at the top end to account for the system full scale. that outlined in Figure 27. System Calibration Description MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE System calibration allows the user to take out system errors IS 62.5% FROM V IS 62.5% FROM V REF REF external to the AD7853/AD7853L as well as calibrate the errors SYS F. S. V + SYS OFFSET REF SYS F.S. V – 1LSB of the AD7853/AD7853L itself. The maximum calibration REF V – 1LSB SYSTEM OFFSET REF CALIBRATION range for the system offset errors is –5% of V and for the REF FOLLOWED BY ANALOG system gain errors is –2.5% of V . This means that the maxi- REF ANALOG INPUT INPUT RANGE mum allowable system offset voltage applied between the RANGE SYSTEM GAIN AIN(+) and AIN(–) pins for the calibration to adjust out this CALIBRATION SYS OFFSET SYS OFFSET error is –0.05 · V (i.e., the AIN(+) can be 0.05 · V above REF REF AGND AGND AIN(–) or 0.05 · V below AIN(–)). For the system gain error REF MAX SYSTEM OFFSET MAX SYSTEM OFFSET the maximum allowable system full-scale voltage, in unipolar IS 65% OF V IS 65% OF V REF REF mode, that can be applied between AIN(+) and AIN(–) for the Figure 30. System (Gain + Offset) Calibration calibration to adjust out this error is V – 0.025 · V (i.e., REF REF the AIN(+) can be V + 0.025 · V above AIN(–) or V – REF REF REF 0.025 · V above AIN(–)). If the system offset or system gain REF REV. B –21– AD7853/AD7853L System Gain and Offset Interaction complete. Next the system offset voltage is applied to the AIN The inherent architecture of the AD7853/AD7853L leads to an pin for a minimum setup time (t ) of 100 ns before the SETUP interaction between the system offset and gain errors when a rising edge of the CONVST and remain until the BUSY signal system calibration is performed. Therefore it is recommended to goes low. The rising edge of the CONVST starts the system perform the cycle of a system offset calibration followed by a offset calibration section of the full system calibration and also system gain calibration twice. Separate system offset and system causes the BUSY signal to go high. The BUSY signal will go gain calibrations reduce the offset and gain errors to at least the low after a time t when the calibration sequence is complete. CAL2 12-bit level. By performing a system offset calibration first and a The timing for a system (gain + offset) calibration is very similar system gain calibration second, priority is given to reducing the to that of Figure 31, the only difference being that the time gain error to zero before reducing the offset error to zero. If the t will be replaced by a shorter time of the order of t as CAL1 CAL2 system errors are small, a system offset calibration would be the internal DAC will not be calibrated. The BUSY signal will performed, followed by a system gain calibration. If the systems signify when the gain calibration is finished and when the part is errors are large (close to the specified limits of the calibration ready for the offset calibration. range), this cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 12-bit level. t = 100ns MIN, t = 50/90ns MIN 5V/3V, 1 14 The advantage of doing separate system offset and system gain t = 2.5 t MAX, t = 111114 t MAX, 15 CLKIN CAL1 CLKIN t = 13899 t calibrations is that the user has more control over when the CAL2 CLKIN analog inputs need to be at the required levels, and the CONVST t 1 signal does not have to be used. (I/P) t Alternatively, a system (gain + offset) calibration can be per- 15 formed. It is recommended to perform three system (gain + BUSY (O/P) t t offset) calibrations to reduce the offset and gain errors to the CAL1 CAL2 t 16 12-bit level. For the system (gain + offset) calibration priority is (I/P) given to reducing the offset error to zero before reducing the t SETUP gain error to zero. Thus if the system errors are small then two V V system (gain + offset) calibrations will be sufficient. If the sys- AIN (I/P) SYSTEM FULL SCALE OFFSET tem errors are large (close to the specified limits of the calibra- tion range), three system (gain + offset) calibrations may be Figure 31. Timing Diagram for Full System Calibration required to reduced the offset and gain errors to at least the The timing diagram for a system offset or system gain calibra- 12-bit level. There will never be any need to perform more than tion is shown in Figure 32. Here again the CAL is pulsed and three system (offset + gain) calibrations. the rising edge of the CAL initiates the calibration sequence (or In Bipolar Mode the midscale error is adjusted for an offset the calibration can be initiated in software by writing to the calibration and the positive full-scale error is adjusted for the control register). The rising edge of the CAL causes the BUSY gain calibration; in Unipolar Mode the zero-scale error is ad- line to go high and it will stay high until the calibration sequence is justed for an offset calibration and the positive full-scale error is finished. The analog input should be set at the correct level for a adjusted for a gain calibration. minimum setup time (t ) of 100 ns before the rising edge of SETUP CAL and stay at the correct level until the BUSY signal goes System Calibration Timing low. The calibration timing diagram in Figure 31 is for a full system calibration where the falling edge of CAL initiates an internal t 1 reset before starting a calibration (note that if the part is in power- (I/P) down mode the CAL pulsewidth must take account of the power-up t 15 time). If a full system calibration is to be performed in software, BUSY (O/P) it is easier to perform separate gain and offset calibrations so that the CONVST bit in the control register does not have to be t CAL2 t SETUP programmed in the middle of the system calibration sequence. AIN (I/P) V OR V The rising edge of CAL starts calibration of the internal DAC SYSTEM FULL SCALE SYSTEM OFFSET and causes the BUSY line to go high. If the control register is set for a full system calibration, the CONVST must be used Figure 32. Timing Diagram for System Gain or System also. The full-scale system voltage should be applied to the Offset Calibration analog input pins from the start of calibration. The BUSY line will go low once the DAC and system gain calibration are –22– REV. B AD7853/AD7853L SERIAL INTERFACE SUMMARY SCLK and SYNC signals (SYNC may be hardwired low) are Table IX details the five interface modes and the serial clock required for Interfaces Modes 1, 2, and 3. In Interface Modes 4 edges from which the data is clocked out by the AD7853/ and 5, the AD7853/AD7853L generates the SCLK and SYNC. AD7853L (DOUT Edge) and that the data is latched in on Some of the more popular mProcessors, mControllers, and the (DIN Edge). The logic level of the POLARITY pin is shown DSP machines that the AD7853/AD7853L will interface to and it is clear that this reverses the edges. directly are mentioned here. This does not cover all mCs, mPs In Interface Modes 4 and 5 the SYNC always clocks out the and DSPs. The interface mode of the AD7853/AD7853L that is first data bit and SCLK will clock out the subsequent bits. mentioned here for a specific mC, mP, or DSP is only a guide and in most cases another interface mode may work just as well. In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK and the POLARITY pin. Thus the SYNC may clock out A more detailed timing description on each of the interface the MSB of data. Subsequent bits will be clocked out by the modes follows. serial clock, SCLK. The conditions for the SYNC clocking out the MSB of data is as follows: Table X. Interface Mode Description With the POLARITY pin high the falling edge of SYNC will clock SM1 SM2 mProcessor/ Interface out the MSB if the serial clock is low when the SYNC goes low. Pin Pin mController Mode With the POLARITY pin low the falling edge of SYNC will clock 0 0 8XC51 1 (2-Wire) out the MSB if the serial clock is high when the SYNC goes low. 8XL51 (DIN is an Input/ PIC17C42 Output pin) Table IX. SCLK Active Edge for Different Interface Modes 0 0 68HC11 2 (3-Wire, SPI/QSPI) Interface POLARITY DOUT DIN 68L11 (Default Mode) Mode Pin Edge Edge 0 1 68HC16 3 (QSPI) 1, 2, 3 0 SCLK›SCLKflPIC16C64 (External Serial 1 SCLKflSCLK›ADSP-21xx Clock, SCLK, and DSP56000 External Frame Sync, 4, 5 0 SCLKflSCLK› DSP56001 SYNC, are required) 1 SCLK›SCLKfl DSP56002 DSP56L002 Resetting the Serial Interface TMS320C30 When writing to the part via the DIN line there is the possibility of writing data into the incorrect registers, such as the test regis- 1 0 68HC16 4 (DSP is Slave) ter for instance, or writing the incorrect data and corrupting the (AD7853/AD7853L serial interface. The SYNC pin acts as a reset. Bringing the generates a SYNC pin high resets the internal shift register. The first data noncontinuous bit after the next SYNC falling edge will now be the first bit of a [16 clocks] Serial new 16-bit transfer. It is also possible that the test register con- Clock, SCLK, and the tents were altered when the interface was lost. Therefore, once Frame Sync, SYNC) the serial interface is reset, it may be necessary to write the 16- 1 1 ADSP-21xx 5 (DSP is Slave) bit word 0100 0000 0000 0010 to restore the test register to its DSP56000 (AD7853/AD7853L default value. Now the part and serial interface are completely DSP56001 generates a reset. It is always useful to retain the ability to program the DSP56002 continuous Serial SYNC line from a port of the mController/DSP to have the DSP56L002 Clock, SCLK, and the ability to reset the serial interface. TMS320C20 Frame Sync, SYNC) Table X summarizes the interface modes provided by the TMS320C25 AD7853/AD7853L. It also outlines the various mP/mC to which TMS320C30 the particular interface is suited. TMS320C5x The interface mode is determined by the serial mode selection TMS320LC5x pins SM1 and SM2. Interface Mode 2 is the default mode. Note that Interface Mode 1 and 2 have the same combination of SM1 and SM2. Interface Mode 1 may only be set by programming the control register (see section on control register). External REV. B –23– AD7853/AD7853L DETAILED TIMING SECTION can be used provided that the SYNC is low for only 16 clock Mode 1 (2-Wire 8051 Interface) pulses in each of the read and write cycles. The POLARITY pin The read and writing takes place on the DIN line and the con- may be used to change the SCLK edge which the data is sampled version is initiated by pulsing the CONVST pin (note that in on and clocked out on. every write cycle the 2/3 Mode bit must be set to 1). The con- In Figure 34 the SYNC line is tied low permanently and this version may be started by setting the CONVST bit in the con- results in a different timing arrangement. With SYNC tied low trol register to 1 instead of using the CONVST line. permanently the DIN pin will never be three-stated. The 16th Below in Figure 33 and in Figure 34 are the timing diagrams for rising edge of SCLK configures the DIN pin as an input or an Interface Mode 1 in Table X where we are in the 2-wire inter- output as shown in the diagram. Here no more than 16 SCLK face mode. Here the DIN pin is used for both input and output pulses must occur for each of the read and write operations. as shown. The SYNC input is level triggered active low and can If reading from and writing to the calibration registers in this be pulsed (Figure 33) or can be constantly low (Figure 34). interface mode, all the selected calibration registers must be In Figure 33 the part samples the input data on the rising edge read from or written to. The read and write operations cannot of SCLK. After the 16th rising edge of SCLK the DIN is con- be aborted. When reading from the calibration registers, the figured as an output. When the SYNC is taken high the DIN is DIN pin will remain as an output for the full duration of all the three-stated. Taking SYNC low disables the three-state on the calibration register read operations. When writing to the calibra- DIN pin and the first SCLK falling edge clocks out the first data tion registers, the DIN pin will remain as an input for the full bit. Once the 16 clocks have been provided the DIN pin will duration of all the calibration register write operations. automatically revert back to an input after a time t . Note that a 14 continuous SCLK shown by the dotted waveform in Figure 33 t = –0.4 t MIN (NONCONTINUOUS SCLK) –/+0.4 t MIN/MAX (CONTINUOUS SCLK), 3 SCLK SCLK POLARITY PIN t = 75/115 MAX (5V/3V), t = 40/60ns MIN (5V/3V), t = 20/30 MIN (5V/3V) 6 7 8 LOGIC HIGH SYNC (I/P) t t t t 3 11 3 11 SCLK (I/P) 116 1 16 t t t 14 7 5A t 12 t t t 8 6 6 DB15 DB0 DB15 DB0 DIN (I/O) THREE-STATE DATA WRITE DATA READ DIN BECOMES AN OUTPUT DIN BECOMES AN INPUT Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0) t = 75/115 MAX (5V/3V), t = 40/60ns MIN (5V/3V), t = 20/30 MIN (5V/3V), 6 7 8 t = 90/130 MAX (5V/3V), t = 50/90ns MAX (5V/3V) 13 14 POLARITY PIN LOGIC HIGH SCLK (I/P) 116 1 616 t 14 t 7 t t t t 8 13 6 6 DIN (I/O) DB0 DB15 DB0 DB15 DATA WRITE DATA READ DIN BECOMES AN INPUT Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low (i.e., Interface Mode 1, SM1 = SM2 = 0) –24– REV. B AD7853/AD7853L Mode 2 (3-Wire SPI/QSPI Interface Mode) high after the 16th SCLK rising edge as shown by the dotted This is the DEFAULT INTERFACE MODE. SYNC line in Figure 36. Thus a frame sync that gives a high In Figure 35 below we have the timing diagram for Interface pulse, of one SCLK cycle minimum duration, at the beginning Mode 2 which is the SPI/QSPI interface mode. Here the SYNC of the read/write operation may be used. The rising edge of input is active low and may be pulsed or tied permanently low. SYNC enables the three-state on the DOUT pin. The falling If SYNC is permanently low 16 clock pulses must be applied to edge of SYNC disables the three-state on the DOUT pin, and the SCLK pin for the part to operate correctly, and with a data is clocked out on the falling edge of SCLK. Once SYNC pulsed SYNC input a continuous SCLK may be applied provided goes high, the three-state on the DOUT pin is enabled. The SYNC is low for only 16 SCLK cycles. In Figure 30 the SYNC data input is sampled on the rising edge of SCLK and thus has going low disables the three-state on the DOUT pin. The first to be valid a time, t , before this rising edge. The POLARITY 7 falling edge of the SCLK after the SYNC going low clocks out pin may be used to change the SCLK edge which the data is the first leading zero on the DOUT pin. The DOUT pin is sampled on and clocked out on. If resetting the interface is three-stated again a time t after the SYNC goes high. With the 12 required, the SYNC must be taken high and then low. DIN pin the data input has to be set up a time, t , before the 7 Modes 4 and 5 (Self-Clocking Modes) SCLK rising edge as the part samples the input data on the The timing diagrams in Figure 38 and Figure 39 are for Inter- SCLK rising edge in this case. The POLARITY pin may be face Modes 4 and 5. Interface Mode 4 has a noncontinuous used to change the SCLK edge which the data is sampled on SCLK output and Interface Mode 5 has a continuous SCLK and clocked out on. If resetting the interface is required, the output. These modes of operation are especially different to all SYNC must be taken high and then low. the other modes since the SCLK and SYNC are outputs. The Mode 3 (QSPI Interface Mode) SYNC is generated by the part as is the SCLK. The master Figure 36 shows the timing diagram for Interface Mode 3. In clock at the CLKIN pin is routed directly to the SCLK pin for this mode the DSP is the master and the part is the slave. Here Interface Mode 5 (Continuous SCLK) and the CLKIN signal is the SYNC input is edge triggered from high to low, and the 16 gated with the SYNC to give the SCLK (noncontinuous) for clock pulses are counted from this edge. Since the clock pulses Interface Mode 4. are counted internally then the SYNC signal does not have to go t = –0.4 t MIN (NONCONTINUOUS SCLK) –/+0.4 t MIN/MAX (CONTINUOUS SCLK), 3 CLKIN SCLK t = 75/115 MAX (5V/3V), t = 40/60ns MIN (5V/3V), t = 20/30 MIN (5V/3V), 6 7 8 POLARITY PIN t = 20/30 MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4 t = ns MIN/MAX (CONTINUOUS SCLK) (5V/3V) 11 SCLK LOGIC HIGH SYNC (I/P) t t 3 t 11 9 16 23 4 5 16 SCLK (I/P) t t t 5 10 12 t t 6 6 THREE- THREE- DB15 DB14 DB13 DB12 DB11 DB10 DB0 DOUT (O/P) STATE STATE t 7 t 8 t 8 DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and SYNC Input (SM1 = SM2 = 0) t = –0.4 t MIN (NONCONTINUOUS SCLK) –/+0.4 t MIN/MAX (CONTINUOUS SCLK), 3 CLKIN SCLK t = 75/115 MAX (5V/3V), t = 40/60ns MIN (5V/3V), t = 20/30 MIN (5V/3V), 6 7 8 POLAR PIN t = 20/30 MIN (5V/3V) 11 LOGIC HIGHITY SYNC (I/P) t t t 11 3 9 16 23 4 5 16 SCLK (I/P) t t t 5 10 12 t t 6 6 THREE- THREE- DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 STATE STATE t 7 t 8 t 8 DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1) REV. B –25– AD7853/AD7853L data on the DIN pin is also clocked in to the AD7853/AD7853L The most important point about these two modes of operation by the same SCLK for the next conversion. The read/write mode is that the result of the current conversion is clocked operations must be complete after sixteen clock cycles (which out during the same conversion and a write to the part dur- takes 4.6ms approximately from the rising edge of CONVST assum- ing this conversion is for the next conversion. The arrangement ing a 4 MHz CLKIN). At this time the conversion will be com- is shown in Figure 37. Figure 38 and Figure 39 show more plete, the SYNC will go high, and the BUSY will go low. The detailed timing for the arrangement of Figure 37. next falling edge of the CONVST must occur at least 400 ns THE CONVERSION RESULT DUE TO after the falling edge of BUSY to allow the track/hold amplifier WRITE N+1 IS READ HERE adequate acquisition time as shown in Figure 38. This gives a WRITE N+1 WRITE N+2 WRITE N+3 throughput time of 5 ms. The maximum throughput rate in this case is 200 kHz (AD7853) and 100 kHz (AD7853L). READ N+1 READ N+2 READ N In these interface modes the part is now the master and the DSP is the slave. Figure 39 is an expansion of Figure 38. The CONVERSION N CONVERSION N+1 CONVERSION N+2 AD7853/AD7853L will ensure SYNC goes low after the rising 5ms 5ms 5ms edge C of the continuous SCLK (Interface Mode 5) in Figure 39. Only in the case of a noncontinuous SCLK (Interface Mode Figure 37. 4) will the time t apply. The first data bit is clocked out from 4 the falling edge of SYNC. The SCLK rising edge clocks out all OUTPUT SERIAL SHIFT subsequent bits on the DOUT pin. The input data present on REGISTER IS RESET the DIN pin is clocked in on the rising edge of the SCLK. The t 1 CONVST POLARITY pin may be used to change the SCLK edge which (I/P) the data is sampled on and clocked out on. The SYNC will go high after the 16th SCLK rising edge and before the falling edge BUSY (O/P) D of the continuous SCLK in Figure 39. This ensures the part will not clock in an extra bit from the DIN pin or clock out an SYNC (O/P) extra bit on the DOUT pin. If the user has control of the CONVST pin but does not want to SCLK (O/P) exercise it for every conversion, the control register may be used to start a conversion. Setting the CONVST bit in the control t = 4.6ms CONVERT 400ns MIN register to 1 starts a conversion. If the user does not have con- CONVERSION IS INITIATED SERIAL READ READ OPERATION trol of the CONVST pin, a conversion should not be initiated AND TRACK/HOLD GOES AND WRITE SHOULD END 500ns INTO HOLD OPERATIONS PRIOR TO NEXT RISING by writing to the control register. The reason for this is that the EDGE OF CONVST CONVERSION ENDS user may get “locked out” and not be able to perform any fur- t = 100ns MIN 1 4.6ms LATER ther write/read operations. When a conversion is started by Figure 38. Mode 4, 5 Timing Diagram (SM1 = 1, SM2 = 1 writing to the control register, the SYNC goes low and read/ and 0) write operations take place while the conversion is in progress. In Figure 38 the first point to note is that the BUSY, SYNC, However, once the conversion is complete, there is no way of and SCLK are all outputs from the AD7853/AD7853L with the writing to the part unless the CONVST pin is exercised. The CONVST being the only input signal. Conversion is initiated CONVST signal triggers the SYNC signal low which allows with the CONVST signal going low. This CONVST falling read/write operations to take place. SYNC must be low to per- edge also triggers the BUSY to go high. The CONVST signal form read/write operations. The SYNC is triggered low by the rising edge triggers the SYNC to go low after a short delay CONVST signal rising edge or setting the CONVST bit in the (0.5 t to 1.5 t typically) after which the SCLK will CLKIN CLKIN control register to 1. Therefore if there is not full control of the clock out the data on the DOUT pin during conversion. The CONVST pin the user may end up getting “locked out.” t = 0.6t (NONCONTINUOUS SCLK), t = 75/115 MAX (5V/3V), 4 SCLK 6 t = 40/60ns MIN (5V/3V), t = 20/30 MIN (5V/3V), t = 50ns MAX POLARITY PIN 7 8 11A LOGIC HIGH SYNC (O/P) C D t t t 4 9 11A SCLK (O/P) 1 23 4 5 6 16 t t 10 12 t 5 t 6 THREE- THREE- DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 STATE STATE t 7 t t 8 8 DB15 DIN (I/P) DB14 DB13 DB12 DB11 DB10 DB0 Figure 39. Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and Noncontinuous) (i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0) –26– REV. B AD7853/AD7853L CONFIGURING THE AD7853/AD7853L In this case there is no writing to the on-chip registers and only AD7853/AD7853L as a Read-Only ADC the conversion result data is read from the part. Interface Mode The AD7853/AD7853L contains fourteen on-chip registers 1 cannot be used in this case as it is necessary to write to the which can be accessed via the serial interface. In the majority of control register to set Interface Mode 1. Here the CLKIN signal applications it will not be necessary to access all of these regis- is applied directly after power-on, the CLKIN signal must be ters. Figure 38 outlines a flowchart of the sequence which is present to allow the part to perform a calibration. This auto- used to configure the AD7853/AD7853L as a Read-Only ADC. matic calibration will be completed approximately 32 ms after the AD7853 has powered up (4 MHz CLK). START DIN CONNECTED TO DGND POWER-ON, APPLY CLKIN SIGNAL, WAIT FOR AUTOMATIC CALIBRATION SERIAL 4, 5 INTERFACE MODE ? 2, 3 PULSE CONVST PIN PULSE CONVST PIN READ DATA YES DURING CONVERSION SYNC AUTOMATICALLY GOES LOW ? AFTER CONVST RISING EDGE NO WAIT APPROXIMATLY 200ns AFTER CONVST RISING EDGE WAIT FOR BUSY SIGNAL TO GO LOW SCLK AUTOMATICALLY ACTIVE, READ CONVERSION RESULT ON DOUT PIN APPLY SYNC (IF REQUIRED), SCLK AND READ CONVERSION RESULT ON DOUT PIN Figure 40. Flowchart for Setting Up and Reading from the AD7853/AD7853L REV. B –27– AD7853/AD7853L Writing to the AD7853/AD7853L equal to a Logic 0, to indicate the end of conversion, the user in For accessing the on-chip registers it is necessary to write to the this case would poll the BUSY bit in the status register. part. To enable Serial Interface Mode 1, the user must also Interface Modes 2 and 3 Configuration write to the part. Figure 41 through 43 outline flowcharts of Figure 41 shows the flowchart for configuring the part in Inter- how to configure the AD7853/AD7853L for each of the differ- face Modes 2 and 3. For these interface modes, the read and ent serial interface modes. The continuous loops on all diagrams write operations take place simultaneously via the serial port. indicate the sequence for more than one conversion. The options Writing all 0s ensures that no valid data is written to any of the of using a hardware (pulsing the CONVST pin) or software registers. When using the software conversion start and transfer- (setting the CONVST bit to 1) conversion start, and reading/ ring data during conversion, Note must be obeyed. writing during or after conversion are shown in Figures 41 and 42. If the CONVST pin is never used then it should be tied to DV permanently. Where reference is made to the BUSY bit DD START POWER-ON, APPLY CLKIN SIGNAL, WAIT FOR AUTOMATIC CALIBRATION SERIAL NOTE: INTERFACE WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING MODE DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL ? REGISTER WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE 2, 3 NEXT CONVERSION. INITIATE CONVERSION YES IN SOFTWARE ? NO TRANSFER YES PULSE CONVST PIN DATA DURING CONVERSION APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS NO CONVERSION RESULT ON DOUT PIN (SEE NOTE) TRANSFER YES DATA DURING CONVERSION APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL ? REGISTER SETTING CONVST BIT TO 1, READ CURRENT CONVERSION RESULT ON DOUT PIN WAIT APPROXIMATLY 200ns AFTER CONVST RISING EDGE NO WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 APPLY SYNC (IF REQUIRED), SCLK, READ PREVIOUS CONVERSION RESULT ON DOUT PIN, AND WRITE ALL 0s ON DIN PIN APPLY SYNC (IF REQUIRED), SCLK, READ CURRENT CONVERSION RESULT ON DOUT PIN, AND WRITE ALL 0s ON DIN PIN Figure 41. Flowchart for Setting Up, Reading and Writing in Interface Modes 2 and 3 –28– REV. B AD7853/AD7853L Interface Modes 4 and 5 Configuration Interface Mode 1 Configuration Figure 43 shows the flowchart for configuring the AD7853/ Figure 42 shows the flowchart for configuring the part in AD7853L in Interface Modes 4 and 5, the self-clocking modes. Interface Mode 1. This mode of operation can only enabled by In this case it is not recommended to use the software conver- writing to the control register and setting the 2/3 MODE bit. sion start option. The read and write operations always occur Reading and writing cannot take place simultaneously in this simultaneously and during conversion. mode as the DIN pin is used for both reading and writing. START START POWER-ON, APPLY CLKIN SIGNAL, POWER-ON, APPLY CLKIN SIGNAL, WAIT 150ms FOR AUTOMATIC CALIBRATION WAIT 150ms FOR AUTOMATIC CALIBRATION SERIAL SERIAL INTERFACE INTERFACE MODE MODE ? ? 4, 5 1 PULSE PIN INITIATE YES CONVERSION IN SOFTWARE AUTOMATICALLY GOES ? LOW AFTER RISING EDGE NO APPLY (IF REQUIRED), SCLK AUTOMATICALLY ACTIVE, READ CURRENT APPLY (IF REQUIRED), SCLK, WRITE TO CONTROL REGISTER CONVERSION RESULT ON DOUT PIN, WRITE SCLK, WRITE TO CONTROL REGISTER SETTING THE TWO-WIRE MODE TO CONTROL REGISTER ON DIN PIN SETTING THE TWO-WIRE MODE AND CONVST BIT TO 1 PULSE PIN Figure 43. Flowchart for Setting Up, Reading and Writing in Interface Modes 4 and 5 READ DATA YES DURING CONVERSION ? WAIT APPROXIMATLY 200ns AFTER RISING EDGE NO OR AFTER END OF CONTROL REGISTER WRITE WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 APPLY (IF REQUIRED), SCLK, READ PREVIOUS CONVERSION RESULT ON DIN PIN APPLY (IF REQUIRED), SCLK, READ CURRENT CONVERSION RESULT ON DIN PIN Figure 42. Flowchart for Setting Up, Reading and Writing in Interface Mode 1 REV. B –29– AD7853/AD7853L writing to the control register via the DIN line setting a conver- MICROPROCESSOR INTERFACING sion start and the 2-wire interface mode (this would be per- In many applications, the user may not require the facility of formed in two 8-bit writes), wait for the conversion to be writing to the on-chip registers. The user may just want to finished (4.5 ms with 4 MHz CLKIN), read the conversion re- hardwire the relevant pins to the appropriate levels and read the sult data on the DIN line (this would be performed in two 8-bit conversion result. In this case the DIN pin can be tied low so reads), and then repeat the sequence. The maximum serial that the on-chip registers are never used. Now the part will frequency will be determined by the data access and hold times operate as a nonprogrammable analog to digital converter where of the 8XC51/PIC16C42 and the AD7853/AD7853L. the CONVST is applied, a conversion is performed and the result may be read using the SCLK to clock out the data from OPTIONAL the output register on to the DOUT pin. Note that the DIN pin AD7853/AD7853L cannot be tied low when using the two-wire interface mode of 4MHz/1.8MHz CONVST (8XC51/L51) operation. /PIC17C42 CLKIN The SCLK can also be connected to the CLKIN pin if the user P3.1/CK SCLK does not want to have to provide separate serial and master MASTER clocks in Interface Modes 1, 2, and 3. With this arrangement P3.0/DT DIN SLAVE OPTIONAL the SYNC signal must be low for 16 SCLK cycles in Interface BUSY (INT0/P3.2)/INT Modes 1 and 2 for the read and write operations. For Interface SYNC Mode 3 the SYNC can be low for more than 16 SCLK cycles for the read and write operations. Note that in Interface Modes SM1 4 and 5 the CLKIN and SCLK cannot be tied together as the SM2 SCLK is an output and the CLKIN is an input. DV FOR 8XC51/L51 POLARITY DD DGND FOR PIC17C42 Figure 45. 8XC51/PIC17C42 Interface CONVERSION CONVST START AD7853/AD7853L to 68HC11/16/L11/PIC16C42 Interface 4 MHz/1.8MHz CLKIN MASTER Figure 46 shows the AD7853/AD7853L SPI/QSPI interface to CLOCK SCLK the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to AD7853/AD7853L SYNC SIGNAL the AD7853/AD7853L when the supply is at 3 V. The SYNC SYNC TO GATE line is not used and is tied to DGND. The mController is config- THE SCLK DIN ured as the master, by setting the MSTR bit in the SPCR to 1, and thus provides the serial clock on the SCK pin. For all the SERIAL DATA DOUT OUTPUT mControllers, the CPOL bit is set to 1 and for the 68HC11/16/ L11, the CPHA bit is set to 1. The CLKIN and CONVST signals can be supplied from the mController or from separate Figure 44. Simplified Interface Diagram with DIN sources. The BUSY signal can be used as an interrupt to tell the Grounded and SCLK Tied to CLKIN mController when the conversion is finished, then the reading AD7853/AD7853L to 8XC51/PIC17C42 Interface and writing can take place. If required the reading and writing Figure 45 shows the AD7853/AD7853L interface to the 8XC51/ can take place during conversion and there will be no need for PIC17C42. The 8XL51 is for interfacing to the AD7853/AD7853L the BUSY signal in this case. For no writing to the part then the when the supply is at 3 V. The 8XC51/PIC17C42 only run at DIN pin can be tied permanently low. For the 68HC16 and the 5 V. The 8XC51 is in Mode 0 operation. This is a two-wire QSPI interface the SM2 pin should be tied high and the SS line interface consisting of the SCLK and the DIN which acts as a tied to the SYNC pin. The microsequencer on the 68HC16 bidirectional line. The SYNC is tied low. The BUSY line can be QSPI port can be used for performing a number of read and used to give an interrupt driven system but this would not nor- write operations independent of the CPU and storing the con- mally be the case with the 8XC51/PIC17C42. For the 8XC51 version results in memory without taxing the CPU. The typical 12 MHz version, the serial clock will run at a maximum of sequence of events would be writing to the control register via 1 MHz so that the serial interface to the AD7853/AD7853L will the DIN line setting a conversion start and at the same time only be running at 1 MHz. The CLKIN signal must be provided reading data from the previous conversion on the DOUT line, separately to the AD7853/AD7853L from a port line on the wait for the conversion to be finished (4.5 ms with 4 MHz 8XC51 or from a source other than the 8XC51. Here the SCLK CLKIN), and then repeat the sequence. The maximum serial cannot be tied to the CLKIN as the 8XC51 only provides a frequency will be determined by the data access and hold times noncontinuous serial clock. The CONVST signal can be pro- of the mControllers and the AD7853/AD7853L. vided from an external timer or conversion can be started in software if required. The sequence of events would typically be –30– REV. B AD7853/AD7853L OPTIONAL of the DSP5600x would be for synchronous operation (SYN = AD7853/AD7853L 1), internal frame sync (SCD2 = 1), Internal clock (SCKD = 4MHz/1.8MHz CONVST 68HC11/L11/16 1), 16-bit word length (WL1 = 1, WL0 = 0), frames sync only DV CLKIN active at beginning of the transfer (FSL1 = 0, FSL0 = 1). A DD SPI HC16, QSPI gated clock can be used (GCK = 1) or if the SCLK is to be tied SS SYNC to the CLKIN of the AD7853/AD7853L, then there must be a SCK SCLK continuous clock (GCK = 0). Again the data access and hold MISO DOUT times of the DSP5600x and the AD7853/AD7853L should MASTER allow for an SCLK of 4 MHz/1.8 MHz. BUSY IRQ OPTIONAL SLAVE MOSI DIN OPTIONAL AD7853/AD7853L DIN AT DGND FOR SM1 4MHz/1.8MHz CONVST NO WRITING TO PART DSP DGND FOR HC11, SPI SM2 56000/1/2/L002 DV FOR HC16, QSPI CLKIN DD DV POLARITY DD SCK SCLK Figure 46. 68HC11 and 68HC16 Interface SRD DOUT AD7853/AD7853L to ADSP-21xx Interface SC2 SYNC MASTER OPTIONAL Figure 47 shows the AD7853/AD7853L interface to the ADSP- IRQ BUSY 21xx. The ADSP-21xx is the slave and the AD7853/AD7853L OPTIONAL SLAVE DIN STD is the master. The AD7853/AD7853L is in Interface Mode 5. For the ADSP-21xx, the bits in the serial port control register SM1 DIN AT DGND FOR should be set up as TFSR = RFSR = 1 (need a frame sync for NO WRITING TO PART SM2 DV DD every transfer), SLEN = 15 (16-bit word length), TFSW = POLARITY RFSW = 1 (alternate framing mode for transmit and receive operations), INVRFS = INVTFS = 1 (active low RFS and Figure 48. DSP56000/1/2 Interface TFS), IRFS = ITFS = 0 (External RFS and TFS), and ISCLK = 0 (external serial clock). The CLKIN and CONVST signals AD7853/AD7853L to TMS320C20/25/5x/LC5x Interface could be supplied from the ADSP-21xx or from an external Figure 49 shows the AD7853/AD7853L to the TMS320Cxx source. The AD7853/AD7853L supplies the SCLK and the interface. The TMS320LC5x is used when the AD7853/AD7853L SYNC signals to the ADSP-21xx and the reading and writing is being operated at 3 V. The AD7853/AD7853L is the master takes place during conversion. The BUSY signal only indicates and operates in Interface Mode 5. For the TMS320Cxx the when the conversion is finished and may not be required. The CLKX, CLKR, FSX, and FSR pins should all be configured as data access and hold times of the ADSP-21xx and the AD7853/ inputs. The CLKX and the CLKR should be connected to- AD7853L allows for a CLKIN of 4 MHz/1.8 MHz at both 5 V gether as should the FSX and FSR. Since the AD7853/AD7853L and 3 V supplies. is the master and the reading and writing occurs during the OPTIONAL conversion, the BUSY only indicates when the conversion is finished and thus may not be required. Again the data access 4MHz/1.8MHz CONVST and hold times of the TMS320Cxx and the AD7853/AD7853L ADSP-21xx allows for a CLKIN of 4 MHz/1.8 MHz. CLKIN SCK SCLK OPTIONAL AD7853/AD7853L DR DOUT 4MHz/1.8MHz CONVST RFS TMS320C20/ SYNC SLAVE 25/5x/LC5x CLKIN TFS CLKX AD7853/AD7853L OPTIONAL IRQ BUSY CLKR SCLK OPTIONAL DT DIN DR DOUT MASTER SM1 FSR SYNC SLAVE DIN AT DGND FOR NO WRITING TO PART FSX SM2 MASTER OPTIONAL INT0 BUSY POLARITY DV DD OPTIONAL DT DIN Figure 47. ADSP-21xx Interface SM1 AD7853/AD7853L to DSP56000/1/2/L002 Interface DIN AT DGND FOR NO WRITING TO PART Figure 48 shows the AD7853/AD7853L to DSP56000/1/2/L002 SM2 interface. Here the DSP5600x is the master and the AD7853/ POLARITY AD7853L is the slave. The AD7853/AD7853L is in Interface DV DD Mode 3. The DSP56L002 is used when the AD7853/AD7853L Figure 49. TMS320C20/25/5x Interface is being operated at 3 V. The setting of the bits in the registers REV. B –31– AD7853/AD7853L APPLICATION HINTS Good decoupling is also important. All analog supplies should Grounding and Layout be decoupled with 10␣mF tantalum in parallel with 0.1␣mF ca- The analog and digital supplies to the AD7853/AD7853L are pacitors to AGND. All digital supplies should have a 0.1␣mF disc independent and separately pinned out to minimize coupling ceramic capacitor to AGND. To achieve the best from these between the analog and digital sections of the device. The part decoupling components, they must be placed as close as pos- has very good immunity to noise on the power supplies as can sible to the device, ideally right up against the device. In systems be seen by the PSRR vs. Frequency graph. However, care where a common supply voltage is used to drive both the AV DD should still be taken with regard to grounding and layout. and DV of the AD7853/AD7853L, it is recommended that DD the system’s AV supply is used. In this case there should be a DD The printed circuit board that houses the AD7853/AD7853L 10 W resistor between the AV pin and DV pin. This supply DD DD should be designed such that the analog and digital sections are should have the recommended analog supply decoupling capaci- separated and confined to certain areas of the board. This facili- tors between the AV pin of the AD7853/AD7853L and DD tates the use of ground planes that can be separated easily. A AGND and the recommended digital supply decoupling ca- minimum etch technique is generally best for ground planes as it pacitor between the DV pin of the AD7853/AD7853L and DD gives the best shielding. Digital and analog ground planes DGND. should only be joined in one place. If the AD7853/AD7853L is the only device requiring an AGND to DGND connection, then Evaluating the AD7853/AD7853L Performance the ground planes should be connected at the AGND and The recommended layout for the AD7853/AD7853L is outlined DGND pins of the AD7853/AD7853L. If the AD7853/AD7853L in the evaluation board for the AD7853/AD7853L. The evalua- is in a system where multiple devices require AGND to DGND tion board package includes a fully assembled and tested evalua- connections, the connection should still be made at one point tion board, documentation, and software for controlling the only, a star ground point which should be established as close as board from the PC via the EVAL-CONTROL BOARD. The possible to the AD7853/AD7853L. EVAL-CONTROL BOARD can be used in conjunction with the AD7853/AD7853L evaluation board, as well as many other Avoid running digital lines under the device as these will couple Analog Devices evaluation boards ending in the CB designator, noise onto the die. The analog ground plane should be allowed to demonstrate/evaluate the ac and dc performance of the to run under the AD7853/AD7853L to avoid noise coupling. AD7853/AD7853L. The power supply lines to the AD7853/AD7853L should use as large a trace as possible to provide low impedance paths and The software allows the user to perform ac (fast Fourier trans- reduce the effects of glitches on the power supply line. Fast form) and dc (histogram of codes) tests on the AD7853/AD7853L. switching signals like clocks should be shielded with digital It also gives full access to all the AD7853/AD7853L on-chip ground to avoid radiating noise to other sections of the board registers allowing for various calibration and power-down op- and clock signals should never be run near the analog inputs. tions to be programmed. Avoid crossover of digital and analog signals. Traces on opposite AD785x Family sides of the board should run at right angles to each other. This All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V. will reduce the effects of feedthrough through the board. A AD7853 – Single Channel Serial microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component AD7854 – Single Channel Parallel side of the board is dedicated to ground planes while signals are AD7858 – Eight Channel Serial placed on the solder side. AD7859 – Eight Channel Parallel –32– REV. B AD7853/AD7853L PAGE INDEX Topic Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 23 PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 DETAILED TIMING SECTION . . . . . . . . . . . . . . . . . . . 24 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 25 TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5 Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 25 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 Modes 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 25 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 CONFIGURING THE AD7853/AD7853L . . . . . . . . . . . . 27 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AD7853/AD7853L as a Read-Only ADC . . . . . . . . . . . . 27 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 Writing to the AD7853/AD7853L . . . . . . . . . . . . . . . . . . 28 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29 Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9 Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 30 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AD7853/AD7853L to 8XC51/PIC17C42 Interface . . . . . 30 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AD7853/AD7853L to 68HC11/16/L11/PIC16C42 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 12 AD7853/AD7853L to ADSP-21xx Interface . . . . . . . . . . 31 Addressing the Calibration Registers . . . . . . . . . . . . . . . . 12 AD7853/AD7853L to DSP56000/1/2/L002 Interface . . . 31 Writing to/Reading from the Calibration Registers . . . . . . 12 AD7853/AD7853L to TMS320C20/25/5x/LC5x Adjusting the Offset Calibration Register . . . . . . . . . . . . . 13 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 13 APPLICATION HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 14 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Evaluating the AD7853/AD7853L Performance . . . . . . . 32 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34 ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE INDEX Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 # Title Page DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I. Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . 9 Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 II. Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 III. Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . 10 REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IV. Calibrating Register Addressing . . . . . . . . . . . . . . . . . 12 PERFORMANCE CURVES . . . . . . . . . . . . . . . . . . . . . . . . 17 V. Analog Input Connections . . . . . . . . . . . . . . . . . . . . . 16 POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18 VI. Power Management Options . . . . . . . . . . . . . . . . . . . 19 POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VII. Power Consumption vs. Throughput . . . . . . . . . . . . . 20 Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19 VIII. Calibration Times . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19 IX. SCLK Active Edge for Different Interface Modes . . . 23 POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20 X. Interface Mode Description . . . . . . . . . . . . . . . . . . . . 23 CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20 Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20 Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 System Calibration Description . . . . . . . . . . . . . . . . . . . . 21 System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22 REV. B –33– AD7853/AD7853L OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 13 24 PIN 1 0.260 – 0.001 (6.61 – 0.03) 1 12 1.228 (31.19) 0.32 (8.128) 1.226 (31.14) 0.30 (7.62) 0.130 (3.30) 0.128 (3.25) SEATING 15° 0.011 (0.28) PLANE 0 0.009 (0.23) 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 0.016 (0.41) 0.09 (2.28) 0.05 (1.27) NOTES 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 24-Lead Small Outline Package (R-24) 24 13 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) PIN 1 0.398 (10.10) 12 1 0.096 (2.44) 0.608 (15.45) 0.089 (2.26) 0.596 (15.13) 0.03 (0.76) 0.02 (0.51) 0.042 (1.067) 6° 0.01 (0.254) 0° 0.018 (0.447) 0.05 (1.27) 0.019 (0.49) 0.013 (0.32) 0.006 (0.15) BSC 0.014 (0.35) 0.009 (0.23) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 24-Lead Shrink Small Outline Package (RS-24) 24 13 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) PIN 1 1 12 0.07 (1.78) 0.328 (8.33) 0.066 (1.67) 0.318 (8.08) 0.037 (0.94) 8° 0.022 (0.559) 0° 0.008 (0.203) 0.0256 (0.65) 0.009 (0.229) 0.002 (0.050) BSC 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS –34– REV. B PRINTED IN U.S.A. C2024b–2.5–11/98