ANALOG DEVICES AD7851

14-Bit 333 kSPS a Serial A/D Converter AD7851 FUNCTIONAL BLOCK DIAGRAM FEATURES Single 5 V Supply AV AGND AGND DD 333 kSPS Throughput Rate/�2 LSB DNL—A Grade 285 kSPS Throughput Rate/�1 LSB DNL—K Grade AIN (+) DV DD T/H A and K Grades Guaranteed to 125�C/238 kSPS AIN (–) AD7851 DGND Throughput Rate 4.096V Pseudo-Differential Input with Two Input Ranges REFERENCE System and Self-Calibration with Autocalibration on REF / Power-Up IN BUF COMP REF OUT Read/Write Capability of Calibration Data AMODE Low Power: 60 mW Typ Power-Down Mode: 5 �W Typ Power Consumption ® Flexible Serial Interface: 8051/SPI /QSPI™/�P Compatible CLKIN C CHARGE REF1 REDISTRIBUTION 24-Lead PDIP, SOIC, and SSOP Packages CONVST DAC SAR + ADC CONTROL C BUSY REF2 APPLICATIONS SLEEP Digital Signal Processing CALIBRATION CAL MEMORY Speech Recognition and Synthesis AND CONTROLLER Spectrum Analysis DSP Servo Control Instrumentation and Control Systems SERIAL INTERFACE/CONTROL REGISTER High Speed Modems Automotive SM1 SM2 SYNC DIN DOUT SCLK POLARITY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7851 is a high speed, 14-bit ADC that operates from a 1. Single 5 V supply. single 5 V power supply. The ADC powers up with a set of default 2. Operates with reference voltages from 4 V to V . DD conditions at which time it can be operated as a read-only ADC. 3. Analog input ranges from 0 V to V . DD The ADC contains self-calibration and system calibration options 4. System and self-calibration including power-down mode. to ensure accurate operation over time and temperature and has a 5. Versatile serial I/O port. number of power-down options for low power applications. The AD7851 is capable of a 333 kHz throughput rate. The input track-and-hold acquires a signal in 0.33 µs and features a pseudo-differential sampling scheme. The AD7851 has the added advantage of two input voltage ranges (0 V to V and REF –V /2 to +V /2 centered about V /2). Input signal REF REF REF range is to V and the part is capable of converting full DD power signals to 20 MHz. CMOS construction ensures low power dissipation (60 mW typ) with power-down mode (5 µW typ). The part is available in a 24-lead, 0.3 inch-wide PDIP, a 24-lead SOIC, and a 24-lead SSOP package. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD7851 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 21 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 21 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5 Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 6 System Calibration Description . . . . . . . . . . . . . . . . . . . . 22 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 7 System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 23 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 23 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 24 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 24 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 DETAILED TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AD7851 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . 10 Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 25 Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . 10 Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 26 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 26 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 27 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 28 CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 13 AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 28 Addressing the Calibration Registers . . . . . . . . . . . . . . . . 13 Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Writing to/Reading from the Calibration Registers . . . . . . 13 Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 29 Adjusting the Offset Calibration Register . . . . . . . . . . . . . 14 Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 30 Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 14 Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 30 CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 15 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 31 CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AD7851 to 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . 31 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15 AD7851 to 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 31 ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AD7851 to ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . 32 Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AD7851 to DSP56000/1/2/L002 Interface . . . . . . . . . . . . . 32 DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AD7851 to TMS320C20/25/5x/LC5x Interface . . . . . . . . . 32 Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 33 AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 18 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34 POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 19 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 20 Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 20 POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20 REV. B –2– AD7851 1, 2 SPECIFICATIONS A Grade: f = 7 MHz (–40�C to +85�C), f = 333 kHz; K Grade: f = 6 MHz (0�C to 85�C), f = 285 kHz; A and K Grade: f = 5 MHz CLKIN SAMPLE CLKIN SAMPLE CLKIN (to 125�C), f = 238 kHz; (AV = DV = 5.0 V � 5%, REF /REF = 4.096 V External Reference; SLEEP = Logic High; T = T to T , SAMPLE DD DD IN OUT A MIN MAX unless otherwise noted.) 1 1 Parameter Version A Version K Unit Test Conditions/Comments DYNAMIC PERFORMANCE 3 Signal-to-Noise + Distortion Ratio (SNR) 77 78 dB min Typically SNR Is 79.5 dB. V = 10 kHz, Sine Wave, f = 333 kHz. IN SAMPLE Total Harmonic Distortion (THD) –86 –86 dB max V = 10 kHz, Sine Wave, f = 333 kHz, IN SAMPLE typically –96 dB. Peak Harmonic or Spurious Noise –87 –87 dB max V = 10 kHz, f = 333 kHz. IN SAMPLE Intermodulation Distortion (IMD) Second-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 333 kHz. SAMPLE Third-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f = 333 kHz. SAMPLE Full Power Bandwidth 20 20 MHz typ @ 3 dB. DC ACCURACY Resolution 14 14 Bits Integral Nonlinearity ±2 ±1 LSB max Differential Nonlinearity ±2 ±1 LSB max Guaranteed No Missed Codes to 14 Bits Unipolar Offset Error ±10 ±10 LSB max Review: Adjusting the Offset Calibration Positive Full-Scale Error ±10 ±10 LSB max Register in the Calibration Registers section. Negative Full-Scale Error ±10 ±10 LSB typ Bipolar Zero Error ±1 ±1 LSB typ ANALOG INPUT Input Voltage Ranges 0 V to V 0 V to V V AIN(+) – AIN(–) = 0 V to V , AIN(–) can be REF REF REF biased up but AIN(+) cannot go below AIN(–). ±V /2 ±V /2 V AIN(+) – AIN(–) = –V /2 to +V /2, AIN(–) REF REF REF REF should be biased up and AIN(+) can go below AIN(–) but cannot go below 0 V. Leakage Current ±1 ±1 µA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REF Input Voltage Range 4/V 4/V V min/max Functional from 1.2 V. IN DD DD Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node. REF Output Voltage 3.696/4.496 3.696/4.496 V min/max OUT REF Temperature Coefficient 50 50 ppm/°C typ OUT LOGIC INPUTS Input High Voltage, V V – 1.0 V – 1.0 V min INH DD DD Input Low Voltage, V 0.4 0.4 V max INL Input Current, I ±10 ±10 µA max V = 0 V or V . IN IN DD 4 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V – 0.4 V – 0.4 V min I = 200 µA. OH DD DD SOURCE Output Low Voltage, V 0.4 0.4 V max I = 0.8 mA. OL SINK Floating State Leakage Current ±10 ±10 µA max 4 Floating State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range. Twos Complement Bipolar Input Range. CONVERSION RATE Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles. Conversion + Track-and-Hold Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate. REV. B –3– AD7851 1 1 Parameter Version A Version K Unit Test Conditions/Comments POWER PERFORMANCE AV DV 4.75/5.25 4.75/5.25 V min/max DD, DD I DD 4 Normal Mode 17 17 mA max AV = DV = 4.75 V to 5.25 V. Typically DD DD 12 mA. 5 Sleep Mode With External Clock On 20 20 µA typ Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 600 600 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 300 300 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 89.25 89.25 mW max V = 5.25 V: Typically 63 mW; SLEEP = V . DD DD Sleep Mode Power Dissipation With External Clock On 105 105 µW typ V = 5.25 V; SLEEP = 0 V. DD With External Clock Off 52.5 52.5 µW max V = 5.25 V; Typically 5.25 µW; SLEEP = 0 V. DD SYSTEM CALIBRATION 6 Offset Calibration Span +0.05 × V /–0.05 × V V max/min Allowable Offset Voltage Span for Calibration. REF REF 6 Gain Calibration Span +1.025 × V /–0.975 × V V max/min Allowable Full-Scale Voltage Span for Calibration. REF REF NOTES 1 Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C. 2 Specifications apply after calibration. 3 SNR calculation includes distortion and noise components. 4 All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV . No load on the digital outputs. Analog inputs at AGND. DD 5 CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV . No load on the digital outputs. DD Analog inputs at AGND. 6 The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V , and the REF allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V ± 0.025 × V ). This is REF REF explained in more detail in the Calibration section of the data sheet. Specifications subject to change without notice. REV. B –4– AD7851 1 (AV = DV = 5.0 V � 5%; f = 6 MHz, T = T to T , unless otherwise noted.) TIMING SPECIFICATIONS DD DD CLKIN A MIN MAX Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin LOW, then the opposite edge of SCLK will apply. Limit at T , T MIN MAX Parameter (A, K Versions) Unit Description 2 f 500 kHz min Master Clock Frequency CLKIN 7 MHz max 3 f 10 MHz max Interface Modes 1, 2, 3 (External Serial Clock) SCLK f MHz max Interface Modes 4, 5 (Internal Serial Clock) CLK IN 4 t 100 ns min CONVST Pulse Width 1 t 50 ns max CONVST↓ to BUSY↑ Propagation Delay 2 t 3.25 µs max Conversion Time = 20 t CONVERT CLKIN t –0.4 t ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input) 3 SCLK ±0.4 t ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input) SCLK t 0.6 t ns min SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only 4 SCLK 5 t 30 ns max Delay from SYNC↓ until DOUT Three-State Disabled 5 5 t 30 ns max Delay from SYNC↓ until DIN Three-State Disabled 5A 5 t 45 ns max Data Access Time after SCLK↓ 6 t 30 ns min Data Setup Time prior to SCLK↑ 7 t 20 ns min Data Valid to SCLK Hold Time 8 6 t 0.4 t ns min SCLK High Pulse Width (Interface Modes 4 and 5) 9 SCLK 6 t 0.4 t ns min SCLK Low Pulse Width (Interface Modes 4 and 5) 10 SCLK t 30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 11 30/0.4 t ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 SCLK t 50 ns max SCLK↑ to SYNC↑ Hold Time 11A 7 t 50 ns max Delay from SYNC↑ until DOUT Three-State Enabled 12 t 90 ns max Delay from SCLK↑ to DIN Being Configured as Output 13 8 t 50 ns max Delay from SCLK↑ to DIN Being Configured as Input 14 t 2.5 t ns max CAL↑ to BUSY↑ Delay 15 CLKIN t 2.5 t ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence 16 CLKIN 9 t 41.7 ms typ Full Self-Calibration Time, Master Clock Dependent CAL (250026 t ) CLKIN 9 t 37.04 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master Clock CAL1 Dependent (222228 t ) CLKIN 9 t 4.63 ms typ System Offset Calibration Time, Master Clock Dependent CAL2 (27798 t ) CLKIN t 65 ns max Delay from CLK to SCLK DELAY NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. See DD Table X and timing diagrams for different interface modes and calibration. 2 Mark/space ratio for the master clock input is 40/60 to 60/40. 3 For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f . CLKIN 4 The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power- Down section). 5 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6 For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t = 0.5 t . SCLK CLKIN 7 The time t is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then 12 extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t as quoted in the timing characteristics is the true bus 12 relinquish time of the part and is independent of the bus loading. 8 The time t is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then 14 extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing that a bus conflict will not occur. 9 The typical time specified for the calibration times is for a master clock of 6 MHz. Specifications subject to change without notice. REV. B –5– AD7851 TYPICAL TIMING DIAGRAMS 1.6mA I OL Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of TO 285 kHz in Interface Modes 2 and 3, reading and writing must 2.1V OUTPUT C L PIN be performed during conversion. Figure 3 shows the timing dia- 50pF gram for Interface Modes 4 and 5 with sample rate of 285 kHz. At least a 330 ns acquisition time must be allowed (the time 200µA I OH from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion begins to ensure that the Figure 1. Load Circuit for Digital Output Timing part is settled to the 14-bit level. If the user does not want to Specifications provide the CONVST signal, the conversion can be initiated in software by writing to the control register. t = 3.25µs MAX, t = 100ns MIN, POLARITY PIN LOGIC HIGH CONVERT 1 t = 30ns MAX, t = 30ns MIN 5 7 t 1 CONVST (I/P) t CONVERT t 2 BUSY (O/P) SYNC (I/P) t t t 3 11 9 15 6 16 SCLK (I/P) t t 10 5 t t 6 t 12 6 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB11 DB0 t 7 t 8 DIN (I/P) DB15 DB11 DB0 Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3) t = 3.25µs MAX, t = 100ns MIN, POLARITY PIN LOGIC HIGH CONVERT 1 t = 30ns MAX, t = 30ns MIN 5 7 t 1 CONVST (I/P) t CONVERT t 2 BUSY (O/P) SYNC (O/P) t t t 4 9 11 15 6 16 SCLK (O/P) t t 10 5 t t 12 6 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB11 DB0 t 7 t 8 DIN (I/P) DB15 DB11 DB0 Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5) REV. B –6– AD7851 1 ABSOLUTE MAXIMUM RATINGS Lead Temperature, Soldering (T = 25°C, unless otherwise noted.) Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C A Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD NOTES AV to DV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DD DD 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- Analog Input Voltage to AGND . . . . . –0.3 V to AV + 0.3 V DD nent damage to the device. This is a stress rating only; functional operation of the Digital Input Voltage to DGND . . . . –0.3 V to DV + 0.3 V DD device at these or any other conditions above those listed in the operational Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V DD sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REF /REF to AGND . . . . . . . . . . –0.3 V to AV + 0.3 V IN OUT DD 2 2 Transient currents of up to 100 mA will not cause SCR latch-up. Input Current to Any Pin Except Supplies . . . . . . . . . ±10 mA Operating Temperature Range PINOUT FOR DIP, SOIC, AND SSOP Commercial (A, K Versions) . . . . . . . . . . . –40°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C SYNC CONVST 24 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C 1 PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW BUSY 2 23 SCLK SLEEP θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W 22 JA 3 CLKIN θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . .34.7°C/W 21 JC REF /REF 4 DIN IN OUT Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . 260°C AV 5 20 DOUT DD AD7851 SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW AGND 19 DGND 6 TOP VIEW (Not to Scale) θ Thermal Impedance . . 75°C/W (SOIC), 122.28°C/W (SSOP) JA C 7 18 DV 1 REF DD θ Thermal Impedance . . . 25°C/W (SOIC), 31.25°C/W (SSOP) JC CAL C 8 17 2 REF AIN(+) 16 SM2 9 10 AIN(–) 15 SM1 NC 11 14 POLARITY AGND 12 13 AMODE NC = NO CONNECT 1 ORDERING GUIDE Linearity Temperature Error Throughput Throughput Package 2 3 Model Range (LSB) Rate (kSPS) at 125�C (kSPS) Description Options AD7851AN –40°C to +85°C ±2 333 238 PDIP N-24 AD7851KN 0°C to 85°C ±1 285 238 PDIP N-24 AD7851AR –40°C to +85°C ±2 333 238 SOIC R-24 AD7851AR-REEL –40°C to +85°C ±2 333 238 SOIC R-24 3 AD7851ARZ –40°C to +85°C ±2 333 238 SOIC R-24 3 AD7851ARZ-REEL –40°C to +85°C ±2 333 238 SOIC R-24 AD7851KR 0°C to 85°C ±1 285 238 SOIC R-24 AD7851KR-REEL 0°C to 85°C ±1 285 238 SOIC R-24 3 AD7851KRZ 0°C to 85°C ±1 285 238 SOIC R-24 3 AD7851KRZ-REEL 0°C to 85°C ±1 285 238 SOIC R-24 AD7851ARS –40°C to +85°C ±2 333 238 SSOP RS-24 AD7851ARS-REEL –40°C to +85°C ±2 333 238 SSOP RS-24 4 EVAL-AD7851CB Evaluation Board 5 EVAL-CONTROL BRD2 Controller Board NOTES 1 Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz). 2 Linearity error refers to the integral linearity error. 3 Z = Pb-free part. 4 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, and a 12 V ac trans- former. See the Evaluation Board application note for more information. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7851 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –7– AD7851 TERMINOLOGY Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of Integral Nonlinearity harmonics to the fundamental. For the AD7851, it is defined as This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- 2 2 2 2 2 VVV ++ ++ VV () 2 3 4 5 6 points of the transfer function are zero scale, a point 1/2 LSB THD(dB) =20log below the first code transition, and full scale, a point 1/2 LSB V 1 above the last code transition. where V is the rms amplitude of the fundamental and V , V , 1 2 3 Differential Nonlinearity V , V , and V are the rms amplitudes of the second through the 4 5 6 This is the difference between the measured and the ideal 1 LSB sixth harmonics. change between any two adjacent codes in the ADC. Peak Harmonic or Spurious Noise Total Unadjusted Error Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the actual code from the ideal code tak- rms value of the next largest component in the ADC output ing all errors into account (gain, offset, integral nonlinearity, and spectrum (up to f /2 and excluding dc) to the rms value of the S other errors) at any point along the transfer function. fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts Unipolar Offset Error where the harmonics are buried in the noise floor, it will be a This is the deviation of the first code transition (00 . . . 000 to noise peak. 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) when operating in unipolar mode. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and Positive Full-Scale Error fb, any active device with nonlinearities will create distortion This applies to unipolar and bipolar modes and is the deviation of products at sum and difference frequencies of mfa ± nfb where the last code transition from the ideal AIN(+) voltage (AIN(–) + m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are full scale – 1.5 LSB) after the offset error has been adjusted out. those for which neither m nor n are equal to zero. For example, Negative Full-Scale Error the second-order terms include (fa + fb) and (fa – fb), while the This applies to bipolar mode only and is the deviation of the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and first code transition (10 . . . 000 to 10 . . . 001) from the ideal (fa – 2fb). AIN(+) voltage (AIN(–) – V /2 + 0.5 LSB). REF Testing is performed using the CCIF standard where two Bipolar Zero Error input frequencies near the top end of the input bandwidth are This is the deviation of the midscale transition (all 1s to all 0s) used. In this case, the second-order terms are usually distanced from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). in frequency from the original sine waves while the third-order Track-and-Hold Acquisition Time terms are usually at a frequency close to the input frequencies. The track-and-hold amplifier returns into track mode at the end As a result, the second- and third-order terms are specified of conversion. Track-and-hold acquisition time is the time separately. The calculation of the intermodulation distortion is required for the output of the track-and-hold amplifier to reach as per the THD specification where it is the ratio of the rms its final value, within ±1/2 LSB, after the end of conversion. sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at Power Supply Rejection Ratio (PSRR) the output of the ADC. The signal is the rms amplitude of the PSRR is defined as the ratio of the power in ADC output at fre- fundamental. Noise is the sum of all nonfundamental signals up quency f to the power of the full-scale sine wave applied to the to half the sampling frequency (f /2), excluding dc. The ratio is S supply voltage (V ). The units are in LSB, % of FS per % of DD dependent on the number of quantization levels in the digitiza- supply voltage, or expressed logarithmically, in dB (PSRR (dB) tion process; the more levels, the smaller the quantization noise. = 10 log (Pf/Pfs)). The theoretical signal-to-(noise + distortion) ratio for an ideal Full Power Bandwidth (FPBW) N-bit converter with a sine wave input is given by FPBW is that frequency at which the amplitude of the recon- Signal-to-(Noise + Distortion) = (6.02 N +1.76)dB structed fundamental (using FFTs and neglecting harmonics and SNR) is reduced by 3 dB for a full-scale input. Thus, for a 14-bit converter, this is 86 dB. REV. B –8– AD7851 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV . DD 2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed its on-chip calibration sequence. 3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the internal voltage reference, provided there is no conversion or calibration being performed. Calibration data is retained. A Logic 1 results in normal operation. See Power-Down section for more details. 4 REF/Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the IN REF reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears OUT at the pin. This pin can be overdriven by an external reference or can be taken as high as AV . When this DD pin is tied to AV , or when an externally applied reference approaches V , then the C pin should also DD DD REF1 be tied to AV . DD 5AV Analog Positive Supply Voltage, 5.0 V ± 5%. DD 6, 12 AGND Analog Ground. Ground reference for track and hold, reference, and DAC. 7C Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is REF1 used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND. 8C Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip REF2 reference. The capacitor should be tied between the pin and AGND. 9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time and cannot go below AIN(–) when the unipolar input range is selected. DD 10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above AV at any time. DD 11 NC No Connect Pin. 13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range 0 to V (i.e., AIN(+) – AIN(–) = 0 to V ). In this case, AIN(+) cannot go below AIN(–) and AIN(–) REF REF cannot go below AGND. A Logic 1 selects range –V /2 to +V /2 (i.e., AIN(+) – AIN(–) = –V /2 to REF REF REF +V /2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V /2 to REF REF allow AIN(+) to go from 0 V to +V V. REF 14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and Table IX for the SCLK active edges. 15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera- tion as described in Table X. 16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera- tion as described in Table X. 17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high. 18 DV Digital Supply Voltage, 5.0 V ± 5%. DD 19 DGND Digital Ground. Ground reference point for digital circuitry. 20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word. 21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X). 22 CLKIN Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times. 23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin. 24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X). REV. B –9– AD7851 AD7851 ON-CHIP REGISTERS The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC. Extra features and flexibility, such as performing different power-down options, different types of calibrations, including system cali- bration, and software conversion starts can be selected by writing to the part. The AD7851 contains a control register, ADC output data register, status register, test register, and 10 calibration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to. Addressing the On-Chip Registers Writing A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which regis- ter is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall write register hierarchy. Table I. Write Register Addressing ADDR1 ADDR0 Comment 00 This combination does not address any register so the subsequent 14 data bits are ignored. 01 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register. 10 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written to the selected calibration register. 11 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. Once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selected register until the read selection bits are changed in the control register. Table II. Read Register Addressing RDSLT1 RDSLT0 Comment 00 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default setting. There will always be two leading zeros when reading from the ADC output data register. 01All successive read operations will be from TEST REGISTER. 10All successive read operations will be from CALIBRATION REGISTERS. 11All successive read operations will be from STATUS REGISTER. RDSLT1, RDSLT0 ADDR1, ADDR0 DECODE DECODE 00 01 10 11 01 10 11 ADC OUTPUT TEST CALIBRATION STATUS TEST CALIBRATION CONTROL DATA REGISTER REGISTER REGISTERS REGISTER REGISTER REGISTERS REGISTER GAIN (1) GAIN (1) GAIN (1) GAIN (1) OFFSET (1) GAIN (1) OFFSET (1) GAIN (1) OFFSET (1) OFFSET (1) OFFSET (1) OFFSET (1) DAC (8) DAC (8) 00 01 10 11 00 01 10 11 CALSLT1, CALSLT0 CALSLT1, CALSLT0 DECODE DECODE Figure 4. Write Register Hierarchy/Address Decoding Figure 5. Read Register Hierarchy/Address Decoding REV. B –10– AD7851 CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0. MSB ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 CONVST CALMD CALSLT1 CALSLT0 STCAL 2/3 MODE LSB Control Register Bit Function Descriptions Bit No. Mnemonic Comment 13 ZERO These four bits must be set to 0 when writing to the control register. 12 ZERO 11 ZERO 10 ZERO 9PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8PMGT0 power-down modes (see Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II. 6 RDSLT0 52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1, Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every write cycle. 4 CONVST Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see Calibration section). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions: 1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per- 0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on Calibration Registers for more details). Table III. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the internal gain error, and finally the internal offset error is calibrated out. This is the default setting. 00 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated out. 01 0This calibrates out the internal offset error only. 01 1This calibrates out the internal gain error only. 10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol- lowed by the system gain error, and finally the system offset error is calibrated out. 10 1Here the system gain error is calibrated out followed by the system offset error. 11 0This calibrates out the system offset error only. 11 1This calibrates out the system gain error only. REV. B –11– AD7851 STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register is described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 6. Flowchart for Reading the Status Register MSB ZERO BUSY ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 X CALMD CALSLT1 CALSLT0 STCAL 2/3 MODE LSB Status Register Bit Function Descriptions Bit No. Mnemonic Comment 15 ZERO This bit is always 0. 14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration in progress. When this bit is 0, there is no conversion or calibration in progress. 13 ZERO These four bits are always 0. 12 ZERO 11 ZERO 10 ZERO 9PMGT1 Power Management Bits. These bits along with the SLEEP pin will indicate whether the part is in a power- 8PMGT0 down mode. (See Table VI in the Power-Down Options section for description.) 7 RDSLT1 Both these bits are always 1 indicating it is the status register that is being read. (See Table II.) 6 RDSLT0 52/3 MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle. 4X Don’t care bit. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates self-calibration is selected, and 1 in this bit indicates a system calibration is selected (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in 1 CALSLT0 progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate which 0 STCAL of the calibration registers are addressed for reading and writing (see the Calibration Registers section for more details) REV. B –12– AD7851 CALIBRATION REGISTERS The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset, and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. Addressing the Calibration Registers The calibration selection bits in the control register, CALSLT1 and CALSLT0, determine which of the calibration registers are addressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time. Table IV. Calibration Register Addressing CALSLT1 CALSLT0 This Combination Addresses the 0 0 Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. 0 1 Gain (1) and Offset (1) Registers. Two registers in total. 1 0 Offset Register. One register in total. 1 1 Gain Register. One register in total. When reading from the calibration registers there will always be Writing to/Reading from the Calibration Registers two leading zeros for each of the registers. When operating in For writing to the calibration registers, a write to the control reg- Serial Interface Mode 1, the read operations to the calibration ister is required to set the CALSLT0 and CALSLT1 bits. For registers cannot be aborted. The full number of read operations reading from the calibration registers, a write to the control regis- must be completed (see the Serial Interface Summary section ter is required to set the CALSLT0 and CALSLT1 bits, but also for more detail). to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the calibration registers for reading). The calibration register pointer is reset on writing to the control register setting the CALSLT1 START and CALSLT0 bits, or upon completion of all the calibration register write/read operations. When reset, it points to the first WRITE TO CONTROL REGISTER SETTING STCAL = 0 calibration register in the selected write/read sequence. The cali- AND CALSLT1, CALSLT0 = 00, 01, 10, 11 bration register pointer will point to the gain calibration register upon reset in all but one case, this case being where the offset CAL REGISTER POINTER IS calibration register is selected on its own (CALSLT1 = 1, AUTOMATICALLY RESET CALSLT0 = 0). Where more than one calibration register is being accessed, the calibration register pointer will be automatically incremented after each calibration register write/read operation. The order in which the 10 calibration registers are arranged is WRITE TO CAL REGISTER (ADDR1 = 1, ADDR0 = 0) shown in Figure 7. The user may abort at any time before all the calibration register write/read operations are completed, and the next control register write operation will reset the cali- CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED bration register pointer. The flowchart in Figure 8 shows the sequence for writing to the calibration registers and Figure 9 shows the sequence for reading. LAST REGISTER CALIBRATION REGISTERS NO WRITE CAL REGISTER GAIN REGISTER (1) OPERATION ADDRESS POINTER OR (2) OFFSET REGISTER ABORT ? (3) DAC 1st MSB REGISTER YES FINISHED (10) DAC 8th MSB REGISTER Figure 8. Flowchart for Writing to the Calibration Registers CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS. Figure 7. Calibration Register Arrangement REV. B –13– AD7851 This gives a resolution of ±0.0006% of V approximately. REF START 13 More accurately the resolution is ±(0.05 × V )/2 V = REF ±0.015 mV, with a 2.5 V reference. The maximum offset that WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, can be compensated for is ±5% of the reference voltage, which RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 equates to ±125 mV with a 2.5 V reference and ±250 mV with a 5 V reference. CAL REGISTER POINTER IS Q. If a +20 mV offset is present in the analog input signal and AUTOMATICALLY RESET the reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset? READ CAL REGISTER A. The 2.5 V reference implies that the resolution in the off- 13 set register is 5% × 2.5 V/2 = 0.015 mV. 20 mV/ 0.015 mV = 1310.72; rounding to the nearest number gives CAL REGISTER POINTER IS 1311. In binary terms this is 0101 0001 1111, therefore AUTOMATICALLY INCREMENTED decrease the offset register by 0101 0001 1111. This method of compensating for offset in the analog input signal LAST allows for fine-tuning the offset compensation. If the offset on the REGISTER NO analog input signal is known, there will be no need to apply the WRITE OPERATION offset voltage to the analog input pins to do a system calibration. OR The offset compensation can take place in software. ABORT ? Adjusting the Gain Calibration Register YES The gain calibration register contains 16 bits, 2 leading 0s, and 14 data bits. The data bits are binary weighted as in the offset FINISHED calibration register. The gain register value is effectively multi- Figure 9. Flowchart for Reading from the plied by the analog input to scale the conversion result over the Calibration Registers full range. Increasing the gain register compensates for a smaller analog input range and decreasing the gain register Adjusting the Offset Calibration Register compensates for a larger input range. The maximum analog The offset calibration register contains 16 bits, 2 leading 0s, and input range that the gain register can compensate for is 1.025 14 data bits. By changing the contents of the offset register, dif- times the reference voltage, and the minimum input range is ferent amounts of offset on the analog input signal can be com- 0.975 times the reference voltage. pensated for. Increasing the number in the offset calibration register compensates for the negative offset on the analog input signal, and decreasing the number in the offset calibration regis- ter compensates for the positive offset on the analog input signal. The default value of the offset calibration register is approxi- mately 0010 0000 0000 0000. This is not an exact value, but the value in the offset register should be close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the reference voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so on down to the LSB which has a weighting of 0.0006%. REV. B –14– AD7851 CIRCUIT INFORMATION mum specified conversion time is 3.25 µs (6 MHz ) and 2.8 µs The AD7851 is a fast, 14-bit single-supply ADC. The part (7 MHz) for the A and K Grades, respectively, for the AD7851 requires an external 6/7 MHz master clock (CLKIN), two (19.5 t CLKIN = 6 MHz/7 MHz). When a conversion is CLKIN, C capacitors, a CONVST signal to start conversion, and completed, the BUSY output goes low, and then the result of REF power supply decoupling capacitors. The part provides the user the conversion can be read by accessing the data through the with track-and-hold, on-chip reference, calibration features, edge of serial interface. To obtain optimum performance from ADC, and serial interface logic functions on a single chip. The the part, the read operation should not occur during the conver- ADC section of the AD7851 consists of a conventional succes- sion or 500 ns prior to the next CONVST rising edge. How- sive approximation converter based around a capacitor DAC. ever, the maximum throughput rates are achieved by reading/ The AD7851 accepts an analog input range of 0 V to +V writing during conversion, and reading/writing during conver- DD where the reference can be tied to V . The reference input to sion is likely to degrade the signal-to-(noise + distortion) by DD the part is buffered on-chip. only 0.5 dBs. The AD7851 can operate at throughput rates up to 333 kHz. For the AD7851, a conversion takes 19.5 CLKIN A major advantage of the AD7851 is that a conversion can be periods; 2 CLKIN periods are needed for the acquisition time initiated in software as well as applying a signal to the CONVST giving a full cycle time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz) pin. Another innovative feature of the AD7851 is self-calibration for the K grade and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for on power-up, which is initiated having a capacitor from the the A grade. CAL pin to AGND, to give superior dc accuracy (see the Automatic Calibration on Power-On section). The part is avail- TYPICAL CONNECTION DIAGRAM able in a 24-lead SSOP package which offers the user consider- Figure 10 shows a typical connection diagram for the AD7851. able space-saving advantages over alternative solutions. The DIN line is tied to DGND so that no data is written to the part. The AGND and the DGND pins are connected together CONVERTER DETAILS at the device for good noise suppression. The CAL pin has a The master clock for the part must be applied to the CLKIN 0.01 µF capacitor to enable an automatic self-calibration on pin. Conversion is initiated on the AD7851 by pulsing the power-up. The SCLK and SYNC are configured as outputs by CONVST input or by writing to the control register and setting having SM1 and SM2 at DV . The conversion result is output DD the CONVST bit to 1. On the rising edge of CONVST (or at in a 16-bit word with 2 leading zeros followed by the MSB of the end of the control register write operation), the on-chip the 14-bit result. Note that after the AV and DV power up, DD DD track-and-hold goes from track to hold mode. The falling edge the part will require approximately 150 ms for the internal refer- of the CLKIN signal which follows the rising edge of the ence to settle and for the automatic calibration on power-up to CONVST signal initiates the conversion, provided the rising be completed. edge of CONVST occurs at least 10 ns typically before this CLKIN edge. The conversion cycle will take 18.5 CLKIN peri- For applications where power consumption is a major concern, the ods from this CLKIN falling edge. If the 10 ns setup time is not SLEEP pin can be connected to DGND. (See the Power-Down met, the conversion will take 19.5 CLKIN periods. The maxi- Options section for more detail on low power applications.) 7MHz/6MHz 333kHz/285kHz PULSE OSCILLATOR GENERATOR ANALOG (5V) SUPPLY 10�F 0.01�F 0.1�F CONVERSION 0V TO V MASTER REF AV DV AIN(+) DD DD START INPUT CLOCK INPUT AIN(–) INPUT UNIPOLAR RANGE OSCILLOSCOPE CLKIN AMODE SCLK CH1 C SERIAL CLOCK OUTPUT REF1 0.1�F 470nF CONVST CH2 AD7851 C REF2 SYNC CH3 0.01�F FRAME SYNC OUTPUT CH4 DOUT SLEEP SERIAL DATA OUTPUT DV POLARITY DD DIN CAL 0.01�F SM1 AGND DIN AT DGND 2 LEADING ZEROS DV DD => NO WRITING FOR ADC DATA SM2 TO DEVICE DGND REF /REF IN OUT SERIAL MODE AUTO CAL ON SELECTION BITS POWER-UP INTERNAL/ 0.1�F EXTERNAL REFERENCE OPTIONAL EXTERNAL AD1584/REF198 REFERENCE ANALOG (5V) SUPPLY 10�F 0.1�F Figure 10. Typical Circuit REV. B –15– AD7851 ANALOG INPUT When no amplifier is used to drive the analog input, the source The equivalent circuit of the analog input section is shown in impedance should be limited to low values. The maximum Figure 11. During the acquisition interval, the switches are both source impedance will depend on the amount of total harmonic in the track position and the AIN(+) charges the 20 pF capacitor distortion (THD) that can be tolerated. The THD will increase through the 125 Ω resistance. On the rising edge of CONVST, as the source impedance increases, and the performance will Switches SW1 and SW2 go into the hold position retaining degrade. Figure 12 shows a graph of the total harmonic distor- charge on the 20 pF capacitor as a sample of the signal on tion versus the analog input signal frequency for different source AIN(+). The AIN(–) is connected to the 20 pF capacitor, and impedances. With the setup as in Figure 13, the THD is at the this unbalances the voltage at Node A at the input of the com- –90 dB level. With a source impedance of 1 kΩ and no capacitor parator. The capacitor DAC adjusts during the remainder of the on the AIN(+) pin, the THD increases with frequency. conversion cycle to restore the voltage at Node A to the correct –50 value. This action transfers a charge, representing the analog input THD VS. FREQUENCY FOR DIFFERENT signal, to the capacitor DAC which in turn forms a digital repre- SOURCE IMPEDANCES –60 sentation of the analog input signal. The voltage on the AIN(–) pin directly influences the charge transferred to the capacitor –70 DAC at the hold instant. If this voltage changes during the con- R = 560� IN version period, the DAC representation of the analog input volt- age will be altered. Therefore, it is most important that the voltage –80 on the AIN(–) pin remain constant during the conversion period. R = 10�, 10nF IN Furthermore, it is recommended that the AIN(–) pin always be –90 AS IN FIGURE 13 connected to AGND or to a fixed dc voltage. –100 125� TRACK AIN(+) CAPACITOR 125� –110 DAC 80 AIN(–) 1 10 20 50 100 120 140 166 SW1 20pF INPUT FREQUENCY (kHz) HOLD NODE A Figure 12. THD vs. Analog Input Frequency SW2 In a single-supply application (5 V), the V+ and V– of the op amp TRACK HOLD COMPARATOR can be taken directly from the supplies to the AD7851 which elimi- C REF2 nates the need for extra external power supplies. When operating Figure 11. Analog Input Equivalent Circuit with rail-to-rail inputs and outputs at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for Acquisition Time the application. In particular, for single-supply applications the The track and hold amplifier enters its tracking mode on the fall- input amplifiers should be connected in a gain of –1 arrangement ing edge of the BUSY signal. The time required for the track and to get the optimum performance. Figure 13 shows the arrangement hold amplifier to acquire an input signal will depend on how for a single-supply application with a 10 Ω and 10 nF low-pass fil- quickly the 20 pF input capacitance is charged. The acquisition ter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the time is calculated using the formula 10 nF is a capacitor with good linearity to ensure good ac t = 9 × (R + 125 Ω) × 20 pF ACQ IN performance. Recommended single-supply op amp is the AD820. where R is the source impedance of the input signal, and IN 5V 125 Ω, 20 pF is the input R, C. 0.1�F 10�F DC/AC Applications 10k� For dc applications, high source impedances are acceptable, 10k� V V+ IN 10� provided there is enough acquisition time between conversions –V /2 TO +V /2 REF REF TO AIN(+) OF 10k� IC1 to charge the 20 pF capacitor. The acquisition time can be cal- AD7851 V /2 10nF REF AD820 V– (NPO) culated from the above formula for different source impedances. 10k� For example, with R = 5 kΩ, the required acquisition time will IN be 922 ns. Figure 13. Analog Input Buffering For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the AIN(+) pin, as shown in Figure 13. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. REV. B –16– THD (dB) AD7851 Input Ranges Transfer Functions The analog input range for the AD7851 is 0 V to V in both REF For the unipolar range, the designed code transitions occur mid- the unipolar and bipolar ranges. way between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is The only difference between the unipolar range and the bipolar straight binary for the unipolar range with 1 LSB = FS/16384 = range is that in the bipolar range the AIN(–) has to be biased up 4.096 V/16384 = 0.25 mV when V = 4.096 V. The ideal REF to +V /2 and the output coding is twos complement (see REF input/output transfer characteristic for the unipolar range is Table V and Figures 14 and 15). The unipolar or bipolar mode shown in Figure 16. is selected by the AMODE pin (0 for the unipolar range and 1 for the bipolar range). OUTPUT CODE Table V. Analog Input Connections 111...111 111...110 Analog Input Input Connections Connection 111...101 Range AIN(+) AIN(–) Diagram AMODE 111...100 1 0 V to V V AGND Figure 8 DGND REF IN 2 ±V /2 V V /2 Figure 9 DV REF IN REF DD NOTES 1 FS Output code format is straight binary. 000...011 1LSB = 2 16384 Range is ± V /2 biased about V /2. Output code format is twos complement. REF REF 000...010 Note that the AIN(–) pin on the AD7851 can be biased up above 000...001 000...000 AGND in the unipolar mode also, if required. The advantage of 0V 1LSB +FS – 1LSB biasing the lower end of the analog input range away from V = (AIN(+) – AIN(–)), INPUT VOLTAGE IN AGND is that the user does not have to have the analog input Figure 16. AD7851 Unipolar Transfer Characteristic swing all the way down to AGND. This has the advantage in true single-supply applications that the input amplifier does not Figure 15 shows the AD7851’s ±V /2 bipolar analog input con- REF have to swing all the way down to AGND. The upper end of the figuration (where AIN(+) cannot go below 0 V, so for the full bipo- analog input range is shifted up by the same amount. Care must lar range the AIN(–) pin should be biased to +V /2). Once again REF be taken so that the bias applied does not shift the upper end of the designed code transitions occur midway between successive the analog input above the AV supply. In the case where the DD integer LSB values. The output coding is twos complement with reference is the supply, AV , the AIN(–) must be tied to DD 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The ideal input/ AGND in unipolar mode. output transfer characteristic is shown in Figure 17. TRACK AND HOLD OUTPUT AIN(+) AMPLIFIER CODE V = 0 TO V STRAIGHT IN REF DOUT 011...111 BINARY AIN(–) FORMAT 011...110 AD7851 UNIPOLAR AMODE ANALOG (V /2) – 1 LSB REF INPUT RANGE 000...001 SELECTED 0V 000...000 Figure 14. 0 V to V Unipolar Input Configuration REF + FS – 1 LSB 111...111 (V /2) + 1 LSB REF TRACK AND HOLD 100...010 FS = V V REF AIN(+) AMPLIFIER FS V = 0 TO V TWOS IN REF DOUT 1LSB = 100...001 16384 COMPLEMENT AIN(–) V /2 FORMAT 100...000 REF DV DD AD7851 V /2 REF UNIPOLAR AMODE V = (AIN(+) – AIN(–)), INPUT VOLTAGE ANALOG IN INPUT RANGE SELECTED Figure 17. AD7851 Bipolar Transfer Characteristic Figure 15. ±V /2 about V /2 Bipolar Input Configuration REF REF REV. B –17– AD7851 REFERENCE SECTION AD7851 PERFORMANCE CURVES For specified performance, it is recommended that when using Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz an external reference this reference should be between 4 V and sample rate and 10 kHz input frequency. the analog supply AV . The connections for the relevant refer- DD 0 ence pins are shown in the typical connection diagrams. If the internal reference is being used, the REF /REF pin should IN OUT AV = DV = 5V DD DD –20 have a 100 nF capacitor connected to AGND very close to the f = 333kHz SAMPLE f = 10kHz REF /REF pin. These connections are shown in Figure 18. IN OUT IN SNR = 79.5dB –40 THD = –95.2 If the internal reference is required for use external to the ADC, it should be buffered at the REF /REF pin and a 100 nF IN OUT –60 capacitor connected from this pin to AGND. The typical noise performance for the internal reference with 5 V supplies is 150 nV/√Hz @ 1 kHz and dc noise is 100 µV p-p. –80 10� ANALOG –100 SUPPLY 0.01�F 10�F 0.1�F 5V –120 0 20 40 60 80 100 AV DV FREQUENCY (kHz) DD DD C REF1 Figure 20. FFT Plot 0.1�F 470nF Figure 21 shows the SNR versus frequency for a 5 V supply and C AD7851 REF2 a 4.096 external reference (5 V reference is typically 1 dB better 0.01�F performance). REF /REF IN OUT 79 0.1�F 78 Figure 18. Relevant Connections When Using Internal Reference The other option is that the REF /REF pin be overdriven IN OUT 77 by connecting it to an external reference. This is possible due to the series resistance from the REF /REF pin to the internal IN OUT reference. This external reference can have a range that includes AV . When using AV as the reference source, the 100 nF 76 DD DD capacitor from the REF /REF pin to AGND should be as IN OUT close as possible to the REF /REF pin, and also the C IN OUT REF1 pin should be connected to AV to keep this pin at the same DD 75 0 10 20 50 80 100 120 140 166 level as the reference. The connections for this arrangement are INPUT FREQUENCY (kHz) shown in Figure 19. When using AV it may be necessary to DD Figure 21. SNR vs. Frequency add a resistor in series with the AV supply. This will have the DD effect of filtering the noise associated with the AV supply. Figure 22 shows the power supply rejection ratio versus fre- DD quency for the part. The power supply rejection ratio is defined 10� ANALOG as the ratio of the power in ADC output at frequency f to the SUPPLY power of a full-scale sine wave. 0.1�F 10�F 0.01�F 5V PSRR (dB) = 10 log (Pf/Pfs) AV DV DD DD Pf is the power at frequency f in ADC output, Pfs is the power C of a full-scale sine wave. Here a 100 mV peak-to-peak sine wave REF1 0.01�F 470nF is coupled onto the AV supply while the digital supply is left DD unaltered. AD7851 10� C REF2 0.01�F REF /REF IN OUT 0.1�F Figure 19. Relevant Connections When Using AV DD as the Reference REV. B –18– S(N+D) RATIO (dB) SNR (dB) AD7851 –72 When using the SLEEP pin, the power management bits AV = DV = 5.0V DD DD –74 PMGT1 and PMGT0 should be set to 0 (default status on 100mV pk-pk SINEWAVE ON AV DD power-up). Bringing the SLEEP pin logic high ensures normal REF = 4.098 EXT REFERENCE –76 IN operation, and the part does not power down at any stage. This –78 may be necessary if the part is being used at high throughput rates when it is not possible to power down between conver- –80 sions. If the user wishes to power down between conversions at –82 lower throughput rates (that is, <100 kSPS for the AD7851) to achieve better power performances, then the SLEEP pin should –84 be tied logic low. –86 If the power-down options are to be selected in software only, –88 then the SLEEP pin should be tied logic high. By setting the power management bits PMGT1 and PMGT0 as shown in –90 0.91 13.4 25.7 38.3 50.3 63.5 74.8 87.4 100 Table VI, a full power-down, full power-up, full power-down INPUT FREQUENCY (kHz) between conversions, and a partial power-down between con- Figure 22. PSRR vs. Frequency versions can be selected. POWER-DOWN OPTIONS A combination of hardware and software selection can also be The AD7851 provides flexible power management to allow the used to achieve the desired effect. user to achieve the best power performance for a given throughput Table VI. Power Management Options rate. The power management options are selected by programming the power management bits, PMGT1 and PMGT0, in the con- PMGT1 PMGT0 SLEEP trol register and by use of the SLEEP pin. Table VI summarizes Bit Bit Pin Comment the power-down options that are available and how they can be selected by using either software, hardware, or a combination of 00 0 Full power-down between both. The AD7851 can be fully or partially powered down. When conversions (HW/SW) fully powered down, all the on-chip circuitry is powered down 00 1 Full power-up (HW/SW) and I is 1 µA typ. If a partial power-down is selected, then all DD 01 X Full power-down between the on-chip circuitry except the reference is powered down and I DD conversions (SW) is 400 µA typ. The choice of full or partial power-down does not give any significant improvement in throughput with a power-down10 X Full power-down (SW) between conversions. (This is discussed in the Power-Up Times 11 X Partial power-down between section which follows.) But a partial power-down does allow the conversions (SW) on-chip reference to be used externally even though the rest of the SW = Software selection, HW = Hardware selection. AD7851 circuitry is powered down. It also allows the AD7851 to be powered up faster after a long power-down period when using the on-chip reference. (See the Using the Internal (On-Chip) Ref- erence section which follows.) CURRENT, I = 12mA TYP 6MHz/7MHz 285kHz/333kHz PULSE ANALOG OSCILLATOR GENERATOR (5V) 0.01�F 0.1�F 10�F 0V TO V MASTER REF AIN(+) AV DV DD DD CLOCK INPUT AIN(–) INPUT UNIPOLAR RANGE CLKIN AMODE SCLK SERIAL CLOCK OUTPUT C REF1 0.1�F 470nF CONVST CONVERSION LOW POWER START INPUT �C/�P SYNC C AD7851 REF2 0.01�F DOUT SLEEP SERIAL DATA OUTPUT AUTO POWER- DOWN AFTER DIN DIN AT DGND DV POLARITY DD CONVERSION => NO WRITING CAL TO DEVICE 0.01�F AGND SM1 SERIAL MODE SELECTION BITS SM2 REF /REF DGND IN OUT AUTO CAL ON 3-WIRE MODE POWER-UP SELECTED INTERNAL OPTIONAL 0.1�F REFERENCE REF198 EXTERNAL REFERENCE Figure 23. Typical Low Power Circuit REV. B –19– PSRR (dB) AD7851 POWER-UP TIMES When using the on-chip reference and powering up when AV DD Using an External Reference and DV are first connected, it is recommended that the DD When the AD7851 is powered up, the part is powered up power-up calibration mode be disabled as explained previously. from one of two conditions: first, when the power supplies When using the on-chip reference, the power-up time is effec- are initially powered up and; secondly, when the parts are tively the time it takes to charge up the external capacitor on the powered up from either a hardware or software power-down REF /REF pin. This time is given by the equation IN OUT (see previous section). t = 9 × R × C UP When AV and DV are powered up, the AD7851 enters a DD DD where R ≈ 150K and C = external capacitor. mode whereby the CONVST signal initiates a timeout followed The recommended value of the external capacitor is 100 nF; by a self-calibration. The total time taken for this timeout and this gives a power-up time of approximately 135 ms before a calibration is approximately 35 ms (see the Automatic Calibra- calibration is initiated and normal operation should commence. tion on Power-On section). During power-up, the functionality of the SLEEP pin is disabled, that is, the part will not power When C is fully charged, the power-up time from a hardware or REF down until the end of the calibration if SLEEP is tied logic low. software power-down reduces to 5 µs. This is because an internal The power-up calibration mode can be disabled if the user switch opens to provide a high impedance discharge path for the writes to the control register before a CONVST signal is applied. If reference capacitor during power-down—see Figure 25. An added the timeout and self-calibration are disabled, then the user advantage of the low charge leakage from the reference capacitor must take into account the time required by the AD7851 to during power-down is that even though the reference is being pow- power up before a self-calibration is carried out. This power-up ered down between conversions, the reference capacitor holds the time is the time taken for the AD7851 to power up when reference voltage to within 0.5 LSBs with throughput rates of 100 power is first applied (300 µs typ), or the time it takes the exter- samples/second and over with a full power-down between conver- nal reference to settle to the 14-bit level—whichever is longer. sions. A high input impedance op amp, such as the AD707, should be used to buffer this reference capacitor if it is being used exter- The AD7851 powers up from a full hardware or software nally. Note, if the AD7851 is left in its powered-down state for power-down in 5 µs typ. This limits the throughput which the more than 100 ms, the charge on C will start to leak away and REF part is capable of to 120 kSPS for the K Grade and 126 kSPS the power-up time will increase. If this long power-up time is a for the A Grade when powering down between conversions. problem, the user can use a partial power-down for the last conver- Figure 24 shows how power-down between conversions is sion so the reference remains powered up. implemented using the CONVST pin. The user first selects the power-down between conversions option by using the SLEEP pin and the power management bits, PMGT1 and SWITCH OPENS PMGT0, in the control register (see previous section). In this AD7851 DURING POWER-DOWN mode, the AD7851 automatically enters a full power-down at REF /REF IN OUT ON-CHIP the end of a conversion, that is, when BUSY goes low. The REFERENCE EXTERNAL falling edge of the next CONVST pulse causes the part to CAPACITOR power up. Assuming the external reference is left powered up, TO OTHER BUF CIRCUITRY the AD7851 should be ready for normal operation 5 µs after this falling edge. The rising edge of CONVST initiates a con- version so the CONVST pulse should be at least 5 µs wide. Figure 25. On-Chip Reference During Power-Down The part automatically powers down on completion of the conversion. Where the software convert start is used, the part POWER VS. THROUGHPUT RATE may be powered up in software before a conversion is initiated. The main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part START CONVERSION ON RISING EDGE at lower throughput rates. When using this mode of operation, POWER UP ON FALLING EDGE the AD7851 is only powered up for the duration of the conver- 5�s 3.25�s sion. If the power-up time of the AD7851 is taken to be 5 µs and it is assumed that the current during power up is 12 mA CONVST typ, then power consumption as a function of throughput can t CONVERT easily be calculated. The AD7851 has a conversion time of BUSY 3.25 µs with a 6 MHz external clock. This means the AD7851 consumes 12 mA typ for 8.25 µs in every conversion cycle if the POWER-UP NORMAL FULL POWER-UP TIME OPERATION POWER-DOWN TIME parts are powered down at the end of a conversion. The graph in Figure 26 shows the power consumption of the AD7851 as a Figure 24. Using the CONVST Pin to Power Up for function of throughput. Table VII lists the power consump- a Conversion tion for various throughput rates. Using the Internal (On-Chip) Reference As in the case of an external reference, the AD7851 can power up from one of two conditions: power up after the supplies are connected or power up from a hardware/software power-down. REV. B –20– AD7851 Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN) Table VII. Power Consumption vs. Throughput Type of Self- or System Calibration Time (ms) Throughput Rate Power AD7851 Full 41.7 1 kSPS 9 mW Gain + Offset 9.26 2 kSPS 18 mW Offset 4.63 Gain 4.63 100 Automatic Calibration on Power-On The CAL pin has a 0.15 µA pull-up current source connected to it 10 internally to allow for an automatic full self-calibration on power- on. A full self-calibration will be initiated on power-on if a 10 nF capacitor is connected from the CAL pin to DGND. The internal 1 current source connected to the CAL pin charges up the external capacitor and the time required to charge the external capacitor will depend on the size of the capacitor itself. This time should be 0.1 large enough to ensure that the internal reference is settled before the calibration is performed. However, if an external reference is being used, this reference must have stabilized before the auto- 0.01 matic calibration is initiated (a larger capacitor on the CAL pin 0 200 400 600 800 1000 1200 1400 1600 1800 2000 should be used if the external reference has not settled when the THROUGHPUT RATE (Hz) autocalibration is initiated). Once the capacitor on the CAL pin Figure 26. Power vs. Throughput AD7851 has charged, the calibration will be performed and will take 32 ms NOTE (4 MHz CLKIN). Therefore, the autocalibration should be com- When setting the power-down mode by writing to the part, plete before operating the part. After calibration, the part is accu- operating in an interface mode other than Interface Modes 4 rate to the 12-bit level and the specifications quoted on the data and 5 is recommended. This way the user has more control to sheet apply. There will be no need to perform another calibra- initiate power-down and power-up commands. tion unless the operating conditions change or unless a system calibration is required. CALIBRATION SECTION Self-Calibration Description Calibration Overview There are a four different calibration options within the self- The automatic calibration that is performed on power-up ensures calibration mode. There is a full self-calibration where the that the calibration options covered in this section will not be DAC, internal offset, and internal gain errors are calibrated required for a significant number of applications. The user will out; there is (Gain + Offset) self-calibration which calibrates not have to initiate a calibration unless the operating conditions out the internal gain error and then the internal offset errors change (CLKIN frequency, analog input mode, reference voltage, (the internal DAC is not calibrated here); and finally, there are temperature, and supply voltages). The AD7851 has a number of self-offset and self-gain calibrations that calibrate out the inter- calibration features that may be required in some applications, nal offset errors and the internal gain errors, respectively. and there are a number of advantages in performing these differ- The internal capacitor DAC is calibrated by trimming each of the ent types of calibration. First, the internal errors in the ADC can capacitors in the DAC. It is the ratio of these capacitors to each be reduced significantly to give superior dc performance; and other that is critical, and so the calibration algorithm ensures second, system offset and gain errors can be removed. This allows that this ratio is at a specific value by the end of the calibration the user to remove reference errors (whether internal or external routine. For the offset and gain there are two separate capaci- references) and to make use of the full dynamic range of the tors, one of which is trimmed when an offset or gain calibration AD7851 by adjusting the analog input range of the part for a is performed. Again, it is the ratio of these capacitors to the specific system. capacitors in the DAC that is critical and the calibration algo- The AD7851 has two main calibration modes: self-calibration rithm ensures that this ratio is at a specified value for both and system calibration. There are various options in both self- the offset and gain calibrations. calibration and system calibration as outlined previously in In bipolar mode, the midscale error is adjusted for an offset cali- Table III. All the calibration functions can be initiated by puls- bration and the positive full-scale error is adjusted for the gain ing the CAL pin or by writing to the control register and setting calibration; in unipolar mode, the zero-scale error is adjusted for the STCAL bit to 1. The timing diagrams that follow involve an offset calibration and the positive full-scale error is adjusted using the CAL pin. for a gain calibration. The duration of each of the different types of calibrations is given in Table VIII for the AD7851 with a 6 MHz/7 MHz mas- ter clock. These calibration times are master-clock dependent. REV. B –21– POWER (mW) AD7851 Self-Calibration Timing MAX SYSTEM FULL SCALE Figure 27 shows the timing for a full self-calibration. Here the IS ±2.5% FROM V REF BUSY line stays high for the full length of the self-calibration. A V + SYS OFFSET REF self-calibration is initiated by bringing the CAL pin low (which V – 1LSB V – 1LSB REF REF initiates an internal reset) and then high again or by writing to SYSTEM OFFSET ANALOG ANALOG the control register and setting the STCAL bit to 1 (note that if INPUT INPUT RANGE the part is in a power-down mode, the CAL pulse width must RANGE CALIBRATION take account of the power-up time). The BUSY line is triggered SYS OFFSET SYS OFFSET high from the rising edge of CAL (or the end of the write to the AGND AGND control register if calibration is initiated in the software), and MAX SYSTEM OFFSET MAX SYSTEM OFFSET BUSY will go low when the full self-calibration is complete after IS ±5% OF V IS ±5% OF V REF REF a time t . CAL Figure 28. System Offset Calibration Figure 29 shows a system gain calibration (assuming a system t = 100ns MIN, 1 full scale greater than the reference voltage) where the analog t = 2.5 t MAX, 15 CLKIN t = 250026 t CAL CLKIN input range has been increased after the system gain calibration t 1 is completed. A system full-scale voltage less than the reference CAL (I/P) voltage may also be accounted for a by a system gain calibration. t 15 BUSY (O/P) MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE IS ±2.5% FROM V IS ±2.5% FROM V REF REF t CAL SYS FULL S. SYS FULL S. Figure 27. Timing Diagram for Full Self-Calibration V – 1LSB V – 1LSB REF REF SYSTEM GAIN For the self-(gain + offset), self-offset, and self-gain calibrations, ANALOG ANALOG INPUT the BUSY line will be triggered high by the rising edge of the INPUT RANGE RANGE CALIBRATION CAL signal (or the end of the write to the control register if cali- AGND bration is initiated in the software) and will stay high for the full AGND duration of the self-calibration. The length of time that the BUSY Figure 29. System Gain Calibration is high will depend on the type of self-calibration that is initiated. Finally in Figure 30 both the system offset and gain are accounted Typical figures are given in Table VIII. The timing diagrams for for by the system offset followed by a system gain calibration. the other self-calibration options will be similar to Figure 27. First the analog input range is shifted upwards by the positive System Calibration Description system offset and then the analog input range is adjusted at the System calibration allows the user to take out system errors top end to account for the system full scale. external to the AD7851 as well as calibrate the errors of the AD7851 itself. The maximum calibration range for the system MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE IS ±2.5% FROM V IS ±2.5% FROM V offset errors is ±5% of V and for the system gain errors is REF REF REF ±2.5% of V . This means that the maximum allowable system REF V + SYS OFFSET REF SYS F.S. SYS F.S. offset voltage applied between the AIN(+) and AIN(–) pins for V – 1LSB V – 1LSB REF REF the calibration to adjust out this error is ±0.05 × V (that is, REF SYSTEM OFFSET the AIN(+) can be 0.05 × V above AIN(–) or 0.05 × V REF REF CALIBRATION ANALOG ANALOG FOLLOWED BY INPUT below AIN(–)). For the system gain error, the maximum allow- INPUT RANGE RANGE able system full-scale voltage, in unipolar mode, that can be SYSTEM GAIN applied between AIN(+) and AIN(–) for the calibration to SYS OFFSET CALIBRATION AGND adjust out this error is V ± 0.025 × V (that is, the AIN(+) REF REF SYS OFFSET AGND can be V + 0.025 × V above AIN(–) or V – 0.025 × MAX SYSTEM OFFSET REF REF REF IS ±5% OF V REF V above AIN(–)). If the system offset or system gain errors REF MAX SYSTEM OFFSET IS ±5% OF V REF are outside the ranges mentioned, the system calibration algo- rithm will reduce the errors as much as the trim range allows. Figure 30. System (Gain + Offset) Calibration Figures 28, 29, and 30 illustrate why a specific type of system calibration might be used. Figure 28 shows a system offset calibration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. A negative offset may also be accounted for by a system offset calibration. REV. B –22– AD7851 System Gain and Offset Interaction Next, the system offset voltage is applied to the AIN pin for a The inherent architecture of the AD7851 leads to an interaction minimum setup time (t ) of 100 ns before the rising edge of SETUP between the system offset and gain errors when a system calibra- the CONVST and remains until the BUSY signal goes low. The tion is performed. Therefore, it is recommended to perform the rising edge of the CONVST starts the system offset calibration cycle of a system offset calibration followed by a system gain cali- section of the full system calibration and also causes the BUSY bration twice. Separate system offset and system gain calibrations signal to go high. The BUSY signal will go low after a time t CAL2 reduce the offset and gain errors to at least the 14-bit level. By when the calibration sequence is complete. performing a system offset calibration first and a system gain The timing for a system (gain + offset) calibration is very similar calibration second, priority is given to reducing the gain error to to that of Figure 31, the only difference being that the time zero before reducing the offset error to zero. If the system errors t will be replaced by a shorter time of the order of t as CAL1 CAL2 are small, a system offset calibration would be performed, fol- the internal DAC will not be calibrated. The BUSY signal will lowed by a system gain calibration. If the systems errors are signify when the gain calibration is finished and when the part is large (close to the specified limits of the calibration range), this ready for the offset calibration. cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 14-bit level. The advantage of t = 100ns MIN, t = 50 MAX, 1 14 doing separate system offset and system gain calibrations is that t = 4 t MAX, t = 222228 t MAX, 15 CLKIN CAL1 CLKIN the user has more control over when the analog inputs need to t = 27798 t CAL2 CLKIN be at the required levels, and the CONVST signal does not have t 1 to be used. CAL (I/P) Alternatively, a system (gain + offset) calibration can be per- t 15 formed. It is recommended to perform three system (gain + BUSY (O/P) offset) calibrations to reduce the offset and gain errors to the t t CAL1 CAL2 t 16 14-bit level. For the system (gain + offset) calibration priority CONVST (I/P) is given to reducing the offset error to 0 before reducing the t SETUP gain error to 0. Thus, if the system errors are small then two AIN (I/P) V V SYSTEM FULL SCALE OFFSET system (gain + offset) calibrations will be sufficient. If the Figure 31. Timing Diagram for Full System Calibration system errors are large (close to the specified limits of the calibration range), three system (gain + offset) calibrations The timing diagram for a system offset or system gain calibration is may be required to reduce the offset and gain errors to at shown in Figure 32. Here again the CAL is pulsed and the rising least the 14-bit level. There will never be any need to perform edge of the CAL initiates the calibration sequence (or the calibra- more than three system (offset + gain) calibrations. tion can be initiated in software by writing to the control register). The rising edge of the CAL causes the BUSY line to go high and it In bipolar mode, the midscale error is adjusted for an offset cali- will stay high until the calibration sequence is finished. The analog bration and the positive full-scale error is adjusted for the gain input should be set at the correct level for a minimum setup time calibration; in unipolar mode, the zero-scale error is adjusted for (t ) of 100 ns before the rising edge of CAL and stay at the SETUP an offset calibration and the positive full-scale error is adjusted correct level until the BUSY signal goes low. for a gain calibration. System Calibration Timing t 1 The calibration timing diagram in Figure 31 is for a full system CAL (I/P) calibration where the falling edge of CAL initiates an internal t 15 reset before starting a calibration (note that if the part is in power- BUSY (O/P) down mode the CAL pulse width must take account of the power-up time). If a full system calibration is performed in the software, it t CAL2 t SETUP is easier to perform separate gain and offset calibrations so V OR V AIN (I/P) SYSTEM FULL SCALE SYSTEM OFFSET that the CONVST bit in the control register does not have to be programmed in the middle of the system calibration sequence. Figure 32. Timing Diagram for System Gain or System The rising edge of CAL starts calibration of the internal DAC Offset Calibration and causes the BUSY line to go high. If the control register is set for a full system calibration, the CONVST must be used also. The full-scale system voltage should be applied to the ana- log input pins from the start of calibration. The BUSY line will go low once the DAC and system gain calibration are complete. REV. B –23– AD7851 SERIAL INTERFACE SUMMARY SM1 and SM2. Interface Mode 1 may only be set by program- Table IX details the five interface modes and the serial clock ming the control register (see the Control Register section). edges from which the data is clocked out by the AD7851 External SCLK and SYNC signals (SYNC may be hardwired (DOUT edge) and that the data is latched in on (DIN edge). low) are required for Interfaces Modes 1, 2, and 3. In Interface The logic level of the POLARITY pin is shown and it is clear Modes 4 and 5, the AD7851 generates the SCLK and SYNC. that this reverses the edges. Some of the more popular µProcessors, µControllers, and the In Interface Modes 4 and 5 the SYNC always clocks out the DSP machines that the AD7851 will interface to directly are first data bit and SCLK will clock out the subsequent bits. mentioned here. This does not cover all µCs, µPs, and DSPs. The interface mode of the AD7851 that is mentioned here for a In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK specific µC, µP, or DSP is only a guide and in most cases another and the POLARITY pin. Thus, the SYNC may clock out the interface mode may work just as well. MSB of data. Subsequent bits will be clocked out by the serial clock, SCLK. The conditions for the SYNC clocking out the A more detailed timing description on each of the interface MSB of data is as follows. modes follows. With the POLARITY pin high, the falling edge of SYNC will Table X. Interface Mode Description clock out the MSB if the serial clock is low when the SYNC goes low. SM1 SM2 �Processor Interface With the POLARITY pin low, the falling edge of SYNC will Pin Pin �Controller Mode clock out the MSB if the serial clock is high when the SYNC 00 8XC51 1 (2-Wire) goes low. 8XL51 DIN Is an Input/ PIC17C42 Output Pin Table IX. SCLK Active Edge for Different Interface Modes 00 68HC11 2 (3-Wire, SPI/QSPI) Interface POLARITY DOUT DIN 68L11 Default Mode Mode Pin Edge Edge 01 68HC16 3 (QSPI) 1, 2, 3 0 SCLK ↑ SCLK ↓ PIC16C64 External Serial 1SCLK ↓ SCLK ↑ ADSP-21xx Clock, SCLK, and DSP56000 External Frame Sync, 4, 5 0 SCLK ↓ SCLK ↑ DSP56001 SYNC Are Required 1SCLK ↑ SCLK ↓ DSP56002 DSP56L002 Resetting the Serial Interface TMS320C30 When writing to the part via the DIN line there is the possibility of writing data into the incorrect registers, such as the test regis- 10 68HC16 4 (DSP Is Slave) ter for instance, or writing the incorrect data and corrupting the AD7851 Generates a serial interface. The SYNC pin acts as a reset. Bringing the Noncontinuous SYNC pin high resets the internal shift register. The first data (16 Clocks) Serial bit after the next SYNC falling edge will now be the first bit of Clock, SCLK, and the a new 16-bit transfer. It is also possible that the test register Frame Sync, SYNC contents were altered when the interface was lost. Therefore, once the serial interface is reset, it may be necessary to write 11 ADSP-21xx 5 (DSP Is Slave) the 16-bit word 0100 0000 0000 0010 to restore the test regis- DSP56000 AD7851 Generates a ter to its default value. Now the part and serial interface are DSP56001 Continuous Serial completely reset. It is always useful to retain the ability to pro- DSP56002 Clock, SCLK, and the gram the SYNC line from a port of the µController/DSP to have DSP56L002 Frame Sync, SYNC the ability to reset the serial interface. TMS320C20 TMS320C25 Table X summarizes the interface modes provided by the TMS320C30 AD7851. It also outlines the various µP/µC to which the par- TMS320C5X ticular interface is suited. TMS320LC5X The interface mode is determined by the serial mode selection Pins SM1 and SM2. Interface Mode 2 is the default mode. Note that Interface Mode 1 and 2 have the same combination of REV. B –24– AD7851 DETAILED TIMING SECTION continuous SCLK shown by the dotted waveform in Figure 33 Mode 1 (2-Wire 8051 Interface) can be used provided the SYNC is low for only 16 clock pulses The read and writing takes place on the DIN line and the conver- in each of the read and write cycles. The POLARITY pin may sion is initiated by pulsing the CONVST pin (note that in every be used to change the SCLK edge which the data is sampled on write cycle the 2/3 MODE bit must be set to 1). The conversion and clocked out on. may be started by setting the CONVST bit in the control register In Figure 34, the SYNC line is tied low permanently, which to 1 instead of using the CONVST line. results in a different timing arrangement. With SYNC tied low Below in Figure 33 and in Figure 34 are the timing diagrams for permanently, the DIN pin will never be three-stated. The 16th Interface Mode 1 in the 2-wire interface mode. Here the DIN pin rising edge of SCLK configures the DIN pin as an input or an is used for both input and output as shown. The SYNC input is output as shown in the diagram. Here no more than 16 SCLK level-triggered active low and can be pulsed (Figure 33) or can be pulses must occur for each of the read and write operations. constantly low (Figure 34). If reading from and writing to the calibration registers in this In Figure 33, the part samples the input data on the rising edge interface mode, all the selected calibration registers must be of SCLK. After the 16th rising edge of SCLK, the DIN is con- read from or written to. The read and write operations cannot figured as an output. When the SYNC is taken high, the DIN is be aborted. When reading from the calibration registers, the three-stated. Taking SYNC low disables the three-state on the DIN pin will remain as an output for the full duration of all DIN pin and the first SCLK falling edge clocks out the first data the calibration register read operations. When writing to the bit. Once the 16 clocks have been provided, the DIN pin will calibration registers, the DIN pin will remain as an input for automatically revert back to an input after a time t . Note that a the full duration of all the calibration register write operations. 14 t = –0.4 t MIN (NONCONTINUOUS SCLK) �0.4 t MIN/MAX (CONTINUOUS SCLK), 3 SCLK SCLK t = 45 MAX, t = 30ns MIN, t = 20 MIN POLARITY PIN 6 7 8 LOGIC HIGH SYNC (I/P) t 3 t t t 3 11 11 116 1 16 SCLK (I/P) t t 5A t 7 14 t t 12 t 6 t 6 8 DIN (I/O) DB15 DB0 DB15 DB0 THREE-STATE DATA READ DATA WRITE DIN BECOMES AN OUTPUT DIN BECOMES AN INPUT Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (Interface Mode 1, SM1 = SM2 = 0) t = 45 MAX, t = 30ns MIN, t = 20 MIN, 6 7 8 t = 90 MAX, t = 50ns MAX 13 14 POLARITY PIN LOGIC HIGH 6 116 1 16 SCLK (I/P) t t 7 14 t t t 13 6 t 6 8 DIN (I/O) DB15 DB0 DB15 DB0 DATA READ DATA WRITE DIN BECOMES AN INPUT Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low (Interface Mode 1, SM1 = SM2 = 0) REV. B –25– AD7851 Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) Default Interface Mode Figure 36 shows the timing diagram for Interface Mode 3. In Figure 35 shows the timing diagram for Interface Mode 2 which this mode, the DSP is the master and the part is the slave. Here is the SPI/QSPI interface mode. Here the SYNC input is active the SYNC input is edge triggered from high to low, and the 16 low and may be pulsed or tied permanently low. If SYNC is clock pulses are counted from this edge. Because the clock permanently low, 16 clock pulses must be applied to the SCLK pulses are counted internally, the SYNC signal does not have to pin for the part to operate correctly, and with a pulsed SYNC go high after the 16th SCLK rising edge as shown by the dotted input a continuous SCLK may be applied provided SYNC is SYNC line. Thus a frame sync that gives a high pulse of one low for only 16 SCLK cycles. In Figure 35, the SYNC going SCLK cycle minimum duration at the beginning of the read/ low disables the three-state on the DOUT pin. The first falling write operation may be used. The rising edge of SYNC enables edge of the SCLK after the SYNC going low clocks out the first the three-state on the DOUT pin. The falling edge of SYNC leading zero on the DOUT pin. The DOUT pin is three-stated disables the three-state on the DOUT pin, and data is clocked again a time t after the SYNC goes high. With the DIN pin, out on the falling edge of SCLK. Once SYNC goes high, the 12 the data input has to be set up a time t before the SCLK rising three-state on the DOUT pin is enabled. The data input is 7 edge as the part samples the input data on the SCLK rising edge sampled on the rising edge of SCLK and thus has to be valid a in this case. The POLARITY pin may be used to change the time t before this rising edge. The POLARITY pin may be 7 SCLK edge which the data is sampled on and clocked out on. If used to change the SCLK edge which the data is sampled on resetting the interface is required, the SYNC must be taken high and clocked out on. If resetting the interface is required, the and then low. SYNC must be taken high and then low. t = –0.4 t MIN (NONCONTINUOUS SCLK) ±0.4 t MIN/MAX (CONTINUOUS SCLK), 3 CLKIN SCLK t = 45ns MAX, t = 30ns MIN, t = 20ns MIN, t = 30ns MIN (NONCONTINUOUS SCLK), 6 7 8 11 POLARITY PIN 30/0.4 t = ns MIN/MAX (CONTINUOUS SCLK) SCLK LOGIC HIGH SYNC (I/P) t t t 9 3 11 16 234 5 SCLK (I/P) 16 t 5 t 10 t t t 6 12 6 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 t 7 t t 8 8 DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output, and SYNC Input (SM1 = SM2 = 0) t = –0.4 t MIN (NONCONTINUOUS SCLK) ±0.4 t MIN/MAX (CONTINUOUS SCLK), 3 CLKIN SCLK POLARITY PIN t = 45ns MAX, t = 30ns MIN, t = 20ns MIN, t = 30ns MIN 6 7 8 11 LOGIC HIGH SYNC (I/P) t t t 9 3 11 16 2345 16 SCLK (I/P) t t 5 10 t t t 6 12 6 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 t 7 t t 8 8 DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1) REV. B –26– AD7851 MODE 4 and 5 (Self-Clocking Modes) this time, the conversion will be complete, the SYNC will go The timing diagrams in Figure 38 and Figure 39 are for Inter- high, and the BUSY will go low. The next falling edge of the face Modes 4 and 5. Interface Mode 4 has a noncontinuous CONVST must occur at least 330 ns after the falling edge of SCLK output and Interface Mode 5 has a continuous SCLK BUSY to allow the track-and-hold amplifier adequate acquisi- output (SCLK is switched off internally during calibration for tion time as shown in Figure 38. This gives a throughput time of both Modes 4 and 5). These modes of operation are especially 3.68 µs. The maximum throughput rate in this case is 272 kHz. different from all the other modes because the SCLK and OUTPUT SERIAL SHIFT SYNC are outputs. The SYNC is generated by the part as is the REGISTER IS RESET t 1 SCLK. The master clock at the CLKIN pin is routed directly to CONVST (I/P) the SCLK pin for Interface Mode 5 (continuous SCLK) and the CLKIN signal is gated with the SYNC to give the SCLK (non- BUSY continuous) for Interface Mode 4. (O/P) SYNC The most important point about these two modes of operation (O/P) is that the result of the current conversion is clocked out during SCLK the same conversion and a write to the part during this conver- (O/P) sion is for the next conversion. The arrangement is shown in t = 3.25�s CONVERT 400ns MIN Figure 37. Figure 38 and Figure 39 show more detailed timing CONVERSION IS INITIATED SERIAL READ READ OPERATION for the arrangement of Figure 37. AND TRACK-AND-HOLD AND WRITE SHOULD END 500ns GOES INTO HOLD OPERATIONS PRIOR TO NEXT RISING THE CONVERSION RESULT DUE TO EDGE OF CONVST WRITE N+1 IS READ HERE t = 100ns MIN CONVERSION ENDS 1 WRITE N+1 WRITE N+2 WRITE N+3 3.25�s LATER Figure 38. Mode 4 and 5 Timing Diagram (SM1 = 1, READ N READ N+1 READ N+2 SM2 = 1 and 0) CONVERSION N CONVERSION N+1 CONVERSION N+2 In these interface modes, the part is now the master and the 3.25�s 3.25�s 3.25�s DSP is the slave. Figure 39 is an expansion of Figure 38. The Figure 37. AD7851 will ensure SYNC goes low after the rising edge C of the continuous SCLK (Interface Mode 5) in Figure 39. Only in In Figure 38 the first point to note is that the BUSY, SYNC, the case of a noncontinuous SCLK (Interface Mode 4) will the and SCLK are all outputs from the AD7851 with the CONVST time t apply. The first data bit is clocked out from the falling 4 being the only input signal. Conversion is initiated with the edge of SYNC. The SCLK rising edge clocks out all subsequent CONVST signal going low. This CONVST falling edge also bits on the DOUT pin. The input data present on the DIN pin triggers the BUSY to go high. The CONVST signal rising edge is clocked in on the rising edge of the SCLK. The POLARITY triggers the SYNC to go low after a short delay (2.5 t to CLKIN pin may be used to change the SCLK edge which the data is 3.5 t typically) after which the SCLK will clock out the CLKIN sampled on and clocked out on. The SYNC will go high after data on the DOUT pin during conversion. The data on the DIN the 16th SCLK rising edge and before the falling edge D of the pin is also clocked in to the AD7851 by the same SCLK for the continuous SCLK in Figure 39. This ensures the part will not next conversion. The read/write operations must be complete clock in an extra bit from the DIN pin or clock out an extra bit after 16 clock cycles (which takes 3.25 µs approximately from on the DOUT pin. the rising edge of CONVST assuming a 6 MHz CLKIN). At t = 0.6 t (NONCONTINUOUS SCLK), t = 45ns MAX, 4 SCLK 6 POLARITY PIN t = 30ns MIN, t = 20ns MIN , t = 50ns MAX 7 8 11A LOGIC HIGH SYNC (O/P) t t C t 4 11A 9 D 16 23 45 SCLK (O/P) 16 t t 10 t t 5 6 12 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 t 7 t 8 t 8 DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0 Figure 39. Mode 4 and 5 Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and Noncontinuous, SM1 = 1, SM2 = 1 and 0) REV. B –27– AD7851 If the user has control of the CONVST pin but does not want to CONFIGURING THE AD7851 exercise it for every conversion, the control register may be used AD7851 as a Read-Only ADC to start a conversion. Setting the CONVST bit in the control The AD7851 contains 14 on-chip registers that can be accessed register to 1 starts a conversion. If the user does not have con- via the serial interface. In the majority of applications, it will not trol of the CONVST pin, a conversion should not be initiated be necessary to access all of these registers. Figure 40 outlines the by writing to the control register. The reason for this is that the sequence used to configure the AD7851 as a read-only ADC. In user may get locked out and not be able to perform any further this case, there is no writing to the on-chip registers and only the write/read operations. When a conversion is started by writing to conversion result data is read from the part. Interface Mode 1 the control register, the SYNC goes low and read/write opera- cannot be used in this case as it is necessary to write to the con- tions take place while the conversion is in progress. However, trol register to set Interface Mode 1. Here the CLKIN signal is once the conversion is complete, there is no way of writing to applied directly after power-on; the CLKIN signal must be the part unless the CONVST pin is exercised. The CONVST present to allow the part to perform a calibration. This automatic signal triggers the SYNC signal low which allows read/write calibration will be completed approximately 42 ms after the operations to take place. SYNC must be low to perform read/ AD7851 has powered up (6 MHz CLK). write operations. The SYNC is triggered low by the CONVST signal rising edge or by setting the CONVST bit in the control register to 1. Therefore, if there is not full control of the CONVST pin, the user may become locked out. START DIN CONNECTED TO DGND POWER ON, APPLY CLKIN SIGNAL, WAIT FOR AUTOMATIC CALIBRATION SERIAL 4, 5 INTERFACE MODE ? 2, 3 PULSE CONVST PIN PULSE CONVST PIN READ DATA YES DURING SYNC AUTOMATICALLY GOES LOW CONVERSION AFTER CONVST RISING EDGE ? NO WAIT APPROXIMATELY 200ns AFTER CONVST RISING EDGE WAIT FOR BUSY SIGNAL TO GO LOW SCLK AUTOMATICALLY ACTIVE, READ CONVERSION RESULT ON DOUT PIN APPLY SYNC (IF REQUIRED), SCLK, AND READ CONVERSION RESULT ON DOUT PIN Figure 40. Flowchart for Setting Up and Reading from the AD7851 REV. B –28– AD7851 Writing to the AD7851 ence is made to the BUSY bit equal to a Logic 0, to indicate the For accessing the on-chip registers, it is necessary to write to the end of conversion, the user in this case would poll the BUSY bit part. To enable Serial Interface Mode 1, the user must also write in the status register. to the part. Figures 41, 42, and 43 shows how to configure the Interface Modes 2 and 3 Configuration AD7851 for each of the different serial interface modes. The Figure 41 shows the flowchart for configuring the part in Inter- continuous loops on all diagrams indicate the sequence for more face Modes 2 and 3. For these interface modes, the read and than one conversion. The options of using a hardware (pulsing write operations take place simultaneously via the serial port. the CONVST pin) or software (setting the CONVST bit to 1) Writing all 0s ensures that no valid data is written to any of the conversion start, and reading/writing during or after conversion registers. When using the software conversion start and transfer- are shown in Figures 41 and 42. If the CONVST pin is never ring data during conversion, the Figure 41 note must be obeyed. used, then it should be tied to DV permanently. Where refer- DD START POWER ON, APPLY CLKIN SIGNAL, WAIT FOR AUTOMATIC CALIBRATION NOTE: WHEN USING THE SOFTWARE CONVERSION START AND SERIAL INTERFACE TRANSFERRING DATA DURING CONVERSION, THE USER MUST ENSURE MODE THE CONTROL REGISTER WRITE OPERATION EXTENDS BEYOND THE ? FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE NEXT CONVERSION. 2, 3 INITIATE CONVERSION YES IN SOFTWARE ? NO TRANSFER YES DATA DURING PULSE CONVST PIN CONVERSION NO TRANSFER YES DATA APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL DURING CONVERSION REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS ? CONVERSION RESULT ON DOUT PIN (SEE NOTE) WAIT APPROXIMATELY 200ns NO AFTER CONVST RISING EDGE APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL REGISTER SETTING CONVST BIT TO 1, READ CURRENT CONVERSION RESULT ON DOUT PIN WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 WAIT FOR BUSY SIGNAL TO GO LOW APPLY SYNC (IF REQUIRED), OR WAIT FOR BUSY BIT = 0 SCLK, READ PREVIOUS CONVERSION RESULT ON DOUT PIN, AND WRITE ALL 0s ON DIN PIN APPLY SYNC (IF REQUIRED), SCLK, READ CURRENT CONVERSION RESULT ON DOUT PIN, AND WRITE ALL 0s ON DIN PIN Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3 REV. B –29– AD7851 Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration Figure 42 shows the flowchart for configuring the part in Inter- Figure 43 shows the flowchart for configuring the AD7851 in face Mode 1. This mode of operation can only be enabled by Interface Modes 4 and 5, the self-clocking modes. In this case, it writing to the control register and setting the 2/3 MODE bit. is not recommended to use the software conversion start option. Reading and writing cannot take place simultaneously in this The read and write operations always occur simultaneously and mode as the DIN pin is used for both reading and writing. during conversion. START START POWER ON, APPLY CLKIN SIGNAL, POWER ON, APPLY CLKIN SIGNAL, WAIT FOR AUTOMATIC CALIBRATION WAIT FOR AUTOMATIC CALIBRATION SERIAL SERIAL INTERFACE INTERFACE MODE MODE ? ? 4, 5 1 PULSE CONVST PIN INITIATE YES CONVERSION IN SOFTWARE SYNC AUTOMATICALLY GOES ? APPLY SYNC (IF REQUIRED), LOW AFTER CONVST RISING EDGE SCLK, WRITE TO CONTROL REGISTER SETTING THE 2-WIRE MODE NO AND CONVST BIT TO 1 SCLK AUTOMATICALLY ACTIVE, READ CURRENT APPLY SYNC (IF REQUIRED), CONVERSION RESULT ON DOUT PIN, WRITE SCLK, WRITE TO CONTROL REGISTER TO CONTROL REGISTER ON DIN PIN SETTING THE 2-WIRE MODE Figure 43. Flowchart for Setting Up, Reading, and Writing PULSE CONVST PIN in Interface Modes 4 and 5 READ DATA YES DURING CONVERSION ? WAIT APPROXIMATLY 200ns AFTER CONVST RISING EDGE NO OR AFTER END OF CONTROL REGISTER WRITE WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 APPLY SYNC (IF REQUIRED), SCLK, READ PREVIOUS CONVERSION RESULT ON DIN PIN APPLY SYNC (IF REQUIRED), SCLK, READ CURRENT CONVERSION RESULT ON DIN PIN Figure 42. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1 REV. B –30– AD7851 MICROPROCESSOR INTERFACING OPTIONAL AD7851 In many applications, the user may not require the facility of 7MHz/6MHz CONVST writing to the on-chip registers. The user may just want to (8XC51/L51) CLKIN /PIC17C42 hardwire the relevant pins to the appropriate levels and read SCLK P3.1/CK the conversion result. In this case, the DIN pin can be tied low MASTER DIN P3.0/DT so that the on-chip registers are never used. Now the part will OPTIONAL (INT0/P3.2)/INT BUSY operate as a nonprogrammable analog-to-digital converter where SLAVE SYNC the CONVST is applied, a conversion is performed, and the result SM1 may be read using the SCLK to clock out the data from the output SM2 register on to the DOUT pin. Note that the DIN pin cannot be tied low when using the 2-wire interface mode of operation. DGND FOR 8XC51/L51 POLARITY DV FOR PIC17C42 The SCLK can also be connected to the CLKIN pin if the user DD does not want to have to provide separate serial and master Figure 45. 8XC51/PIC17C42 Interface clocks in Interface Modes 1, 2, and 3. With this arrangement, AD7851 to 68HC11/16/L11/PIC16C42 Interface the SYNC signal must be low for 16 SCLK cycles in Interface Figure 46 shows the AD7851 SPI/QSPI interface to the Modes 1 and 2 for the read and write operations. For Interface 68HC11/16/L11/PIC16C42. The SYNC line is not used and is Mode 3, the SYNC can be low for more than 16 SCLK cycles tied to DGND. The µController is configured as the master by for the read and write operations. Note that in Interface Modes 4 setting the MSTR bit in the SPCR to 1, and thus provides the and 5 the CLKIN and SCLK cannot be tied together as the serial clock on the SCK pin. For all the µControllers, the CPOL SCLK is an output and the CLKIN is an input. bit is set to 1, and for the 68HC11/16/L11, the CPHA bit is set to 1. The CLKIN and CONVST signals can be supplied from CONVERSION CONVST the µController or from separate sources. The BUSY signal can START be used as an interrupt to tell the µController when the conver- 7 MHz/6MHz CLKIN MASTER sion is finished, then the reading and writing can take place. If SCLK CLOCK required, the reading and writing can take place during conver- AD7851 SYNC SIGNAL SYNC TO GATE sion and there will be no need for the BUSY signal in this case. THE SCLK For no writing to the part then the DIN pin can be tied perma- DIN nently low. For the 68HC16 and the QSPI interface, the SM2 SERIAL DATA DOUT OUTPUT pin should be tied high and the SS line tied to the SYNC pin. The microsequencer on the 68HC16 QSPI port can be used for Figure 44. Simplified Interface Diagram with DIN performing a number of read and write operations independent Grounded and SCLK Tied to CLKIN of the CPU and storing the conversion results in memory with- AD7851 to 8XC51/PIC17C42 Interface out taxing the CPU. The typical sequence of events would be Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42, writing to the control register via the DIN line setting a conversion which only runs at 5 V. The 8XC51 is in Mode 0 operation. start and at the same time reading data from the previous conver- This is a 2-wire interface consisting of the SCLK and the DIN sion on the DOUT line, wait for the conversion to be finished which acts as a bidirectional line. The SYNC is tied low. The (3.25 µs with 6 MHz CLKIN), and then repeat the sequence. The BUSY line can be used to give an interrupt driven system but maximum serial frequency will be determined by the data access this would not normally be the case with the 8XC51/PIC17C42. and hold times of the µControllers and the AD7851. For the 8XC51, 12 MHz version, the serial clock will run at a maximum of 1 MHz so that the serial interface to the AD7851 OPTIONAL AD7851 will only be running at 1 MHz. The CLKIN signal must be pro- 7MHz/6MHz CONVST 68HC11/16/ vided separately to the AD7851 from a port line on the 8XC51 DV L11/PIC16C42 DD CLKIN or from a source other than the 8XC51. Here the SCLK cannot SPI HC16, QSPI SYNC SS be tied to the CLKIN as the 8XC51 only provides a noncon- SCK SCLK tinuous serial clock. The CONVST signal can be provided from an external timer or conversion can be started in software if MISO DOUT required. The sequence of events would typically be writing to IRQ MASTER BUSY the control register via the DIN line setting a conversion start OPTIONAL MOSI DIN SLAVE and the 2-wire interface mode (this would be performed in two SM1 8-bit writes), wait for the conversion to be finished (3.25 µs with DIN AT DGND FOR NO WRITING TO PART 6 MHz CLKIN), read the conversion result data on the DIN line DV FOR HC11, SPI DD SM2 (this would be performed in two 8-bit reads), and then repeat the DGND FOR HC16, QSPI sequence. The maximum serial frequency will be determined by POLARITY DV DD the data access and hold times of the 8XC51/PIC17C42 and the Figure 46. 68HC11 and 68HC16 Interface AD7851. REV. B –31– AD7851 AD7851 to ADSP-21xx Interface OPTIONAL AD7851 Figure 47 shows the AD7851 interface to the ADSP-21xx. The 7MHz/6MHz CONVST ADSP-21xx is the slave and the AD7851 is the master. The DSP CLKIN AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in 56000/1/2/L002 SCK SCLK the serial port control register should be set up as TFSR = RFSR SRD DOUT = 1 (need a frame sync for every transfer), SLEN = 15 (16-bit SYNC word length), TFSW = RFSW = 1 (alternate framing mode for SC2 OPTIONAL transmit and receive operations), INVRFS = INVTFS = 1 (active IRQ BUSY MASTER OPTIONAL low RFS and TFS), IRFS = ITFS = 0 (external RFS and TFS), STD DIN and ISCLK = 0 (external serial clock). The CLKIN and SLAVE DIN AT DGND FOR CONVST signals could be supplied from the ADSP-21xx or SM1 NO WRITING TO PART from an external source. The AD7851 supplies the SCLK and SM2 DV DD the SYNC signals to the ADSP-21xx and the reading and writing POLARITY takes place during conversion. The BUSY signal only indicates Figure 48. DSP56000/1/2/L002 Interface when the conversion is finished and may not be required. The data access and hold times of the ADSP-21xx and the AD7851 AD7851 to TMS320C20/25/5x/LC5x Interface allow for a CLKIN of 7 MHz/6 MHz with a 5 V supply. Figure 49 shows the AD7851 to the TMS320Cxx interface. The AD7851 is the master and operates in Interface Mode 5. For the OPTIONAL TMS320Cxx, the CLKX, CLKR, FSX, and FSR pins should all AD7851 7MHz/6MHz be configured as inputs. The CLKX and the CLKR should be CONVST connected together as should the FSX and FSR. Because the CLKIN ADSP-21xx AD7851 is the master and the reading and writing occurs during SCK SCLK the conversion, the BUSY only indicates when the conversion is DR DOUT finished and thus may not be required. Again the data access and RFS SYNC hold times of the TMS320Cxx and the AD7851 allow for a TFS SLAVE CLKIN of 7 MHz/6 MHz. OPTIONAL IRQ BUSY OPTIONAL DIN DT MASTER OPTIONAL AD7851 TMS320C20/ 7MHz/6MHz CONVST SM1 25/5x/LC5x DIN AT DGND FOR CLKIN NO WRITING TO PART CLKX SM2 CLKR SCLK POLARITY DV DD DR DOUT SYNC FSR Figure 47. ADSP-21xx Interface SLAVE FSX MASTER OPTIONAL AD7851 to DSP56000/1/2/L002 Interface INT0 BUSY OPTIONAL Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface. DT DIN Here the DSP5600x is the master and the AD7851 is the slave. SM1 DIN AT DGND FOR The AD7851 is in Interface Mode 3. The setting of the bits in NO WRITING TO PART SM2 the registers of the DSP5600x would be for synchronous opera- POLARITY DV DD tion (SYN = 1), internal frame sync (SCD2 = 1), internal clock (SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames Figure 49. TMS320C20/25/5x Interface sync only active at beginning of the transfer (FSL1 = 0, FSL0 = 1). A gated clock can be used (GCK = 1) or if the SCLK is to be tied to the CLKIN of the AD7851, then there must be a con- tinuous clock (GCK = 0). Again the data access and hold times of the DSP5600x and the AD7851 should allow for an SCLK of 7 MHz/6 MHz. REV. B –32– AD7851 APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance The analog and digital supplies to the AD7851 are independent The recommended layout for the AD7851 is outlined in the and separately pinned out to minimize coupling between the evaluation board for the AD7851. The evaluation board package analog and digital sections of the device. The part has very good includes a fully assembled and tested evaluation board, documen- immunity to noise on the power supplies as can be seen by the tation, and software for controlling the board from the PC via the PSRR versus frequency graph. However, care should still be EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD taken with regard to grounding and layout. can be used in conjunction with the AD7851 Evaluation Board, as well as many other Analog Devices evaluation boards ending in The printed circuit board that houses the AD7851 should be the CB designator, to demonstrate/evaluate the ac and dc perfor- designed such that the analog and digital sections are separated mance of the AD7851. and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum The software allows the user to perform ac (Fast Fourier Trans- etch technique is generally best for ground planes as it gives the form) and dc (histogram of codes) tests on the AD7851. It also best shielding. Digital and analog ground planes should only be gives full access to all the AD7851 on-chip registers allowing for joined in one place. If the AD7851 is the only device requiring various calibration and power-down options to be programmed. an AGND to DGND connection, then the ground planes should AD785x Family be connected at the AGND and DGND pins of the AD7851. If All parts are 12 bit, 200 kSPS, 3.0 V to 5.5 V, except the the AD7851 is in a system where multiple devices require AGND AD7856 which is 14 bit, 285 kSPS, 5 V supply. to DGND connections, the connection should still be made at AD7853 – Single-Channel Serial one point only, a star ground point which should be established as AD7854 – Single-Channel Parallel close as possible to the AD7851. AD7856 – Eight-Channel Serial Avoid running digital lines under the device as these will couple AD7858 – Eight-Channel Serial noise onto the die. The analog ground plane should be allowed AD7859 – Eight-Channel Parallel to run under the AD7851 to avoid noise coupling. The power supply lines to the AD7851 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF ca- pacitors to AGND. All digital supplies should have a 0.1 µF disc ceramic capacitor to DGND. To achieve the best from these de- coupling components, they must be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AV DD and DV of the AD7851, it is recommended that the system’s DD AV supply is used. In this case, there should be a 10 Ω resistor DD between the AV pin and DV pin. This supply should have the DD DD recommended analog supply decoupling capacitors between the AV pin of the AD7851 and AGND and the recommended DD digital supply decoupling capacitor between the DV pin of the DD AD7851 and DGND. REV. B –33– AD7851 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1.185 (30.01) 0.295 (7.49) 1.165 (29.59) 1.145 (29.08) 0.285 (7.24) 0.275 (6.99) 24 13 1 12 0.325 (8.26) 0.310 (7.87) 0.180 0.300 (7.62) 0.015 (0.38) MIN (4.57) 0.150 (3.81) MAX 0.135 (3.43) 0.120 (3.05) 0.150 (3.81) 0.130 (3.30) 0.015 (0.38) 0.100 0.022 (0.56) 0.060 (1.52) SEATING 0.110 (2.79) 0.010 (0.25) (2.54) PLANE 0.018 (0.46) 0.050 (1.27) 0.008 (0.20) BSC 0.014 (0.36) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MO-095AG CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 24-Lead Standard Small Outline Package [SOIC] Wide Body (R-24) Dimensions shown in millimeters and (inches) 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 12 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) � 45� 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8� 1.27 (0.0500) 0.51 (0.0201) SEATING 0� 1.27 (0.0500) 0.33 (0.0130) COPLANARITY BSC PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) 0.10 COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. B –34– AD7851 24-Lead Shrink Small Outline Package [SSOP] (RS-24) Dimensions shown in millimeters 8.50 8.20 7.90 24 13 5.60 8.20 5.30 7.80 5.00 7.40 1 12 1.85 1.75 0.10 2.00 MAX 1.65 COPLANARITY 0.95 8� 0.25 0.75 0.65 0.38 4� 0.05 MIN 0.09 0.55 BSC 0.22 SEATING 0� PLANE COMPLIANT TO JEDEC STANDARDS MO-150AG REV. B –35– AD7851 Revision History Location Page 3/04—Data Sheet changed from REV. A to REV. B. Moved Page Index from Page 33 to Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated TERMINOLOGY section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Updated Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated CONTROL REGISTER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Updated Status Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated TYPICAL CONNECTION DIAGRAM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Updated Figure 18 and Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Updated Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Updated Automatic Calibration on Power-On section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated Mode 4 and 5 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Updated AD7851 as a Read-Only ADC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Updated Figure 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Updated Figure 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Updated Figures 42 and 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Updated Figure 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 REV. B –36– C01332–0–3/04(B)