ANALOG DEVICES AD7849

Serial Input, 14-Bit/16-Bit DAC AD7849 FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD CC 14-bit/16-bit multiplying DAC R V REF+ Guaranteed monotonicity R OFS R Output control on power-up and power-down internal or A1 R external control RST IN G1 Versatile serial interface A3 V OUT 10-BIT/ R DAC clears to 0 V in both unipolar and bipolar output ranges 12-BIT DAC G2 LOGIC 10/ 12 CIRCUITRY APPLICATIONS A2 DAC R LATCH V REF– Industrial process controls VOLTAGE 10/ AGND MONITOR 4 12 PC analog I/O boards RST OUT Instrumentation INPUT LATCH AD7849 INPUT SHIFT REGISTER/ CONTROL LOGIC DGND SDIN SCLK SYNC CLR BIN/ DCEN SDOUT LDAC V SS COMP Figure 1. GENERAL DESCRIPTION The AD7849 is a 14-bit/16-bit serial input multiplying digital- The AD7849 has a versatile serial interface structure and can be to-analog converter (DAC). The DAC architecture ensures controlled over three lines to facilitate opto-isolator applications. excellent differential linearity performance, and monotonicity is SDOUT is the output of the on-chip shift register and can be guaranteed to 14 bits for the A grade and to 16 bits for all other used in a daisy-chain fashion to program devices in the multi- grades over the specified temperature ranges. channel system. The daisy-chain enable (DCEN) input controls this function. During power-up and power-down sequences (when the supply voltages are changing), the VOUT pin is clamped to 0 V via a low The BIN/COMP pin sets the DAC coding; with BIN/COMP set impedance path. To prevent the output of A3 from being shorted to to 0, the coding is straight binary; and with BIN/COMP set to 1, 0 V during this time, Transmission Gate G1 is also opened. These the coding is twos complement. This allows the user to reset the conditions are maintained until the power supplies stabilize, DAC to 0 V in both the unipolar and bipolar output ranges. and a valid word is written to the DAC register. At this time, G2 The part is available in a 20-lead PDIP package and a 20-lead SOIC opens and G1 closes. Both transmission gates are also externally package. controllable via the reset in (RSTIN) control input. For instance, if the RSTIN input is driven from a battery supervisor chip, then at power-off or during a brown out, the RSTIN input is driven low to open G1 and close G2. The DAC must be reloaded, with RSTIN high, to reenable the output. Conversely, the on-chip RSTOUT voltage detector output ( ) is also available to the user to control other parts of the system. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 16-SEGMENT SWITCH MATRIX 01008-001 AD7849 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................8  Applications....................................................................................... 1  Terminology.................................................................................... 10  Functional Block Diagram .............................................................. 1  Circuit Description......................................................................... 11  General Description ......................................................................... 1  Digital-to-Analog Conversion.................................................. 11  Revision History ............................................................................... 2  Digital Interface.......................................................................... 12  Specifications..................................................................................... 3  Applying the AD7849 ................................................................ 13  Reset Specifications...................................................................... 4  Microprocessor Interfacing....................................................... 15  AC Performance Characteristics ................................................ 5  Applications Information .............................................................. 17  Timing Characteristics ................................................................ 5  Opto-Isolated Interface ............................................................. 17  Absolute Maximum Ratings............................................................ 6  Outline Dimensions....................................................................... 18  ESD Caution.................................................................................. 6  Ordering Guide .......................................................................... 19  Pin Configuration and Function Descriptions............................. 7  REVISION HISTORY 3/11—Rev. B to Rev. C Deleted 20-Lead CERDIP (Q-20) Package and T Version .............................................................................Universal Updated Format..................................................................Universal Deleted AD7849-to-ADSP-2101/ADSP-2102 Interface Section and Figure 20; Renumbered Sequentially.................................... 12 Rev. C | Page 2 of 20 AD7849 SPECIFICATIONS VDD = 14.25 V to 15.75 V; VSS = −14.25 V to −15.75 V; VCC = 4.75 V to 5.25 V; VOUT loaded with 2 kΩ, 200 pF to 0 V; VREF+ = 5 V; ROFS connected to 0 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for A, B, C versions is −40°C to +85°C. Table 1. Parameter A Version B Version C Version Unit Test Conditions/Comments 14 RESOLUTION 14 16 16 Bits A version: 1 LSB = 2 (VREF+ − VREF−)/2 ; 16 B, C versions: 1 LSB = 2 (VREF+ − VREF−)/2 UNIPOLAR OUTPUT V = 0 V, V = 0 V to 10 V REF− OUT Relative Accuracy at 25°C ±4 ±6 ±4 LSB typ TMIN to TMAX ±5 ±16 ±8 LSB max Differential Nonlinearity ±0.25 ±0.9 ±0.5 LSB max All grades guaranteed monotonic over temperature Gain Error at 25°C ±1 ±4 ±4 LSB typ V load = 10 MΩ OUT T to T ±4 ±16 ±16 LSB max MIN MAX Offset Error at 25°C ±1 ±4 ±4 LSB typ TMIN to TMAX ±6 ±24 ±16 LSB max 1 Gain Temperature Coefficient ±2 ±2 ±2 ppm FSR/ °C typ 1 Offset Temperature Coefficient ±2 ±2 ±2 ppm FSR/ °C typ BIPOLAR OUTPUT V = 5 V, V = −10 V to +10 V REF− OUT Relative Accuracy at 25°C ±2 ±3 ±2 LSB typ TMIN to TMAX ±3 ±8 ±4 LSB max Differential Nonlinearity ±0.25 ±0.9 ±0.5 LSB max All grades guaranteed monotonic over temperature Gain Error at 25°C ±1 ±4 ±4 LSB typ V load = 10 MΩ OUT T to T ±4 ±16 ±16 LSB max MIN MAX Offset Error at 25°C ±0.5 ±2 ±2 LSB typ TMIN to TMAX ±3 ±12 ±8 LSB max Bipolar Zero Error at 25°C ±0.5 ±2 ±2 LSB typ TMIN to TMAX ±4 ±12 ±8 LSB max 1 Gain Temperature Coefficient ±2 ±2 ±2 ppm FSR/ °C typ 1 Offset Temperature Coefficient ±2 ±2 ±2 ppm FSR/ °C typ Bipolar Zero Temperature ±2 ±2 ±2 ppm FSR/ Coefficient1 °C typ REFERENCE INPUT Input Resistance 25 25 25 kΩ min Resistance from VREF+ to VREF− 43 43 43 kΩ max Typically 34 kΩ V Range V + 6 to V + 6 to V + 6 to V REF+ SS SS SS V − 6 V − 6 V − 6 DD DD DD VREF− Range VSS + 6 to VSS + 6 to VSS + 6 to V VDD − 6 VDD − 6 VDD − 6 OUTPUT CHARACTERISTICS Output Voltage Swing VSS + 4 to VSS + 4 to VSS + 4 to V max VDD − 4 VDD − 4 VDD − 4 Resistive Load 2 2 2 kΩ min To 0 V Capacitive Load 200 200 200 pF max To 0 V Output Resistance 0.3 0.3 0.3 Ω typ Short-Circuit Current ±25 ±25 ±25 mA typ Voltage range: −10 V to +10 V Rev. C | Page 3 of 20 AD7849 Parameter A Version B Version C Version Unit Test Conditions/Comments DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 0.8 V max Input Current, I ±10 ±10 ±10 μA max INH Input Capacitance, C 10 10 10 pF max IN DIGITAL OUTPUTS Output Low Voltage, V 0.4 0.4 0.4 V max I = 1.6 mA OL SINK Output High Voltage, V 4.0 4.0 4.0 V min I = 400 μA OH SOURCE Floating State Leakage Current ±10 ±10 ±10 μA max Floating State Output 10 10 10 pF max Capacitance 2 POWER REQUIREMENTS VDD 14.25/15.75 14.25/15.75 14.25/15.75 V min/V max VSS −14.25/−15.75 −14.25/−15.75 −14.25/−15.75 V min/V max V 4.75/5.25 4.75/5.25 4.75/5.25 V min/V max CC I 5 5 5 mA max V unloaded, V = V – 0.1 V, DD OUT INH DD V = 0.1 V INL ISS 5 5 5 mA max VOUT unloaded, VINH = VDD – 0.1 V, VINL = 0.1 V ICC 2.5 2.5 2.5 mA max VINH = VDD – 0.1 V, VINL = 0.1 V 3 Power Supply Sensitivity 0.4 1.5 1.5 LSB/V max Power Dissipation 100 100 100 mW typ V unloaded OUT 1 Guaranteed by design and characterization, not production tested. 2 The AD7849 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section. 3 Sensitivity of gain error, offset error, and bipolar zero error to V , V variations. DD SS RESET SPECIFICATIONS These specifications apply when the device goes into reset mode during power-up or power-down sequence. VOUT unloaded. Table 2. Parameter All Versions Unit Test Conditions/Comments 1 V , Low Threshold Voltage for V , V 1.2 V max This is the lower V /V threshold voltage for the reset function. A DD SS DD SS 0 V typ Above this, the reset is activated. VB, High Threshold Voltage for VDD, VSS 9.5 V max This is the higher VDD/VSS threshold voltage for the reset function. 6.4 V min Below this, the reset is activated. Typically, 8 V. VC, Low Threshold Voltage for VCC 1 V max This is the lower VCC threshold voltage for the reset function. 0 V typ Above this, the reset is activated. V , High Threshold Voltage for V 4 V max This is the higher V threshold voltage for the reset function. D CC CC 2.5 V min Below this, the reset is activated. Typically, 3 V. G2 RON 1 kΩ typ On resistance of G2; VDD = 2 V; VSS = −2 V; IG2 = 1 mA. 1 A pull-down resistor (65 kΩ) on VOUT maintains 0 V output when VDD/VSS is below VA. Rev. C | Page 4 of 20 AD7849 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are no subject to test. VREF+ = 5 V; VDD = 14.25 V to 15.75 V; VSS = −14.25 V to −15.75 V; VCC = 4.75 V to 5.25 V; ROFS connected to 0 V. Table 3. Parameter A, B, C Versions Unit Test Conditions/Comments DYNAMIC PERFORMANCE 1 Output Settling Time 7 μs typ To 0.006% FSR. VOUT loaded. VREF− = 0 V. 10 μs typ To 0.003% FSR. VOUT loaded. VREF− = −5 V. Slew Rate 4 V/μs typ Digital-to-Analog Glitch Impulse 250 nV-sec typ DAC alternatively loaded with 00 … 00 and 111 … 11. VOUT loaded. LDAC permanently low. BIN/COMP set to 1. VREF− = −5 V. 150 nV-sec typ LDAC frequency = 100 kHz. AC Feedthrough 1 mV p-p typ V = 0 V, V = 1 V rms, 10 kHz sine wave. REF− REF+ DAC loaded with all 0s. BIN/COMP set to 0. Digital Feedthrough 5 nV-sec typ DAC alternatively loaded with all 1s and 0s. SYNC high. Output Noise Voltage Density, 1 kHz to 100 kHz 80 nV/√Hz typ Measured at VOUT. VREF+ = VREF− = 0 V. BIN/COMP set to 0. 1 LDAC = 0. Settling time does not include deglitching time of 5 μs (typical). TIMING CHARACTERISTICS V = 14.25 V to 15.75 V; V = −14.25 V to −15.75 V; V = 4.75 V to 5.25 V; R = 2 kΩ, C = 200 pF. All specifications T to T , DD SS CC L L MIN MAX unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a voltage level of 1.6 V. Table 4. Parameter Limit at 25°C (All Versions) Limit at T , T (All Versions) Unit Test Conditions/Comments MIN MAX 1 t 200 200 ns min SCLK cycle time 1 t 50 50 ns min SYNC-to-SCLK setup time 2 t3 70 70 ns min SYNC-to-SCLK hold time t4 10 10 ns min Data setup time t5 40 40 ns min Data hold time 2 t 80 80 ns max SCLK falling edge to SDO valid 6 t 80 80 ns min LDAC, CLR pulse width 7 t 30 30 μs max Digital input rise time r tf 30 30 μs max Digital input fall time 1 SCLK mark/space ratio range is 40/60 to 60/40. 2 SDO load capacitance is 50 pF. Rev. C | Page 5 of 20 AD7849 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to DGND −0.4 V to +17 V DD section of this specification is not implied. Exposure to absolute 1 V to DGND −0.4 V, V + 0.4 V or CC DD maximum rating conditions for extended periods may affect +7 V (whichever is device reliability. lower) VSS to DGND −0.4 V to −17 V V to DGND V + 0.4 V, V − 0.4 V REF+ DD SS ESD CAUTION V to DGND V + 0.4 V, V − 0.4 V REF− DD SS 2 V to DGND OUT VDD + 0.4 V, VSS − 0.4 V or ±10 V (whichever is lower) R to DGND V + 0.4 V, V − 0.4 V OFS DD SS Digital Input Voltage to DGND −0.4 V to V + 0.4 V CC 3 Input Current to any Pin Except Supplies ±10 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 20-Lead PDIP Power Dissipation 875 mW θ Thermal Impedance 102°C/W JA Lead Temperature (Soldering, 10 sec) 260°C 20-Lead SOIC Power Dissipation 875 mW θ Thermal Impedance 74°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 VCC must not exceed VDD by more than 0.4 V. If it is possible for this to happen during power-up or power-down (for example, if V is greater than CC 0.4 V while VDD is still 0 V), the following diode protection scheme ensures protection. V V DD CC SD103C 1N5711 1N4148 1N5712 V V DD CC AD7849 2 VOUT can be shorted to DGND, + 10 V, − 10 V, provided that the power dissipation of the package is not exceeded. 3 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. C | Page 6 of 20 01008-002 AD7849 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V R REF+ 1 20 OFS V V REF– 2 19 OUT V 3 18 NC SS SYNC V 4 17 DD AD7849 SCLK 5 16 AGND TOP VIEW V 6 15 RSTOUT CC (Not to Scale) 7 14 SDOUT RSTIN DCEN 8 13 CLR BIN/COMP 9 12 SDIN 10 11 DGND LDAC NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V V Input. The DAC is specified for V of 5 V. The DAC is fully multiplying so that the V range is +5 V to –5 V. REF+ REF+ REF+ REF+ 2 VREF− VREF− Input. The DAC is specified for VREF− of –5 V. The DAC is fully multiplying so that the VREF− range is –5 V to +5 V. 3 VSS Negative supply for the analog circuitry. This is nominally –15 V. 4 SYNC Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data-word. 5 SCLK Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge. 6 V Positive supply for the digital circuitry. This is nominally 5 V. CC 7 SDOUT Serial Data Output. With DCEN at Logic 1, this output is enabled, and the serial data in the input shift register is clocked out on each rising edge of SCLK. 8 DCEN Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used; otherwise, this pin must be connected low. 9 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In the unipolar output range, natural binary format is selected by connecting the input to Logic 0. In the bipolar output range, offset binary is selected by connecting this input to Logic 0, and twos complement is selected by connecting it to a Logic 1. 10 DGND Digital Ground. Ground reference point for the on-chip digital circuitry. 11 LDAC Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this signal, or alternatively, if this input is permanently low, an automatic update mode is selected where the DAC is updated on the 16th falling SCLK edge. 12 SDIN Serial Data Input. The 16-bit serial data-word is applied to this input. 13 CLR Clear Logic Input. Taking this input low sets VOUT to 0 V in both the unipolar output range and the bipolar twos complement output range. It sets V to V in the offset binary bipolar output range. OUT REF– 14 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying Logic 0 to this input, resets the DAC output to 0 V. In normal operation, it should be tied to Logic 1. 15 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It can be used to control other system components, if desired. 16 AGND This is the analog ground for the device. It is the point to which the output gets shorted in reset mode. 17 V Positive Supply for the Analog Circuitry. This is 15 V nominal. DD 18 NC No Connect. Leave unconnected. 19 V DAC Output Voltage Pin. OUT 20 ROFS Input to Summing Resistor of DAC Output Amplifier. This is used to select the output voltage ranges. Also, see Figure 20 to Figure 23 in the Applying the AD7849 section. Rev. C | Page 7 of 20 01008-003 AD7849 TYPICAL PERFORMANCE CHARACTERISTICS 7 V =+15V DD V = –15V SS C1 FREQ V =1V rms 6 REF+ 9.9942kHz V =0V REF– V 1 REF+ 5 C1 RMS 728mV 4 3 C4 RMS 2 V 4 OUT 556µV 1 0 CH1 1.00V M 20.0µs CH1 –300mV 100 1k 10k 100k 1M CH4 1.00mV FREQUENCY (Hz) Figure 3. AC Feedthrough Figure 6. AC Feedthrough vs. Frequency LDAC SYNC 1 1 2 SDIN 2 SDIN C4 AREA 247.964nV S V 4 OUT V 4 OUT CH1 5.00V CH2 5.00V M 1.00µs CH1 3.7V CH1 5.00V CH2 5.00V M 5.00µs CH1 –2.3V CH4 200mV CH4 50.0mV Figure 4. Digital-to-Analog Glitch Impulse Without Internal Deglitcher Figure 7. Digital-to-Analog Glitch Impulse With Internal Deglitcher 22 20 C1 p-p 10.4V 18 V 1 REF+ 16 14 C2 p-p 12 20.8V 10 C2 RISE 2.79230µs 8 V 2 OUT V =+15V DD 6 V =–15V C2 FALL SS V =±5 SINEWAVE 3.20385µs REF+ 4 V =0V REF– GAIN = 2 2 CH1 10.0V CH2 20.0V M 2.5µs CH1 –400mV 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 8. Pulse Response (Large Signal) Figure 5. Large Signal Frequency Response Rev. C | Page 8 of 20 V (V p-p) OUT 01008-006 01008-005 01008-004 V (mVp-p) OUT 01008-007 01008-008 01008-009 AD7849 C1 RISE V DD 3.808ms C1 p-p 1 V REF+ 104mV 1 C2 RISE V OUT 8µs 2 C2 p-p 2 V OUT 216mV C2 RISE 458ns LDAC 3 C2 FALL 452.4ns CH1 100mV CH2 200mV M 2.00µs CH1 –10mV CH1 10.0V CH2 10.0V M 10.0ms CH1 7.8mV CH3 5.0V Figure 9. Pulse Response (Small Signal) Figure 12. Turn-On Characteristics 2.0 T = 25°C A V =5V REF+ V =0V REF– 7.8V GAIN = 1 V DD C1 FALL 1.5 4.7621ms 1 1.0 V OUT 0.5 2 0 11.00 12.25 13.50 14.75 16.00 CH1 10.0V CH2 10.0V M 1.00ms CH1 7.8mV V /V (V) DD SS Figure 13. Turn-Off Characteristics Figure 10. Typical Integral Nonlinearity vs. Supplies 0.500 T = 25°C A V =5V REF+ V =0V REF– GAIN = 1 0.375 0.250 0.125 0 11 12 13 14 15 16 V /V (V) DD SS Figure 11. Typical Differential Nonlinearity vs. Supplies Rev. C | Page 9 of 20 DNL (LSB) INL (LSB) 01008-012 01008-011 01008-010 01008-014 01008-013 AD7849 TERMINOLOGY Offset Error Least Significant Bit This is the error present at the device output with all 0s loaded This is the analog weighting of 1 bit of the digital word in a in the DAC. It is due to the op amp input offset voltage and bias DAC. For the B version and the C versions, 1 LSB = (VREF+ − 16 14 current and the DAC leakage current. VREF−)/2 . For the A version, 1 LSB = (VREF+ − VREF−)/2 . Bipolar Zero Error Relative Accuracy When the AD7849 is connected for bipolar output and (100 … Relative accuracy or endpoint nonlinearity is a measure of the 000) is loaded to the DAC, the deviation of the analog output maximum deviation from a straight line passing through the from the ideal midscale of 0 V is called the bipolar zero error. endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (that is, offset and gain errors are Digital-to-Analog Glitch Impulse adjusted out) and is normally expressed in least significant bits This is the amount of charge injected from the digital inputs to or as a percentage of full-scale range. the analog output when the inputs change state. Normally, this is specified as the area of the glitch in nV-secs. Differential Nonlinearity Differential nonlinearity is the difference between the measured Multiplying Feedthrough Error change and the ideal change between any two adjacent codes. A This is an ac error due to capacitive feedthrough from either of specified differential nonlinearity of less than ±1 LSB over the the V terminals to V when the DAC is loaded with all 0s. REF OUT operating temperature range ensures monotonicity. Digital Feedthrough Gain Error When the DAC is not selected (SYNC is held high), high Gain error is a measure of the output error between an ideal frequency logic activity on the digital inputs is capacitively DAC and the actual device output with all 1s loaded after offset coupled through the device to show up as noise on the VOUT pin. error has been adjusted out. Gain error is adjustable to zero This noise is digital feedthrough. with an external potentiometer. Rev. C | Page 10 of 20 AD7849 CIRCUIT DESCRIPTION R OFS RSTIN DIGITAL-TO-ANALOG CONVERSION R R Figure 15 shows the digital-to-analog section of the AD7849. There 10kΩ 10kΩ are three on-chip DACs, each of which has its own buffer amplifier. C1 DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string, G3 G1 but they have their own analog multiplexers. The voltage reference V OUT is applied to the resistor string. DAC3 is a 12-bit voltage mode DAC 3 G2 DAC with its own output stage. LOGIC ONE-SHOT CIRCUITRY The four MSBs of the 16-bit digital input code drive DAC1 and DAC2, while the 12 LSBs control DAC3. Using DAC1 and DAC2, AGND VOLTAGE LDAC MONITOR the MSBs select a pair of adjacent nodes on the resistor string RSTOUT and present that voltage to the positive and negative inputs of Figure 14. Output Stage DAC3. This DAC interpolates between these two voltages to When the supply voltages are changing, the VOUT pin is clamped produce the analog output voltage. to 0 V via a low impedance path. To prevent the output of A3 To prevent nonmonotonicity in the DAC due to amplifier offset from being shorted to 0 V during this time, Transmission Gate G1 voltages, DAC1 and DAC2 leap-frog along the resistor string. is opened. These conditions are maintained until the power For example, when switching from Segment 1 to Segment 2, DAC1 supplies stabilize, and a valid word is written to the DAC register. switches from the bottom of Segment 1 to the top of Segment 2 At this time, G2 opens and G1 closes. Both transmission gates while DAC 2 remains connected to the top of Segment 1. The RSTIN are also externally controllable via the reset in ( ) control code driving DAC3 is automatically complemented to compensate input. For instance, if the RSTIN input is driven from a battery for the inversion of its inputs. This means that any linearity supervisor chip, then at power-off or during a brownout, the effects due to amplifier offset voltages remain unchanged when RSTIN input will be driven low to open G1 and closeG2. The switching from one segment to the next, and 16-bit monotonicity is DAC has to be reloaded, with RSTIN high, to reenable the output. ensured if DAC3 is monotonic. Therefore, 12-bit resistor matching RSTOUT Conversely, the on-chip voltage detector output ( ) is in DAC3 guarantees overall 16-bit monotonicity. This is much also available to the user to control other parts of the system. more achievable than the 16-bit matching that a conventional The AD7849 output buffer is configured as a track-and-hold R-2R structure would need. amplifier. Although normally tracking its input, this amplifier Output Stage isplaced in hold mode for approximately 5 μs after the leading The output stage of the AD7849 is shown in Figure 14. It is capable edge of LDAC. This short state keeps the DAC output at its of driving a 2 kΩ load in parallel with 200 pF. The feedback and previous voltage while the AD7849 is internally changing to its offset resistors allow the output stage to be configured for gains of new value. therefore, any glitches that occur in the transition are 1 or 2. Additionally, the offset resistor can be used to shift the LDAC not seen at the output. In systems where is permanently output range. The AD7849 has a special feature to ensure output low, deglitching is not in operation. stability during power-up and power-down sequences. This feature is available for control applications where actuators must not be allowed to move in an uncontrolled fashion. V REF+ R DAC 1 DAC 2 R S2 S1 R DAC 3 S4 S3 OUTPUT A1 STAGE 10-BIT/12-BIT DAC S15 S14 S17 S16 R 10/12 R DB15 TO DB12 DB15 TO DB12 R V REF– A2 Figure 15. Digital-to-Analog Conversion Rev. C | Page 11 of 20 01008-016 01008-015 AD7849 t 1 SCLK t t 3 2 SYNC BIN/COMP t 4 t 5 SDIN DB0 DB15 (AD7849B/C) t 4 t 5 SDIN DB13 DB0 (AD7849A) t 7 LDAC, CLR NOTES 1. DCEN IS TIED PERMANENTLY LOW. Figure 16. Timing Diagram (Standalone Mode) The DAC latch, and hence the analog output, can be updated in DIGITAL INTERFACE two ways. The status of the LDAC input is examined after SYNC The AD7849 contains an input serial-to-parallel shift register and a is taken low. Depending on its status, one of two update modes DAC latch. A simplified diagram of the input loading circuitry is is selected. shown in Figure 16. Serial data on the SDIN input is loaded to the input register under control of DCEN, SYNC and SCLK. LDAC If = 0, then automatic update mode is selected. In this mode, When a complete word is held in the shift register, it can then be the DAC latch and analog output are updated automatically when loaded into the DAC latch under control of LDAC. Only the data the last bit in the serial data stream is clocked in. The update thus takes place on the 16th falling SCLK edge. in the DAC latch determines the analog output on the AD7849. The daisy-chain enable (DCEN) input is used to select either the If LDAC = 1, then automatic update mode is disabled. The DAC standalone mode or the daisy-chain mode. The loading format latch update and output update are now separate. The DAC latch is is slightly different depending on which mode is selected. updated on the falling edge of LDAC. However, the output update is delayed for a further 5 μs by means of an internal track-and-hold Serial Data Loading Format (Standalone Mode) amplifier in the output stage. This function results in a lower When DCEN is at Logic 0, standalone mode is selected. In this digital-to-analog glitch impulse at the DAC output. Note that SYNC mode, a low input provides the frame synchronization LDAC the input must be taken back high again before the next signal that tells the AD7849 that valid serial data on the SDIN data transfer is initiated. input is available for the next 16 falling edges of SCLK. An internal counter/decoder circuit provides a low gating signal so that only DCEN SYNC 16 data bits are clocked into the input shift register. After 16 SCLK GATED RESET EN SIGNAL pulses, the internal gating signal goes inactive (high), thus locking INPUT ÷16 SCLK SHIFT REGISTER COUNTER/ out any further clock pulses. Therefore, either a continuous clock GATED (16 BITS) DECODER SCLK or a burst clock source can be used to clock in data. SDOUT SDIN SYNC The input is taken high after the complete 16-bit word is AUTO-UPDATE CIRCUITRY loaded in. LDAC DAC LATCH (14/16 BITS) CLR The B version and C version are 16-bit resolution DACs and have a straight 16-bit load format, with the MSB (DB15) being loaded Figure 17. Simplified Loading Structure first. The A version is a 14-bit DAC; however, the loading structure is still 16 bit. The MSB (DB13) is loaded first, and the final two bits of the 16-bit stream must be 0s. Rev. C | Page 12 of 20 01008-017 01008-018 AD7849 t 1 SCLK t t 2 3 SYNC BIN/COMP t 4 t 5 SDIN DB15 DB0 DB15 (N) DB0 (N) (N + 1) (N + 1) (AD7849B/C) t 6 SDOUT DB15 (N) DB0 (N) (AD7849B/C) t 4 t 5 SDIN DB13 DB0 DB13 (N) DB0 (N) (N + 1) (N + 1) (AD7849A) t 6 SDOUT DB13 (N) DB0 (N) (AD7849A) t 7 LDAC, CLR NOTES 1. DCEN IS TIED PERMANENTLY HIGH. Figure 18. Timing Diagram (Daisy-Chain Mode) Serial Data Loading Format (Daisy-Chain Mode) Clear Function (CLR) By connecting DCEN high, daisy-chain mode is enabled. This The clear function bypasses the input shift register and loads mode of operation is designed for multiDAC systems where CLR the DAC latch with all 0s. It is activated by taking low. In several AD7849s can be connected in cascade. In this mode, the all ranges, except the offset binary bipolar range (–5 V to +5 V), internal gating circuitry on SCLK is disabled, and a serial data the output voltage is reset to 0 V. In the offset binary bipolar output facility is enabled. The internal gating signal is permanently range, the output is set to V . This clear function is distinct and REF– active (low) so that the SCLK signal is continuously applied to separate from the automatic power-on reset feature of the device. the input shift register when SYNC is low. The data is clocked APPLYING THE AD7849 into the register on each falling SCLK edge after SYNC goes low. If Power Supply Sequencing and Decoupling more than 16 clock pulses are applied, the data ripples out of the In the AD7849, VCC should not exceed VDD by more than 0.4 V. shift register and appears on the SDOUT line. By connecting this If this happens, then an internal diode is turned on, and it produces line to the SDIN input on the next AD7849 in the chain, a latch-up in the device. Care should be taken to employ the multiDAC interface can be constructed. Sixteen SCLK pulses following power supply sequence: V V and then V . In DD, SS, CC are required for each DAC in the system. Therefore, the total systems where it is possible to have an incorrect power sequence number of clock cycles must equal 16 × N, where N is the total (for example, if V is greater than 0.4 V while V is still 0 V), CC DD number of devices in the chain. When the serial transfer to all the circuit shown in Figure 19 can be used to ensure that the SYNC devices is complete, is taken high, which prevents any Absolute Maximum Ratings are not exceeded. further data from being clocked into the input register. V V DD CC SYNC A continuous SCLK source can be used if is held low for SD103C the correct number of clock cycles. Alternatively, a burst clock 1N4148 1N5711 1N5712 containing the exact number of clock cycles can be used and SYNC taken high some time later. V V DD CC When the transfer to all input registers is complete, a common AD7849 LDAC signal updates all DAC latches with the data in each input register. All analog outputs are therefore updated simultaneously, Figure 19. Power Supply Protection LDAC 5 μs after the falling edge of . Rev. C | Page 13 of 20 01008-020 01008-019 AD7849 Unipolar Configuration Bipolar Configuration Figure 20 shows the AD7849 in the unipolar binary circuit Figure 21 shows the AD7849 set up for ±10 V bipolar operation. configuration. The DAC is driven by the AD586, 5 V reference. The AD588 provides precision ±5 V tracking outputs that are Because ROFS is tied to 0 V, the output amplifier has a gain of ×2, fed to the VREF+ and VREF− inputs of the AD7849.The code table and the output range is 0 V to 10 V. If a 0 V to 5 V range is for the circuit shown in Figure 21 is shown in Table 8. required, R should be tied to V , configuring the output OFS OUT Full-scale and bipolar-zero adjustment are provided by varying stage for a gain of ×1. Table 7 gives the code table for the circuit the gain and balance on the AD588. R2 varies the gain on the shown in Figure 20. AD588, while R3 adjusts the +5 V and −5 V outputs together +15V +5V with respect to ground. +15V +5V V V DD CC 2 R1 V OUT V OUT 39kΩ (0V TO 10V) 8 V V 6 V DD CC REF+ R OFS V AD586 4 6 OUT V OUT R1 (–10V TO +10V) AD7849* 5 2 C1 10kΩ 7 1nF C1 4 R 3 V REF+ OFS 1µF AGND 9 V 1 REF– AD7849* DGND AD588 V SS R2 AGND 5 14 SIGNAL GND 100kΩ 10 V DGND 15 REF– SIGNAL 11 16 V GND SS –15V *ADDITIONAL PINS OMITTED FOR CLARITY. 12 8 13 R3 Figure 20. Unipolar Binary Operation 100kΩ –15V *ADDITIONAL PINS OMITTED FOR CLARITY Table 7. Code Table for Figure 20 Figure 21. Bipolar ±10 V Operation Binary Number in DAC Latch MSB LSB Analog Output (VOUT) Table 8. Code Table for Figure 21 1111 1111 1111 1111 10 (65,535/65,536) V Binary Number in DAC Latch 1000 0000 0000 0000 10 (32,768/65,536) V MSB LSB Analog Output (V ) OUT 0000 0000 0000 0001 10 (1/65,536) V 1111 1111 1111 1111 +10 (32,767/32,768) V 0000 0000 0000 0000 0 V 1000 0000 0000 0001 +10 (1/32,768) V 16 Table 7 assumes a 16-bit resolution; 1 LSB = 10 V/2 = 1000 0000 0000 0001 0 V 10 V/65,536 = 152 μV. 0111 1111 1111 1111 −10 (1/32,768) V 0000 0000 0000 0000 −10 (32,768/32,768) V Offset and gain can be adjusted in Figure 20 as follows: 16 Table 8 assumes a 16-bit resolution; 1 LSB = 20 V/2 = 305 μV. • To adjust offset, disconnect the VREF− input from 0 V, load the DAC with all 0s, and adjust the V voltage until V = 0 V. REF− OUT For bipolar-zero adjustment on the AD7849, load the DAC with • To adjust gain, load the AD7849 with all 1s and adjust R1 100 … 000 and adjust R3 until V = 0 V. Full scale is adjusted OUT until V = 10 (65,535/65,536) = 9.9998474 V for the 16-bit, by loading the DAC with all 1s and adjusting R2 until V = OUT OUT B and C versions. For the 14-bit A version, V should be 9.999694 V. OUT 10 (16,383/16,384) = 9.9993896 V. When bipolar-zero and full-scale adjustment are not needed, omit R2 and R3, connect Pin 11 to Pin 12 on the AD588 and If a simple resistor divider is used to vary the VREF− voltage, it is leave Pin 5 on the AD588 floating. important that the temperature coefficients of these resistors match that of the DAC input resistance (−300 ppm/°C). Otherwise, If a ±5 V output range is desired with the circuit shown in extra offset errors will be introduced over temperature. Many Figure 21, tie Pin 20 (R ) to Pin 19 (V ), thus reducing the OFS OUT circuits do not require these offset and gain adjustments. In output gain stage to unity and giving an output range of ±5 V. these circuits, R1 can be omitted. Pin 5 of the AD586 may be left open circuit, and Pin 2 (V ) of the AD7849 tied to 0 V. REF− Rev. C | Page 14 of 20 01008-021 01008-022 AD7849 Other Output Voltage Ranges MICROPROCESSOR INTERFACING In some cases, users may require output voltage ranges other than Microprocessor interfacing to the AD7849 is via a serial bus those already mentioned. One example is systems that need the that uses standard protocol compatible with DSP processors output voltage to be a whole number of millivolts (that is,1 mV or and microcontrollers. The communications channel requires a 2 mV). If the circuit shown in Figure 22 is used, then the LSB size is 3-wire interface consisting of a clock signal, a data signal, and a 125 μV. This makes it possible to program whole millivolt values at synchronization signal. The AD7849 requires a 16-bit data-word the output. Table 9 shows the code table for the circuit shown in with data valid on the falling edge of SCLK. For all the interfaces, Figure 22. the DAC update can be done automatically when all data is +15V +5V clocked in, or it can be done under control of LDAC. Figure 24 through Figure 27 show the AD7849 configured for V V DD interfacing to a number of popular DSP processors and CC 8 microcontrollers. R OFS V R1 REF+ 8.192V V 1 V OUT OUT AD7849-to-DSP56000 Interface (0V TO 8.192V) AD584 AD7849* R2 A serial interface between the AD7849 and the DSP56000 is DGND 4 shown in Figure 24. The DSP56000 is configured for normal V REF– AGND mode asynchronous operation with a gated clock. It is also SIGNAL setup for a 16-bit word with SCK and SC2 as outputs and the GND FSL control bit set to 0. SCK is internally generated on the *ADDITIONAL PINS OMITTED FOR CLARITY. DSP56000 and applied to the AD7849 SCLK input. Data from Figure 22. 0 V to 8.192 V Output Range the DSP56000 is valid on the falling edge of SCK. The SC2 output Table 9. Code Table for Figure 22 provides the framing pulse for valid data. This line must be Binary Number in DAC Latch inverted before being applied to the SYNC input of the AD7849. MSB LSB Analog Output (V ) OUT In this interface, an LDAC pulse generated from an external timer 1111 1111 1111 1111 8.192 V (65,535/65,536) = 8.1919 V is used to update the outputs of the DAC. This update can also 1000 0000 0000 0000 8.192 V (32,768/65,536) = 4.096 V be produced using a bit programmable control line from the 0000 0000 0000 1000 8.192 V (8/65,536) = 0.001 V DSP56000. 0000 0000 0000 0100 8.192 V (4/65,536) = 0.0005 V 0000 0000 0000 0010 8.192 V (2/65,536) = 0.00025 V TIMER 0000 0000 0000 0001 8.192 V (1/65,536) = 0.000125 V LDAC 16 Table 9 assumes a 16-bit resolution; 1 LSB = 8.192 V/2 = 125 μV. SCK SCLK Generating a ±5 V Output Range from a Single +5 V STD SDIN Reference SC2 SYNC Figure 23 shows how to generate a ±5 V output range when DSP56000 AD7849* using a single +5 V reference. V is connected to 0 V, and R REF− OFS *ADDITIONAL PINS OMITTED FOR CLARITY. is connected to V . The 5 V reference input is applied to these REF+ Figure 24. AD7849-to-DSP56000 Interface pins. With all 0s loaded to the DAC, the noninverting terminal of the output stage amplifier is at 0 V, and VOUT is the inverse of VREF+. With all 1s loaded to the DAC, the noninverting terminal of the output stage amplifier is 5 V and, therefore, VOUT is also 5 V. +15V +5V V V DD CC 2 R OFS 8 V OUT 6 V V REF+ OUT (–5V TO +5V) AD586 R1 AD7849* 5 C1 10kΩ 1nF 4 DGND V REF– AGND V SS SIGNAL GND –15V *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 23. Generating a ±5 V Output Range from a Single +5 V Rev. C | Page 15 of 20 01008-024 01008-023 01008-029 AD7849 AD7849-to-TMS320C2x Interface LDAC Figure 26 shows the input of the AD7849 being driven from another bit programmable port line (PC1). As a result, the Figure 25 shows a serial interface between the AD7849 and the LDAC DAC can be updated by taking low after the DAC input TMS320C2x DSP processor. In this interface, the CLKX and register has been loaded. FSX signals for the TMS320C2x should be generated using external clock/timer circuitry. The FSX pin of the TMS320C2x must be configured as an input. Data from the TMS320C2x is PC1 LDAC valid on the falling edge of CLKX. PC0 SYNC SCK SCLK CLOCK/TIMER MOSI SDIN LDAC AD7849* 68HC11* FSX SYNC *ADDITIONAL PINS OMITTED FOR CLARITY. CLKX SCLK Figure 26. AD7849-to-68HC11 Interface SDIN DX AD7849-to-87C51 Interface TMS320C2x AD7849* A serial interface between the AD7849 and the 87C51 *ADDITIONAL PINS OMITTED FOR CLARITY. microcontroller is shown in Figure 27. TXD of the 87C51 drives Figure 25. AD7849-to-TMS320C2x Interface SCLK of the AD7849, while RXD drives the serial data line of LDAC The clock/timer circuitry generates the signal for the the part. The SYNC signal is derived from the P3.3 port line, AD7849 to synchronize the update of the output with the serial LDAC and the line is driven from the P3.2 port line. transmission. Alternatively, the automatic update mode can be The 87C51 provides the LSB of its SBUF register as the first bit selected by connecting LDAC to DGND. in the serial data stream. Therefore, ensure that the data in the AD7849-to-68HC11 Interface SBUF register is arranged correctly so that the most significant bits are the first to be transmitted to the AD7849, and the last Figure 26 shows a serial interface between the AD7849 and the bit to be sent is the LSB of the word to be loaded to the AD7849. 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of When data is transmitted to the part, P3.3 is taken low. Data on the AD7849, while the MOSI output drives the serial data line RXD is valid on the falling edge of TXD. The 87C51 transmits of the AD7849. The SYNC signal is derived from a port line its serial data in 8-bit bytes, with only eight falling clock edges (PC0 shown). occurring in the transmit cycle. To load data to the AD7849, P3.3 is For correct operation of this interface, the 68HC11 should be left low after the first eight bits are transferred, and a second byte of configured such that its CPOL bit is a 0 and its CPHA bit is a 1. data is then transferred serially to the AD7849. When the second When data is transmitted to the part, PC0 is taken low. When serial transfer is complete, the P3.3 line is taken high. the 68HC11 is configured like this, data on MOSI is valid on the Figure 27 shows the LDAC input of the AD7849 driven from falling edge of SCK. The 68HC11 transmits its serial data in 8-bit the bit programmable P3.2 port line. As a result, the DAC output bytes with only eight falling clock edges occurring in the transmit LDAC can be updated by taking the line low following the cycle. To load data to the AD7849, PC0 is left low after the first LDAC eight bits are transferred, and a second byte of data is then completion of the write cycle. Alternatively, can be transferred serially to the AD7849. When the second serial hardwired low, and the analog output is updated on the 16th transfer is complete, the PC0 line is taken high. falling edge of TXD after the SYNC signal for the DAC goes low. P3.2 LDAC SYNC P3.3 TXD SCLK RXD SDIN 87C51* AD7849* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. AD7849-to-87C51 Interface Rev. C | Page 16 of 20 01008-030 01008-026 01008-025 AD7849 APPLICATIONS INFORMATION The sequence of events to program the output channels in OPTO-ISOLATED INTERFACE Figure 28 is as follows: In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being 1. Take the SYNC line low. controlled. Opto-isolators can provide voltage isolation in 2. Transmit the data as four 16-bit words. A total of 64 clock excess of 3 kV. The serial loading structure of the AD7849 pulses is required to clock the data through the chain. makes it ideal for opto-isolated interfaces because the number SYNC 3. Take the line high. of interface lines is kept to a minimum. LDAC 4. Pulse the line low. This updates all output channels LDAC simultaneously on the falling edge of . Figure 28 shows a 4-channel isolated interface using the AD7849. The DCEN pin must be connected high to enable the daisy-chain To reduce the number of optocouplers, the LDAC line can be facility. Four channels with 14-bit or 16-bit resolution are provided driven from one shot that is triggered by the rising edge on the in the circuit shown, but this can be expanded to accommodate SYNC line. A low level pulse of 100 ns duration or greater is all any number of DAC channels without any extra isolation circuitry. that is required to update the outputs. The only limitation is the output update rate. For example, if an output update rate of 10 kHz is required, then all DACs must be loaded and updated in 100 μs. Operating at the maximum clock rate of 5 MHz means that it takes 3.2 μs to load a DAC. This means that the total number of channels for this update rate is 31, which LDAC leaves 800 ns for the pulse. Of course, as the update rate requirement decreases, the number of possible channels increases. V DD DATA OUT V DD SDIN CLOCK OUT SCLK V V A OUT OUT V DD SYNC AD7849* SYNC OUT LDAC DCEN 5V V DD SDOUT CONTROL OUT CONTROLLER SDIN V SCLK V B OUT OUT QUAD OPTO-COUPLER SYNC AD7849* LDAC DCEN 5V SDOUT SDIN V SCLK V C OUT OUT SYNC AD7849* LDAC 5V DCEN SDOUT SDIN SCLK V V D OUT OUT SYNC AD7849* 5V LDAC DCEN SDOUT *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 28. 4-Channel Opto-Isolated Interface Rev. C | Page 17 of 20 01008-031 AD7849 OUTLINE DIMENSIONS 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 10 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE PLANE 0.014 (0.36) 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 29. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 1.27 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE (0.0500) 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) BSC COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 30. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) Rev. C | Page 18 of 20 0.75 (0.0295) 0.25 (0.0098) 06-07-2006-A 070706-A AD7849 ORDERING GUIDE 1 Model Temperature Range Resolution (Bits) Bipolar INL (LSB) Package Description Package Option AD7849ANZ −40°C to +85°C 14 ±3 20-Lead PDIP N-20 AD7849BNZ −40°C to +85°C 16 ±8 20-Lead PDIP N-20 AD7849CNZ −40°C to +85°C 16 ±4 20-Lead PDIP N-20 AD7849AR −40°C to +85°C 14 ±3 20-Lead SOIC_W RW-20 AD7849AR-REEL −40°C to +85°C 14 ±3 20-Lead SOIC_W RW-20 AD7849ARZ −40°C to +85°C 14 ±3 20-Lead SOIC_W RW-20 AD7849ARZ-REEL −40°C to +85°C 14 ±3 20-Lead SOIC_W RW-20 AD7849BR −40°C to +85°C 16 ±8 20-Lead SOIC_W RW-20 AD7849BR-REEL −40°C to +85°C 16 ±8 20-Lead SOIC_W RW-20 AD7849BRZ −40°C to +85°C 16 ±8 20-Lead SOIC_W RW-20 AD7849BRZ-REEL −40°C to +85°C 16 ±8 20-Lead SOIC_W RW-20 AD7849CR −40°C to +85°C 16 ±4 20-Lead SOIC_W RW-20 AD7849CR-REEL −40°C to +85°C 16 ±4 20-Lead SOIC_W RW-20 AD7849CRZ −40°C to +85°C 16 ±4 20-Lead SOIC_W RW-20 AD7849CRZ-REEL −40°C to +85°C 16 ±4 20-Lead SOIC_W RW-20 1 Z = RoHS Compliant Part. Rev. C | Page 19 of 20 AD7849 NOTES ©1995–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01008-0-3/11(C) Rev. C | Page 20 of 20