ANALOG DEVICES AD7846

2 LC MOS 16-Bit Voltage Output DAC AD7846 FEATURES FUNCTIONAL BLOCK DIAGRAM V V CC DD 16-bit monotonicity over temperature 21 4 ±2 LSBs integral linearity error V REF+ 7 Microprocessor compatible with readback capability AD7846 R R 6 R A2 IN Unipolar or bipolar output R 16 Multiplying capability SEGMENT R Low power (100 mW typical) SWITCH 5 V A3 OUT MATRIX 12-BIT DAC R 12 A1 23 CS V 8 REF– DAC LATCH 22 4 R/W CONTROL 12 LOGIC 25 LDAC I/O LATCH 24 CLR 9 10 3 20 V DB15 DB0 DGND SS Figure 1. GENERAL DESCRIPTION The AD7846 is a 16-bit DAC constructed with the Analog Devices, to 00…000 or 10…000 depending on the state of R/W. This 2 Inc., LC MOS process. It has VREF+ and VREF− reference inputs means that the DAC output can be reset to 0 V in both the and an on-chip output amplifier. These can be configured to unipolar and bipolar configurations. give a unipolar output range (0 V to +5 V, 0 V to +10 V) or The AD7846 is available in 28-lead plastic, ceramic, and PLCC bipolar output ranges (±5 V, ±10 V). packages. The DAC uses a segmented architecture. The four MSBs in the PRODUCT HIGHLIGHTS DAC latch select one of the segments in a 16-resistor string. 1. 16-Bit Monotonicity Both taps of the segment are buffered by amplifiers and fed to a The guaranteed 16-bit monotonicity over temperature 12-bit DAC, which provides a further 12 bits of resolution. This makes the AD7846 ideal for closed-loop applications. architecture ensures 16-bit monotonicity. Excellent integral 2. Readback linearity results from tight matching between the input offset The ability to read back the DAC register contents voltages of the two buffer amplifiers. minimizes software routines when the AD7846 is used in In addition to the excellent accuracy specifications, the AD7846 ATE systems. also offers a comprehensive microprocessor interface. There are 3. Power Dissipation CS 16 data I/O pins, plus control lines ( , R/W, LDAC and CLR). Power dissipation of 100 mW makes the AD7846 the R/W and CS allow writing to and reading from the I/O latch. lowest power, high accuracy DAC on the market. This is the readback function, which is useful in ATE applications. LDAC allows simultaneous updating of DACs in a multi-DAC CLR system and the line will reset the contents of the DAC latch Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08490-001 AD7846 TABLE OF CONTENTS Features .............................................................................................. 1  Output Stage ................................................................................ 12  Functional Block Diagram .............................................................. 1  Unipolar Binary Operation ........................................................... 13  General Description ......................................................................... 1  Bipolar Operation ........................................................................... 14  Product Highlights ........................................................................... 1  Multiplying Operation ............................................................... 14  Revision History ............................................................................... 2  Position Measurement Application .............................................. 15  Specif ica t ions ..................................................................................... 3  Microprocessor Interfacing ........................................................... 16  AC Performance Characteristics ................................................ 4  AD7846-to-8086 Interface ........................................................ 16  Timing Characteristics ................................................................ 5  AD7846-to-MC68000 Interface ............................................... 16  Absolute Maximum Ratings ............................................................ 6  Digital Feedthrough ....................................................................... 17  ESD Caution .................................................................................. 6  Application Hints ........................................................................... 18  Pin Configurations and Function Descriptions ........................... 7  Noise ............................................................................................ 18  Typical Performance Characteristics ............................................. 8  Grounding ................................................................................... 18  Terminology .................................................................................... 10  Printed Circuit Board Layout ................................................... 18  Circuit Description ......................................................................... 11  Outline Dimensions ....................................................................... 20  Digital Section ............................................................................. 11  Ordering Guide .......................................................................... 22  Digital-to-Analog Conversion .................................................. 11  REVISION HISTORY 4/10—Rev. F to Rev. G Change to Figure 1 ........................................................................... 1 12/09—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Table 4 ............................................................................ 6 Deleted Other Output Voltage Ranges Section ............................ 9 Deleted Figure 20 and Table 5; Renumbered Sequentially ......... 9 Deleted Test Application Section and Figure 21 ........................ 10 Deleted Figure 29 to Figure 31 ...................................................... 14 Changes to Printed Circuit Board Layout Section ..................... 18 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 22 Rev. G | Page 2 of 24 AD7846 SPECIFICATIONS VDD = +14.25 V to +15.75 V; VSS = −14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V. VOUT loaded with 2 kΩ, 1000 pF to 0 V; VREF+ = +5 V; RIN connected to 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter J, A Versions K, B Versions Unit Test Conditions/Comments RESOLUTION 16 16 Bits UNIPOLAR OUTPUT VREF− = 0 V, VOUT = 0 V to +10 V Relative Accuracy at +25°C ±12 ±4 LSB typ 1 LSB = 153 μV T to T ±16 ±8 LSB max MIN MAX Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic Gain Error at +25°C ±12 ±6 LSB typ VOUT load = 10 MΩ TMIN to TMAX ±16 ±16 LSB max Offset Error at +25°C ±12 ±6 LSB typ T to T ±16 ±16 LSB max MIN MAX 2 Gain TC ±1 ±1 ppm FSR/°C typ 2 Offset TC ±1 ±1 ppm FSR/°C typ BIPOLAR OUTPUT V = –5 V, V = −10 V to +10 V REF− OUT Relative Accuracy at +25°C ±6 ±2 LSB typ 1 LSB = 305 μV T to T ±8 ±4 LSB max MIN MAX Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic Gain Error at +25°C ±6 ±4 LSB typ VOUT load = 10 MΩ TMIN to TMAX ±16 ±16 LSB max Offset Error at +25°C ±6 ±4 LSB typ V load = 10 MΩ OUT T to T ±16 ±12 LSB max MIN MAX Bipolar Zero Error at +25°C ±6 ±4 LSB typ TMIN to TMAX ±12 ±8 LSB max 2 Gain TC ±1 ±1 ppm FSR/°Ctyp 2 Offset TC ±1 ±1 ppm FSR/°Ctyp 2 Bipolar Zero TC ±1 ±1 ppm FSR/°Ctyp REFERENCE INPUT Input Resistance 20 20 kΩ min Resistance from VREF+ to VREF− 40 40 kΩ max Typically 30 kΩ V Range V + 6 to V + 6 to V min to REF+ SS SS V − 6 V − 6 V max DD DD VREF− Range VSS + 6 to VSS + 6 to V min to VDD − 6 VDD − 6 V max OUTPUT CHARACTERISTICS Output Voltage Swing V max VSS + 4 to VSS + 4 to VDD − 3 VDD − 3 Resistive Load 2 2 kΩ min To 0 V Capacitive Load 1000 1000 pF max To 0 V Output Resistance 0.3 0.3 Ω typ Short Circuit Current ±25 ±25 mA typ To 0 V or any power supply DIGITAL INPUTS V (Input High Voltage) 2.4 2.4 V min IH V (Input Low Voltage) 0.8 0.8 V max IL I (Input Current) ±10 ±10 μA max IN 2 CIN (Input Capacitance) 10 10 pF max Rev. G | Page 3 of 24 AD7846 1 Parameter J, A Versions K, B Versions Unit Test Conditions/Comments DIGITAL OUTPUTS VOL (Output Low Voltage) 0.4 0.4 V max ISINK = 1.6 mA VOH (Output High Voltage) 4.0 4.0 V min ISOURCE = 400 μA Floating State Leakage Current ±10 ±10 μA max DB0 to DB15 = 0 to VCC 2 Floating State Output Capacitance 10 10 pF max 3 POWER REQUIREMENTS VDD +11.4/+15.75 +11.4/+15.75 V min/V max V −11.4/−15.75 −11.4/−15.75 V min/V max SS V +4.75/+5.25 +4.75/+5.25 V min/V max CC I 5 5 mA max V unloaded DD OUT ISS 5 5 mA max VOUT unloaded ICC 1 1 mA max 4 Power Supply Sensitivity 1.5 1.5 LSB/V max Power Dissipation 100 100 mW typ V unloaded OUT 1 Temperature ranges as follows: J, K versions: 0°C to +70°C; A, B versions: −40°C to +85°C. 2 Guaranteed by design and characterization, not production tested. 3 The AD7846 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section. 4 Sensitivity of gain error, offset error, and bipolar zero error to VDD, VSS variations. AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are not subject to test. VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = −14.25 V to −15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V, unless otherwise noted. Table 2. Parameter Limit at T to T (All Versions) Unit Test Conditions/Comments MIN MAX 1 Output Settling Time 6 μs max To 0.006% FSR, VOUT loaded, VREF− = 0 V, typically 3.5 μs 9 μs max To 0.003% FSR, VOUT loaded, VREF− = –5 V, typically 6.5 μs Slew Rate 7 V/μs typ Digital-to-Analog Glitch Impulse 70 nV-sec typ DAC alternately loaded with 10…0000 and 01…1111, VOUT unloaded AC Feedthrough 0.5 mV p-p typ VREF− = 0 V, VREF+ = 1 V rms, 10 kHz sine wave, DAC loaded with all 0s Digital Feedthrough 10 nV-sec typ DAC alternately loaded with all 1s and all 0s. CS high Output Noise Voltage 50 nV/√Hz typ Measured at V , DAC loaded with 0111011…11, OUT Density, 1 kHz to 100 kHz VREF+ = VREF− = 0 V 1 LDAC = 0. Settling time does not include deglitching time of 2.5 μs (typ). Rev. G | Page 4 of 24 AD7846 TIMING CHARACTERISTICS VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted. Table 3. 1 Parameter Limit at TMIN to TMAX (All Versions) Unit Test Conditions/Comments t 0 ns min R/W to CS setup time 1 t 60 ns min CS pulse width (write cycle) 2 t 0 ns min R/W to CS hold time 3 t4 60 ns min Data setup time t 0 ns min Data hold time 5 2 t 120 ns max Data access time 6 3 t7 10 ns min Bus relinquish time 60 ns max 0 ns min CLR setup time t8 70 ns min CLR pulse width t9 0 ns min CLR hold time t10 70 ns min LDAC pulse width t11 t 130 ns min CS pulse width (read cycle) 12 1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3 t is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6. 7 t t t t 1 3 1 3 5V R/W 0V t 12 t 2 5V CS 0V t 5 t t 7 t 4 6 5V DB0 DATA VALID DATA VALID TO 0V DB15 t t t t t t 8 9 10 8 9 10 5V CLR 0V t 11 5V LDAC 0V Figure 2. Timing Diagram DBn DBn 3kΩ 100pF 3kΩ 10pF DGND DGND Figure 3. Load Circuit for Access Time (t6)—High Z to VOH Figure 5. Load Circuit for Access Time (t7)—High Z to VOH 5V 5V 3kΩ 3kΩ DBn DBn 100pF 10pF DGND DGND Figure 4. Load Circuits for Bus Relinquish Time (t )—High Z to V Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL 6 OL Rev. G | Page 5 of 24 08490-003 08490-002 08490-006 08490-005 08490-004 AD7846 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to DGND −0.4 V to +17 V DD other conditions above those indicated in the operational V to DGND −0.4 V, V + 0.4 V, or +7 V CC DD section of this specification is not implied. Exposure to absolute (whichever is lower) maximum rating conditions for extended periods may affect VSS to DGND +0.4 V to −17 V device reliability. VREF+ to DGND VDD + 0.4 V, VSS − 0.4 V VREF− to DGND VDD + 0.4 V, VSS − 0.4 V ESD CAUTION 1 V to DGND V + 0.4 V, V − 0.4 V, or ±10 V OUT DD SS (whichever is lower) RIN to DGND VDD + 0.4 V, VSS − 0.4 V Digital Input Voltage to DGND −0.4 V to VCC + 0.4 V Digital Output Voltage to DGND −0.4 V to VCC + 0.4 V Power Dissipation (Any Package) To +75°C 1000 mW Derates above +75°C 10 mW/°C Operating Temperature Range J, K Versions 0°C to +70°C A, B Versions −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering) +300°C 1 V can be shorted to DGND, V , V , or V provided that the power OUT DD SS CC dissipation of the package is not exceeded. Rev. G | Page 6 of 24 AD7846 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DB2 1 DB3 28 4 3 2 1 28 27 26 DB1 2 DB4 27 DB0 3 DB5 V 5 PIN 1 25 26 OUT LDAC IDENTIFIER V 4 R 6 24 25 IN CLR DD LDAC V 7 23 5 CS V 24 CLR REF+ OUT AD7846 V 8 22 R/W 6 REF– R 23 CS TOP VIEW IN AD7846 (Not to Scale) V 9 21 V 7 SS CC V 22 R/W REF+ TOP VIEW DB15 10 20 DGND 8 (Not to Scale) V 21 V REF– CC DB14 11 19 DB6 9 V 20 DGND SS 10 DB15 19 DB6 12 13 14 15 16 17 18 11 DB14 18 DB7 12 DB13 17 DB8 13 DB12 16 DB9 14 DB11 15 DB10 Figure 7. PDIP Pin Configuration Figure 8. CERDIP Pin Configuration Table 5. Pin Function Descriptions Pin Mnemonic Description 1 to 3 DB2 to DB0 Data I/Os. DB0 is LSB. 4 VDD Positive Supply for Analog Circuitry. This is +15 V nominal. 5 VOUT DAC Output Voltage. 6 R Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6. IN 7 V V Input. The DAC is specified for V = +5 V. REF+ REF+ REF+ 8 V REF− VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is specified for both conditions. 9 VSS Negative Supply for the Analog Circuitry. This is −15 V nominal. 10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB. 20 DGND Ground for Digital Circuitry. 21 V Positive Supply for Digital Circuitry. This is +5 V nominal. CC 22 R/W R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents. 23 CS Chip Select Input. This pin selects the device. 24 CLR Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7. 25 LDAC Asynchronous Load Input to DAC. 26 to 28 DB5 to DB3 Data I/Os. Table 6. Output Voltage Ranges Output Range VREF+ VREF− RIN 0 V to +5 V +5 V 0 V V OUT 0 V to +10 V +5 V 0 V 0 V +5 V to −5 V +5 V −5 V VOUT +5 V to −5 V +5 V 0 V +5 V +10 V to −10 V +5 V −5 V 0 V Rev. G | Page 7 of 24 08490-007 DB13 V DD DB12 DB0 DB11 DB1 DB2 DB10 DB9 DB3 DB4 DB8 DB7 DB5 08490-008 AD7846 TYPICAL PERFORMANCE CHARACTERISTICS 500 A1 –0.40V 450 V = V = 0V REF+ REF– GAIN = +1 400 DAC LOADED WITH ALL 1s 350 300 250 200 150 100 50 1V 2mV 20µs 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Noise Spectral Density Figure 9. AC Feedthrough, VREF+ = 1 V rms, 10 kHz Sine Wave 8 V = +15V DD 7 V = –15V SS V + = +1V rms REF 50mV/DIV V OUT 6 V – = 0V REF 5 4 3 2 5V/DIV DATA 1 0 0.5µs/DIV 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 10. AC Feedthrough to VOUT vs. Frequency Figure 13. Digital-to-Analog Glitch Impulse Without Internal Deglitcher (10…000 to 011…111 Transition) 30 V = +15V DD V = –15V SS V = ±5V SINE WAVE 25 REF+ V = 0V REF– 50mV/DIV V OUT GAIN = +2 20 15 5V/DIV LDAC 10 5V/DIV 5 DATA 0 1µs/DIV 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 14. Digital-to-Analog Glitch Impulse with Internal Deglitcher Figure 11. Large Signal Frequency Response (10…000 to 011…111 Transition) Rev. G | Page 8 of 24 V (V p-p) OUT V (mV p-p) OUT 08490-009 08490-010 08490-011 NOISE SPECTRAL DENSITY (nV/√Hz) 08490-014 08490-013 08490-012 AD7846 4.0 A1 0V T = +25°C A V = +5V REF+ 3.5 V +, ±5V V = 0V REF REF– GAIN = +1 3.0 2.5 2.0 1.5 V +, ±10V OUT 1.0 10V 5V 2µs 0.5 11 12 13 14 15 16 V , V (V) DD SS Figure 18. Typical Integral Nonlinearity vs. VDD/VSS Figure 15. Pulse Response (Large Signal) 1.0 A1 0.025V T = +25°C A 0.9 V = +5V REF+ V = 0V REF– V +, ±50mV REF 0.8 GAIN = +1 0.7 0.6 0.5 0.4 0.3 0.2 V +, ±100mV OUT 0.1 100mV 50mV 1µs 0 11 12 13 14 15 16 V , V (V) DD SS Figure 19. Typical Differential Nonlinearity vs. VDD/VSS Figure 16. Pulse Response (Small Signal) REF 2.24V MARKER 442.0Hz 10dB/DIV RANGE 3.98V 1.70V START 100.0Hz STOP 2000.0Hz RBW 3Hz VBW 10Hz ST 422 SEC Figure 17. Spectral Response of Digitally Constructed Sine Wave Rev. G | Page 9 of 24 08490-016 08490-015 08490-017 DNL (LSB) INL (LSB) 08490-019 08490-018 AD7846 TERMINOLOGY Offset Error Least Significant Bit This is the error present at the device output with all 0s loaded This is the analog weighting of 1 bit of the digital word in a 16 in the DAC. It is due to op amp input offset voltage and bias DAC. For the AD7846, 1 LSB = (VREF+ − VREF−)/2 . current and the DAC leakage current. Relative Accuracy Bipolar Zero Error Relative accuracy or endpoint nonlinearity is a measure of the When the AD7846 is connected for bipolar output and 10…000 maximum deviation from a straight line passing through the is loaded to the DAC, the deviation of the analog output from endpoints of the DAC transfer function. It is measured after the ideal midscale of 0 V is called the bipolar zero error. adjusting for both endpoints (that is, offset and gain errors are adjusted out) and is normally expressed in least significant bits Digital-to-Analog Glitch Impulse or as a percentage of full-scale range. This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally Differential Nonlinearity specified as the area of the glitch in either pA-sec or nV-sec Differential nonlinearity is the difference between the measured depending upon whether the glitch is measured as a current or change and the ideal change between any two adjacent codes. A a voltage. specified differential nonlinearity of ±1 LSB over the operating temperature range ensures monotonicity. Multiplying Feedthrough Error This is an ac error due to capacitive feedthrough from either of Gain Error the VREF terminals to VOUT when the DAC is loaded with all 0s. Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset Digital Feedthrough error has been adjusted out. Gain error is adjustable to zero When the DAC is not selected (that is, CS is held high), high with an external potentiometer. frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the V pin. OUT This noise is digital feedthrough. Rev. G | Page 10 of 24 AD7846 CIRCUIT DESCRIPTION DIGITAL SECTION Table 7. Control Logic Truth Table R/ CS W LDAC CLR Figure 20 shows the digital control logic and on-chip data latches Function in the AD7846. Table 7 is the associated truth table. The digital- 1 X X X 3-state DAC I/O latch in high-Z state to-analog converter (DAC) has two latches that are controlled 0 0 X X DAC I/O latch loaded with DB15 to DB0 by four signals: CS, R/W, LDAC, and CLR. The input latch is 0 1 X X Contents of DAC I/O latch available connected to the data bus (DB15 to DB0). A word is written to on DB15 to DB0 the input latch by bringing CS low and R/W low. The contents X X 0 1 Contents of DAC I/O latch transferred of the input latch can be read back by bringing CS low and R/W to DAC latch high. This feature is called readback and is used in system X 0 X 0 DAC latch loaded with 000…000 diagnostic and calibration routines. X 1 X 0 DAC latch loaded with 100…000 Data is transferred from the input latch to the DAC latch with DIGITAL-TO-ANALOG CONVERSION LDAC the strobe. The equivalent analog value of the DAC latch Figure 21 shows the digital-to-analog section of the AD7846. contents appears at the DAC output. The CLR pin resets the There are three DACs, each of which has its own buffer DAC latch contents to 000…000 or 100…000, depending on the amplifiers. DAC1 and DAC2 are 4-bit DACs. They share a state of R/W. Writing a CLR loads 000…000 and reading a CLR 16-resistor string but have their own analog multiplexers. The loads 100…000. To reset a DAC to 0 V in a unipolar system, the voltage reference is applied to the resistor string. DAC3 is a CLR W user should assert while R/ is low; to reset to 0 V in a 12-bit voltage mode DAC with its own output stage. CLR W bipolar system, assert the while R/ is high. The four MSBs of the 16-bit digital code drive DAC1 and DAC2, R/W and the 12 LSBs control DAC3. Using DAC1 and DAC2, the CLR MSBs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of DAC DAC3. This DAC interpolates between these two voltages to produce the analog output voltage. 16 To prevent nonmonotonicity in the DAC due to amplifier offset DB15 RST LDAC DB15 TO DB0 voltages, DAC1 and DAC2 leap along the resistor string. For DB15 SET LATCHES example, when switching from Segment 1 to Segment 2, DAC1 DB14 TO DB0 RST switches from the bottom of Segment 1 to the top of Segment 2 16 while DAC2 stays connected to the top of Segment 1. The code 3-STATE I/O driving DAC3 is automatically complemented to compensate LATCH CS for the inversion of its inputs. This means that any linearity 16 effects due to amplifier offset voltages remain unchanged when switching from one segment to the next and 16-bit monotonicity is DB15 DB0 ensured if DAC3 is monotonic. Thus, 12-bit resistor matching Figure 20. Input Control Logic in DAC3 guarantees overall 16-bit monotonicity. This is much more achievable than 16-bit matching, which a conventional R-2R structure needs. Rev. G | Page 11 of 24 08490-020 AD7846 V REF+ SEGMENT 16 R DAC1 DAC2 R IN S1 S2 R DAC3 S3 S4 A1 V A3 OUT 12-BIT DAC S15 S14 S17 S16 A2 DB11 TO DB0 DB15 TO DB12 DB15 TO DB12 SEGMENT 1 V REF– Figure 21. Digital-to-Analog Conversion operation. Figure 13 and Figure 14 show the outputs of the OUTPUT STAGE AD7846 without and with the deglitcher. The output stage of the AD7846 is shown in Figure 22. It is capable R IN of driving a 2 kΩ/1000 pF load. It also has a resistor feedback network that allows the user to configure it for gains of 1 or 2. 10kΩ 10kΩ Table 6 shows the different output ranges that are possible. C1 An additional feature is that the output buffer is configured as a track-and-hold amplifier. Although normally tracking its input, V OUT this amplifier is placed in a hold mode for approximately 2.5 μs DAC3 after the leading edge of LDAC. This short state keeps the DAC ONE output at its previous voltage while the AD7846 is internally SHOT changing to its new value. Thus, any glitches that occur in the transition are not seen at the output. In systems where the LDAC LDAC is tied permanently low, the deglitching is not in Figure 22. Output Stage Rev. G | Page 12 of 24 08490-021 08490-022 AD7846 UNIPOLAR BINARY OPERATION Figure 23 shows the AD7846 in the unipolar binary circuit Table 8. Code Table for Figure 23 configuration. The DAC is driven by the AD586 +5 V reference. Binary Number in DAC Latch Because RIN is tied to 0 V, the output amplifier has a gain of 2 1 MSB LSB Analog Output (V ) OUT and the output range is 0 V to +10 V. If a 0 V to +5 V range is 1111 1111 1111 1111 +10 (65,535/65,536) V required, R should be tied to V , configuring the output IN OUT 1000 0000 0000 0000 +10 (32,768/65,536) V stage for a gain of 1. Table 8 gives the code table for the circuit 0000 0000 0000 0001 +10 (1/65,536) V of Figure 23. 0000 0000 0000 0000 0 V +15V +5V 1 16 LSB = 10 V/2 = 10 V/65,536 = 152 μV. 4 21 Offset and gain can be adjusted in Figure 23 as follows: 2 V V DD CC • To adjust offset, disconnect the VREF− input from 0 V, load V OUT V 5 67 V REF+ OUT (0V TO +10V) the DAC with all 0s, and adjust the V voltage until V AD586 REF− OUT 8 R1 5 = 0 V. 10kΩ AD7846* C1 R 6 IN 1µF 4 • For gain adjustment, the AD7846 should be loaded with all 8 V REF– 1s and R1 adjusted until V = 10 (65,535)/(65,536) = DGND 20 OUT 9.999847 V. If a simple resistor divider is used to vary the V SS SIGNAL GROUND VREF− voltage, it is important that the temperature *ADDITIONAL PINS coefficients of these resistors match that of the DAC input –15V OMITTED FOR CLARITY resistance (−300 ppm/°C). Otherwise, extra offset errors are Figure 23. Unipolar Binary Operation introduced over temperature. Many circuits do not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 can be left open circuit and Pin 8 (V ) of the AD7846 tied to 0 V. REF− Rev. G | Page 13 of 24 08490-023 AD7846 BIPOLAR OPERATION Figure 24 shows the AD7846 set up for ±10 V bipolar operation. Full-scale and bipolar zero adjustment are provided by varying The AD588 provides precision ±5 V tracking outputs that are the gain and balance on the AD588. R2 varies the gain on the fed to the VREF+ and VREF− inputs of the AD7846. The code table AD588 while R3 adjusts the +5 V and −5 V outputs together for Figure 24 is shown in Table 9. with respect to ground. +15V +15V +5V For bipolar zero adjustment on the AD7846, load the DAC with R1 39kΩ 100…000 and adjust R3 until V = 0 V. Full scale is adjusted OUT 4 21 46 by loading the DAC with all 1s and adjusting R2 until V = OUT V V DD CC 2 +15V 7 9.999694 V. C1 V V 5 V 3 7 REF+ OUT OUT 1µF 9 (–10V TO +10V) When bipolar zero and full-scale adjustment are not needed, R2 1 AD588 AD7846* R2 and R3 can be omitted, Pin 12 on the AD588 should be connected 5 10kΩ R 6 IN 14 to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V 10 15 8 V output range, there are two choices. By tying Pin 6 (RIN) of the REF– DGND 20 11 16 –15V AD7846 to V (Pin 5), the output stage gain is reduced to OUT SIGNAL V SS GROUND unity and the output range is ±5 V. If only a positive 5 V reference 12 8 13 9 R3 is available, bipolar ±5 V operation is still possible. Tie V to 100kΩ REF− –15V 0 V and connect RIN to VREF+. This also gives a ±5 V output *ADDITIONAL PINS OMITTED FOR CLARITY range. However, the linearity, gain, and offset error specifications Figure 24. Bipolar ±10 V Operation are the same as the unipolar 0 V to 5 V range. Table 9. Offset Binary Code Table for Figure 24 MULTIPLYING OPERATION Binary Number in DAC Latch The AD7846 is a full multiplying DAC. To obtain four-quadrant 1 Analog Output (V ) MSB LSB OUT multiplication, tie VREF− to 0 V, apply the ac input to VREF+, and 1111 1111 1111 1111 +10 (32,767/32,768) V tie RIN to VREF+. Figure 11 shows the large signal frequency 1000 0000 0000 0001 +10 (1/32,768) V response when the DAC is used in this fashion. 1000 0000 0000 0000 0 V 0111 1111 1111 1111 −10 (1/32,768) V 0000 0000 0000 0000 −10 (32,768/32,768) V 1 15 LSB = 10 V/2 = 10 V/32,768 = 305 μV. Rev. G | Page 14 of 24 08490-024 AD7846 POSITION MEASUREMENT APPLICATION ASIN ω t Figure 25 shows the AD7846 in a position measurement applica- LVDT x ASIN ω t V OUT 5 7 V REF+ tion using an linear variable displacement transducer (LVDT), R 6 IN an AD630 synchronous demodulator and a comparator to make AD7846* a 16-bit LVDT-to-digital converter. The LVDT is excited with a 8 V REF– fixed frequency and fixed amplitude sine wave (usually 2.5 kHz, –(1–x) ASIN ω t DGND 20 2 V p-p). The outputs of the secondary coil are in antiphase and DB15 DB0 SIGNAL 10 3 GROUND their relative amplitudes depend on the position of the core in the LVDT. The AD7846 output interpolates between these two inputs PROCESSOR DATA BUS in response to the DAC input code. The AD630 is set up so that it rectifies the DAC output signal. Thus, if the output of the DAC is 9 16 in phase with the VREF+ input, the inverting input to the compara- R1 10 AD630* 100kΩ tor is positive, and if it is in phase with VREF−, the output is nega- 13 C1 tive. By turning on each bit of the DAC in succession starting 1µF with the MSB and deciding to leave it on or turn it off based on TO the comparator output, a 16-bit measurement of the core position PROCESSOR PORT is obtained. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. AD7846 in Position Measurement Application Rev. G | Page 15 of 24 08490-027 AD7846 MICROPROCESSOR INTERFACING AD7846-TO-8086 INTERFACE AD7846-TO-MC68000 INTERFACE Figure 26 shows the 8086 16-bit processor interfacing to the Interfacing between the AD7846 and MC68000 is accomplished AD7846. The double buffering feature of the DAC is not used in using the circuit of Figure 28. The following routine writes data LDAC this circuit because is permanently tied to 0 V. AD0 to to the DAC latches and then outputs the data via the DAC latch. AD15 (the 16-bit data bus) are connected to the DAC data bus 1000 MOVE.W #W, The desired DAC data, (DB0 to DB15). The 16-bit word is written to the DAC in one D0 W, is loaded into MOV instruction and the analog output responds immediately. Data Register 0. W In this example, the DAC address is 0xD000. may be any value ADDRESS BUS between 0 and 65535 (decimal) or 0 and ADDRESS CS FFFF (hexadecimal). DECODE 16-BIT LDAC ALE LATCH MOVE.W D0, The data, W, is 8086 $E000 transferred between +5V CLR DEN D0 and the DAC AD7846* RD register. R/W WR MOVE.W #228, Control is returned AD0 TO AD15 DATA BUS DB0 TO DB15 TRAP D7 to the System Monitor #14 using these two instructions. *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 26. AD7846-to-8086 Interface Circuit In a multiple DAC system, the double buffering of the AD7846 A1 TO A23 ADDRESS BUS allows the user to simultaneously update all DACs. In Figure 27, MC68000 ADDRESS a 16-bit word is loaded to the input latches of each of the DACs CS DS DECODE +5V CLR in sequence. Then, with one instruction to the appropriate DTACK LDAC CS4 LDAC address, (that is, ) is brought low, updating all the AD7846* DACs simultaneously. R/W R/W ADDRESS BUS DATA BUS D0 TO D15 DB0 TO DB15 ADDRESS CS *LINEAR CIRCUITRY OMITTED FOR CLARITY DECODE 16-BIT ALE Figure 28. AD7846-to-MC68000 Interface LATCH 8086 LDAC DEN AD7846* RD R/W WR CLR +5V AD0 TO AD15 DATA BUS DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V DB0 TO DB15 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 27. AD7846-to-8086 Interface: Multiple DAC System Rev. G | Page 16 of 24 08490-029 08490-028 08490-030 AD7846 DIGITAL FEEDTHROUGH In the preceding interface configurations, most digital inputs to the DAC from the noise source. Figure 29 shows an interface the AD7846 are directly connected to the microprocessor bus. circuit that isolates the DAC from the bus. Even when the device is not selected, these inputs are constantly Note that to make use of the AD7846 readback feature using changing. The high frequency logic activity on the bus can feed the isolation technique of Figure 29, the latch needs to be through the DAC package capacitance to show up as noise on bidirectional. the analog output. To minimize this digital feedthrough, isolate A1 TO A15 ADDRESS BUS ADDRESS CS DECODE MICRO- +5V CLR PROCESSOR LDAC R/W R/W DIR G AD7846* DATA BUS B BUS A BUS D0 TO D15 DB0 TO DB15 2× 74LS245 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 29. AD7846 Interface Circuit Using Latches to Minimize Digital Feedthrough Rev. G | Page 17 of 24 08490-031 AD7846 APPLICATION HINTS R1 to R5 represent lead and track resistances on the printed NOISE circuit board. R1 is the resistance between the analog power In high resolution systems, noise is often the limiting factor. supply ground and the signal ground. Because current flowing With a 10 V span, a 16-bit LSB is 152 μV (–96 dB). Thus, the in R1 is very low (bias current of AD588 sense amplifier), the noise floor must stay below −96 dB in the frequency range of effect of R1 is negligible. R2 and R3 represent track resistance interest. Figure 12 shows the noise spectral density for the between the AD588 outputs and the AD7846 reference inputs. AD7846. Because of the force and sense outputs on the AD588, these resistances will also have a negligible effect on accuracy. GROUNDING As well as noise, the other prime consideration in high resolution R4 is the resistance between the DAC output and the load. If RL DAC systems is grounding. With an LSB size of 152 μV and a is constant, then R4 introduces a gain error only that can be load current of 5 mA, 1 LSB of error can be introduced by series trimmed out in the calibration cycle. R5 is the resistance resistance of only 0.03 Ω. between the load and the analog common. If the output voltage is sensed across the load, R5 introduces a further gain error, Figure 30 shows recommended grounding for the AD7846 in a which can be trimmed out. If, on the other hand, the output typical application. voltage is sensed at the analog supply common, R5 appears as ANALOG SUPPLY DIGITAL SUPPLY part of the load and therefore introduces no errors. +15V 0V –15V +5V DGND PRINTED CIRCUIT BOARD LAYOUT Figure 31 shows the AD7846 in a typical application with the AD588 reference, producing an output analog voltage in the R1 ±10 V range. Full-scale and bipolar zero adjustment are SIGNAL GROUND provided by Potentiometer R2 and Potentiometer R3. Latches 2 9 16 4 9 21 20 (2 × 74LS245) isolate the DAC digital inputs from the active R2 microprocessor bus and minimize digital feedthrough. 1 7 6 3 AD588* AD7846* R4 V OUT R3 5 15 8 (+5V TO –5V) R L 14 R5 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 30. AD7846 Grounding Rev. G | Page 18 of 24 08490-032 AD7846 +15V J1 C5 C6 10µF 0.1µF +5V C1 4 21 C31/A31 10µF C7 0.1µF R1 DB15 10 39kΩ 20 C2 2 18 C4/A4 DB14 11 0.1µF 3 17 C5/A5 DB13 12 4 16 C6/A6 4 6 2 5 15 C12 13 74LS245 DB12 C7/A7 1µF 6 14 C8/A8 7 3 7 DB11 14 7 13 V REF+ C9/A9 8 12 C10/A10 15 1 DB10 9 11 C11/A11 AD7846 DB9 16 10 119 AD588 5 14 17 R2 DB8 100kΩ +5V DB7 18 15 8 V REF– 10 20 2 18 –15V 19 C12/A12 DB6 3 17 11 C13/A13 DB5 26 4 16 16 9 V SS C14/A14 C4 C3 5 15 DB4 27 74LS245 C15/A15 12 0.1µF 10µF 6 14 C16/A16 DB3 28 7 13 C17/A17 813 9 8 12 C18/A18 DB2 1 9 11 C19/A19 DB1 2 C20/A20 20 10 DGND 119 R3 100kΩ C21/A21 DB0 3 C22/A22 6 R C23/A23 IN 22 R/W C32/A32 23 CS V OUT V 5 CLR 24 OUT (+10V TO –10V) 25 LDAC Figure 31. Schematic for AD7846 Board Rev. G | Page 19 of 24 08490-033 AD7846 OUTLINE DIMENSIONS 0.005 (0.13) 0.100 (2.54) MIN MAX 28 15 0.610 (15.49) 0.500 (12.70) 114 PIN 1 0.620 (15.75) 0.015 (0.38) 0.225(5.72) 1.490 (37.85) MAX 0.590 (14.99) MIN MAX 0.150 (3.81) MIN 0.018 (0.46) 0.008 (0.20) 0.200 (5.08) 15° 0.125 (3.18) 0° 0.100 0.070 (1.78) SEATING (2.54) PLANE 0.030 (0.76) 0.026 (0.66) BSC 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 32. 28-Lead Ceramic Dual In-Line Package [CERDIP] (Q-28-2) Dimensions shown in inches and (millimeters) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 114 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.195 (4.95) 0.250 (6.35) 0.015 (0.38) 0.125 (3.17) MAX GAUGE PLANE 0.015 (0.38) 0.200 (5.08) MIN 0.115 (2.92) 0.015 (0.38) SEATING PLANE 0.008 (0.20) 0.700 (17.78) 0.022 (0.56) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 33. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev. G | Page 20 of 24 030106-A 071006-A AD7846 0.300 (7.62) REF 0.100 (2.54) 0.075 0.064 (1.63) 0.020 (0.51) (1.91) MIN REF 19 25 0.028 (0.71) 26 18 0.022 (0.56) 0.05 (1.27) 0.458 28 BOTTON 0.458 (11.63) (11.63) 1 SQ VIEW MAX 0.442 (11.23) 0.15 (3.81) SQ REF 0.075 (1.91) REF 12 4 11 5 0.095 (2.41) 0.088 (2.24) 0.055 (1.40) 0.075 (1.90) 0.054 (1.37) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 34. 28-Terminal Ceramic Leadless Chip Carrier [LCC] (E-28-1) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) 0.042 (1.07) MIN 4 26 0.048 (1.22) 5 25 0.021 (0.53) PIN 1 0.042 (1.07) IDENTIFIER 0.013 (0.33) BOTTOM 0.050 TOP VIEW 0.430 (10.92) VIEW (1.27) (PINS DOWN) 0.390 (9.91) (PINS UP) BSC 0.032 (0.81) 0.026 (0.66) 11 19 12 18 0.045 (1.14) R 0.456 (11.582) 0.025 (0.64) SQ 0.120 (3.04) 0.450 (11.430) 0.090 (2.29) 0.495 (12.57) SQ 0.485 (12.32) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 35. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) Rev. G | Page 21 of 24 022106-A 042508-A AD7846 ORDERING GUIDE 1 Model Temperature Range Relative Accuracy Package Description Package Option 5962-89697013A −55°C to +125°C ±16 LSB 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1 5962-8969701XA −55°C to +125°C ±16 LSB 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2 AD7846JN 0°C to +70°C ±16 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846JNZ 0°C to +70°C ±16 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846KN 0°C to +70°C ±8 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846KNZ 0°C to +70°C ±8 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846JP 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846JP-REEL 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846JPZ 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846JPZ-REEL 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KP 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KP-REEL 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KPZ 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KPZ-REEL 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846AP −40°C to +85°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846APZ −40°C to +85°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846AQ −40°C to +85°C ±16 LSB 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2 AD7846BP −40°C to +85°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846BPZ −40°C to +85°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846ACHIPS −40°C to +85°C ±16 LSB DIE 1 Z = RoHS Compliant Part. Rev. G | Page 22 of 24 AD7846 NOTES Rev. G | Page 23 of 24 AD7846 NOTES ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08490-0-4/10(G) Rev. G | Page 24 of 24