ANALOG DEVICES AD7845

2 LC MOS a Complete 12-Bit Multiplying DAC AD7845 FUNCTIONAL BLOCK DIAGRAM FEATURES 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Guaranteed Monotonic (T to T ) MIN MAX Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc. 2 Low Power LC MOS APPLICATIONS Automatic Test Equipment Digital Attenuators Programmable Power Supplies Programmable Gain Amplifiers Digital-to-4–20 mA Converters GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7845 is the industry’s first 4-quadrant multiplying D/A 1. Voltage Output Multiplying DAC converter with an on-chip amplifier. It is fabricated on the The AD7845 is the first DAC which has a full 4-quadrant 2 MOS process, which allows precision linear components LC multiplying capability and an output amplifier on chip. All and digital circuitry to be implemented on the same chip. specifications include amplifier performance. The 12 data inputs drive latches which are controlled by stan- 2. Matched Application Resistors dard CS and WR signals, making microprocessor interfacing Three application resistors provide an easy facility for gain simple. For stand-alone operation, the CS and WR inputs can ranging, voltage offsetting, etc. be tied to ground, making all latches transparent. All digital 3. Space Saving inputs are TTL and 5 V CMOS compatible. The AD7845 saves space in two ways. The integration of the The output amplifier can supply –10 V into a 2 kW load. It is output amplifier on chip means that chip count is reduced. internally compensated, and its input offset voltage is low due to The part is housed in skinny 24-lead 0.3" DIP, 28-terminal laser trimming at wafer level. For normal operation, R is tied LCC and PLCC and 24-terminal SOIC packages. FB , but the user may alternatively choose R , R or R to to V OUT A B C scale the output voltage range. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 (V = +15 V, 6 5%, V = –15 V, 6 5%, V = +10 V, AGND = DGND = O V, AD7845–SPECIFICATIONS DD SS REF V connected to R . V load = 2 kV, 100 pF. All specifications T to T unless otherwise noted.) OUT FB OUT MIN MAX Parameter J Version K Version A Version B Version S Version T Version Units Test Conditions/Comments ACCURACY V REF Resolution 12 12 12 12 12 12 Bits 1 LSB = = 2.4 mV 12 2 Relative Accuracy at +25°C–1–1/2–1–1/2–1–1/2 LSB max All Grades Are Guaranteed T to T–1–3/4–1–3/4–1–3/4 LSB max Monotonic over Temperature MIN MAX Differential Nonlinearity–1–1–1–1–1–1 LSB max DAC Register Loaded with Zero Code Offset Error All 0s. at +25°C–2–1–2–1–2–1mV max T to T–3–2–3–2–4–3mV max MIN MAX Offset Temperature Coefficient; 2 (DOffset/DTemperature)–5–5–5–5–5–5mV/°C typ Gain Error–3–2–3–2–3–2 LSB max R , V Connected FB OUT –6–6–6–6–6–6 LSB max R , V Connected, V = +5 V C OUT REF –6–6–6–6–6–6 LSB max R , V Connected, V = +5 V B OUT REF –7–7–7–7–7–7 LSB max R , V Connected, V = +2.5 V A OUT REF Gain Temperature Coefficient; 2 (DGain/DTemperature)–2–2–2–2–2–2 ppm of FSR/°CR , V Connected FB OUT typ REFERENCE INPUT Input Resistance, Pin 17 8888 88 kW min Typical Input Resistance = 12 kW 16 16 16 16 16 16 kW max APPLICATION RESISTOR RATIO MATCHING 0.5 0.5 0.5 0.5 0.5 0 5 % max Matching Between R , R , R A B C DIGITAL INPUTS V (Input High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min IH V (Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max IL I (Input Current)–1–1–1–1–1–1mA max Digital Inputs at 0 V and V IN DD 2 C (Input Capacitance) 7777 77 pF max IN 4 POWER SUPPLY V Range 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 V min/V max DD Range –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/V max VSS Power Supply Rejection –0.01–0.01–0.01–0.01–0.01–0.01 % per % max V = +15 V – 5%, V = –10 VDGain/DVDD DD REF –0.01–0.01–0.01–0.01–0.01–0.01 % per % max V = –15 V – 5%.DGain/DVSS SS 6666 66 mA max V Unloaded IDD OUT I 4444 44 mA max V Unloaded SS OUT AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance and are not subject to test. DYNAMIC PERFORMANCE Output Voltage Settling Time5555 55ms max To 0.01% of Full-Scale Range Load = 2 kW, 100 pF. V OUT DAC Register Alternately Loaded with All 0s and All 1s. Typically 2.5 ms at 25°C. Load = 2 kW, 100 pF. Slew Rate 11 11 11 11 11 11 V/ms typ V OUT = 0 V. Digital-to-Analog 55 55 55 55 55 55 nV–s typ Measured with V REF Glitch Impulse DAC Register Alternately Loaded with All 0s and All 1s. = –10 V, 10 kHz Sine Wave Multiplying Feedthrough5555 55 mV p-p typ V REF 3 DAC Register Loaded with All 0s. Error Unity Gain Small Signal , R Connected. DAC Loaded Bandwidth 600 600 600 600 600 600 kHz typ V OUT FB = 100 mV p-p with All 1s V REF Sine Wave. , R Connected. DAC Loaded Full Power Bandwidth 175 175 175 175 175 175 kHz typ V OUT FB = 20 V p-p with All 1s. V REF = 2 kW. Sine Wave. R L Total Harmonic Distortion –90 –90 –90 –90 –90 –90 dB typ V = 6 V rms, 1 kHz Sine Wave. REF 5 OUTPUT CHARACTERISTICS Open Loop Gain 85 85 85 85 85 85 dB min V , R Not Connected OUT FB V = –10 V, R = 2 kWOUT L Output Voltage Swing–10–10–10–10–10–10 V min R = 2 kW, C = 100 pF L L Output Resistance 0.2 0.2 0.2 0.2 0.2 0.2W typ R , V Connected, FB OUT Short Circuit Current @ +25°C 11 11 11 11 11 11 mA typ V Shorted to AGND OUT Output Noise Voltage Includes Noise Due to Output (0.1 Hz to 10 Hz) @ +25°C2222 22mV rms typ Amplifier and Johnson Noise f = 10 Hz 250 250 250 250 250 250 nV/√Hz typ of R FB f = 100 Hz 100 100 100 100 100 100 nV/√Hz typ f = 1 kHz 50 50 50 50 50 50 nV/√Hz typ f = 10 kHz 50 50 50 50 50 50 nV/√Hz typ f = 100 kHz 50 50 50 50 50 50 nV/√Hz typ NOTES 1 Temperature ranges are as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C. 2 Guaranteed by design and characterization, not production tested. 3 The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND). 4 The device is functional with a power supply of –12 V. 5 Minimum specified load resistance is 2 kW. Specifications subject to change without notice. –2– REV. B AD7845 1 TIMING CHARACTERISTICS (V = +15 V, 6 5%. V = –15 V, 6 5%. V = +10 V. AGND = DGND = O V.) DD SS REF Limit at T to T MIN MAX Parameter (All Versions) Units Test Conditions/Comments t 30 ns min Chip Select to Write Setup Time CS 0 ns min Chip Select to Write Hold Time t CH 30 ns min Write Pulsewidth t WR 80 ns min Data Setup Time t DS t 0 ns min Data Hold Time DH NOTES 1 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. 1 ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (T = +25°C unless otherwise stated) A Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V DD Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C V to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V SS Extended (S, T Versions) . . . . . . . . . . . . –55°C to +125°C V to AGND . . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V REF DD SS Storage Temperature Range . . . . . . . . . . . –65°C to +150°C V to AGND . . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V RFB DD SS Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C V to AGND . . . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V RA DD SS NOTES 1 V to AGND . . . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V RB DD SS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional V to AGND . . . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V RC DD SS 2 operation of the device at these or any other conditions above those indicated in V to AGND . . . . . . . . . . . . . . . V + 0.3 V, V – 0.3 V OUT DD SS the operational sections of this specification is not implied. Exposure to absolute AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V DD maximum rating conditions for extended periods of time may affect device Digital Input Voltage to DGND . . . . . –0.3 V to V + 0.3 V DD reliability. Only one Absolute Maximum Rating may be applied at any one time. 2 Power Dissipation (Any Package) V may be shorted to AGND provided that the power dissipation of the OUT package is not exceeded. To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. 1 ORDERING GUIDE t t CS CH 5V Relative CS Temperature Accuracy Package 2 3 0V Model Range @ +258C Option t WR AD7845JN 0°C to +70°C–1 LSB N-24 5V WR AD7845KN 0°C to +70°C–1/2 LSB N-24 0V AD7845JP 0°C to +70°C–1 LSB P-28A t t DS DH AD7845KP 0°C to +70°C–1/2 LSB P-28A 5V AD7845JR 0°C to +70°C–1 LSB R-24 DATA AD7845KR 0°C to +70°C–1/2 LSB R-24 0V AD7845AQ –40°C to +85°C–1 LSB Q-24 NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM AD7845BQ –40°C to +85°C–1/2 LSB Q-24 10% TO 90% OF +5V. t = t = 20ns. R F V + V IH IL AD7845AR –40°C to +85°C–1 LSB R-24 2. TIMING MEASUREMENT REFERENCE LEVEL IS 2 AD7845BR –40°C to +85°C–1/2 LSB R-24 AD7845SQ/883B –55°C to +125°C–1 LSB Q-24 AD7845TQ/883B –55°C to +125°C–1/2 LSB Q-24 Figure 1. AD7845 Timing Diagram AD7845SE/883B –55°C to +125°C–1 LSB E-28A NOTES 1 Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip (Q-24) hermetic packages. 2 To order MIL-STD-883, Class B processed parts, add /883B to part number. 3 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. REV. B –3– AD7845 PIN CONFIGURATIONS DIP, SOIC LCC PLCC TERMINOLOGY LEAST SIGNIFICANT BIT DIGITAL-TO-ANALOG GLITCH IMPULSE This is the analog weighting of 1 bit of the digital word in a This is the amount of charge injected from the digital inputs to V REF the analog output when the inputs change state. This is nor- DAC. For the AD7845, 1 LSB = . 12 mally specified as the area of the glitch in either pA-secs or 2 nV-secs depending upon whether the glitch is measured as a = current or voltage. The measurement takes place with V REF RELATIVE ACCURACY AGND. Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the DIGITAL FEEDTHROUGH endpoints of the DAC transfer function. It is measured after When the DAC is not selected (i.e., CS is high) high frequency adjusting for both endpoints (i.e., offset and gain error are ad- logic activity on the device digital inputs is capacitively coupled justed out) and is normally expressed in least significant bits or pin. This through the device to show up as noise on the V OUT as a percentage of full-scale range. noise is digital feedthrough. DIFFERENTIAL NONLINEARITY MULTIPLYING FEEDTHROUGH ERROR Differential nonlinearity is the difference between the measured This is ac error due to capacitive feedthrough from the V REF change and the ideal 1 LSB change between any two adjacent terminal to V when the DAC is loaded with all 0s. OUT codes. A specified differential nonlinearity of +1 LSB max over the operating temperature range ensures monotonicity. OPEN-LOOP GAIN Open-loop gain is defined as the ratio of a change of output GAIN ERROR pin with all 1s loaded voltage to the voltage applied at the V REF Gain error is a measure of the output error between an ideal in the DAC. It is specified at dc. DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero UNITY GAIN SMALL SIGNAL BANDWIDTH with an external potentiometer. See Figure 13. This is the frequency at which the magnitude of the small signal voltage gain of the output amplifier is 3 dB below unity. The ZERO CODE OFFSET ERROR device is operated as a closed-loop unity gain inverter (i.e., This is the error present at the device output with all 0s loaded DAC is loaded with all 1s). in the DAC. It is due to the op amp input offset voltage and bias current and the DAC leakage current. OUTPUT RESISTANCE This is the effective output source resistance. TOTAL HARMONIC DISTORTION This is the ratio of the root-mean-square (rms) sum of the har- FULL POWER BANDWIDTH monics to the fundamental, expressed in dBs. Full power bandwidth is specified as the maximum frequency, at unity closed-loop gain, for which a sinusoidal input signal will OUTPUT NOISE produce full output at rated load without exceeding a distortion This is the noise due to the white noise of the DAC and the level of 3%. input noise of the amplifier. –4– REV. B Typical Performance Characteristics–AD7845 Figure 2. Frequency Response, G = –1 Figure 3. Output Voltage Swing vs. Figure 4. Noise Spectral Density Resistive Load Figure 6. Typical AD7845 Linearity Figure 7. Multiplying Feedthrough Figure 5. THD vs. Frequency vs. Power Supply Error vs. Frequency 80 70 60 50 40 30 20 10 0 –10 –20 0 22 4 6 8 1012 14 16180 TIME – s Figure 8. Unity Gain Inverter Pulse Figure 9. Unity Gain Inverter Pulse Figure 10. Digital-to-Analog Glitch Response (Large Signal) Response (Small Signal) Impulse (All 1s to All 0s Transition) REV. B –5– OUTPUT – mV AD7845 PIN FUNCTION DESCRIPTION (DIP) Pin Mnemonic Description 1V Voltage Output Terminal OUT 2-11 DB11–DB2 Data Bit 11 (MSB) to Data Bit 2 12 DGND Digital Ground. The metal lid on the ceramic package is connected to this pin 13-14 DB1–DB0 Data Bit 1 to Data Bit 0 (LSB) 15 WR Write Input. Active low 16 CS Chip Select Input. Active low 17 V Reference Input Voltage which can be an ac or dc signal REF 18 AGND Analog Ground. This is the reference point for external analog circuitry 19 V Negative power supply for the output amplifier (nominal –12 V to +15 V) SS 20 V Positive power supply (nominal +12 V to +15 V) DD 21 R Application resistor. R = 4 R A A FB 22 R Application resistor. R = 2 R B B FB 23 R Application resistor. R = 2 R C C FB 24 R Feedback resistor in the DAC. For normal operation this is connected to V FB OUT CIRCUIT INFORMATION Each of the switches A–C steers 1/4 of the total reference cur- Digital Section rent with the remaining 1/4 passing through the R-2R section. Figure 11 is a simplified circuit diagram of the AD7845 input An output amplifier and feedback resistor perform the current- control logic. When CS and WR are both low, the DAC latch is to-voltage conversion giving loaded with the data on the data inputs. All the digital inputs V = – D · V OUT REF are TTL, HCMOS and +5 V CMOS compatible, facilitating easy microprocessor interfacing. All digital inputs incorporate where D is the fractional representation of the digital word. (D standard protection circuitry. can be set from 0 to 4095/4096.) The amplifier can maintain –10 V across a 2 kW load. It is inter- nally compensated and settles to 0.01% FSR (1/2 LSB) in less than 5 ms. The input offset voltage is laser trimmed at wafer level. The amplifier slew rate is typically 11 V/ms, and the unity gain small signal bandwidth is 600 kHz. There are three extra on-chip resistors (R , R , R ) connected to the amplifier invert- A B C ing terminal. These are useful in a number of applications in- cluding offset adjustment and gain ranging. V REF RR R Figure 11. AD7845 Input Control Logic 2R 2R 2R 2R 2R 2R 2R C BA S9 S8 S0 D/A Section Figure 12 shows a simplified circuit diagram for the AD7845 I OUT D/A section and output amplifier. A segmented scheme is used whereby the 2 MSBs of the 12-bit AGND SHOWN FOR ALL 1s ON DAC data word are decoded to drive the three switches A-C. The remaining 10 bits drive the switches (S0–S9) in a standard R-2R Figure 12. Simplified Circuit Diagram for the AD7845 D/A ladder configuration. Section –6– REV. B AD7845 UNIPOLAR BINARY OPERATION BIPOLAR OPERATION Figure 13 shows the AD7845 connected for unipolar binary (4-QUADRANT MULTIPLICATION) is an ac signal, the circuit performs operation. When V IN The recommended circuit for bipolar operation is shown in 2-quadrant multiplication. The code table for Figure 13 is given Figure 14. Offset binary coding is used. in Table I. The offset specification of this circuit is determined by the matching of internal resistors R and R and by the zero code B C offset error of the device. Gain error may be adjusted by varying the ratio of R1 and R2. To use this circuit without trimming and keep within the gain error specifications, resistors R1 and R2 should be ratio matched to 0.01%. The code table for Figure 14 is given in Table II. Figure 13. Unipolar Binary Operation Table I. Unipolar Binary Code Table for AD7845 Binary Number In DAC Register Analog Output, V OUT MSB LSB   4095 1111 1111 1111 –V   IN Ł4096ł   2048 1000 0000 0000 –V = –1/2 V   IN IN Ł4096ł Figure 14. Bipolar Offset Binary Operation   1 Table II. Bipolar Code Table for Offset Binary Circuit of 0000 0000 0001 –V   IN Ł4096łFigure 14 0000 0000 0000 0 V Binary Number In DAC Register Analog Output, V OUT OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13 MSB LSB   2047 Zero Offset Adjustment 1111 1111 1111 +V   IN 2048Łł 1. Load DAC with all 0s. 2. Trim R3 until V = 0 V. OUT   1 Gain Adjustment 1000 0000 0001 +V   IN 2048Łł 1. Load DAC with all 1s. 4095 1000 0000 0000 0 V . 2. Trim R1 so that V = –V OUT IN 4096   1 0111 1111 1111 –V   IN In fixed reference applications, full scale can also be adjusted by 2048Łł omitting R1 and R2 and trimming the reference voltage magni- tude. For high temperature applications, resistors and potenti- ometers should have a low temperature coefficient.  2048  0000 0000 0000 –V   = –V IN IN 2048Łł REV. B –7– AD7845 APPLICATIONS CIRCUITS PROGRAMMABLE CURRENT SOURCES The AD7845 is ideal for designing programmable current PROGRAMMABLE GAIN AMPLIFIER (PGA) The AD7845 performs a PGA function when connected as in sources using a minimum of external components. Figures 16 Figure 15. In this configuration, the R-2R ladder is connected and 17 are examples. The circuit of Figure 16 drives a program- into a load referenced to a negative supply. in the amplifier feedback loop. R is the amplifier input resis- mable current I FB L tor. As the code decreases, the R-2R ladder resistance increases Figure 17 shows the circuit for sinking a programmable current, . The same set of circuit equations apply for both diagrams. and so the gain increases. I L   1 4095 = I = I + I R I L 3 2 1 DAC D = 0 to = –V · · , V   OUT IN R 4096ŁłD FB   D·|V | 4095 IN D = 0 to 1 I = ,   R ±V 1 DAC IN RŁ4096ł= –V · · = , since R = R DAC IN FB DAC R DAC D D   1 D·|V | IN D·|V | IN I = R = , since R = R   2 FB FB DAC R1 RŁłDAC R1 D·|V | D·|V | IN IN I = + L R DAC R1   R1 D·|V | IN 1 + = ·   ŁRłR1 DAC Note that by making R1 much smaller than R , the circuit DAC and its becomes insensitive to both the absolute value of R DAC temperature variations. Now, the only resistor determining load is the sense resistor R1. current I L If R1 = 100 W, then the programming range is 0 mA to 100 mA, and the resolution is 0.024 mA. Figure 15. AD7845 Connected as PGA As the programmed gain increases, the error and noise also increase. For this reason, the maximum gain should be limited to 256. Table III shows gain versus code. Note that instead of using R as the input resistor, it is also FB possible to use combinations of the other application resistors, , R and R . For instance, if R is used instead of R , the R A B C B FB gain range for the same codes of Table II now goes from l/2 to 128. Table III. Gain and Error vs. Input Code for Figure 15 Digital Inputs Gain Error (%) 1111 1111 1111 4096/4095 » 10.04 1000 0000 0000 2 0.07 0100 0000 0000 4 0.13 0010 0000 0000 8 0.26 0001 0000 0000 16 0.51 Figure 16. Programmable Current Source 0000 1000 0000 32 1.02 0000 0100 0000 64 2.0 0000 0010 0000 128 4.0 0000 0001 0000 256 8.0 –8– REV. B AD7845 Figure 17. Programmable Current Sink Figure 18. 4–20 mA Current Loop 4–20 mA CURRENT LOOP APPLICATION HINTS The AD7845 provides an excellent way of making a 4-20 mA General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the current loop circuit. This is basically a variation of the circuits analog output. The simplest method of ensuring that voltages at in Figures 16 and 17 and is shown in Figure 18. The application (Value 4R) produces the effective 4 mA offset. AGND and DGND are equal is to tie AGND and DGND resistor R A together at the AD7845. In more complex systems where the I = I = I + I L 3 2 1 AGND and DGND intertie is on the backplane, it is recom- Since I > I , 2 1 mended that two diodes be connected in inverse parallel be- tween the AD7845 AGND and DGND pins (IN914 or  2.5 2.5  V 1 equivalent). X·R +·D·R = – =  FB FB · I L 4R RŁłDAC 156 156 Digital Glitches: When a new digital word is written into the DAC, it results in a change of voltage applied to some of the and since R =R =R DAC FB DAC switch gates. This voltage change is coupled across the switch stray capacitance and appears as an impulse on the cur-  2.5  1000 + D·2.5·mA =   rent output bus of the DAC. In the AD7845, impulses on this I L 4 156Łł bus are converted to a voltage by R and the output amplifier. FB The output voltage glitch energy is specified as the area of the = [4 + (16 · D)]mA, where D goes from 0 to 1 with resulting spike in nV-seconds. It is measured with V con- REF Digital Code nected to analog ground and for a zero to full-scale input code When D = 0 (Code of all 0s): transition. Since microprocessor based systems generally have I = 4 mA L noisy grounds which couple into the power supplies, the AD7845 V and V terminals should be decoupled to signal When D = 1 (Code of all 1s): DD SS ground. I = 20 mA L Temperature Coefficients: The gain temperature coefficient The above circuit succeeds in significantly reducing the circuit of the AD7845 has a maximum value of 5 ppm/°C. This corre- component count. Both the on-chip output amplifier and the sponds to worst case gain shift of 2 LSBs over a 100°C tem- application resistor R contribute to this. A perature range. When trim resistors R1 and R2 in Figure 13 are used to adjust full-scale range, the temperature coefficient of R1 and R2 must be taken into account. The offset tempera- ture coefficient is 5 ppm of FSR/°C maximum. This corre- sponds to a worst case offset shift of 2 LSBs over a 100°C temperature range. The reader is referred to Analog Devices Application Note “Gain Error and Gain Temperature Coefficient of CMOS Mul- tiplying DACs,” Publication Number E630C-5-3/86. REV. B –9– AD7845 MICROPROCESSOR INTERFACING 8-BIT MICROPROCESSOR SYSTEMS 16-BIT MICROPROCESSOR SYSTEMS Figure 22 shows an interface circuit for the AD7845 to the Figures 19, 20 and 21 show how the AD7845 interfaces to 8085A 8-bit microprocessor. The software routine to load data three popular 16-bit microprocessor systems. These are the to the device is given in Table IV. Note that the transfer of the MC68000, 8086 and the TM32010. The AD7845 is treated as 12 bits of data requires two write operations. The first of these a memory-mapped peripheral to the processors. In each case, a loads the 4 MSBs into the 7475 latch. The second write opera- write instruction loads the AD7845 with the appropriate data. tion loads the 8 LSBs plus the 4 MSBs (which are held by the The particular instructions used are as follows: latch) into the DAC. MC68000: MOVE 8086: MOV TMS32010: OUT Figure 22. 8085A Interface Table IV. Subroutine Listing for Figure 22 Figure 19. AD7845 to MC68000 Interface 2000 LOAD DAC: LXI H,#3000 The H,L register pair are loaded with latch address 3000. MVI A,#“MS” Load the 4 MSBs of data into accumulator. MOV M,A Transfer data from accumulator to latch. INR L Increment H,L pair to AD7845 address. MVI A,#“LS” Load the 8 LSBs of data into accumulator. MOV M,A Transfer data from accumulator to DAC. Figure 20. AD7845 to 8086 Interface RET End of routine. Figure 21. TMS32010 –10– REV. B AD7845 Figure 23 and 24 are the interface circuits for the Z80 and DIGITAL FEEDTHROUGH MC6809 microprocessors. Again, these use the same basic In the preceding interface configurations, most digital inputs to format as the 8085A interface. the AD7845 are directly connected to the microprocessor bus. Even when the device is not selected, these inputs will be con- stantly changing. The high frequency logic activity on the bus can feed through the DAC package capacitance to show up as noise on the analog output. To minimize this digital feedthrough isolate the DAC from the noise source. Figure 25 shows an interface circuit which uses this technique. All data inputs are latched from the busy by the CS signal. One may also use other means, such as peripheral interface devices, to reduce the digital feedthrough. Figure 23. AD7845 to Z80 Interface Figure 25. AD7845 Interface Circuit Using Latches to Minimize Digital Feedthrough Figure 24. MC6809 Interface REV. B –11– AD7845 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP 28-Terminal Leadless Ceramic Chip Carrier (N-24) (E-28A) 24-Lead Cerdip 28-Terminal Plastic Leaded Chip Carrier (Q-24) (P-28A) 24-Lead Ceramic DIP 24-Lead SOIC (D-24A) (R-24) 0.6141 (15.60) 0.5985 (15.20) 24 13 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 12 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) 3 458 0.0926 (2.35) 0.0098 (0.25) 88 0.0500 SEATING 08 0.0118 (0.30) 0.0192 (0.49) 0.0500 (1.27) 0.0125 (0.32) (1.27) PLANE 0.0040 (0.10) 0.0138 (0.35) 0.0157 (0.40) 0.0091 (0.23) BSC –12– REV. B PRINTED IN U.S.A. C1189b–1–9/99