ANALOG DEVICES AD7843

Touch Screen Digitizer AD7843 FEATURES FUNCTIONAL BLOCK DIAGRAM 4-wire touch screen interface +V PENIRQ CC Specified throughput rate of 125 kSPS Low power consumption: PEN 1.37 mW max at 125 kSPS with VCC = 3.6 V AD7843 INTERRUPT X+ Single supply, VCC of 2.2 V to 5.25 V X– Ratiometric conversion High speed serial interface Y+ T/H Programmable 8-bit or 12-bit resolution Y– 4-TO-1 2 auxiliary analog inputs I/P MUX Shutdown mode: 1 µA max IN3 COMP 16-lead QSOP and TSSOP packages IN4 V GND REF APPLICATIONS CHARGE Personal digital assistants REDISTRIBUTION DAC Smart hand-held devices +V CC Touch screen monitors SAR + ADC Point-of-sales terminals CONTROL LOGIC Pagers SPORT DIN CS DOUT DCLK BUSY Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7843 is a 12-bit successive approximation ADC with a 1. Ratiometric conversion mode available eliminating errors synchronous serial interface and low on resistance switches for due to on-board switch resistances. driving touch screens. The part operates from a single 2.2 V to 2. Maximum current consumption of 380 µA while operating 5.25 V power supply and features throughput rates greater than at 125 kSPS. 125 kSPS. 3. Power-down options available. 4. Analog input range from 0 V to V . REF The external reference applied to the AD7843 can be varied 5. Versatile serial I/O port. from 1 V to +VCC, while the analog input range is from 0 V to V The device includes a shutdown mode that reduces the REF. current consumption to less than 1 µA. The AD7843 features on-board switches. This, coupled with low power and high speed operation, make this device ideal for battery-powered systems such as personal digital assistants with resistive touch screens, and other portable equipment. The part is available in a 16-lead 0.15" quarter size outline package (QSOP) and a 16-lead thin shrink small outline package (TSSOP). Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 02144-B-001 AD7843 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Input ............................................................................... 12 Timing Specifications .................................................................. 4 Control Register ......................................................................... 14 Absolute Maximum Ratings............................................................ 5 Power vs. Throughput Rate....................................................... 15 ESD Caution.................................................................................. 5 Serial Interface ............................................................................ 16 Pin Configuration and Function Descriptions............................. 6 Detailed Serial Interface Timing .............................................. 17 Terminology ...................................................................................... 7 Pen Interrupt Request................................................................ 19 Typical Performance Characteristics ............................................. 8 Grounding and Layout .............................................................. 19 Circuit Information........................................................................ 11 Outline Dimensions ....................................................................... 20 ADC Transfer Function............................................................. 11 Ordering Guide .......................................................................... 20 Typical Connection Diagram ................................................... 11 REVISION HISTORY 3/04—Data Sheet Changed from Rev. A to Rev. B Updated Format..................................................................Universal Changes to Absolute Maximum Ratings ....................................... 5 Addition to the PD0 and PD1 Section......................................... 14 Additions to Ordering Guide........................................................ 20 3/03—Data Sheet Changed from Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 16 Rev. B | Page 2 of 20 AD7843 SPECIFICATIONS VCC = 2.7 V to 3.6 V, VREF = 2.5 V, fSCLK = 2 MHz, TA = −40°C to +85°C, unless otherwise noted. Table 1. 1 Parameter AD7843A Unit Test Conditions/Comments DC ACCURACY Resolution 12 Bits No Missing Codes 11 Bits min 2 Integral Nonlinearity ±2 LSB max 2 Offset Error ±6 LSB max VCC = 2.7 V 3 Offset Error Match 1 LSB max 0.1 LSB typ 2 Gain Error ±4 LSB max 3 Gain Error Match 1 LSB max 0.1 LSB typ Power Supply Rejection 70 dB typ SWITCH DRIVERS 2 On-Resistance Y+, X+ 5 Ω typ Y−, X− 6 Ω typ ANALOG INPUT Input Voltage Ranges 0 to V V REF DC Leakage Current ±0.1 µA typ Input Capacitance 37 pF typ REFERENCE INPUT V Input Voltage Range 1.0/+V V min/max REF CC DC Leakage Current ±1 µA max VREF Input Impedance 5 GΩ typ CS = GND or +VCC 3 VREF Input Current 20 µA max 8 µA typ 1 µA typ f = 12.5 kHz SAMPLE 1 µA max CS = +V ; 0.001 µA typ CC LOGIC INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.4 V max INL Input Current, I ±1 µA max Typically 10 nA, V = 0 V or +V IN IN CC 4 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 250 µA; V = 2.2 V to 5.25 V OH CC SOURCE CC Output Low Voltage, VOL 0.4 V max ISINK = 250 µA PENIRQ Output Low Voltage, VOL 0.4 V max ISINK = 250 µA; 100 kW pull-up Floating-State Leakage Current ±10 µA max 4 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 12 DCLK Cycles max Track-and-Hold Acquisition Time 3 DCLK Cycles min Throughput Rate 125 kSPS max Footnotes on next page. Rev. B | Page 3 of 20 AD7843 1 Parameter AD7843A Unit Test Conditions/Comments POWER REQUIREMENTS VCC (Specified Performance) 2.7/3.6 V min/max Functional from 2.2 V to 5.25 V 5 I Digital I/Ps = 0 V or V CC CC Normal Mode (f = 125 kSPS) 380 µA max V = 3.6 V, 240 µA typ SAMPLE CC Normal Mode (f = 12.5 kSPS) 170 µA typ V = 2.7 V, f = 200 kHz SAMPLE CC DCLK Normal Mode (Static) 150 µA typ V = 3.6 V CC Shutdown Mode (Static) 1 µA max 5 Power Dissipation Normal Mode (fSAMPLE = 125 kSPS) 1.368 mW max VCC = 3.6 V Shutdown 3.6 µW max VCC = 3.6 V 1 Temperature range as follows: A Version: −40°C to +85°C. 2 See the Terminology section. 3 Guaranteed by design. 4 Sample tested @ 25°C to ensure compliance. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS T = T to T , unless otherwise noted; V = 2.7 V to 3.6 V, V = 2.5 V. A MIN MAX CC REF 1 Table 2. Timing Specifications Parameter Limit at T , T Unit Description MIN MAX 2 fDCLK 10 kHz min 2 MHz max t 1.5 µs min Acquisition time ACQ t 10 ns min CS falling edge to First DCLK rising edge 1 t 60 ns max CS falling edge to BUSY three-state disabled 2 CS falling edge to DOUT three-state disabled t3 60 ns max t4 200 ns min DCLK high pulse width t5 200 ns min DCLK low pulse width t 60 ns max DCLK falling edge to BUSY rising edge 6 t7 10 ns min Data setup time prior to DCLK rising edge t8 10 ns min Data valid to DCLK hold time 3 t 200 ns max Data access time after DCLK falling edge 9 t 0 ns min CS rising edge to DCLK ignored 10 t 200 ns max CS rising edge to BUSY high impedance 11 4 CS rising edge to DOUT high impedance t12 200 ns max 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V. 4 t is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated 12 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. B | Page 4 of 20 02144-B-002 AD7843 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating +V to GND −0.3 V to +7 V CC Analog Input Voltage to GND −0.3 V to V + 0.3 V CC Digital Input Voltage to GND −0.3 V to VCC + 0.3 V Digital Output Voltage to GND −0.3 V to VCC + 0.3 V VREF to GND −0.3 V to VCC + 0.3 V 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Stresses above those listed under Absolute Maximum Rating Commercial −40°C to +85°C may cause permanent damage to the device. This is a stress Storage Temperature Range −65°C to +150°C rating only; functional operation of the device at these or any Junction Temperature 150°C other conditions above those listed in the operational sections QSOP, TSSOP Package, Power Dissipation 450 mW of this specification is not implied. Exposure to absolute θJA Thermal Impedance 149.97°C/W (QSOP) maximum rating conditions for extended periods may affect 150.4°C/W (TSSOP) device reliability. θJC Thermal Impedance 38.8°C/W (QSOP) 27.6°C/W (TSSOP) IR Reflow Soldering Peak Temperture 220°C (±5°C) Time-to-Peak Temperture 10 sec to 30 sec Ramp-Down Rate 6°C/sec max Pb-free parts only Peak Temperture 250°C Time-to-Peak Temperture 20 sec to 40 sec Ramp-Up Rate 3°C/sec max Ramp-Down Rate 6°C/sec max ________________ 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 20 AD7843 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS +V 1 16 DCLK CC X+ 2 15 CS 3 Y+ 14 DIN AD7843 4 X– 13 BUSY TOP VIEW 5 12 Y– DOUT (Not to Scale) 6 GND 11 PENIRQ 7 10 IN3 +V CC 9 IN4 8 V REF Figure 3. Pin Configuration QSOP/TSSOP Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1, 10 +V Power Supply Input. The +V range for the AD7843 is from 2.2 V to 5.25 V. Both +V pins should be connected CC CC CC directly together. 2 X+ X+ Position Input. ADC Input Channel 1. 3 Y+ Y+ Position Input. ADC Input Channel 2. 4 X− X− Position Input. 5 Y− Y− Position Input. 6 GND Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and any external reference signal should be referred to this GND voltage. 7 IN3 Auxiliary Input 1. ADC Input Channel 3. 8 IN4 Auxiliary Input 2. ADC Input Channel 4. 9 VREF Reference Input for the AD7843. An external reference must be applied to this input. The voltage range for the external reference is 1.0 V to +V . For specified performance, it is 2.5 V. CC 11 PENIRQ Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up register externally). 12 DOUT Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high. 13 BUSY BUSY Output. Logic Output. This output is high impedance when CS is high. 14 DIN Data In. Logic input. Data to be written to the AD7843 control register is provided on this input and is clocked into the register on the rising edge of DCLK (see the Control Register section). 15 CS Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating conversions on the AD7843 and also enables the serial input/output register. 16 DCLK External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7843 conversion process. Rev. B | Page 6 of 20 02144-B-003 AD7843 TERMINOLOGY Integral Nonlinearity Track-and-Hold Acquisition Time This is the maximum deviation from a straight line passing The track-and-hold amplifier enters the acquisition phase on through the endpoints of the ADC transfer function. The the fifth falling edge of DCLK after the START bit has been endpoints of the transfer function are zero scale, a point 1 LSB detected. Three DCLK cycles are allowed for the track-and-hold below the first code transition, and full scale, a point 1 LSB acquisition time. The input signal is fully acquired to the 12-bit above the last code transition. level within this time even with the maximum specified DCLK frequency. See the Analog Input section for more details. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB On Resistance change between any two adjacent codes in the ADC. This is a measure of the ohmic resistance between the drain and source of the switch drivers. Offset Error This is the deviation of the first code transition (00…000) to (00…001) from the ideal, that is, AGND + 1 LSB. Gain Error This is the deviation of the last code transition (111…110) to (111…111) from the ideal (V − 1 LSB) after the offset error REF has been adjusted out. Rev. B | Page 7 of 20 AD7843 TYPICAL PERFORMANCE CHARACTERISTICS 207 141 206 140 205 139 204 138 203 202 137 201 136 200 135 199 198 134 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 4. Supply Current vs. Temperature Figure 7. Power-Down Supply Current vs. Temperature 230 1000 220 f = 12.5kHz SAMPLE V = +V REF CC 210 200 190 V = +V 180 REF CC 170 160 150 100 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 2.2 2.7 3.2 3.7 4.2 4.7 5.2 +V (V) +V (V) CC CC Figure 8. Maximum Sample Rate vs. +V Figure 5. Supply Current vs. +V CC CC 0.6 0.20 0.15 0.4 0.10 0.2 0.05 0 0 –0.05 –0.2 –0.10 –0.4 –0.15 –0.6 –0.20 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Change in Offset vs. Temperature Figure 6. Change in Gain vs. Temperature Rev. B | Page 8 of 20 DELTA FROM +25°C (LSB) SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 02144-B-006 02144-B-005 02144-B-004 DELTA FROM +25°C (LSB) SAMPLE RATE (kSPS) SUPPLY CURRENT (nA) 02144-B-009 02144-B-008 02144-B-007 AD7843 14 7.5 13 6.5 12 11 5.5 10 9 4.5 8 3.5 7 6 2.5 5 4 1.5 3 0.5 2 10 25 40 55 70 85 100 115 130 –40 –20 020 40 60 80 SAMPLE RATE (kHz) TEMPERATURE (°C) Figure 10. Reference Current vs. Sample Rate Figure 13. Reference Current vs. Temperature 10 9 9 8 Y+ Y+ X+ X+ 8 7 X– 7 6 Y– X– 6 5 Y– 5 4 4 3 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100 +V (V) TEMPERATURE (°C) CC Figure 14. Switch-On Resistance vs. Temperature Figure 11. Switch-On Resistance vs. +V CC (X+, Y+:+VCC to Pin; X−, Y−: Pin to GND) (X+, Y+: +V to Pin; X−, Y−: Pin to GND) CC 0 2.0 f = 125kHz SAMPLE 1.8 f = 15kHz IN 20 SNR = 68.34dB 1.6 INL: R = 2kΩ 1.4 40 1.2 INL: R = 500Ω 60 1.0 0.8 80 DNL: R = 2kΩ 0.6 0.4 100 DNL: R = 500Ω 0.2 120 0 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 60.0 15 35 55 75 95 115 135 155 175 195 FREQUENCY (kHz) SAMPLING RATE (kSPS) Figure 15. Auxiliary Channel Dynamic Performance Figure 12. Maximum Sampling Rate vs. R IN (fSAMPLE =125 kHz, fINPUT = 15 kHz) Rev. B | Page 9 of 20 ERROR (LSB) R (Ω) REFERENCE CURRENT (µA) ON 02144-B-012 02144-B-011 02144-B-010 SNR (dB) R (Ω) REFERENCE CURRENT (µA) ON 02144-B-015 02144-B-014 02144-B-013 AD7843 0 Figure 16 shows the power supply rejection ratio versus V CC V = 3V, V = 2.5V CC REF supply frequency for the AD7843. The power supply rejection 100mV p-p SINEWAVE ON +V CC –20 f = 125kHz, f = 20kHz SAMPLE IN ratio is defined as the ratio of the power in the ADC output at full-scale frequency fS to the power of a 100 mV sine wave –40 applied to the ADC VCC supply of frequency fS: –60 PSRR (dB) = 10 log (Pf/Pfs) where: –80 Pf is the power at frequency f in ADC output. –100 Pfs is the power at frequency f coupled onto the ADC V S CC supply. –120 0 1020 3040 50 6070 8090 100 Here a 100 mV p-p sine wave is coupled onto the V supply. CC V RIPPLE FREQUENCY (kHz) CC Decoupling capacitors of 10 µF and 0.1 µF were used on the Figure 16. AC PSRR vs. Supply Ripple Frequency supply. Rev. B | Page 10 of 20 PSRR (dB) 02144-B-016 AD7843 CIRCUIT INFORMATION The AD7843 is a fast, low-power, 12-bit, single-supply, A/D converter. The AD7843 can be operated from a 2.2 V to 5.25 V 111...111 111...110 supply. When operated from either a 5 V supply or a 3 V supply, the AD7843 is capable of throughput rates of 125 kSPS when 111...000 1LSB = V /4096 provided with a 2 MHz clock. REF 011...111 The AD7843 provides the user with an on-chip track-and-hold, 000...010 multiplexer, ADC, and serial interface housed in tiny 16-lead 000...001 000...000 QSOP or TSSOP packages, which offer the user considerable 1LSB +V –1LSB REF 0V space-saving advantages over alternative solutions. The serial ANALOG INPUT clock input (DCLK) accesses data from the part and also provides Figure 17. AD7843 Transfer Characteristic the clock source for the successive approximation ADC. The analog input range is 0 V to VREF (where the externally-applied V can be between 1 V and V ). REF CC TYPICAL CONNECTION DIAGRAM The analog input to the ADC is provided via an on-chip Figure 18 shows a typical connection diagram for the AD7843 multiplexer. This analog input can be any one of the X and Y in a touch screen control application. The AD7843 requires an panel coordinates. The multiplexer is configured with low external reference and an external clock. The external reference resistance switches that allow an unselected ADC input channel can be any voltage between 1 V and V . The value of the CC to provide power and an accompanying pin to provide ground reference voltage sets the input range of the converter. The for an external device. For some measurements, the on resistance conversion result is output MSB first, followed by the remaining of the switches could present a source of error. However, with a 11 bits and three trailing zeroes, depending on the number of differential input to the converter and a differential reference clocks used per conversion. (See the Serial Interface section.) architecture, this error can be negated. For applications where power consumption is a concern, the power management option should be used to improve power ADC TRANSFER FUNCTION performance. See Table 7 for the available power management The output coding of the AD7843 is straight binary. The options. designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSBs, and so forth.). The LSB size equals V /4096. The ideal transfer characteristic for the AD7843 is REF shown in Figure 17. 2.2V TO 5V 1µF TO 10µF 0.1µF 1 +V DCLK CC 16 SERIAL/CONVERSION CLOCK (OPTIONAL) 2 15 CHIP SELECT X+ CS AD7843 3 SERIAL DATA IN Y+ DIN 14 4 X– BUSY 13 CONVERTER STATUS TOUCH 5 SERIAL DATA OUT Y– DOUT 12 SCREEN 6 GND 11 PENIRQ PEN INTERRUPT 7 IN3 +V 10 CC AUXILIARY INPUTS 100kΩ 8 IN4 V 9 REF (OPTIONAL) 0.1µF Figure 18. Typical Application Circuit Rev. B | Page 11 of 20 ADC CODE 02144-B-017 02144-B-018 AD7843 ANALOG INPUT Acquisition Time Figure 19 shows an equivalent circuit of the analog input The track-and-hold amplifier enters tracking mode on the structure of the AD7843, which contains a block diagram of the falling edge of the fifth DCLK after the START bit us detected input multiplexer, the differential input of the ADC, and the (see Figure 24). The time required for the track-and-hold differential reference. amplifier to acquire an input signal depends on how quickly the Table 5 shows the multiplexer address corresponding to each 37 pF input capacitance is charged. With zero source impedance DFR analog input, both for the SER/ bit in the control register on the analog input, three DCLK cycles are always sufficient to set high and low. The control bits are provided serially to the acquire the signal to the 12-bit level. With a source impedance device via the DIN pin. For more information on the control R on the analog input, the actual acquisition time required is IN register, see the Control Register section. calculated using the formula: When the converter enters hold mode, the voltage difference t = 8.4×(R +100Ω)× 37 pF ACQ IN between the +IN and −IN inputs (see Figure 19) is captured on the internal capacitor array. The input current on the analog where R is the source impedance of the input signal and 100 Ω IN inputs depends on the conversion rate of the device. During the and 37 pF is the input RC value. Depending on the frequency of sample period, the source must charge the internal sampling DCLK used, three DCLK cycles may or may not be sufficient to capacitor (typically 37 pF). Once the capacitor is fully charged, acquire the analog input signal with various source impedance there is no further input current. The rate of charge transfer values. from the analog source to the converter is a function of conversion rate. V CC X+ X– Y+ REF Y– X+ Y+ EXT 3-TO-1 ON-CHIP SWITCHES MUX X+ REF+ IN+ Y+ 4-TO-1 IN+ ADC CORE DATA OUT MUX IN3 IN– REF– IN4 3-TO-1 MUX X– Y– GND Figure 19. Equivalent Analog Input Circuit Table 5. Analog Input, Reference, and Touch Screen Control 1 1 1 2 2 SER/DFR A2 A1 A0 Analog Input X Switches Y Switches +REF –REF 0 0 1 1 X+ OFF ON V GND REF 0 1 0 1 IN3 OFF OFF VREF GND 1 0 1 1 Y+ ON OFF VREF GND 1 1 0 1 IN4 OFF OFF VREF GND 0 0 1 0 X+ OFF ON Y+ Y− 1 0 1 0 Y+ ON OFF X+ X− 1 1 0 0 Outputs Identity Code, 1000 0000 0000 1 All remaining configurations are invalid addresses. 2 Internal node − not directly accessible by the user. Rev. B | Page 12 of 20 02144-B-019 AD7843 Touch Screen Settling switches that supply the external touch screen can be turned off once the acquisition is complete, resulting in a power saving. In some applications, external capacitors could be required However, the on resistance of the Y drivers affects the input across the touch screen to filter noise associated with it, for voltage that can be acquired. The full touch screen resistance example, noise generated by the LCD panel or backlight may be in the order of 200 Ω to 900 Ω, depending on the manu- circuitry. The value of these capacitors causes a settling time facturer. Therefore if the on resistance of the switches is requirement when the panel is touched. The settling time approximately 6 Ω, true full-scale and zero-scale voltages cannot typically appears as a gain error. There are several methods for be acquired regardless of where the pen/stylus is on the touch minimizing or eliminating this issue. The problem could be that screen. Note that the minimum touch screen resistance the input signal, reference, or both have not settled to their final recommended for use with the AD7843 is approximately 70 Ω. value before the sampling instant of the ADC. Additionally, the +V CC reference voltage could still be changing during the conversion cycle. One option is to stop, or slow down the DCLK for the Y+ required touch screen settling time. This allows the input and V REF reference to stabilize for the acquisition time, which resolves the REF+ X+ IN+ issue for both single-ended and differential modes. IN+ ADC CORE REF– IN– The other option is to operate the AD7843 in differential mode Y– only for the touch screen and to program the AD7843 to keep the touch screen drivers on and not go into power-down (PD0 GND = PD1 = 1). Several conversions might be required, depending Figure 21. Single-Ended Reference Mode (SER/DFR = 1) on the settling time required and the AD7843 data rate. Once the required number of conversions are made, the AD7843 can In this mode of operation, therefore, some voltage is likely to be then be placed into a power-down state on the last lost across the internal switches and, in addition to this, it is measurement. The last method is to use the 15 DCLK cycle unlikely that the internal switch resistance will track the resis- mode, which maintains the touch screen drivers on until it is tance of the touch screen over temperature and supply, providing commanded to stop by the processor. an additional source of error. Reference Input DFR The alternative to this situation is to set the SER/ bit low. If The voltage difference between +REF and −REF (see Figure 19) one again considers making a Y-coordinate measurement, but sets the analog input range. The AD7843 operates with a refer- now the +REF and −REF nodes of the ADC are connected . The voltage into the V ence input in the range of 1 V to VCC REF directly to the Y+ and Y− pins, this means the analog-to-digital input is not buffered and directly drives the capacitor DAC conversion is ratiometric. The result of the conversion is always portion of the AD7843. Figure 20 shows the reference input a percentage of the external resistance, independent of how it circuitry. Typically, the input current is 8 µA with VREF = 2.5 V could change with respect to the on resistance of the internal and fSAMPLE = 125 kHz. This value varies by a few microamps, switches. Figure 22 shows the configuration for a ratiometric Y- depending on the result of the conversion. The reference current coordinate measurement. It should be noted that the differential diminishes directly with both conversion rate and reference reference mode can be used only with +V since the source of CC voltage. As the current from the reference is drawn on each bit the +REF voltage and cannot be used with VREF. decision, clocking the converter more quickly during a given conversion period does not reduce the overall current drain The disadvantage of this mode of operation is that during both from the reference. the acquisition phase and conversion process, the external touch X+ screen must remain powered. This results in additional supply 3-TO-1 Y+ ADC MUX V current for the duration of the conversion. REF +V CC Figure 20. Reference Input Circuitry When making touch screen measurements, conversions can be Y+ made in the differential (ratiometric) mode or the single-ended DFR mode. If the SER/ bit is set to 1 in the control register, a REF+ X+ IN+ IN+ ADC CORE single-ended conversion is performed. Figure 21 shows the IN– REF– configuration for a single-ended Y-coordinate measurement. Y– The X+ input is connected to the analog to digital converter, the Y+ and Y− drivers are turned on, and the voltage on X+ is GND digitized. The conversion is performed with the ADC referenced DFR Figure 22. Differential Reference Mode (SER/ = 0) from GND to VREF. The advantage of this mode is that the Rev. B | Page 13 of 20 02144-B-020 02144-B-022 02144-B-021 AD7843 CONTROL REGISTER derived from the voltage at the switch drivers, which is almost The control word provided to the ADC via the DIN pin is the same as the voltage to the touch screen. In this case, a shown in Table 6. This provides the conversion start, channel separate reference voltage is not needed because the reference addressing, ADC conversion resolution, configuration, and voltage to the ADC is the voltage across the touch screen. In power-down of the AD7843. single-ended mode, the reference voltage to the converter is Table 6 provides detailed information on the order and always the difference between the V and GND pins. See REF description of these control bits within the control word. Table 5 and Figure 19 through Figure 22 for further information. Initiate START The first bit, the S bit, must always be set to 1 to initiate the start Because the supply current required by the device is so low, a of the control word. The AD7843 ignores any inputs on the DIN precision reference can be used as the supply source to the line until the START bit is detected. AD7843. It may also be necessary to power the touch screen from the reference, which could require 5 mA to 10 mA. A Channel Addressing REF19x voltage reference can source up to 30 mA and, as such, The next three bits in the control register, A2, A1, and A0, select could supply both the ADC and the touch screen. Care must be the active input channel(s) of the input multiplexer (see Table 5 taken, however, to ensure that the input voltage applied to the and Figure 19), touch screen drivers, and the reference inputs. ADC does not exceed the reference voltage and therefore the MODE supply voltage. See the Absolute Maximum Ratings section. The MODE bit sets the resolution of the analog to digital Note that the differential mode can only be used for X-position converter. With 0 in this bit, the following conversion has 12 bits and Y-Position measurements. All other measurements require of resolution. With 1 in this bit, the following conversion has 8 single-ended mode. bits of resolution. PD0 and PD1 DFR SER/ The power management options are selected by programming DFR The SER/ bit controls the reference mode, which can be the power management bits, PD0 and PD1, in the control either single-ended or differential if 1 or 0 is written to this bit, register. Table 7 summarizes the available options. On power-up, respectively. The differential mode is also referred to as the PD0 defaults to 0, while PD1 defaults to 1.. ratiometric conversion mode. This mode is optimum for X-position and Y-position measurements. The reference is Table 6. Control Register Bit Function Description MSB LSB S A2 A1 A0 MODE SER/DFR PD1 PD0 Bit Mnemonic Comment 7 S Start Bit. The control word starts with the first high bit on DIN. A new control word can start every 15th DCLK cycle when in the 12-bit conversion mode, or every 11th DCLK cycle when in 8-bit conversion mode. 6–4 A2–A0 Channel Select Bits. These three address bits, along with the SER/DFR bit, control the setting of the multiplexer input, switches, and reference inputs, as described in Table 5. 3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the resolution of the following conversion. With 0 in this bit, the conversion has a 12-bit resolution, or with 1 in this bit, the conversion has a 8-bit resolution. 2 SER/DFR Single-Ended/Differential Reference Select Bit. Along with Bits A2–A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, as described in Table 5. 1, 0 PD1, PD0 Power Management Bits. These two bits decode the power-down mode of the AD7843, as shown in Table 7. Rev. B | Page 14 of 20 AD7843 POWER VS. THROUGHPUT RATE 1000 By using the power-down options on the AD7843 when not converting, the average power consumption of the device f = 16× f DCLK SAMPLE decreases at lower throughput rates. Figure 23 shows how, as the throughput rate is reduced while maintaining the DCLK 100 frequency at 2 MHz, the device remains in its power-down state longer and the average current consumption over time drops accordingly. f = 2MHz DCLK 10 For example, if the AD7843 is operated in a 24 DCLK continuous sampling mode, with a throughput rate of 10 kSPS V = 2.7V CC and a SCLK of 2 MHz, and the device is placed in the power- T = –40°C TO +95°C A down mode between conversions, (PD0, PD1 = 0, 0), the current 1 consumption is calculated as follows. The power dissipation 0 0 20 40 60 80 100 120 during normal operation is typically 210 µA (V = 2.7 V). The CC THROUGHPUT (kSPS) power-up time of the ADC is instantaneous, so when the part is Figure 23. Supply Current vs. Throughput (µA) converting, it consumes 210 µA. In this mode of operation, the part powers up on the fourth falling edge of DCLK after the start bit is recognized. It goes back into power-down at the end of conversion on the 20th falling edge of DCLK. This means the part consumes 210 µA for 16 DCLK cycles only, 8 µs, during each conversion cycle. With a throughput rate of 10 kSPS, the cycle time is 100 µs and the average power dissipated during each cycle is (8/100) × (210 µA) = 16.8 µA. Table 7. Power Management Options PD1 PD0 PENIRQ Description 0 0 Enabled This configuration results in power-down of the device between conversions. The AD7843 only powers down between conversions. Once PD1 and PD0 are set to 0, 0, the conversion is performed first, and the AD7843 powers down upon completion of that conversion. At the start of the next conversion, the ADC instantly powers up to full power. This means there is no need for additional delays to ensure full operation, and the very first conversion is valid. The Y− switch is on while in power-down. 0 1 Disabled This configuration results in the same behavior as when PD1 and PD0 have been programmed with 0, 0, except that PENIRQ is disabled. The Y− switch is off while in power-down. 1 0 Enabled This configuration results in keeping the AD7843 permanently powered up with PENIRQ enabled. 1 1 Disabled This configuration results in keeping the AD7843 always powered up with PENIRQ disabled. Rev. B | Page 15 of 20 SUPPLY CURRENT (µA) 02144-B-023 AD7843 SERIAL INTERFACE control word is complete (the power management bits are now Figure 24 shows the typical operation of the serial interface of updated) and the converter enters conversion mode. At this the AD7843. The serial clock provides the conversion clock and point, track-and-hold goes into hold mode, the input signal is also controls the transfer of information to and from the sampled, and the BUSY output goes high (BUSY returns low on AD7843. One complete conversion can be achieved with 24 the next falling edge of DCLK). The internal switches may also DCLK cycles. turn off at this point if in single-ended mode. CS The signal initiates the data transfer and conversion process. The next 12 DCLK cycles are used to perform the conversion The falling edge of CS takes the BUSY output and the serial bus and to clock out the conversion result. If the conversion is out of three-state. The first eight DCLK cycles are used to write ratiometric (SER/DFR set low), the internal switches are on to the control register via the DIN pin. The control register is during the conversion. A 13th DCLK cycle is needed to allow updated in stages as each bit is clocked in. Once the converter the DSP/microcontroller to clock in the LSB. Three more DCLK has enough information about the following conversion to set cycles clock out the three trailing zeroes and complete the 24 the input multiplexer and switches appropriately, the converter DCLK transfer. The 24 DCLK cycles can be provided from a enters acquisition mode and, if required, the internal switches DSP or via three bursts of 8 clock cycles from a microcontroller. are turned on. During the acquisition mode, the reference input data is updated. After the three DCLK cycles of acquisition, the CS t ACQ 18 1 8 1 8 DCLK SER/ S A2 A1 A0 MODE PD1 PD0 DFR DIN (START) IDLE ACQUIRE CONVERSION IDLE THREE-STATE THREE-STATE BUSY THREE-STATE THREE-STATE 11 10 9 8 7 6 5 4 3 2 1 0 ZERO FILLED DOUT (MSB) (LSB) 1 OFF ON OFF X/Y SWITCHES (SER/DFR HIGH) 1,2 OFF OFF X/Y SWITCHES ON (SER/DFR LOW) NOTES 1 Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2–A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2–A0 = 101). 1 WHEN PD1, PD0 = 10 OR 00, Y– WILL TURN ON AT THE END OF THE CONVERSION. 2 DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE, 1 OR POWER-DOWN MODE IS CHANGED. Figure 24. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. Rev. B | Page 16 of 20 02144-B-024 AD7843 DETAILED SERIAL INTERFACE TIMING the part waits for the next START bit to initiate the next Figure 25 shows the detailed timing diagram for serial conversion. This means that each conversion does not interfacing to the AD7843. Writing information to the control CS CS necessarily need to be framed by , because once goes low, register takes place on the first eight rising edges of DCLK in a the part detects each START bit and clocks in the control word data transfer. The control register is written to only if a START after it on DIN. When the AD7843 is in the 12-bit conversion bit is detected (see the Control Register section) on DIN. The mode, a second START bit is not detected until seven DCLK initiation of the following conversion also depends on the pulses have elapsed after a control word is clocked in on DIN, presence of the START bit. Throughout the eight DCLK cycles that is, another START bit can be clocked in on the eighth when data is being written to the part, the DOUT line is driven DCLK rising edge after a control word is written to the device low. The MSB of the conversion result is clocked out on the (see the Fifteen Clocks per Cycle section). If the device is in the falling edge of the ninth DCLK cycle and is valid on the rising 8-bit conversion mode, a second START bit is not recognized edge of the tenth DCLK cycle; therefore, nine leading zeros can until three DCLK pulses elapse after the control word is clocked be clocked out prior to the MSB. This means the data seen on in, that is, another START bit can be clocked in on the fourth the DOUT line in the 24 DCLK conversion cycle is presented in DCLK rising edge after a control word is written to the device. the form of nine leading zeros, twelve bits of data, and three trailing zeros. Because a START bit can be recognized during a conversion, the control word for the next conversion can be clocked in during The rising edge of CS puts the bus and the BUSY output back the current conversion, enabling the AD7843 to complete a into three-state, the DIN line is ignored, and, if a conversion is conversion cycle in less than 24 DCLKs. CS in progress at the time, this is also aborted. However, if is not brought high after the completion of the conversion cycle, then CS t 4 t t t t t 6 6 9 10 1 t 5 DCLK t 8 t 7 PD0 DIN t 2 BUSY t 11 t 12 t 3 DB11 DB10 DOUT Figure 25. Detailed Timing Diagram Rev. B | Page 17 of 20 02144-B-025 AD7843 Sixteen Clocks per Cycle 8-Bit Conversion The control bits for the next conversion can be overlapped with By setting the MODE bit to 1 in the control register, the the current conversion to allow for a conversion every 16 DCLK AD7843 can operate in 8-bit rather than 12-bit mode. This cycles, as shown in Figure 26. This timing diagram also allows mode allows a faster throughput rate to be achieved, assuming for the possibility of communication with other serial peripherals 8-bit resolution is sufficient. When using the 8-bit mode, a between each (eight DCLK) byte transfer between the processor conversion is complete four clock cycles earlier than in the and the converter. However, the conversion must be completed 12-bit mode. This could be used with serial interfaces that within a short enough time frame to avoid capacitive droop provide 12 clock transfers, or two conversions could be effects that could distort the conversion result. It should also be completed with three 8-clock transfers. The throughput rate noted that the AD7843 is fully powered while other serial increases by 25% as a result of the shorter conversion cycle, but communications are taking place between byte transfers. the conversion itself can occur at a faster clock rate because the internal settling time of the AD7843 is not as critical because Fifteen Clocks per Cycle settling to 8 bits is all that is required. The clock rate can be as Figure 27 shows the fastest way to clock the AD7843. This much as 50% faster. The faster clock rate and fewer clock cycles scheme does not work with most microcontrollers or DSPs combine to provide double the conversion rate. because, in general, they are not capable of generating a 15-clock-cycle-per-serial transfer. However, some DSPs allow the number of clocks per cycle to be programmed; this method could also be used with FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits). As in the 16-clocks-per-cycle case, the control bits for the next conversion are overlapped with the current conversion to allow a conversion every 15 DCLK cycles, using 12 DCLKs to perform the conversion and three DCLKs to acquire the analog input. This effectively increases the throughput rate of the AD7843 beyond that used for the specifications that are tested using 16 DCLKs per cycle, and DCLK = 2 MHz. CS 1 8811 81 DCLK S S DIN CONTROL BITS CONTROL BITS BUSY 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 DOUT Figure 26. Conversion Timing, 16 DCLKS per Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. CS 1 15 1 15 1 DCLK SER/ SER/ DIN S A2 A1 A0 MODE PD1 PD0 SA2 A1 A0 MODE PD1 PD0 SA2 DFR DFR BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 Figure 27. Conversion Timing, 15 DCLKS per Cycle, Maximum Throughput Rate Rev. B | Page 18 of 20 02144-B-026 02144-B-027 AD7843 PEN INTERRUPT REQUEST The pen interrupt equivalent output circuitry is outlined in Once the START bit is detected, the pen interrupt function is Figure 28. By connecting a pull-up resistor (10 kΩ to 100 kΩ) disabled and the PENIRQ cannot respond to screen touches. between VCC and this CMOS logic open-drain output, the PENIRQ The output remains low until the fourth falling edge PENIRQ PENIRQ output remains high normally. If is enabled of DCLK after the START bit has been clocked in, at which (see Table 7), when the touch screen connected to the AD7843 point it returns high as soon as possible, regardless of the touch PENIRQ is touched via a pen or finger, the output goes low, screen capacitance. This does not mean that the pen interrupt initiating an interrupt to a microprocessor that can then instruct function is now enabled again because the power-down bits a control word to be written to the AD7843 to initiate a conver- have not yet been loaded to the control register. Regardless of sion. This output can also be enabled between conversions whether PENIRQ is to be enabled again or not, the PENIRQ during power-down (see Table 7 ), allowing power-up to be output normally always idles high. Assuming that the PENIRQ initiated only when the screen is touched. The result of the first is enabled again as shown in Figure 29, once the conversion is touch screen coordinate conversion after power-up is valid, PENIRQ complete, the output responds to a screen touch again. assuming any external reference is settled to the 12- or 8-bit PENIRQ level as required. The fact that returns high almost immediately after the fourth falling edge of DCLK means the user avoids any +V CC spurious interrupts on the microprocessor or DSP, which could Y+ EXTERNAL 100kΩ occur if the interrupt request line on the microprocessor/DSP PULL-UP was unmasked during or toward the end of conversion with the +V CC PENIRQ PENIRQ pin still low. Once the next START bit is detected by X+ PENIRQ the AD7843, the function is disabled again. TOUCH PENIRQ SCREEN If the control register write operation overlaps with the data ENABLE Y– read, a START bit is always detected prior to the end of ON conversion. This means that even if the PENIRQ function has been enabled in the control register, it is disabled by the START Figure 28. PENIRQ Functional Block Diagram bit again before the end of the conversion is reached; therefore PENIRQ Figure 29 assumes that the function is enabled in the the PENIRQ function effectively cannot be used in this mode. PENIRQ last write or that the part has just been powered up, so However, as conversions are occurring continuously, the is enabled by default. Once the screen is touched, the PENIRQ PENIRQ function is not necessary and, therefore, redundant. output goes low a time tPEN later. This delay is approximately GROUNDING AND LAYOUT 5 µs, assuming a 10 nF touch screen capacitance, and varies with the touch screen resistance actually used. For information on grounding and layout considerations for the AD7843, refer to Application Note AN-577, Layout and Grounding Recommendations for Touch Screen Digitizers. SCREEN TOUCHED PD1 = 1, PD0 = 0, PENIRQ t PEN HERE NO RESPONSE TO TOUCH ENABLED AGAIN PENIRQ INTERRUPT PROCESSOR CS 1 8 1 13 16 DCLK SER/ MODE SA2 A1 A0 1 0 DFR DIN (START) Figure 29. PENIRQ Timing Diagram Rev. B | Page 19 of 20 02144-B-028 02144-B-029 AD7843 OUTLINE DIMENSIONS 5.10 5.00 0.193 4.90 BSC 16 9 16 9 0.154 4.50 6.40 BSC 4.40 BSC 0.236 4.30 1 BSC 8 1 8 PIN 1 PIN 1 1.20 0.069 0.065 MAX 0.053 0.049 0.15 0.20 0.05 0.75 0.09 8° 0.60 8° 0.30 0.010 0.65 0° 0.025 0.45 0° 0.19 0.012 0.050 SEATING 0.004 SEATING 0.010 BSC BSC 0.008 PLANE 0.016 PLANE COPLANARITY 0.006 COPLANARITY 0.004 0.10 COMPLIANT TO JEDEC STANDARDS MO-137AB COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 30. 16-Lead Shrink Small Outline Package [QSOP] Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RQ-16) (RU-16) Dimensions shown in inches Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Linearity Error (LSB) Package Description Package Option AD7843ARQ −40°C to +85°C ±2 QSOP RQ-16 AD7843ARQ-REEL −40°C to +85°C ±2 QSOP RQ-16 AD7843ARQ-REEL7 −40°C to +85°C ±2 QSOP RQ-16 2 AD7843ARQZ −40°C to +85°C ±2 QSOP RQ-16 2 AD7843ARQZ-REEL −40°C to +85°C ±2 QSOP RQ-16 2 AD7843ARQZ-REEL7 −40°C to +85°C ±2 QSOP RQ-16 AD7843ARU −40°C to +85°C ±2 TSSOP RU-16 AD7843ARU-REEL −40°C to +85°C ±2 TSSOP RU-16 AD7843ARU-REEL7 −40°C to +85°C ±2 TSSOP RU-16 3 EVAL-AD7843CB Evaluation Board 4 EVAL-CONTROL BRD2 Controller Board 1 Linearity error here refers to integral linearity error. 2 Z = Pb-free part. Pb-free parts are branded with a # before the date code. 3 This can be used as a stand-alone evaluation board, or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. 4 This Evaluation Board Controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02144–0–3/04(B) Rev. B | Page 20 of 20