ANALOG DEVICES AD7841

Octal 14-Bit, Parallel Input, a Voltage-Output DAC AD7841 GENERAL DESCRIPTION FEATURES The AD7841 contains eight 14-bit DACs on one monolithic Eight 14-Bit DACs in One Package chip. It has output voltages with a full-scale range of ±10 V Voltage Outputs from reference voltages of ±5 V. Offset Adjust for Each DAC Pair Reference Range of �5 V The AD7841 accepts 14-bit parallel loaded data from the exter- Maximum Output Voltage Range of �10 V nal bus into one of the input registers under the control of the �15 V � 10% Operation WR, CS, and DAC channel address pins, A0–A2. Clear Function to User-Defined Voltage The DAC outputs are updated on reception of new data into 44-Lead MQFP Package the DAC registers. All the outputs may be updated simulta- APPLICATIONS neously by taking the LDAC input low. Automatic Test Equipment Each DAC output is buffered with a gain-of-two amplifier into Process Control which an external DAC offset voltage can be inserted via the General Purpose Instrumentation DUTGNDx pins. The AD7841 is available in a 44-lead MQFP package. FUNCTIONAL BLOCK DIAGRAM V (+) V (–) REF REF DUTGND DUTGND V V V CC SS DD CD AB AB AB AD7841 RR 14 14 14 INPUT DAC DAC A REG REG V A OUT A A RR DB13 14 14 14 DAC INPUT REG REG DAC B V B OUT B B DB0 R 14 14 14 R INPUT DAC REG REG DAC C V C C C OUT WR R R 14 14 14 INPUT DAC CS DAC D REG REG V D OUT D D A0 A1 14 14 14 INPUT DAC REG REG DAC E A2 E E V E LDAC OUT 14 14 14 R R INPUT DAC REG REG DAC F F F V F OUT R 14 14 14 R INPUT DAC REG REG DAC G G G V G OUT 14 14 14 INPUT DAC R R DAC H REG REG H H V H OUT R R V (+) V (–) V (+) V (–) GND DUTGND DUTGND REF REF REF REF CLR EF GH GH GH CDEF CDEF REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com otherwise under any patent or patent rights of Analog Devices. ADDRESS DECODE (V = 5 V � 5%; V = 15 V � 10%; V = –15 V � 10%; GND = DUTGND = CC DD SS 1 0 V; R = 5 k� and C = 50 pF to GND, T = T to T , unless otherwise noted) AD7841–SPECIFICATIONS L L A MIN MAX Parameter A B Unit Test Conditions/Comments ACCURACY Resolution 14 14 Bits Relative Accuracy ± 4 ±2 LSB max Differential Nonlinearity –0.9/2 ±1 LSB max Guaranteed Monotonic Over Temperature for All Grades Zero-Scale Error ± 8 ±8 LSB max V (+) = +5 V, V (–) = –5 V. Typically within REF REF ±2 LSB Full-Scale Error ± 8 ±8 LSB max V (+) = +5 V, V (–) = –5 V. Typically within REF REF ±2 LSB Gain Error ± 2 ±2 LSB typ V (+) = +5 V, V (–) = –5 V REF REF 2 Gain Temperature Coefficient 0.5 0.5 ppm FSR/°C typ 10 10 ppm FSR/°C max 2 DC Crosstalk 120 120 µV max See Terminology. Typically 75 µV 2 REFERENCE INPUTS DC Input Impedance 100 100 MΩ typ Input Current ± 1 ± 1 µA max Per Input. Typically ±0.03 µA V (+) Range 0/5 0/5 V min/max REF V (–) Range –5/0 –5/0 V min/max REF [V (+) – V (–)] 2/10 2/10 V min/max For Specified Performance. Can Go as Low as 0 V, REF REF but Performance Not Guaranteed 2 DUTGND INPUTS DC Input Impedance 60 60 kΩ typ Max Input Current ±0.3 ±0.3 mA typ Per Input 3 Input Range –2/+2 –2/+2 V min/max 2 OUTPUT CHARACTERISTICS Output Voltage Swing V + 2.5 V to V + 2.5 V to V typ V = 2 × (V (–) + [V (+) – V (–)] × D) SS SS OUT REF REF REF V – 2.5 V V – 2.5 V – V DD DD DUTGND Short Circuit Current 15 15 mA max Resistive Load 5 5 kΩ min To 0 V Capacitive Load 50 50 pF max To 0 V DC Output Impedance 0.5 0.5 Ω max 2 DIGITAL INPUTS V , Input High Voltage 2.4 2.4 V min INH V , Input Low Voltage 0.8 0.8 V max INL I , Input Current Total for All Pins INH @ 25°C ± 1 ± 1 µA max T to T ±10 ±10 µA max MIN MAX C , Input Capacitance 10 10 pF max IN 4 POWER REQUIREMENTS V 4.75/+5.25 4.75/+5.25 V min/max For Specified Performance CC V 15 V ± 10% 15 V ± 10% V min/max For Specified Performance DD V –15 V ± 10% –15 V ± 10% V min/max For Specified Performance SS 2 Power Supply Sensitivity ∆Full Scale/∆V 90 90 dB typ DD ∆Full Scale/∆V 90 90 dB typ SS I 0.5 0.5 mA max V = V , V = GND. Dynamic Current CC INH CC INL I 10 10 mA max Outputs Unloaded. Typically 8 mA DD I 10 10 mA max Outputs Unloaded. Typically 8 mA SS NOTES 1 Temperature range for A and B Versions: –40°C to +85°C. 2 Guaranteed by characterization. Not production tested. 3 See DUTGND Voltage Range section. 4 The AD7841 is functional with power supplies of ±12 V ±10% with reduced output range. Output amplifier requires 2.5 V of head room at the bottom and top ends of the transfer for function. At 12 V supplies it is recommended to restrict the reference range to ±4 V. Specifications subject to change without notice. REV. B –2– AD7841 (These characteristics are included for Design Guidance and are not subject AC PERFORMANCE CHARACTERISTICS to production testing.) A & B Parameter Versions Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 31 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Slew Rate 0.7 V/µs typ Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V (+) = +5 V, V (–) = –5 V. DAC Latch REF REF Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent on Load Conditions Channel-to-Channel Isolation 99 dB typ See Terminology DAC-to-DAC Crosstalk 40 nV-s typ See Terminology Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test Output Noise Spectral Density @ 1 kHz 200 nV/√Hz typ All 1s Loaded to DAC. V (+) = V (–) = 0 V REF REF Specifications subject to change without notice. 1, 2 TIMING SPECIFICATIONS (V = 5 V � 5%; V = 15 V � 10%; V = –15 V � 10%; GND = DUTGND = 0 V) CC DD SS Parameter Limit at T T Unit Description MIN, MAX t 15 ns min Address to WR Setup Time 1 t 0 ns min Address to WR Hold Time 2 t 50 ns min CS Pulsewidth Low 3 t 50 ns min WR Pulsewidth Low 4 t 0 ns min CS to WR Setup Time 5 t 0 ns min WR to CS Hold Time 6 t 20 ns min Data Setup Time 7 t 0 ns min Data Hold Time 8 t 31 µs typ Settling Time 9 t 300 ns max CLR Pulse Activation Time 10 t 50 ns min LDAC Pulsewidth Low 11 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. t t 1 2 A0, A1, A2 t t 5 6 t 3 CS t 4 WR t 8 t 7 DATA t 9 V OUT t 10 CLR V OUT t 11 LDAC Figure 1. Timing Diagram REV. B –3– AD7841 1, 2 ABSOLUTE MAXIMUM RATINGS Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C (T = 25°C unless otherwise noted) A MQFP Package 3 Power Dissipation . . . . . . . . . . . . . . . . . (T Max – T )/θ J A JA V to GND . . . . . . . . . . . . . . –0.3 V, +7 V or V + 0.3 V CC DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W JA (Whichever Is Lower) V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V DD V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V SS Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, V + 0.3 V CC V (+) to V (–) . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V REF REF NOTES V (+) to GND . . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V REF SS DD 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- V (–) to GND . . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V REF SS DD nent damage to the device. This is a stress rating only; functional operation of the DUTGND to GND . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V SS DD device at these or any other conditions above those indicated in the operational V (A–H) to GND . . . . . . . . . . . . V – 0.3 V, V + 0.3 V OUT SS DD section of this specification is not implied. Exposure to absolute maximum rating Operating Temperature Range conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C 3 V must not exceed V by more than 0.3 V. If it is possible for this to happen CC DD Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C during power supply sequencing, the following diode protection scheme will ensure protection. V V DD CC IN4148 HP5082-2811 V V DD CC AD7841 PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 DUTGND_AB 1 33 DUTGND_GH PIN 1 IDENTIFIER V A 2 32 V H OUT OUT 3 31 V (–)AB V (–)GH REF REF V (+)AB 4 30 V (+)GH REF REF 5 29 V DD CLR AD7841 DB13 V 6 28 TOP VIEW SS (Not to Scale) 7 27 LDAC DB12 A2 8 26 DB11 A1 9 25 DB10 A0 10 24 DB9 11 23 CS DB8 12 13 14 15 16 17 18 19 20 21 22 REV. B –4– WR V B OUT V CC V C OUT GND DUTGND_CD DB0 V D OUT DB1 V (–)CDEF REF DB2 V (+)CDEF REF V DB3 DD DB4 V E OUT DB5 DUTGND_EF DB6 V F OUT DB7 V G OUT AD7841 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DUTGND_AB Device Sense Ground for DACs A and B. V A and V B are referenced to the voltage OUT OUT applied to this pin. 2, 44, 43, V A..V H DAC Outputs. OUT OUT 41, 37, 35, 34, 32 3, 4 V (–)AB, V (+)AB Reference Inputs for DACs A and B. These reference voltages are referred to GND. REF REF 5, 38 V Positive Analog Power Supply; +15 V ± 10% for specified performance. DD 6V Negative Analog Power Supply; –15 V ± 10% for specified performance. SS 7 LDAC Load DAC Logic Input (active low). When this logic input is taken low the contents of the registers are transferred to their respective DAC registers. LDAC can be tied permanently low enabling the outputs to be updated on the rising edge of WR. 8, 9, 10 A2, A1, A0 Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a data transfer. 11 CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low. 12 WR Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7841 data registers. Data is latched into the selected input register on the rising edge of WR. 13 V Logic Power Supply; 5 V ± 5%. CC 14 GND Ground. 15–28 DB0 . . DB12 Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. 29 CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUTGND pin. The con- tents of input registers and DAC registers A to H are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert to their original outputs as determined by the data in their DAC registers. 30, 31 V (+)GH, V (–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND. REF REF 33 DUTGND_GH Device Sense Ground for DACs G and H. V G and V H are referenced to the voltage OUT OUT applied to this pin. 36 DUTGND_EF Device Sense Ground for DACs E and F. V E and V F are referenced to the voltage OUT OUT applied to this pin. 39 V (+)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. REF 40 V (–)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. REF 42 DUTGND_CD Device Sense Ground for DACs C and D. V C and V D are referenced to the voltage OUT OUT applied to this pin. REV. B –5– AD7841 TERMINOLOGY DC Output Impedance Relative Accuracy This is the effective output source resistance. It is dominated by Relative accuracy or endpoint linearity is a measure of the max- package lead resistance. imum deviation from a straight line passing through the endpoints Full-Scale Error of the DAC transfer function. It is measured after adjusting for This is the error in DAC output voltage when all 1s are loaded zero-scale error and full-scale error and is expressed in Least into the DAC latch. Ideally the output voltage, with all 1s loaded Significant Bits. into the DAC latch, should be 2 V (+) – 1 LSB. REF Differential Nonlinearity Zero-Scale Error Differential nonlinearity is the difference between the measured Zero-scale error is the error in the DAC output voltage when all change and the ideal 1 LSB change between any two adjacent 0s are loaded into the DAC latch. Ideally the output voltage, codes. A specified differential nonlinearity of 1 LSB maximum with all 0s in the DAC latch should be equal to 2 V (–). Zero- REF ensures monotonicity. scale error is mainly due to offsets in the output amplifier. DC Crosstalk Gain Error Although the common input reference voltage signals are inter- Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error). nally buffered, small IR drops in the individual DAC reference inputs across the die can mean that an update to one channel GENERAL DESCRIPTION can produce a dc output change in one or another of the chan- DAC Architecture—General nel outputs. Each channel consists of a straight 14-bit R-2R voltage-mode The eight DAC outputs are buffered by op amps that share DAC. The full-scale output voltage range is equal to twice the common V and V power supplies. If the dc load current reference span of V (+) – V (–). The DAC coding is straight DD SS REF REF changes in one channel (due to an update), this can result in a binary; all 0s produces an output of 2 V (–); all 1s produces REF further dc change in one or another of the channel outputs. This an output of 2 V (+) – 1 LSB. REF effect is most obvious at high load currents and reduces as the The analog output voltage of each DAC channel reflects the load currents are reduced. With high impedance loads the effect contents of its own DAC register. Data is transferred from is virtually impossible to measure. the external bus to the input register of each DAC on a per Output Voltage Settling Time channel basis. This is the amount of time it takes for the output to settle to a Bringing the CLR line low switches all the signal outputs, V A OUT specified level for a full-scale input change. to V H, to the voltage level on the relevant DUTGND pin. OUT Digital-to-Analog Glitch Impulse When the CLR signal is brought back high, the output voltages This is the amount of charge injected into the analog output from the DACs will reflect the data stored in the relevant when the inputs change state. It is specified as the area of the DAC registers. glitch in nV-secs. It is measured with V (+) = +5 V and REF Data Loading to the AD7841 V (–) = –5 V and the digital inputs toggled between 1FFFH REF Data is loaded into the AD7841 in straight parallel 14-bit wide and 2000H. words. Channel-to-Channel Isolation The DAC output voltages, V A – V H are updated to OUT OUT Channel-to-channel isolation refers to the proportion of input reflect new data in the DAC registers. signal from one DAC’s reference input that appears at the out- The actual input register being written to is determined by the put of another DAC. It is expressed in dBs. logic levels present on the device’s address lines, as shown in DAC-to-DAC Crosstalk Table I. DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital Table I. Address Line Truth Table change and subsequent analog O/P change at another converter. It is specified in nV-secs. A2 A1 A0 DAC Selected Digital Crosstalk 0 0 0 INPUT REG A (DAC A) The glitch impulse transferred to the output of one converter 0 0 1 INPUT REG B (DAC B) due to a change in digital input code to the other converter is 0 1 0 INPUT REG C (DAC C) defined as the digital crosstalk and is specified in nV-secs. 0 1 1 INPUT REG D (DAC D) 1 0 0 INPUT REG E (DAC E) Digital Feedthrough 1 0 1 INPUT REG F (DAC F) When the device is not selected, high frequency logic activity on 1 1 0 INPUT REG G (DAC G) the device’s digital inputs can be capacitively coupled both 1 1 1 INPUT REG H (DAC H) across and through the device to show up as noise on the V OUT pins. This noise is digital feedthrough. REV. B –6– Typical Performance Characteristics–AD7841 1 4 2 V = +15V DD V = –15V V = +15V SS DD 0.75 V (+) = +5V V = –15V REF SS V (+) = +5V V (–) = –5V REF REF 0.5 2 1 V (–) = –5V REF T = 25�C A 0.25 0 0 0 –0.25 V = +15V DD V = –15V SS –0.5 –2 –1 V (+) = +5V REF V (–) = –5V REF –0.75 T = 25�C A –1 –1 –2 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 –40 –20 0 20 406080 100 CODE CODE TEMPERATURE – �C TPC 1. Typical INL Plot TPC 2. Typical DNL Plot TPC 3. Typical INL Error vs. Temperature 4 6 1 V = +5V V = +15V CC DD V = +15V 5 V = –15V DD SS V = –15V SS V = +5V REF(+) 0.5 2 V = –5V 4 REF(–) V = +15V DD DIGITAL INPUTS @ V = –15V SS ZERO-SCALE ERROR THRESHOLDS V (+) = +5V 3 REF V (+) = –5V 0 0 REF 2 1 FULL-SCALE ERROR –0.5 –2 DIGITAL INPUTS @ SUPPLIES 0 –1 –4 –1 –40 –20 0 204060 80 100 –40 –20 0 2040 6080 100 –40 –20 0 20 406080 100 TEMPERATURE – �C TEMPERATURE – �C TEMPERATURE – �C TPC 4. Typical DNL Error vs. TPC 5. Zero-Scale and Full-Scale TPC 6. I vs. Temperature CC Temperature Error vs. Temperature 0.6 10 V = +15V DD 0.5 10.19 V = –15V SS V = +5V CC 0.4 I DD 8 0.3 10.18 I SS 0.2 0.1 10.17 6 0 –0.1 10.16 –0.2 4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 27 28 29 30 31 32 33 –40 –20 0 20 40 60 80 100 TEMPERATURE – °C SETTLING TIME – �s TPC 7. Typical Digital-to-Analog TPC 8. Settling Time (+) TPC 9. I , I vs. Temperature DD SS Glitch Impulse REV. B –7– Volts DNL ERROR – LSBs INL ERROR – LSBs DNL ERROR – LSBs V – Volts OUT ERROR – LSBs I – mA INL ERROR – LSBs I /I – mA CC DD SS AD7841 Unipolar Configuration When bipolar-zero and full-scale adjustment are not needed, R2 Figure 2 shows the AD7841 in the unipolar binary circuit and R3 can be omitted. Pin 12 on the AD588 should be con- configuration. The V (+) input of the DAC is driven by the nected to Pin 11 and Pin 5 should be left floating. REF AD586, a 5 V reference. V (–) is tied to ground. Table II REF R1 +15V +5V gives the code table for unipolar operation of the AD7841. 39k� Other suitable references include the REF02, a precision 5 V reference, and the REF195, a low dropout, micropower preci- 46 sion 5 V reference. V V DD CC 7 2 V V C1 OUT OUT 3 +15V +5V 1�F 9 V (+) (–10V TO +10V) REF 1 AD588 AD7841* 5 14 R2 DUTGND 2 100k� 10 15 V V DD CC V (–) REF 6 11 16 V V V (+) REF OUT OUT V GND 8 SS (0 TO +10V) AD586 12 8 13 5 R1 AD7841* R3 SIGNAL C1 10k� 100k� GND DUTGND 1�F 4 –15V V (–) REF GND *ADDITIONAL PINS OMITTED FOR CLARITY V SS SIGNAL SIGNAL Figure 3. Bipolar ±10 V Operation GND GND –15V Table III. Code Table for Bipolar Operation *ADDITIONAL PINS OMITTED FOR CLARITY Binary Number in DAC Figure 2. Unipolar 10 V Operation Register Analog Output Offset and gain may be adjusted in Figure 2 as follows: To MSB LSB (V ) OUT adjust offset, disconnect the V (–) input from 0 V, load the REF DAC with all 0s and adjust the V (–) voltage until V = 0 V. REF OUT 11 1111 1111 1111 2[V (–) + V (16383/16384)] V REF REF For gain adjustment, the AD7841 should be loaded with all 1s 10 0000 0000 0001 2[V (–) + V (8193/16384)] V REF REF and R1 adjusted until V = 2 V (+) – 1 LSB = 10 V(16383/ OUT REF 10 0000 0000 0000 2[V (–) + V (8192/16384)] V REF REF 16384) = 9.99939 V. 01 1111 1111 1111 2[V (–) + V (8191/16384)] V REF REF 00 0000 0000 0001 2[V (–) + V (1/16384)] V REF REF Many circuits will not require these offset and gain adjustments. 00 0000 0000 0000 2[V (–)] V REF In these circuits R1 can be omitted. Pin 5 of the AD586 may be left open circuit and Pin 2 (V (–)) of the AD7841 tied to 0 V. REF NOTES V = (V (+) – V (–)). REF REF REF 14 For V (+) = +5 V, and V (–) = –5 V, V = 10 V, 1 LSB = 2 V V/2 = REF REF REF REF Table II. Code Table for Unipolar Operation 20 V/16384 = 1.22 mV. Binary Number in DAC Register Analog Output CONTROLLED POWER-ON OF THE OUTPUT STAGE MSB LSB (V ) OUT A block diagram of the output stage of the AD7841 is shown in 11 1111 1111 1111 2 V (16383/16384) V REF Figure 4. It is capable of driving a load of 5 kΩ in parallel with 10 0000 0000 0000 2 V (8192/16384) V REF 50 pF. G to G are transmission gates used to control the 1 6 01 1111 1111 1111 2 V (8191/16384) V REF power on voltage present at V . On power up G and G are OUT 1 2 00 0000 0000 0001 2 V (1/16384) V REF also used in conjunction with the CLR input to set V to the OUT 00 0000 0000 0000 0 V user defined voltage present at the DUTGND pin. When CLR is taken back high, the DAC outputs reflect the data in the NOTES V= V (+); V (–) = 0 V for unipolar operation. REF REF DAC registers. 14 For V (+) = 5 V, 1 LSB = 10 V/2 = 10 V/16384 = 610 µV. REF G 1 Bipolar Configuration G 6 DAC Figure 3 shows the AD7841 set up for ±10 V operation. The V OUT AD588 provides precision ±5 V tracking outputs that are fed to G 3 the V (+) and V (–) inputs of the AD7841. The code table REF REF for bipolar operation of the AD7841 is shown in Table III. G G 2 4 R = 60k� In Figure 3, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. R2 varies the R G 5 14k� gain on the AD588 while R3 adjusts the offset of both the +5 V and –5 V outputs together with respect to ground. For bipolar-zero adjustment, the DAC is loaded with DUTGND 1000... 0000 and R3 is adjusted until V = 0 V. Full scale OUT Figure 4. Block Diagram of AD7841 Output Stage is adjusted by loading the DAC with all 1s and adjusting R2 until V = 10(8191/8192) V = 9.99878 V. OUT REV. B –8– AD7841 G 1 Power-On with CLR Low G 6 DAC The output stage of the AD7841 has been designed to allow V OUT output stability during power-on. If CLR is kept low during G 3 power-on, then just after power is applied to the AD7841, the situation is as depicted in Figure 5. G , G and G are open 1 4 6 G G 2 4 while G , G and G are closed. R 2 3 5 R G G 1 5 14k� G 6 DAC V OUT G 3 DUTGND Figure 7. Output Stage After CLR Is Taken High G G 2 4 R Power-On with CLR High R If CLR is high on the application of power to the device, the G 5 14k� output stages of the AD7841 are configured as in Figure 8 while V is less than 7 V and V is more positive than –3 V. G is DD SS 1 closed and G is open, thereby connecting the output of the 2 DUTGND DAC to the input of its output amplifier. G and G are closed 3 5 Figure 5. Output Stage with V < 7 V or V > –3 V; CLR DD SS while G and G are open, thus connecting the output amplifier as 4 6 Low a unity gain buffer. V is connected to DUTGND via G OUT 5 V is kept within a few hundred millivolts of DUTGND via through a 14 kΩ resistor until V exceeds 7 V and V is more OUT DD SS G and a 14 kΩ resistor. This thin-film resistor is connected in negative than –3 V. 5 parallel with the gain resistors of the output amplifier. The G 1 output amplifier is connected as a unity gain buffer via G , and 3 G 6 DAC the DUTGND voltage is applied to the buffer input via G . The 2 V OUT amplifier’s output is thus at the same voltage as the DUTGND G 3 pin. The output stage remains configured as in Figure 5 until the voltage at V exceeds 7 V and V is more negative than DD SS G G 2 4 –3 V. By now the output amplifier has enough headroom to R handle signals at its input and has also had time to settle. The R G 5 internal power-on circuitry opens G and G and closes G and 3 5 4 14k� G . This situation is shown in Figure 6. Now the output ampli- 6 fier is configured in its noise gain configuration via G and G . 4 6 DUTGND The DUTGND voltage is still connected to the noninverting input via G and this voltage appears at V . 2 OUT Figure 8. Output Stage Powering Up with CLR High While V < 7 V or V > –3 V DD SS G 1 G 6 When the difference between the supply voltages reaches 10 V, DAC V OUT the internal power-on circuitry opens G and G and closes G 3 5 4 G 3 and G configuring the output stage as shown in Figure 9. 6 G G G 2 4 1 R G 6 DAC V OUT R G 5 G 14k� 3 G G 2 4 R DUTGND Figure 6. Output Stage with V > 7 V and V < –3 V; CLR R DD SS G 5 14k� Low V has been disconnected from the DUTGND pin by the OUT DUTGND opening of G , but will track the voltage present at DUTGND 5 via the configuration shown in Figure 6. Figure 9. Output Stage Powering Up with CLR High When V > 7 V and V < –3 V When CLR is taken back high, the output stage is configured as DD SS shown in Figure 7. The internal control logic closes G and 1 opens G . The output amr})fier is connected in a noninverting 2 gain-of-two configuration. The voltage that appears on the V OUT pins is determined by the data present in the DAC registers. REV. B –9– AD7841 DUTGND Voltage Range �CONTROLLER/ AD7841 During power-on, the V pins of the AD7841 are connected OUT DSP PROCESSOR* to the relevant DUTGND pins via G and the 14 kΩ thin-film 5 resistor. The DUTGND potential must obey the max ratings at D13 D13 DATA all times. Thus, the voltage at DUTGND must always be within BUS D0 D0 the range V – 0.3 V, V + 0.3 V. However, in order that the SS DD voltages at the V pins of the AD7841 stay within ±2 V of the OUT CS UPPER BITS OF ADDRESS ADDRESS BUS relevant DUTGND potential during power-on, the voltage DECODE LDAC applied to DUTGND should also be kept within the range GND – 2 V, GND + 2 V. A2 A2 A1 A1 Once the AD7841 has powered on and the on-chip amplifiers A0 A0 have settled, any voltage that is now applied to the DUTGND R/W WR pin is subtracted from the DAC output, which has been gained *ADDITIONAL PINS OMITTED FOR CLARITY up by a factor of two. Thus, for specified operation, the maximum voltage that can be applied to the DUTGND pin increases to the Figure 10. Parallel Interface maximum allowable 2 V (+) voltage, and the minimum volt- REF age that can be applied to DUTGND is the minimum 2 V (–) REF APPLICATIONS voltage. After the AD7841 has fully powered on, the outputs Power Supply Bypassing and Grounding can track any DUTGND voltage within this minimum/maxi- In any circuit where accuracy is important, careful consideration mum range. of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the Power Supply Sequencing AD7841 is mounted should be designed such that the analog When operating the AD7841, it is important that ground be and digital sections are separated and confined to certain areas connected at all times to avoid high current states. The recom- of the board. This facilitates the use of ground planes that can mended power-up sequence is V /V followed by V . If V DD SS CC CC be easily separated. A minimum etch technique is generally best can exceed V on power-up, the diode scheme shown in the DD for ground planes as it gives the best shielding. Digital and ana- absolute maximum ratings section will ensure protection. The log ground planes should be joined at only one place. The GND reference inputs and digital inputs should be powered up last. pin of the AD7841 should be connected to the AGND of the Should the references exceed V /V on power-up, current DD SS system. If the AD7841 is in a system where multiple devices limiting resistors should be inserted in series with the reference require an AGND-to-DGND connection, the connection should inputs to limit the current to 20 mA. Logic inputs should not be be made at one point only, a star ground point that should be applied before V . Current limiting resistors (470Ω) in series CC established as close as possible to the AD7841. with the logic inputs should be inserted if these inputs come up before V . CC Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane MICROPROCESSOR INTERFACING should be allowed to run under the AD7841 to avoid noise Interfacing the AD7841—16-Bit Interface coupling. The power supply lines of the AD7841 should use as The AD7841 can be interfaced to a variety of 16-bit micro- large a trace as possible to provide low impedance paths and controllers or DSP processors. Figure 10 shows the AD7841 reduce the effects of glitches on the power supply line. Fast interfaced to a generic 16-bit microcontroller/DSP processor. switching signals like clocks should be shielded with digital The lower address lines from the processor are connected to A0, ground to avoid radiating noise to other parts of the board and A1 and A2 on the AD7841 as shown. The upper address lines should never be run near the analog inputs. are decoded to provide a chip select signal or an LDAC signal Avoid crossover of digital and analog signals. Traces on opposite for the AD7841. The fast interface timing of the AD7841 allows sides of the board should run at right angles to each other. This direct interface to a wide variety of microcontrollers and DSPs reduces the effects of feedthrough through the board. A micro- as shown in Figure 10. strip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. REV. B –10– AD7841 The AD7841 should have ample supply bypassing located as V . However, the output of the pin driver will vary from OFFSET close to the package as possible, ideally right up against the –10 V to +10 V with respect to DUTGND as the DAC input device. Figure 11 shows the recommended capacitor values of code varies from 000... 000 to 111... 111. The V OFFSET 10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF voltage is also applied to the DUTGND pins. When a clear is capacitors are the tantalum bead type. The 0.1 µF capacitor performed on the AD7841, the output of the pin driver will be should have low Effective Series Resistance (ESR) and Effective 0 V with respect to DUTGND. Series Inductance (ESI), such as the common ceramic types, The other AD588 is used to provide a reference voltage for which provide a low impedance path to ground at high frequen- DACs G and H. These provide the reference voltages for the cies to handle transient currents due to internal logic switching. window comparator shown in the diagram. Note that Pin 9 of this AD588 is connected to Device GND. This causes V (+)GH REF and V (–)GH to be referenced to Device GND. As DAC G REF V V CC DD and DAC H input codes vary from 000... 000 to 111... 111, 0.1�F1 10�F 0�F 0.1�F V G and V H vary from –10 V to +10 V with respect to OUT OUT AD7841 Device GND. Device GND is also connected to DUTGND. When the AD7841 is cleared, V G and V H are cleared to OUT OUT V SS 0 V with respect to Device GND. 10�F 0.1�F Programmable Reference Generation for the AD7841 in an ATE Application Figure 11. Recommended Decoupling Scheme for AD7841 The AD7841 is particularly suited for use in an automated test Automated Test Equipment environment. The reference input for the AD7841 octal 14-bit The AD7841 is particularly suited for use in an automated test DAC requires three differential references for the eight DACs. environment. Figure 12 shows the AD7841 providing the neces- Programmable references may be a requirement in some ATE sary voltages for the pin driver and the window comparator in a applications as the offset and gain errors at the output of a DAC typical ATE pin electronics configuration. AD588s are used to can be adjusted by varying the voltages on the reference pins of provide reference voltages for the AD7841. In the configuration the DAC. To trim offset errors, the DAC is loaded with the shown, the AD588s are configured so that the voltage at Pin 1 is digital code 000... 000 and the voltage on the V (–) pin is REF 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is adjusted until the desired negative output voltage is obtained. 5 V less than the voltage at Pin 9. To trim out gain errors, first the offset error is trimmed. Then the DAC is loaded with the code 111... 111 and the voltage +15V –15V V OFFSET on the V (+) pin is adjusted until the desired full-scale voltage REF 2 16 minus one LSB is obtained. 4 3 +15V 6 1 V (+)AB It is not uncommon in ATE design, to have other circuitry at REF 8 15 V A OUT PIN AD588 the output of the AD7841 that can have offset and gain errors of V (–)AB REF 13 14 DRIVER up to say ±300 mV. These offset and gain errors can be easily 10 V B OUT 9 11 DUTGND_AB removed by adjusting the reference voltages of the AD7841. 12 0.1�F –15V The AD7841 uses nominal reference values of ±5 V to achieve 7 AD7841* an output span of ±10 V. Since the AD7841 has a gain of two 1�F from the reference inputs to the DAC output, adjusting the DUTGND_GH DEVICE V +15V –15V OUT reference voltages by ±150 mV will adjust the DAC offset and GND 2 16 gain by ±300 mV. V G 4 3 OUT DEVICE There are a number of suitable 8- and 10-bit DACs available 6 1 GND V (+)GH REF 8 that would be suitable to drive the reference inputs of the AD7841, 15 V H OUT V (–)GH AD588 REF 13 such as the AD7804, a quad 10-bit digital-to-analog converter 14 10 with serial load capabilities. The voltage output from this DAC 9 GND 11 is in the form of V ± V and rail-to-rail operation is 12 BIAS SWING DEVICE WINDOW achievable. The voltage reference for this DAC can be inter- GND 7 COMPARATOR 1�F nally generated or provided externally. This DAC also contains TO TESTER *ADDITIONAL PINS OMITTED FOR CLARITY an 8-bit SUB DAC which can be used to shift the complete trans- fer function of each DAC around the V point. This can be BIAS Figure 12. ATE Application used as a fine trim on the output voltage. In this application two One of the AD588s is used as a reference for DACs A and B. AD7804s are required to provide programmable reference capabil- These DACs are used to provide high and low levels for the pin ity for all eight DACs. One AD7804 is used to drive the V (+) REF driver. The pin driver may have an associated offset. This can pins and the second package used to drive the V (–) pins. REF be nulled by applying an offset voltage to Pin 9 of the AD588. Another suitable DAC for providing programmable reference First, the code 1000... 0000 is loaded into the DACA latch ® capability is the AD8803. This is an octal 8-bit TRIMDAC and the pin driver output is set to the DACA output. The and provides independent control of both the top and bottom V voltage is adjusted until 0 V appears between the pin OFFSET ends of the TRIMDAC. This is helpful in maximizing the reso- driver output and DUTGND. This causes both V (+) and REF lution of devices with a limited allowable voltage control range. V (–) to be offset with respect to GND by an amount equal to REF TRIMDAC is a registered trademark of Analog Devices, Inc. REV. B –11– AD7841 The AD8803 has an output voltage range of GND to V (0 V provide a positive output voltage and then to level shift that ana- DD to 5 V). To trim the V (+) input, the appropriate trim range log voltage to the required negative range. Alternatively these REF on the AD8803 DAC can be set using the V and V pins DACs can be operated with supplies of 0 V and –5 V, with the REFL REFH allowing 8 bits of resolution between the two points. This will V pin connected to 0 V and the GND pin connected to –5 V. DD allow the V (+) pin to be adjusted to remove gain errors. Now these can be used to provide the negative reference volt- REF ages for the V (–) inputs on the AD7841. However, the digital REF To trim the V (–) voltage, some method of providing a trim REF signals driving the DACs need to be level-shifted from the 0 V voltage in the required negative voltage range is required. Neither to +5 V range to the –5 V to 0 V range. Figure 13 shows a the AD7804 or the AD8803 can provide this range in normal typical application circuit to provide programmable reference operation as their output range is 0 V to 5 V. There are two capabilities for the AD7841. methods of producing this negative voltage. One method is to ADDR BUS +5V ADDR DECODER V 8/10-BIT DD DAC FSIN/CS A0, A1, A2 0V TO +5V D IN V (+)AB SDATA REF V A V A OUT OUT SCLK SCLK GND AD7841* LOGIC LEVEL SHIFT CONTROLLER V 8/10-BIT DD DAC FSIN/CS 0V TO �5V D IN V (�)AB REF V B SCLK V B OUT OUT GND �5V DATA BUS DATA BUS GND *ADDITIONAL PINS OMITTED FOR CLARITY Figure 13. Programmable Reference Generation for the AD7841 –12– REV. B AD7841 OUTLINE DIMENSIONS 14.15 1.03 13.90 SQ 2.45 0.88 MAX 13.65 0.73 34 44 1 33 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 2.20 0.23 2.00 0.11 1.80 23 11 7° 12 22 0.25 MIN 0° 0.10 0.45 COPLANARITY 0.30 0.80 BSC LEAD WIDTH LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Figure 14. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE Package 1 Model Linearity Error (LSBs) DNL (LSBs) Temperature Range Package Description Option AD7841ASZ ±4 −0.9/+2 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 AD7841ASZ-REEL ±4 −0.9/+2 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 AD7841BSZ ±2 ±1 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 AD7841BSZ-REEL ±2 ±1 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 EVAL-AD7841EBZ Evaluation Board 1 Z = RoHS Compliant Part. REVISION HISTORY 1/11—Rev. A to Rev. B Changes to Absolute Maximum Ratings, Lead Temperature ...... 4 Updated Outline Dimensions ........................................................ 13 Moved and Changes to Ordering Guide ...................................... 13 ©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09645-0-1/11(B) Rev. B | Page 13 of 13 1.95 REF SEATING PLANE VIEW A 041807-A