ANALOG DEVICES AD7839

Octal 13-Bit, Parallel Input, a Voltage-Output DAC AD7839 FEATURES GENERAL DESCRIPTION Eight 13-Bit DACs in One Package The AD7839 contains eight 13-bit DACs on one monolithic Voltage Outputs chip. It has output voltages with a full-scale range of –10 V Offset Adjust for Each DAC Pair from reference voltages of –5 V. Reference Range of 65 V The AD7839 accepts 13-bit parallel loaded data from the exter- Maximum Output Voltage Range of 610 V nal bus into one of the input registers under the control of the Clear Function to User-Defined Voltage WR, CS and DAC channel address pins, A0–A2. 44-Lead MQFP Package The DAC outputs are updated on reception of new data into APPLICATIONS the DAC registers. All the outputs may be updated simulta- Automatic Test Equipment neously by taking the LDAC input low. Process Control Each DAC output is buffered with a gain-of-two amplifier into General Purpose Instrumentation which an external DAC offset voltage can be inserted via the DUTGNDx pins. The AD7839 is available in a 44-lead MQFP package. FUNCTIONAL BLOCK DIAGRAM V (+) V (–) REF REF DUTGND DUTGND V V V CC SS DD AB AB CD AB AD7839 RR 13 13 13 INPUT DAC REG REG DAC A V A OUT A A RR DB12 13 13 INPUT DAC 13 REG REG DAC B V B OUT B B DB0 R 13 13 INPUT DAC 13 R DAC C REG REG V C C C OUT WR R R 13 13 INPUT DAC 13 CS DAC D REG REG V D OUT D D A0 A1 13 13 INPUT DAC 13 REG REG DAC E A2 E E V E LDAC OUT 13 13 R R INPUT DAC 13 REG REG DAC F F F V F OUT 13 13 R R INPUT DAC 13 REG REG DAC G G G V G OUT 13 13 INPUT DAC 13 R R REG REG DAC H H H V H OUT R R GND V (+) V (–) V (+) V (–) DUTGND DUTGND CLR REF REF REF REF EF GH GH GH CDEF CDEF REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 ADDRESS DECODE (V = +5 V 6 5%; V = +15 V 6 5%; V = –15 V 6 5%; GND = DUTGND = 0 V; CC DD SS 1 R = 5 kV and C = 50 pF to GND, T = T to T , unless otherwise noted.) AD7839–SPECIFICATIONS L L A MIN MAX Parameter A Version Units Test Conditions/Comments ACCURACY Resolution 13 Bits Relative Accuracy–2 LSB max Typically –0.5 LSB Differential Nonlinearity–0.9 LSB max Guaranteed Monotonic Over Temperature Zero-Scale Error–4LSB max V (+) = +5 V, V (–) = –5 V. Typically within –1 LSB REF REF Full-Scale Error–4LSB max V (+) = +5 V, V (–) = –5 V. Typically within –1 LSB REF REF Gain Error–1 LSB typ V (+) = +5 V, V (–) = –5 V REF REF 2 Gain Temperature Coefficient 0.5 ppm FSR/°C typ 10 ppm FSR/°C max 2 DC Crosstalk 120mV max See Terminology. Typically 75 mV 2 REFERENCE INPUTS DC Input Impedance 100 MW typ Input Current–1mA max Per Input. Typically –0.03 mA V (+) Range 0/+5 V min/max REF V (–) Range –5/0 V min/max REF [V (+) – V (–)] +2/+10 V min/max For Specified Performance. Can Go as Low as 0 V, but REF REF Performance Not Guaranteed 2 DUTGND INPUTS DC Input Impedance 60 kW typ Max Input Current–0.3 mA typ Per Input Input Range –2/+2 V min/max 2 OUTPUT CHARACTERISTICS Output Voltage Swing–10 V min 2 · (V (–) + [V (+) – V (–)] · D) – V REF REF REF DUTGND Short Circuit Current 15 mA max Resistive Load 5 kW min To 0 V Capacitive Load 50 pF max To 0 V DC Output Impedance 0.5W max 2 DIGITAL INPUTS V , Input High Voltage 2.4 V min INH V , Input Low Voltage 0.8 V max INL I , Input Current Total for All Pins INH @ +25°C1mA max T to T–10mA max MIN MAX C , Input Capacitance 10 pF max IN 3 POWER REQUIREMENTS V +4.75/+5.25 V min/max For Specified Performance CC V +14.25/+15.75 V min/max For Specified Performance DD V –14.25/–15.75 V min/max For Specified Performance SS 2 Power Supply Sensitivity ␣␣DFull Scale/DV 90 dB typ DD ␣␣DFull Scale/DV 90 dB typ SS I 0.5 mA max V = V , V = GND. Dynamic Current CC INH CC INL I 10 mA max Outputs Unloaded. Typically 8 mA DD I 10 mA max Outputs Unloaded. Typically 8 mA SS NOTES 1 Temperature range for A Version: –40°C to +85°C 2 Guaranteed by characterization. Not production tested. 3 The AD7839 is functional with power supplies of –12 V – 10% with reduced output range. At 12 V it is recommended to restrict reference range to –4 V due to output amplifier headroom limitations Specifications subject to change without notice. –2– REV. 0 AD7839 (These characteristics are included for Design Guidance and are not subject AC PERFORMANCE CHARACTERISTICS to production testing.) Parameter A Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 30ms typ Full-Scale Change to –1/2 LSB. DAC Latch Contents Alternately 40ms max Loaded with All 0s and All 1s Slew Rate 0.7 V/ms typ Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V (+) = +5 V, V (–) = –5 V. DAC Latch REF REF Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent on Load Conditions Channel-to-Channel Isolation 99 dB typ See Terminology DAC-to-DAC Crosstalk 40 nV-s typ See Terminology Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test Output Noise Spectral Density ␣␣@ 1 kHz 200 nV/√Hz typ All 1s Loaded to DAC. V (+) = V (–) = 0 V REF REF Specifications subject to change without notice. 1, 2 (V = +5 V 6 5%; V = +15 V 6 5%; V = –15 V 6 5%; GND = DUTGND = 0 V) TIMING SPECIFICATIONS CC DD SS Parameter Limit at T T Units Description MIN, MAX t 15 ns min Address to WR Setup Time 1 t 0 ns min Address to WR Hold Time 2 t 50 ns min CS Pulsewidth Low 3 t 50 ns min WR Pulsewidth Low 4 t 0 ns min CS to WR Setup Time 5 t 0 ns min WR to CS Hold Time 6 t 20 ns min Data Setup Time 7 t 0 ns min Data Hold Time 8 t 30ms typ Settling Time 9 t 300 ns max CLR Pulse Activation Time 10 t 50 ns min LDAC Pulsewidth Low 11 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. t t 1 2 A0, A1, A2 t t 5 6 t CS 3 t 4 WR t 8 t 7 DATA t 9 V OUT t 10 CLR V OUT t 11 LDAC Figure 1. Timing Diagram REV. 0 –3– AD7839 1, 2 ABSOLUTE MAXIMUM RATINGS Lead Temperature, Soldering (T = +25°C unless otherwise noted) Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C A 3 Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C V to GND . . . . . . . . . . . . . . .–0.3 V, +7 V or V + 0.3 V CC DD ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V (Whichever Is Lower) NOTES V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V DD 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V SS nent damage to the device. This is a stress rating only; functional operation of the Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, V + 0.3 V CC device at these or any other conditions above those indicated in the operational V (+) to V (–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V REF REF section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V (+) to GND . . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V REF SS DD 2 Transient currents of up to 100 mA will not cause SCR latch-up. V (–) to GND . . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V REF SS DD 3 V must not exceed V by more than 0.3 V. If it is possible for this to happen CC DD DUTGND to GND . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V SS DD during power supply sequencing, the following diode protection scheme will ensure V (A–H) to GND . . . . . . . . . . . . V – 0.3 V, V + 0.3 V OUT SS DD protection. V V DD CC Operating Temperature Range IN4148 Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C HP5082-2811 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C V V DD CC Junction Temperature (T max) . . . . . . . . . . . . . . . . . .+150°C J AD7839 MQFP Package Power Dissipation . . . . . . . . . . . . . . . . . . (T max – T )/q J A JA q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W JA ORDERING GUIDE Linearity Temperature Error DNL Package Model Range (LSBs) (LSBs) Option* AD7839AS –40°C to +85°C–2–1 S-44 *S = Plastic Quad Flatpack (MQFP). PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 1 33 DUTGND_AB DUTGND_GH PIN 1 IDENTIFIER V A 2 32 V H OUT OUT 3 V (–)AB 31 V (–)GH REF REF 4 30 V (+)AB V (+)GH REF REF 5 29 V V DD SS AD7839 6 28 CLR V TOP VIEW SS (Not to Scale) 7 LDAC 27 DB12 A2 8 26 DB11 9 25 A1 DB10 A0 10 24 DB9 11 23 CS DB8 12 13 14 15 16 17 18 19 20 21 22 –4– REV. 0 WR V B OUT V CC V C OUT GND DUTGND_CD DB0 V D OUT DB1 V (–)CDEF REF DB2 V (+)CDEF REF V DB3 DD DB4 V E OUT DB5 DUTGND_EF DB6 V F OUT DB7 V G OUT AD7839 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DUTGND_AB Device Sense Ground for DACs A and B. V A and V B are referenced to the voltage OUT OUT applied to this pin. 2, 44, 43, V A..V H DAC Outputs. OUT OUT 41, 37, 35, 34, 32 4, 3 V (+)AB, V (–)AB Reference Inputs for DACs A and B. These reference voltages are referred to GND. REF REF 5V Positive Analog Power Supply; +15 V – 5%. DD 6V Negative Analog Power Supply; –15 V – 5%. SS 7 LDAC Load DAC Logic Input (active low). When this logic input is taken low the contents of the input registers are transferred to their respective DAC registers. LDAC can be tied perma- nently low enabling the outputs to be updated on the rising edge of WR. 10, 9, 8 A0, A1, A2 Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a data transfer. 11 CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low. 12 WR Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7839 input registers. Data is latched into the selected input register on the rising edge of WR. 13 V Logic Power Supply; +5 V – 5%. CC 14 GND Ground. 15–27 DB0␣ .␣ .␣ DB12 Parallel Data Inputs. The AD7839 can accept a straight 13-bit parallel word on DB0 to DB12 where DB12 is the MSB and DB0 is the LSB. 28 CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUTGND pin. The con- tents of input registers and DAC registers A to H are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert to their original outputs as determined by the data in their DAC registers. 30, 31 V (+)GH, V (–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND. REF REF 33 DUTGND_GH Device Sense Ground for DACs G and H. V G and V H are referenced to the voltage OUT OUT applied to this pin. 36 DUTGND_EF Device Sense Ground for DACs E and F. V E and V F are referenced to the voltage OUT OUT applied to this pin. 39 V (+)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. REF 40 V (–)CDEF REF 42 DUTGND_CD Device Sense Ground for DACs C and D. V C and V D are referenced to the voltage OUT OUT applied to this pin. REV. 0 –5– AD7839 TERMINOLOGY Full-Scale Error Relative Accuracy This is the error in DAC output voltage when all 1s are loaded Relative accuracy or endpoint linearity is a measure of the max- into the DAC latch. Ideally the output voltage, with all 1s loaded imum deviation from a straight line passing through the end- into the DAC latch, should be 2 V (+) – 1 LSB. REF points of the DAC transfer function. It is measured after adjust- Zero-Scale Error ing for zero error and full-scale error and is normally expressed Zero-scale error is the error in the DAC output voltage when all in Least Significant Bits. 0s are loaded into the DAC latch. Ideally the output voltage, Differential Nonlinearity with all 0s in the DAC latch should be equal to 2 V (–). Zero- REF Differential nonlinearity is the difference between the measured scale error is mainly due to offsets in the output amplifier. change and the ideal 1 LSB change between any two adjacent Gain Error codes. A specified differential nonlinearity of 1 LSB maximum Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error). ensures monotonicity. DC Crosstalk GENERAL DESCRIPTION Although the common input reference voltage signals are inter- DAC Architecture—General nally buffered, small IR drops in the individual DAC reference Each channel consists of a straight 13-bit R-2R voltage-mode inputs across the die can mean that an update to one channel DAC. The full-scale output voltage range is equal to twice the can produce a dc output change in one or another of the chan- reference span of V (+) – V (–). The DAC coding is straight REF REF nel outputs. binary; all 0s produces an output of 2 V (–); all 1s produces REF an output of 2 V (+) – 1 LSB. REF The eight DAC outputs are buffered by op amps that share common V and V power supplies. If the dc load current The analog output voltage of each DAC channel reflects the DD SS changes in one channel (due to an update), this can result in a contents of its own DAC register. Data is transferred from the further dc change in one or another of the channel outputs. This external bus to the input register of each DAC on a per channel effect is most obvious at high load currents and reduces as the basis. load currents are reduced. With high impedance loads the effect Bringing the CLR line low switches all the signal outputs, V A OUT is virtually unmeasurable. to V H, to the voltage level on the DUTGND pin. When the OUT Output Voltage Settling Time CLR signal is brought back high, the output voltages from the This is the amount of time it takes for the output to settle to a DACs will reflect the data stored in the relevant DAC registers. specified level for a full-scale input change. Data Loading to the AD7839 Digital-to-Analog Glitch Impulse Data is loaded into the AD7839 in straight parallel 13-bit wide This is the amount of charge injected into the analog output words. when the inputs change state. It is specified as the area of the The DAC output voltages, V A – V H are updated to OUT OUT glitch in nV-secs. It is measured with V (+) = +5 V and REF reflect new data in the DAC registers. V (–) = –5 V and the digital inputs toggled between 0FFFH and REF The actual input register being written to is determined by the 1000H. logic levels present on the device’s address lines, as shown in Channel-to-Channel Isolation Table I. Channel-to-channel isolation refers to the proportion of input signal from one DAC’s reference input that appears at the out- Table I. Address Line Truth Table put of another DAC. It is expressed in dBs. A2 A1 A0 DAC Selected DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is defined as the glitch impulse that 0 0 0 INPUT REG A (DAC A) appears at the output of one converter due to both the digital 0 0 1 INPUT REG B (DAC B) change and subsequent analog O/P change at another converter. 0 1 0 INPUT REG C (DAC C) It is specified in nV-secs. 0 1 1 INPUT REG D (DAC D) 1 0 0 INPUT REG E (DAC E) Digital Crosstalk 1 0 1 INPUT REG F (DAC F) The glitch impulse transferred to the output of one converter 1 1 0 INPUT REG G (DAC G) due to a change in digital input code to the other converter is 1 1 1 INPUT REG H (DAC H) defined as the digital crosstalk and is specified in nV-secs. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the V OUT pins. This noise is digital feedthrough. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. –6– REV. 0 Typical Performance Characteristics–AD7839 2.0 1.0 0.50 V = +15V V = +15V DD DD V = –15V V = –15V 1.5 SS 0.75 SS V = +5V REF(+) V = +5V REF(+) V = –5V MAX INL REF(–) V = –5V 1.0 0.50 REF(–) 0.25 T = +258C A 0.5 0.25 0.0 0.0 0.0 –0.5 –0.25 MIN INL V = +15V DD V = –15V –0.25 –0.50 SS –1.0 V = +5V REF(+) V = –5V –1.5 –0.75 REF(–) T = +258C A –1.0 –0.50 –2.0 0 –40 –20 0 20 406080 100 2048 4096 6144 8191 0 2048 4096 6144 8192 CODE CODE TEMPERATURE – 8C Figure 2. Typical INL Plot Figure 3. Typical DNL Plot Figure 4. Typical INL Error vs. Temperature 1.0 2.0 6 V = +15V DD V = +15V DD V = +5V CC V = –15V SS V = –15V 1.5 0.75 SS V = +15V 5 DD V = +5V REF(+) V = +5V REF(+) V = –15V SS V = –5V REF(–) 0.50 V = –5V 1.0 REF(–) FULL-SCALE ERROR MAX DNL 4 DIGITAL INPUTS @ 0.5 0.25 THRESHOLDS 3 0 0 2 –0.25 –0.5 MIN DNL 1 ZERO-SCALE ERROR –0.50 –1.0 DIGITAL INPUTS @ SUPPLIES 0 –1.5 –0.75 –1 –2.0 –1.0 –40 –20 0 20 40 60 80 100 –40 –20 020 40 60 80 100 –40 –20 0 204060 80 100 TEMPERATURE – 8C TEMPERATURE – 8C TEMPERATURE – 8C Figure 5. Typical DNL Error vs. Figure 7. I vs. Temperature Figure 6. Zero-Scale and Full-Scale CC Temperature Error vs. Temperature 0.6 10 V = +15V DD 0.5 10.19 V = –15V SS V = +5V CC 0.4 I DD 8 0.3 10.18 I SS 0.2 0.1 10.17 6 0 20.1 10.16 20.2 4 27 28 29 30 31 32 33 –40 –20 0 20 40 60 80 100 0 50 150 200 250 300 350 400 450 500 550 TEMPERATURE – °C SETTLING TIME – ms Figure 8. Typical Digital-to-Analog Figure 9. Settling Time (+) Figure 10. I , I vs. Temperature DD SS Glitch Impulse REV. 0 –7– DNL ERROR – LSBs INL ERROR – LSBs VOLTS DNL ERROR – LSBs V – Volts OUT ERROR – LSBs INL ERROR – LSBs I /I – mA I – mA DD SS CC AD7839 Unipolar Configuration When bipolar-zero and full-scale adjustment are not needed, R2 Figure 11 shows the AD7839 in the unipolar binary circuit and R3 can be omitted. Pin 12 on the AD588 should be con- configuration. The V (+) input of the DAC is driven by the nected to Pin 11 and Pin 5 should be left floating. REF AD586, a +5 V reference. V (–) is tied to ground. Table II REF R1 +15V +5V gives the code table for unipolar operation of the AD7839. 39kV Other suitable references include the REF02, a precision +5 V reference, and the REF195, a low dropout, micropower preci- 46 sion +5 V reference. V V DD CC 7 2 +15V +5V V V C1 OUT OUT 3 1mF 9 V (+) (–10V TO +10V) REF 1 AD588 AD7839* 5 14 2 R2 V V DD CC DUTGND 6 100kV 10 15 V (+) V V V (–) REF OUT OUT REF 8 11 16 AD586 (0 TO +10V) V GND SS 5 AD7839* R1 12 8 13 C1 10kV R3 DUTGND SIGNAL 1mF 4 100kV GND V (–) –15V REF GND V SS *ADDITIONAL PINS OMITTED FOR CLARITY SIGNAL SIGNAL Figure 12. Bipolar –10 V Operation GND GND –15V *ADDITIONAL PINS OMITTED FOR CLARITY Table III. Code Table for Bipolar Operation Figure 11. Unipolar +10 V Operation Binary Number in DAC Offset and gain may be adjusted in Figure 11 as follows: To Register Analog Output adjust offset, disconnect the V (–) input from 0 V, load the REF MSB LSB (V ) OUT DAC with all 0s and adjust the V (–) voltage until V = 0 V. REF OUT 1 1111 1111 1111 2[V (–) + V (8191/8192)] V REF REF For gain adjustment, the AD7839 should be loaded with all 1s 1 0000 0000 0001 2[V (–) + V (4097/8192)] V REF REF and R1 adjusted until V = 2 V (+) – 1 LSB = 10 V(8191/ OUT REF 1 0000 0000 0000 2[V (–) + V (4096/8192)] V REF REF 8192) = 9.99878 V. 0 1111 1111 1111 2[V (–) + V (4095/8192)] V REF REF Many circuits will not require these offset and gain adjustments. 0 0000 0000 0001 2[V (–) + V (1/8192)] V REF REF In these circuits R1 can be omitted. Pin 5 of the AD586 may be 0 0000 0000 0000 2[V (–)] V REF left open circuit and Pin 2 (V (–)) of the AD7839 tied to 0 V. REF NOTES V = (V (+) – V (–)). REF REF REF Table II. Code Table for Unipolar Operation 13 For V (+) = +5 V, and V (–) = –5 V, V = 10 V, 1 LSB = 2 V V/2 = REF REF REF REF 20 V/8192 = 2.44 mV. Binary Number in DAC Register Analog Output MSB␣␣␣␣␣␣␣␣ LSB (V ) OUT CONTROLLED POWER-ON OF THE OUTPUT STAGE 1 1111 1111 1111 2 V (8191/8192) V REF A block diagram of the output stage of the AD7839 is shown in 1 0000 0000 0000 2 V (4096/8192) V REF Figure 13. It is capable of driving a load of 5 kW in parallel with 0 1111 1111 1111 2 V (4095/8192) V REF 50 pF. G to G are transmission gates used to control the 1 6 0 0000 0000 0001 2 V (1/8192) V REF power on voltage present at V . On power up G and G are OUT 1 2 0 0000 0000 0000 0 V also used in conjunction with the CLR input to set V to the OUT user defined voltage present at the DUTGND pin. When CLR NOTES is taken back high, the DAC outputs reflect the data in the DAC V = V (+); V (–) = 0 V for unipolar operation. REF REF REF 13 For V (+) = +5 V, 1 LSB = +10 V/2 = +10 V/8192 = 1.22 mV. registers. REF Bipolar Configuration G 1 Figure 12 shows the AD7839 set up for –10 V operation. The G 6 DAC AD588 provides precision –5 V tracking outputs that are fed to V OUT the V (+) and V (–) inputs of the AD7839. The code table REF REF G 3 for bipolar operation of the AD7839 is shown in Table III. G G 2 4 In Figure 12, full-scale and bipolar zero adjustments are pro- R = 60kV vided by varying the gain and balance on the AD588. R2 varies R the gain on the AD588 while R3 adjusts the offset of both the G 5 14kV +5 V and –5 V outputs together with respect to ground. For bipolar-zero adjustment, the DAC is loaded with DUTGND 1000␣ .␣ .␣ .␣ 0000 and R3 is adjusted until V = 0 V. Full OUT Figure 13. Block Diagram of AD7839 Output Stage scale is adjusted by loading the DAC with all 1s and adjusting R2 until V = 10(4095/4096) V = 9.997559 V. OUT –8– REV. 0 AD7839 G 1 Power-On with CLR Low G 6 DAC The output stage of the AD7839 has been designed to allow V OUT output stability during power-on. If CLR is kept low during G 3 power-on, then just after power is applied to the AD7839, the situation is as depicted in Figure 14. G , G and G are open 1 4 6 G G 2 4 while G , G and G are closed. R 2 3 5 R G G 1 5 14kV G 6 DAC V OUT G 3 DUTGND Figure 16. Output Stage After CLR Is Taken High G G 2 4 R Power-On with CLR High If CLR is high on the application of power to the device, the R G 5 14kV output stages of the AD7839 are configured as in Figure 17 while V is less than 7 V and V is more positive than –3 V. DD SS G is closed and G is open, thereby connecting the output of the 1 2 DUTGND DAC to the input of its output amplifier. G and G are closed 3 5 Figure 14. Output Stage with V < 7 V or V > –3 V; DD SS while G and G are open, thus connecting the output amplifier as 4 6 CLR Low a unity gain buffer. V is connected to DUTGND via G OUT 5 V is kept within a few hundred millivolts of DUTGND via through a 14 kW resistor until V exceeds 7 V and V is more OUT DD SS G and a 14 kW resistor. This thin-film resistor is connected in negative than –3 V. 5 parallel with the gain resistors of the output amplifier. The G 1 output amplifier is connected as a unity gain buffer via G , and 3 G 6 DAC the DUTGND voltage is applied to the buffer input via G . The 2 V OUT amplifier’s output is thus at the same voltage as the DUTGND G 3 pin. The output stage remains configured as in Figure 14 until the voltage at V exceeds 7 V and V is more negative than DD SS G G 2 4 –3 V. By now the output amplifier has enough headroom to R handle signals at its input and has also had time to settle. The R G 5 internal power-on circuitry opens G and G and closes G and 3 5 4 14kV G . This situation is shown in Figure 15. Now the output ampli- 6 fier is configured in its noise gain configuration via G and G . 4 6 DUTGND The DUTGND voltage is still connected to the noninverting Figure 17. Output Stage Powering Up with CLR High input via G and this voltage appears at V . 2 OUT While V < 7 V or V > –3 V DD SS G 1 When the difference between the supply voltages reaches +10 V, G 6 DAC the internal power-on circuitry opens G and G and closes G V 3 5 4 OUT and G configuring the output stage as shown in Figure 18. 6 G 3 G 1 G G 2 4 G R 6 DAC V OUT R G G 3 5 14kV G G 2 4 R DUTGND Figure 15.␣ Output Stage with V > 7 V and V < –3 V; R DD SS G 5 14kV CLR Low V has been disconnected from the DUTGND pin by the OUT DUTGND opening of G , but will track the voltage present at DUTGND 5 Figure 18.␣ Output Stage Powering Up with CLR High; via the configuration shown in Figure 15. V > 7 V and V < –3 V DD SS When CLR is taken back high, the output stage is configured as shown in Figure 16. The internal control logic closes G and 1 opens G . The output amplifier is connected in a noninverting 2 gain-of-two configuration. The voltage that appears on the V OUT pins is determined by the data present in the DAC registers. REV. 0 –9– AD7839 DUTGND Voltage Range APPLICATIONS During power-on, the V pins of the AD7839 are connected Power Supply Bypassing and Grounding OUT to the relevant DUTGND pins via G and the 14 kW thin-film In any circuit where accuracy is important, careful consideration 5 resistor. The DUTGND potential must obey the max ratings at of the power supply and ground return layout helps to ensure all times. Thus, the voltage at DUTGND must always be within the rated performance. The printed circuit board on which the the range V – 0.3 V, V + 0.3 V. However, in order that the AD7839 is mounted should be designed such that the analog SS DD voltages at the V pins of the AD7839 stay within –2 V of the and digital sections are separated and confined to certain areas OUT relevant DUTGND potential during power-on, the voltage of the board. This facilitates the use of ground planes that can applied to DUTGND should also be kept within the range be easily separated. A minimum etch technique is generally best GND – 2␣ V, GND + 2 V. for ground planes as it gives the best shielding. Digital and ana- log ground planes should be joined at only one place. The GND Once the AD7839 has powered on and the on-chip amplifiers pin of the AD7839 should be connected to the AGND of the have settled, any voltage that is now applied to the DUTGND system. If the AD7839 is in a system where multiple devices pin is subtracted from the DAC output, which has been gained require an AGND-to-DGND connection, the connection should up by a factor of two. Thus, for specified operation, the maxi- be made at one point only, a star ground point that should be mum voltage that can be applied to the DUTGND pin in- established as close as possible to the AD7839. creases to the maximum allowable 2 V (+) voltage, and the REF minimum voltage that can be applied to DUTGND is the Digital lines running under the device should be avoided as minimum 2 V (–) voltage. After the AD7839 has fully these will couple noise onto the die. The analog ground plane REF powered on, the outputs can track any DUTGND voltage within should be allowed to run under the AD7839 to avoid noise this minimum/maximum range. coupling. The power supply lines of the AD7839 should use as large a trace as possible to provide low impedance paths and Power Supply Sequencing reduce the effects of glitches on the power supply line. Fast When operating the AD7839, it is important that ground be switching signals like clocks should be shielded with digital connected at all times to avoid high current states. The recom- ground to avoid radiating noise to other parts of the board and mended power-up sequence is V /V followed by V . If V DD SS CC CC should never be run near the analog inputs. can exceed V on power-up, the diode scheme shown in the DD absolute max ratings will ensure protection. The reference in- Avoid crossover of digital and analog signals. Traces on opposite puts and digital inputs should be powered up last. Should the sides of the board should run at right angles to each other. This references exceed V /V on power-up, current limiting resis- reduces the effects of feedthrough through the board. A micro- DD SS tors should be inserted in series with the reference inputs to strip technique is by far the best but not always possible with a limit the current to 20 mA. Logic inputs should not be applied double sided board. In this technique, the component side of before V . Current limiting resistors (470 W), in series with the the board is dedicated to ground plane while signal traces are CC logic inputs, should be inserted if these inputs come up before V . placed on the solder side. CC The AD7839 should have ample supply bypassing located as MICROPROCESSOR INTERFACING close to the package as possible, ideally right up against the Interfacing the AD7839—16-Bit Interface device. Figure 20 shows the recommended capacitor values of The AD7839 can be interfaced to a variety of 16-bit micro- 10 mF in parallel with 0.1 mF on each of the supplies. The 10 mF controllers or DSP processors. Figure 19 shows the AD7839 capacitors are the tantalum bead type. The 0.1 mF capacitor interfaced to a generic 16-bit microcontroller/DSP processor. should have low Effective Series Resistance (ESR) and Effective The lower address lines from the processor are connected to A0, Series Inductance (ESI), such as the common ceramic types, A1 and A2 on the AD7839 as shown. The upper address lines which provide a low impedance path to ground at high frequen- are decoded to provide a chip select signal or an LDAC signal cies to handle transient currents due to internal logic switching. for the AD7839. The fast interface timing of the AD7839 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure 19. V V CC DD 0.1mF1 10mF 0mF 0.1mF AD7839 mCONTROLLER/ AD7839 DSP PROCESSOR* V SS D12 10mF D12 0.1mF DATA BUS D0 D0 Figure 20. Recommended Decoupling Scheme for AD7839 UPPER BITS OF CS ADDRESS ADDRESS BUS DECODE LDAC A2 A2 A1 A1 A0 A0 WR R/W *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. AD7839 Parallel Interface –10– REV. 0 AD7839 Automated Test Equipment Programmable Reference Generation for the AD7839 in an The AD7839 is particularly suited for use in an automated test ATE Application environment. Figure 21 shows the AD7839 providing the neces- The AD7839 is particularly suited for use in an automated test sary voltages for the pin driver and the window comparator in a environment. The reference input for the AD7839 octal 13-bit typical ATE pin electronics configuration. AD588s are used to DAC requires three differential references for the eight DACs. provide reference voltages for the AD7839. In the configuration Programmable references may be a requirement in some ATE shown, the AD588s are configured so that the voltage at Pin 1 is applications as the offset and gain errors at the output of a DAC 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is can be adjusted by varying the voltages on the reference pins of 5 V less than the voltage at Pin 9. the DAC. To trim offset errors, the DAC is loaded with the digital code 000␣ .␣ .␣ .␣ 000 and the voltage on the V (–) pin is REF +15V –15V V OFFSET adjusted until the desired negative output voltage is obtained. 2 16 To trim out gain errors, first the offset error is trimmed. Then 4 3 +15V the DAC is loaded with the code 111␣ .␣ .␣ .␣ 111 and the voltage 6 1 V (+)AB REF on the V (+) pin is adjusted until the desired full-scale voltage REF 8 15 V A OUT PIN AD588 V (–)AB minus one LSB is obtained. REF 13 14 DRIVER 10 V B OUT It is not uncommon in ATE design, to have other circuitry at 9 11 DUTGND AB the output of the AD7839 that can have offset and gain errors of 12 0.1mF –15V up to say –300 mV. These offset and gain errors can be easily 7 AD7839* 1mF removed by adjusting the reference voltages of the AD7839. DUTGND GH The AD7839 uses nominal reference values of –5 V to achieve DEVICE V +15V –15V OUT GND an output span of –10 V. Since the AD7839 has a gain of two 2 16 from the reference inputs to the DAC output, adjusting the V G 4 3 OUT DEVICE 6 1 reference voltages by –150 mV will adjust the DAC offset and GND V (+)GH REF 8 15 V H gain by –300 mV. OUT V (–)GH AD588 REF 13 14 There are a number of suitable 8- and 10-bit DACs available 10 9 GND 11 that would be suitable to drive the reference inputs of the 12 AD7839, such as the AD7804, a quad 10-bit digital-to-analog DEVICE WINDOW GND 7 converter with serial load capabilities. The voltage output from COMPARATOR 1mF TO TESTER this DAC is in the form of V –V and rail-to-rail opera- BIAS SWING *ADDITIONAL PINS OMITTED FOR CLARITY tion is achievable. The voltage reference for this DAC can be Figure 21. ATE Application internally generated or provided externally. This DAC also One of the AD588s is used as a reference for DACs A and B. contains an 8-bit SUB DAC which can be used to shift the These DACs are used to provide high and low levels for the pin complete transfer function of each DAC around the V point. BIAS driver. The pin driver may have an associated offset. This can This can be used as a fine trim on the output voltage. In this be nulled by applying an offset voltage to Pin 9 of the AD588. application two AD7804s are required to provide programmable First, the code 1000␣ .␣ .␣ .␣ 0000 is loaded into the DACA latch reference capability for all eight DACs. One AD7804 is used to and the pin driver output is set to the DACA output. The drive the V (+) pins and the second package used to drive the REF V voltage is adjusted until 0 V appears between the pin OFFSET V (–) pins. REF driver output and DUT GND. This causes both V (+) and REF Another suitable DAC for providing programmable reference V (–) to be offset with respect to GND by an amount equal to REF ® capability is the AD8803. This is an octal 8-bit trimDAC and V . However, the output of the pin driver will vary from OFFSET provides independent control of both the top and bottom ends –10 V to +10 V with respect to DUTGND as the DAC input of the trimDAC. This is helpful in maximizing the resolution of code varies from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111. The V OFFSET devices with a limited allowable voltage control range. voltage is also applied to the DUTGND pins. When a clear is The AD8803 has an output voltage range of GND to V (0 V DD performed on the AD7839, the output of the pin driver will be to +5 V). To trim the V (+) input, the appropriate trim range REF 0 V with respect to DUTGND. on the AD8803 DAC can be set using the V and V pins REFL REFH The other AD588 is used to provide a reference voltage for allowing 8 bits of resolution between the two points. This will DACs G and H. These provide the reference voltages for the allow the V (+) pin to be adjusted to remove gain errors. REF window comparator shown in the diagram. Note that Pin 9 of To trim the V (–) voltage, some method of providing a trim REF this AD588 is connected to Device GND. This causes V (+)GH REF voltage in the required negative voltage range is required. Nei- and V (–)GH to be referenced to Device GND. As DAC G REF ther the AD7804 or the AD8803 can provide this range in nor- and DAC H input codes vary from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111, mal operation as their output range is 0 V to +5 V. There are V G and V H vary from –10 V to +10 V with respect to OUT OUT two methods of producing this negative voltage. One method is Device GND. Device GND is also connected to DUTGND. to provide a positive output voltage and then to level shift that When the AD7839 is cleared, V G and V H are cleared to OUT OUT analog voltage to the required negative range. Alternatively 0 V with respect to Device GND. TrimDAC is a registered trademark of Analog Devices, Inc. REV. 0 –11– AD7839 these DACs can be operated with supplies of 0 V and –5 V, with digital signals driving the DACs need to be level-shifted from the V pin connected to 0 V and the GND pin connected to the 0 V to +5 V range to the –5 V to 0 V range. Figure 22 shows DD –5 V. Now these can be used to provide the negative reference a typical application circuit to provide programmable reference voltages for the V (–) inputs on the AD7839. However, the capabilities for the AD7839. REF ADDR BUS +5V ADDR DECODER 8/10-BIT V DD DAC FSIN/CS A0, A1, A2 0V TO +5V D IN V (+)AB SDATA REF V A V A OUT OUT SCLK SCLK GND AD7839* LOGIC LEVEL SHIFT CONTROLLER V 8/10-BIT DD DAC FSIN/CS 0V TO 25V D IN V (2)AB REF V B SCLK V B OUT OUT GND 25V DATA BUS DATA BUS GND *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Programmable Reference Generation for the AD7839 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead MQFP (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8° 0.025 (0.64) 33 23 0.8° 34 22 SEATING PLANE TOP VIEW (PINS DOWN) 12 44 1 11 0.040 (1.02) 0.040 (1.02) 0.032 (0.81) 0.032 (0.81) 0.016 (0.41) 0.033 (0.84) 0.083 (2.11) 0.029 (0.74) 0.012 (0.30) 0.077 (1.96) –12– REV. 0 PRINTED IN U.S.A. C3168–2–4/99