ANALOG DEVICES AD7837

1 (V = +15 V � 5%, V = –15 V � 5%, AGNDA = AGNDB = DGND AD7837/AD7847–SPECIFICATIONS DD SS = O V. V = V = +10 V, R = 2 k�, C = 100 pF [V connected to R AD7837]. All specifications T to T unless otherwise noted.) REFA REFB L L OUT FB MIN MAX Parameter A Version B Version S Version Units Test Conditions/Comments STATIC PERFORMANCE Resolution 12 12 12 Bits 2 Relative Accuracy ±1 ±1/2 ±1 LSB max 2 Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed Monotonic 2 Zero Code Offset Error @ +25°C ±2 ±2 ±2 mV max DAC Latch Loaded with All 0s T to T ±4 ±3 ±4 mV max Temperature Coefficient = ±5 µV/°C typ MIN MAX 2 Gain Error @ +25°C ±4 ±2 ±4 LSB max DAC Latch Loaded with All 1s T to T ±5 ±3 ±5 LSB max Temperature Coefficient = ±2 ppm of MIN MAX FSR/°C typ REFERENCE INPUTS V Input Resistance 8/13 8/13 8/13 kΩ min/max Typical Input Resistance = 10 kΩ REF V , V Resistance Matching ±2 ±2 ±2 % max Typically ±0.25% REFA REFB DIGITAL INPUTS Input High Voltage, V 2.4 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 0.8 V max INL Input Current ±1 ±1 ±1 µA max Digital Inputs at 0 V and V DD 3 Input Capacitance 8 8 8 pF max ANALOG OUTPUTS DC Output Impedance 0.2 0.2 0.2 Ω typ Short Circuit Current 11 11 11 mA typ V Connected to AGND OUT 4 POWER REQUIREMENTS V Range 14.25/15.75 14.25/15.75 14.25/15.75 V min/max DD V Range –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max SS Power Supply Rejection ∆Gain/∆V ±0.01 ±0.01 ±0.01 % per % max V = 15 V ± 5%, V = –10 V DD DD REF ∆Gain/∆V ±0.01 ±0.01 ±0.01 % per % max V = –15 V ± 5%, V = +10 V SS SS REF I 8 8 8 mA max Outputs Unloaded. Inputs at Thresholds. DD Typically 5 mA I 6 6 6 mA max Outputs Unloaded. Inputs at Thresholds. SS Typically 3 mA 2, 3 AC CHARACTERISTICS Voltage Output Settling Time 3 3 3 µs typ Settling Time to Within ±1/2 LSB of Final 55 5 µs max Value. DAC Latch Alternately Loaded with All 0s and All 1s Slew Rate 11 11 11 V/µs typ Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ 1 LSB Change Around Major Carry Channel-to-Channel Isolation V to V –95 –95 –95 dB typ V = 20 V p-p, 10 kHz Sine Wave. REFA OUTB REFA DAC Latches Loaded with All 0s V to V –95 –95 –95 dB typ V = 20 V p-p, 10 kHz Sine Wave. REFB OUTA REFB DAC Latches Loaded with All 0s Multiplying Feedthrough Error –90 –90 –90 dB typ V = 20 V p-p, 10 kHz Sine Wave. REF DAC Latch Loaded with All 0s Unity Gain Small Signal BW 750 750 750 kHz typ V = 100 mV p-p Sine Wave. DAC REF Latch Loaded with All 1s Full Power BW 175 175 175 kHz typ V = 20 V p-p Sine Wave. DAC REF Latch Loaded with All 1s Total Harmonic Distortion –88 –88 –88 dB typ V = 6 V rms, 1 kHz. DAC Latch REF Loaded with All 1s Digital Crosstalk 1 1 1 nV secs typ Code Transition from All 0s to All 1s and Vice Versa Output Noise Voltage @ +25°C See Typical Performance Graphs (0.1 Hz to 10 Hz) 2 2 2 µV rms typ Amplifier Noise and Johnson Noise of R FB Digital Feedthrough 1 1 1 nV secs typ NOTES 1 Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C. 2 See Terminology. 3 Guaranteed by design and characterization, not production tested. 4 The Devices are functional with V /V = ±12 V (See typical performance graphs.). DD SS Specifications subject to change without notice. –2– REV. C AD7837/AD7847 1, 2, 3 TIMING CHARACTERISTICS (V = +15 V � 5%, V = –15 V � 5%, AGNDA = AGNDB = DGND = O V) DD SS Limit at T , T MIN MAX Parameter (All Versions) Unit Conditions/Comments t 0 ns min CS to WR Setup Time 1 t 0 ns min CS to WR Hold Time 2 t 30 ns min WR Pulsewidth 3 t 80 ns min Data Valid to WR Setup Time 4 t 0 ns min Data Valid to WR Hold Time 5 4 t 0 ns min Address to WR Setup Time 6 4 t 0 ns min Address to WR Hold Time 7 4 t 50 ns min LDAC Pulsewidth 8 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 3 and 5. 3 Guaranteed by design and characterization, not production tested. 4 AD7837 only. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (T = +25°C unless otherwise noted) A Temperature Relative Package V to DGND, AGNDA, AGNDB . . . . . . . –0.3 V to +17 V DD 1 2 Model Range Accuracy Option 1 V to DGND, AGNDA, AGNDB . . . . . . . +0.3 V to –17 V SS V , V to AGNDA, AGNDB REFA REFB AD7837AN –40°C to +85°C ±1 LSB N-24 . . . . . . . . . . . . . . . . . . . . . . . . . . V – 0.3 V to V + 0.3 V SS DD AD7837BN –40°C to +85°C ±1/2 LSB N-24 AGNDA, AGNDB to DGND . . . . . . . –0.3 V to V + 0.3 V DD AD7837AR –40°C to +85°C ±1 LSB R-24 2 2 V , V to AGNDA, AGNDB OUTA OUTB AD7837BR –40°C to +85°C ±1/2 LSB R-24 . . . . . . . . . . . . . . . . . . . . . . . . . . V – 0.3 V to V + 0.3 V SS DD AD7837AQ –40°C to +85°C ±1 LSB Q-24 3 3 R , R to AGNDA, AGNDB FBA FBB AD7837BQ –40°C to +85°C ±1/2 LSB Q-24 . . . . . . . . . . . . . . . . . . . . . . . . . . V – 0.3 V to V + 0.3 V SS DD AD7837SQ –55°C to +125°C ±1 LSB Q-24 Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V + 0.3 V DD AD7847AN –40°C to +85°C ±1 LSB N-24 Operating Temperature Range AD7847BN –40°C to +85°C ±1/2 LSB N-24 Commercial/Industrial (A, B Versions) . . . –40°C to +85°C AD7847AR –40°C to +85°C ±1 LSB R-24 Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C AD7847BR –40°C to +85°C ±1/2 LSB R-24 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C AD7847AQ –40°C to +85°C ±1 LSB Q-24 Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C AD7847BQ –40°C to +85°C ±1/2 LSB Q-24 Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW AD7847SQ –55°C to +125°C ±1 LSB Q-24 Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C NOTES NOTES 1 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. If V is open circuited with V and either AGND applied, the V pin will float SS DD SS 2 N = Plastic DIP; Q = Cerdip; R = SOIC. positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode connected between V and AGND (cathode to AGND) ensures SS the Maximum Ratings will be observed. 2 The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. 3 AD7837 only. *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– AD7837/AD7847 Channel-to-Channel Isolation TERMINOLOGY This is an ac error due to capacitive feedthrough from the V Relative Accuracy (Linearity) REF input on one DAC to V on the other DAC. It is measured Relative accuracy, or endpoint linearity, is a measure of the OUT with the DAC latches loaded with all 0s. maximum deviation of the DAC transfer function from a straight line passing through the endpoints. It is measured after Digital Feedthrough allowing for zero and full-scale errors and is expressed in LSBs Digital feedthrough is the glitch impulse injected from the digi- or as a percentage of full-scale reading. tal inputs to the analog output when the data inputs change state, but the data in the DAC latches is not changed. Differential Nonlinearity Differential nonlinearity is the difference between the measured For the AD7837, it is measured with LDAC held high. For the change and the ideal 1 LSB change between any two adjacent AD7847, it is measured with CSA and CSB held high. codes. A specified differential nonlinearity of ±1 LSB or less Digital Crosstalk over the operating temperature range ensures monotonicity. Digital crosstalk is the glitch impulse transferred to the output Zero Code Offset Error of one converter due to a change in digital code on the DAC Zero code offset error is the error in output voltage from V OUTA latch of the other converter. It is specified in nV secs. or V with all 0s loaded into the DAC latches. It is due to a OUTB Digital-to-Analog Glitch Impulse combination of the DAC leakage current and offset errors in the This is the voltage spike that appears at the output of the DAC output amplifier. when the digital code changes, before the output settles to its Gain Error final value. The energy in the glitch is specified in nV secs and is Gain error is a measure of the output error between an ideal measured for a 1 LSB change around the major carry transition DAC and the actual device output with all 1s loaded. It does (0111 1111 1111 to 1000 0000 0000 and vice versa). not include offset error. Unity Gain Small Signal Bandwidth Total Harmonic Distortion This is the frequency at which the small signal voltage output This is the ratio of the root-mean-square (rms) sum of the har- from the output amplifier is 3 dB below its dc level. It is mea- monics to the fundamental, expressed in dBs. sured with the DAC latch loaded with all 1s. Multiplying Feedthrough Error Full Power Bandwidth This is an ac error due to capacitive feedthrough from the V REF This is the maximum frequency for which a sinusoidal input input to V of the same DAC when the DAC latch is loaded OUT signal will produce full output at rated load with a distortion with all 0s. less than 3%. It is measured with the DAC latch loaded with all 1s. AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin Mnemonic Description 1 CS Chip Select. Active low logic input. The device is selected when this input is active. 2R Amplifier Feedback Resistor for DAC A. FBA 3V Reference Input Voltage for DAC A. This may be an ac or dc signal. REFA Analog Output Voltage from DAC A. 4V OUTA 5 AGNDA Analog Ground for DAC A. 6V Positive Power Supply. DD Negative Power Supply. 7V SS 8 AGNDB Analog Ground for DAC B. 9V Analog Output Voltage from DAC B. OUTB Reference Input Voltage for DAC B. This may be an ac or dc signal. 10 V REFB 11 DGND Digital Ground. Ground reference for digital circuitry. 12 R Amplifier Feedback Resistor for DAC B. FBB 13 WR Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to write data to the input latches. 14 LDAC DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when LDAC is taken low. 15 A1 Address Input. Most significant address input for input latches (see Table II). 16 A0 Address Input. Least significant address input for input latches (see Table II). 17–20 DB7–DB4 Data Bit 7 to Data Bit 4. 21–24 DB3–DB0 Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8. –4– REV. C AD7837/AD7847 AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin Mnemonic Description 11 CSA Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low. 12 CSB Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low. 13V Reference Input Voltage for DAC A. This may be an ac or dc signal. REFA 14V Analog Output Voltage from DAC A. OUTA 15 AGNDA Analog Ground for DAC A. 16V Positive Power Supply. DD 17V Negative Power Supply. SS 18 AGNDB Analog Ground for DAC B. 19V Analog Output Voltage from DAC B. OUTB 10 V Reference Input Voltage for DAC B. This may be an ac or dc signal. REFB 11 DGND Digital Ground. 12 DB11 Data Bit 11 (MSB). 13 WR Write Input. WR is a positive edge triggered input which is used in conjunction with CSA and CSB to write data to the DAC latches. 14–24 DB10–DB0 Data Bit 10 to Data Bit 0 (LSB). AD7837 PIN CONFIGURATION AD7847 PIN CONFIGURATION DIP AND SOIC DIP AND SOIC 1 24 1 24 CS DB0 CSA DB0 R 2 23 2 23 FBA DB1 CSB DB1 V 3 22 V 3 22 DB2 DB2 REFA REFA V 4 21 V 4 21 DB3 DB3 OUTA OUTA 5 20 5 20 AGNDA DB4 AGNDA DB4 AD7837 AD7847 V 6 19 V 6 19 DB5 DB5 DD DD TOP VIEW TOP VIEW (Not to Scale) (Not to Scale) V 7 18 V 7 18 DB6 DB6 SS SS 8 17 8 17 AGNDB DB7 AGNDB DB7 V 9 16 V 9 16 A0 DB8 OUTB OUTB V 10 15 V 10 15 A1 DB9 REFB REFB DB10 11 14 11 14 DGND LDAC DGND R 12 13 12 13 WR DB11 WR FBB REV. C –5– AD7837/AD7847–Typical Performance Graphs 10 25 0.6 V = +15V 0.4 DD DAC A V = –15V SS 0.2 20 0 0 –0.2 15 –0.4 –0.6 –10 0.6 V = +15V DD 10 0.4 DAC B V = –15V SS V = +15V 0.2 DD V = +20Vp–p REF –20 V = –15V SS 0 DAC CODE = 111...111 5 V = +20Vp–p @ 1kHz REF –0.2 DAC CODE = 111...111 –0.4 –30 0 –0.6 4 5 6 7 10 100 1k 10k 0 2048 4095 10 10 10 10 CODE LOAD RESISTANCE – � FREQUENCY – Hz Figure 2. Output Voltage Swing vs. Figure 1. Frequency Response Figure 3. DAC-to-DAC Linearity Resistive Load Matching 0.5 –40 400 –50 0.4 V = 7.5V REF 300 V = +15V DD V = +15V V = –15V DD –60 SS 0.3 V = –15V V = 6V rms SS REF V = 0V DAC CODE = 111...111 REF –70 200 DAC CODE = 111...111 0.2 INL –80 100 0.1 –90 DNL 0.0 –100 0 100 0 11 13 15 17 0.1 110 0.01 0.1 1 10 100 V /V – Volts FREQUENCY – kHz DD SS FREQUENCY – Hz Figure 4. Linearity vs. Power Supply Figure 5. Noise Spectral Density vs. Figure 6. THD vs. Frequency Frequency –50 A1 –0.01V –60 V = +15V DD V = –15V SS V = 20V p-p REF –70 DAC CODE = 000...000 FULL SCALE –80 V OUT –90 ZERO SCALE B 2�s 200mV 50mV w L –100 0.1 1 10 100 1000 HORIZ 2�s/DIV VERT 2V/DIV FREQUENCY – kHz Figure 7. Multiplying Feedthrough Figure 9. Small Signal Pulse Figure 8. Large Signal Pulse Error vs. Frequency Response Response –6– REV. C GAIN – dB FEEDTHROUGH – dB ERROR – LSB NOISE SPECTRAL DENSITY – nV/ Hz V – Volts p–p OUT ERROR – LSB THD – dB AD7837/AD7847 CIRCUIT INFORMATION Table I. AD7847 Truth Table D/A SECTION C CCSA C C CSB WR Function A simplified circuit diagram for one of the D/A converters and output amplifier is shown in Figure 10. X X 1 No Data Transfer A segmented scheme is used whereby the 2 MSBs of the 12-bit 1 1 X No Data Transfer data word are decoded to drive the three switches A-C. The 01 g Data Latched to DAC A remaining 10 bits drive the switches (S0–S9) in a standard R-2R 10 g Data Latched to DAC B ladder configuration. 00 g Data Latched to Both DACs g 1 0 Data Latched to DAC A Each of the switches A–C steers 1/4 of the total reference cur- 1 g 0 Data Latched to DAC B rent with the remaining 1/4 passing through the R-2R section. gg 0 Data Latched to Both DACs The output amplifier and feedback resistor perform the current X = Don’t Care. g = Rising Edge Triggered. to voltage conversion giving V = – D × V OUT REF CSA, CSB where D is the fractional representation of the digital word. (D t t 1 2 can be set from 0 to 4095/4096.) t 3 WR The output amplifier can maintain ±10 V across a 2 kΩ load. It t is internally compensated and settles to 0.01% FSR (1/2 LSB) 5 t 4 in less than 5 µs. Note that on the AD7837, V must be con- OUT VALID DATA nected externally to R . DATA FB Figure 12. AD7847 Write Cycle Timing Diagram R R R V REF 2R 2R 2R 2R 2R 2R 2R INTERFACE LOGIC INFORMATION—AD7837 R/2 C B A S9 S8 S0 The input loading structure on the AD7837 is configured for interfacing to microprocessors with an 8-bit-wide data bus. The V OUT part contains two 12-bit latches per DAC—an input latch and SHOWN FOR ALL 1s ON DAC AGND a DAC latch. Each input latch is further subdivided into a least- significant 8-bit latch and a most-significant 4-bit latch. Only the Figure 10. D/A Simplified Circuit Diagram data held in the DAC latches determines the outputs from the part. The input control logic for the AD7837 is shown in Figure 13, INTERFACE LOGIC INFORMATION—AD7847 while the write cycle timing diagram is shown in Figure 14. The input control logic for the AD7847 is shown in Figure 11. The part contains a 12-bit latch for each DAC. It can be treated as two independent DACs, each with its own CS input and a com- DAC A DAC B LDAC LATCH LATCH mon WR input. CSA and WR control the loading of data to the CS DAC A latch, while CSB and WR control the loading of the 12 12 WR DAC B latch. The latches are edge triggered so that input data 4 is latched to the respective latch on the rising edge of WR. If CSA DAC A MS INPUT and CSB are both low and WR is taken high, the same data will LATCH 8 A0 be latched to both DAC latches. The control logic truth table is DAC A LS shown in Table I, while the write cycle timing diagram for the INPUT A1 LATCH part is shown in Figure 12. 4 DAC B LS INPUT LATCH CSA 8 DAC A LATCH WR DAC B LS INPUT LATCH DAC B LATCH CSB 8 DB7 DB0 Figure 11. AD7847 Input Control Logic Figure 13. AD7837 Input Control Logic REV. C –7– AD7837/AD7847 UNIPOLAR BINARY OPERATION A0/A1 ADDRESS DATA Figure 15 shows DAC A on the AD7837/AD7847 connected for unipolar binary operation. Similar connections apply for t t 6 7 DAC B. When V is an ac signal, the circuit performs 2-quad- IN CS rant multiplication. The code table for this circuit is shown in t t Table III. Note that on the AD7847 the feedback resistor R is FB 1 2 t 3 internally connected to V . OUT WR V DD t 5 t 4 V AD7837 DD R FBA * VALID AD7847 DATA DATA V V REFA OUTA t DAC A V V 8 OUT IN LDAC V DGND AGNDA *INTERNALLY SS CONNECTED ON AD7847 Figure 14. AD7837 Write Cycle Timing Diagram V SS Figure 15. Unipolar Binary Operation CS, WR, A0 and A1 control the loading of data to the input latches. The eight data inputs accept right-justified data. Data Table III. Unipolar Code Table can be loaded to the input latches in any sequence. Provided that LDAC is held high, there is no analog output change as a result DAC Latch Contents of loading data to the input latches. Address lines A0 and A1 MSB LSB Analog Output, V OUT determine which latch data is loaded to when CS and WR are low. The control logic truth table for the part is shown in Table II.  4095 –V × 1111 1111 1111 IN   4096   Table II. AD7837 Truth Table   2048 CS WR A1 A0 LDAC Function –V × = –1/2 V 1000 0000 0000 IN   IN 4096   1 X X X 1 No Data Transfer X 1 X X 1 No Data Transfer  1  –V × 0 0 0 0 1 DAC A LS Input Latch Transparent IN 0000 0000 0001   4096   0 0 0 1 1 DAC A MS Input Latch Transparent 0000 0000 0000 0 V 0 0 1 0 1 DAC B LS Input Latch Transparent 0 0 1 1 1 DAC B MS Input Latch Transparent V IN Note 1 LSB = . 1 1 X X 0 DAC A and DAC B DAC Latches 4096 Updated Simultaneously from the Respective Input Latches X = Don’t Care. The LDAC input controls the transfer of 12-bit data from the input latches to the DAC latches. When LDAC is taken low, both DAC latches, and hence both analog outputs, are updated at the same time. The data in the DAC latches is held on the rising edge of LDAC. The LDAC input is asynchronous and indepen- dent of WR. This is useful in many applications especially in the simultaneous updating of multiple AD7837s. However, care must be taken while exercising LDAC during a write cycle. If an LDAC operation overlaps a CS and WR operation, there is a possibility of invalid data being latched to the output. To avoid this, LDAC must remain low after CS or WR return high for a period equal to or greater than t , the minimum LDAC pulsewidth. 8 –8– REV. C AD7837/AD7847 BIPOLAR OPERATION APPLICATIONS (4-QUADRANT MULTIPLICATION) PROGRAMMABLE GAIN AMPLIFIER (PGA) Figure 16 shows the AD7837/AD7847 connected for bipolar The dual DAC/amplifier combination along with access to R FB operation. The coding is offset binary as shown in Table IV. make the AD7837 ideal as a programmable gain amplifier. In this When V is an ac signal, the circuit performs 4-quadrant multi- IN application, the DAC functions as a programmable resistor in the plication. To maintain the gain error specifications, resistors R1, amplifier feedback loop. This type of configuration is shown R2 and R3 should be ratio matched to 0.01%. Note that on the in Figure 17 and is suitable for ac gain control. The circuit con- AD7847 the feedback resistor R is internally connected to FB sists of two PGAs in series. Use of a dual configuration provides V . OUT greater accuracy over a wider dynamic range than a single PGA solution. The overall system gain is the product of the individual R2 gain stages. The effective gains for each stage are controlled by 20k� R1 the DAC codes. As the code decreases, the effective DAC 20k� resistance increases, and so the gain also increases. V DD AD711 V OUT V AD7837 DD R FBA * V REFA AD7847 R3 DAC A 10k� V V OUTA R REFA FBA V DAC A V V IN IN OUTA *INTERNALLY AGNDA CONNECTED V DGND AGNDA SS ON AD7847 AD7837 V REFB DAC B V SS R FBB V OUTB Figure 16. Bipolar Offset Binary Operation V OUT AGNDB Table IV. Bipolar Code Table Figure 17. Dual PGA Circuit DAC Latch Contents MSB LSB Analog Output, V OUT The transfer function is given by V R R EQA EQB OUT  2047 = × (1) +V × 1111 1111 1111 IN   V R R IN FBA FBB  2048 where R , R are the effective DAC resistances controlled EQA EQB   1 by the digital input code: +V × 1000 0000 0001 IN   2048   12 2 R IN 1000 0000 0000 0 V R = (2) EQ N  1  where R is the DAC input resistance and is equal to R and –V × IN FB IN 0111 1111 1111   2048   N = DAC input code in decimal. The transfer function in (1) thus simplifies to  2048 –V × = –V IN   IN 0000 0000 0000 2048   12 12 V 2 2 OUT = × (3) V N N V IN A B IN Note 1 LSB = . 2048 where N = DAC A input code in decimal and N = DAC B A B input code in decimal. 12 N , N may be programmed between 1 and (2 –1). The zero A B code is not allowed as it results in an open loop amplifier response. To minimize errors, the digital codes N and N A B should be chosen to be equal to or as close as possible to each other to achieve the required gain. REV. C –9– AD7837/AD7847 ANALOG PANNING CIRCUIT 0.6 In audio applications it is often necessary to digitally “pan” or split a single signal source into a two-channel signal while main- 0.5 taining the total power delivered to both channels constant. This may be done very simply by feeding the signal into the V REF 0.4 input of both DACs. The digital codes are chosen such that the code applied to DAC B is the two's complement of that applied 0.3 to DAC A. In this way the signal may be panned between both channels as the digital code is changed. The total power varia- 0.2 tion with this arrangement is 3 dB. For applications which require more precise power control the 0.1 circuit shown in Figure 18 may be used. This circuit requires the AD7837/AD7847, an AD712 dual op amp and eight equal 0.0 value resistors. 1 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE N A Again both channels are driven with two's complementary data. The maximum power variation using this circuit is only 0.5 dBs. Figure 19. Power Variation for Circuit in Figure 9 R R APPLYING THE AD7837/AD7847 General Ground Management 1/2 AC or transient voltages between the analog and digital grounds V AD712 REFA i.e., between AGNDA/AGNDB and DGND can cause noise AD7837/ AD7847 injection into the analog output. The best method of ensuring R R V OUTA that both AGNDs and DGND are equal is to connect them R R together at the AD7837/AD7847 on the circuit board. In more V V IN OUTB complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in 1/2 V AD712 REFB inverse parallel between the AGND and DGND pins (1N914 or equivalent). R R Power Supply Decoupling V V OUTA OUTB In order to minimize noise it is recommended that the V and DD RL RL A B the V lines on the AD7837/AD7847 be decoupled to DGND SS using a 10 µF in parallel with a 0.1 µF ceramic capacitor. Figure 18. Analog Panning Circuit Operation with Reduced Power Supply Voltages The AD7837/AD7847 is specified for operation with V /V = DD SS The voltage output expressions for the two channels are as ±15 V ± 5%. The part may be operated down to V /V = DD SS follows: ±10 V without significant linearity degradation. See typical  N  performance graphs. The output amplifier however requires A V = –V OUTA IN  12 approximately 3 V of headroom so the V input should not 2 + N REF   A approach within 3 V of either power supply voltages in order to  N  maintain accuracy. B V = –V OUT B IN  12 2 + N  B MICROPROCESSOR INTERFACING–AD7847 Figures 20 to 22 show interfaces between the AD7847 and three where N = DAC A input code in decimal (1 ≤ N ≤ 4095) A A popular 16-bit microprocessor systems, the 8086, MC68000 and and N = DAC B input code in decimal (1 ≤ N ≤ 4095) B B the TMS320C10. In all interfaces, the AD7847 is memory- with N = 2s complement of N . mapped with a separate memory address for each DAC latch. B A The two's complement relationship between N and N causes AD7847–8086 Interface A B N to increase as N decreases and vice versa. Figure 20 shows an interface between the AD7847 and the 8086 B A microprocessor. A single MOV instruction loads the 12-bit word Hence N + N = 4096. A B into the selected DAC latch and the output responds on the ris- With N = 2048, then N = 2048 also; this gives the balanced A B ing edge of WR. condition where the power is split equally between both chan- nels. The total power variation as the signal is fully panned from Channel B to Channel A is shown in Figure 19. –10– REV. C TOTAL POWER VARIATION – dB AD7837/AD7847 MICROPROCESSOR INTERFACING–AD7837 ADDRESS BUS Figures 23 to 25 show the AD7837 configured for interfacing to 8086 microprocessors with 8-bit data bus systems. In all cases, data is CSA ADDRESS right-justified and the AD7837 is memory-mapped with the two 16 BIT DECODE CSB ALE LATCH lowest address lines of the microprocessor address bus driving AD7847* WR WR the A0 and A1 inputs of the AD7837. Five separate memory DB11 addresses are required, one for the each MS latch and one for DB0 each LS latch and one for the common LDAC input. Data is written to the respective input latch in two write operations. AD15 ADDRESS/DATA BUS Either high byte or low byte data can be written first to the AD0 *ADDITIONAL PINS OMITTED FOR CLARITY input latch. A write to the AD7837 LDAC address transfers the data from the input latches to the respective DAC latches and Figure 20. AD7847 to 8086 Interface updates both analog outputs. Alternatively, the LDAC input AD7847–MC68000 Interface can be asynchronous and can be common to several AD7837s Figure 21 shows an interface between the AD7847 and the for simultaneous updating of a number of voltage channels. MC68000. Once again a single MOVE instruction loads the AD7837–8051/8088 Interface 12-bit word into the selected DAC latch. CSA and CSB are Figure 23 shows the connection diagram for interfacing the AND-gated to provide a DTACK signal when either DAC AD7837 to both the 8051 and the 8088. On the 8051, the latch is selected. signal PSEN is used to enable the address decoder while DEN is used on the 8088. A23 ADDRESS BUS A1 A15 MC68000 ADDRESS CSA ADDRESS BUS DECODE A8 CSB EN AS A0 A1 8051/8088 ADDRESS AD7847* CS DECODE DTACK LDAC PSEN OR DEN EN LDS WR R/W OCTAL AD7837* DB11 ALE LATCH DB0 WR WR D15 DB7 DATA BUS D0 DB0 *ADDITIONAL PINS OMITTED FOR CLARITY AD7 ADDRESS/DATA BUS AD0 Figure 21. AD7847 to MC68000 Interface *ADDITIONAL PINS OMITTED FOR CLARITY AD7847–TMS320C10 Interface Figure 23. AD7837 to 8051/8088 Interface Figure 22 shows an interface between the AD7847 and the AD7837–MC68008 Interface TMS320C10 DSP processor. A single OUT instruction loads An interface between the AD7837 and the MC68008 is shown the 12-bit word into the selected DAC latch. in Figure 24. In the diagram shown, the LDAC signal is derived from an asynchronous timer but this can be derived from the A11 ADDRESS BUS address decoder as in the previous interface diagram. A0 TMS320C10 ADDRESS CSA TIMER DECODE CSB MEN EN A19 AD7847* ADDRESS BUS A0 WE WR DB11 A0 A1 MC68008 ADDRESS CS DB0 DECODE LDAC AS EN D15 DATA BUS DTACK AD7837* D0 *ADDITIONAL PINS OMITTED FOR CLARITY DS WR R/W DB7 Figure 22. AD7847 to TMS320C10 Interface DB0 D7 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. AD7837 to 68008 Interface REV. C –11– AD7837/AD7847 AD7837–6502/6809 Interface Figure 25 shows an interface between the AD7837 and the 6502 or 6809 microprocessor. For the 6502 microprocessor, the φ2 clock is used to generate the WR, while for the 6809 the E sig- nal is used. A15 ADDRESS BUS A0 A0 A1 6502/6809 ADDRESS CS DECODE LDAC R/W EN AD7837* �2 OR E WR DB7 DB0 D7 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. AD7837 to 6502/6809 Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 24-Lead Cerdip (Q-24) 1.228 (31.19) 1.226 (31.14) 24 13 0.295 PIN 1 24 13 (7.493) 0.261 � 0.001 0.320 (8.128) MAX 112 (6.61 � 0.03) 0.32 (8.128) 112 0.290 (7.366) 0.30 (7.62) 0.070 (1.778) 1.290 (32.77) MAX PIN 1 0.180 0.020 (0.508) 0.225 (5.715) (4.572) 0.130 (3.30) MAX MAX 0.128 (3.25) 0.125 (3.175) SEATING MIN SEATING 0.012 (0.305) PLANE PLANE 0.011 (0.28) 0.021 (0.533) 0.110 (2.794) 0.065 (1.651) 15° 0.008 (0.203) 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 15° 0.009 (0.23) 0.015 (0.381) 0.090 (2.286) 0° 0.055 (1.397) TYP 0° 0.016 (0.41) 0.09 (2.28) 0.05 (1.27) TYP TYP 1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH. 1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH. 2. PLASTIC LEADS WILL EITHER BE SOLDER DIPPED OR TIN LEAD PLATED. 2. CERDIP LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED. IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 24-Lead SOIC (R-24) 0.608 (15.45) 0.596 (15.13) 24 13 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) 1 12 0.398 (10.10) PIN 1 0.096 (2.44) 0.03 (0.76) 0.089 (2.26) 0.02 (0.51) 6� 0.05 0.019 (0.49) SEATING 0� 0.01 (0.254) 0.042 (1.067) 0.013 (0.32) (1.27) PLANE 0.006 (0.15) 0.014 (0.35) 0.018 (0.457) 0.009 (0.23) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. SOIC LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. –12– REV. C PRINTED IN U.S.A. C01007a–0–8/00 (rev. C)