ANALOG DEVICES AD7836

2 LC MOS a Quad 14-Bit DAC AD7836 GENERAL DESCRIPTION FEATURES The AD7836 contains four 14-bit DACs on one monolithic Four 14-Bit DACs in One Package chip. It has output voltages with a full-scale range of ±10 V Voltage Outputs from reference voltages of ±5 V. Separate Offset Adjust for Each Output Reference Range of �5 V The AD7836 accepts 14-bit parallel loaded data from the exter- Maximum Output Voltage Range of �10 V nal bus into one of the input latches under the control of the Clear Function to User-Defined Code WR, CS and DAC channel address pins, A0–A2. 44-Pin MQFP Package The DAC outputs are updated individually, on reception of new APPLICATIONS data. In addition, the SEL input can be used to apply the user Process Control programmed value in DAC Register E to all DACs, thus setting Automatic Test Equipment all DAC output voltages to the same level. The contents of the General Purpose Instrumentation DAC data registers are not affected by the SEL input. Each DAC output is buffered with a gain of two amplifier into which an external DAC offset voltage can be inserted via the DUTGNDx pins. The AD7836 is available in a 44-lead MQFP package. FUNCTIONAL BLOCK DIAGRAM V (+)A V (–)A V (+)B V (–)B V V V REF REF REF REF CC SS DD X1 X1 AD7836 14 DATA 14 REG 14 MUX DAC A A V A OUT R X1 X1 DB13 14 14 INPUT R DATA BUFFER DUTGND A REG DB0 DAC B B MUX V B OUT WR R CS R DATA DUTGND B REG MUX C DAC B A0 V C OUT ADDRESS R A1 DECODE X1 X1 A2 R DATA DUTGND C REG MUX DAC D D V D OUT R DATA X1 X1 R REG DUTGND D E DGND AGND SEL V (+)D V (–)D V (+)C V (–)C REF REF REF REF CLR REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 (V = +5 V � 5%; V = +15 V � 5%; V = –15 V � 5%; AGND = DGND = DUTGND CC DD SS 1 AD7836–SPECIFICATIONS = 0 V; R = 5 k� and C = 50 pF to GND, T = T to T , unless otherwise noted) L L A MIN MAX Parameter A Units Test Conditions/Comments ACCURACY Resolution 14 Bits Relative Accuracy ±2 LSB max Differential Nonlinearity ±0.9 LSB max Guaranteed Monotonic Over Temperature (+) = +5 V, V (–) = –5 V. Typically within ±1 LSB Full-Scale Error ±8 LSB max V REF REF Zero-Scale Error ±8 LSB max V (+) = +5 V, V (–) = –5 V. Typically within ±1 LSB REF REF Gain Error ±2 mV typ V (+) = +5 V, V (–) = –5 V REF REF 2 20 ppm FSR/°C typ Gain Temperature Coefficient 40 ppm FSR/°C max 2 DC Crosstalk 50 µV max See Terminology. R = 5 kΩ L REFERENCE INPUTS DC Input Resistance 100 MΩ typ Input Current ± 1 µA max Per Input. Typically ±20 nA V (+) Range 0/+5 V min/max REF V (–) Range –5/0 V min/max REF [V (+) – V (–)] 2/10 V min/max For Specified Performance. Can Go as Low as 0 V, REF REF but Performance Not Guaranteed OUTPUT CHARACTERISTICS Output Voltage Swing ±10 V min 2 × (V (–)+[V (+)-V (–)]•D) – V REF REF REF DUTDGN Short Circuit Current 25 mA max Resistive Load 5 kΩ min To 0 V Capacitive Load 50 pF max To 0 V DIGITAL INPUTS V , Input High Voltage 2.4 V min INH V , Input Low Voltage 0.8 V max INL I , Input Current ±10 µA max Total for All Pins INH C , Input Capacitance 10 pF max IN POWER REQUIREMENTS V 5.0 V nom ±5% for Specified Performance CC V 15.0 V nom ±5% for Specified Performance DD V –15.0 V nom ±5% for Specified Performance SS Power Supply Sensitivity ∆Full Scale/∆V 110 dB typ DD ∆Full Scale/∆V 100 dB typ SS I 0.5 mA max V = V , V = DGND. Dynamic Current CC INH CC INL 8 mA max V = 2.4 V min, V = 0.8 V max INH INL I 14 mA max Outputs Unloaded. Typically 7 mA DD I 14 mA max Outputs Unloaded. Typically 7 mA SS (These characteristics are included for Design Guidance and are not AC PERFORMANCE CHARACTERISTICS subject to production testing.) Parameter A Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 16 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Digital-to-Analog Glitch Impulse 150 nV-s typ Measured with V (+) = +5 V, V (–) = –5 V. DAC Latch REF REF Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent on Load Conditions DC Output Impedance 0.3 Ω max See Terminology Channel-to-Channel Isolation 115 dB typ See Terminology DAC-to-DAC Crosstalk 10 nV-s typ See Terminology Digital Crosstalk 10 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough 0.2 nV-s typ Effect of Input Bus Activity on DAC Output Under Test Output Noise Spectral Density @ 1 kHz 40 nV/√Hz typ All 1s Loaded to DAC. V (+) = V (–) = 0 V REF REF NOTES 1 Temperature range for A Version: –40°C to +85°C 2 Guaranteed by design. Specifications subject to change without notice. –2– REV. A AD7836 1 (V = +5 V � 5%; V = +15 V � 5%; V = –15 V � 5%; AGND = DGND = 0 V) TIMING SPECIFICATIONS CC DD SS Parameter Limit at T T Units Description MIN, MAX t 15 ns min A0, A1, A2 to WR Setup Time 1 t 0 ns min A0, A1, A2 to WR Hold Time 2 t 0 ns min CS to WR Setup Time 3 t 0 ns min WR to CS Hold Time 4 t 44 ns min WR Pulsewidth 5 t 15 ns min Data Setup Time 6 t 4.5 ns min Data Hold Time 7 t 44 ns min WR Pulse Interval 8 t 16 µs typ Settling Time 9 t 300 ns max CLR Pulse Activation Time 10 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. t t 2 1 A0, A1, A2 t t 3 4 CS t 8 t 5 WR t 7 t 6 DATA t 9 V OUT t 10 CLR V OUT Figure 1. Timing Diagram REV. A –3– AD7836 1 ABSOLUTE MAXIMUM RATINGS MQFP Package, Power Dissipation . . . . . . . . . . . . . . 480 mW (T = +25°C unless otherwise noted) A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W JA Lead Temperature, Soldering V to DGND . . . . . . . . . . . . . . .–0.3 V, +7 V or V + 0.3 V CC DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C (Whichever Is Lower) Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V DD NOTES V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V SS 1 Stresses above those listed under “Absolute Maximum Ratings” may cause AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V permanent damage to the device. This is a stress rating only and functional Digital Inputs to DGND . . . . . . . . . . . . . –0.3 V, V + 0.3 V CC operation of the device at these or any other conditions above those indicated in V (+) to V (–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V REF REF the operational section of this specification is not implied. Exposure to absolute V (+) to AGND . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V maximum rating conditions for extended periods may affect device reliability. REF SS DD 2 Transient currents of up to 100 mA will not cause SCR latch-up. V (–) to AGND . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V REF SS DD DUTGND to AGND . . . . . . . . . . . V – 0.3 V, V + 0.3 V SS DD V (A–D) to AGND . . . . . . . . . . V – 0.3 V, V + 0.3 V OUT SS DD Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C ORDERING GUIDE Linearity Temperature Error DNL Package Model Range (LSBs) (LSBs) Option* AD7836AS –40°C to +85°C ±2 ±0.9 S-44 *S = Plastic Quad Flatpack (MQFP). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –4– AD7836 PIN DESCRIPTION Pin Mnemonic Description V Logic Power Supply; +5 V ± 5%. CC V Negative Analog Power Supply; –15 V ± 5%. SS V Positive Analog Power Supply; +15 V ± 5%. DD DGND Digital Ground. AGND Analog Ground. V (+)A, V (–)A Reference Inputs for DAC A. These reference voltages are referred to AGND. REF REF V (+)B, V (–)B Reference Inputs for DAC B. These reference voltages are referred to AGND. REF REF V (+)C, V (–)C Reference Inputs for DAC C. These reference voltages are referred to AGND. REF REF V (+)D, V (–)D Reference Inputs for DAC D. These reference voltages are referred to AGND. REF REF V A...V D DAC Outputs. OUT OUT CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low. DB0 . . . DB13 Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. A0, A1, A2 Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer. CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert back to their original outputs as determined by the data in their data registers. WR Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR. DUTGND A Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin. DUTGND B Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin. DUTGND C Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin. DUTGND D Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin. SEL Select pin, active high level triggered input. When the SEL input is high, the user programmed value in DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The con- tents of the other DATA REGs (A–D) will not be affected by the SEL pin. PIN CONFIGURATION 33 32 31 30 29 28 27 26 25 24 23 34 22 V C DB7 OUT V (–)C 35 21 DB6 REF 36 20 V (+)C DB5 REF AGND 37 19 DB4 38 18 NC DB3 AD7836 TOP VIEW 39 17 V DB2 DD (Not to Scale) 40 NC 16 DB1 41 15 V DB0 SS 14 V (+)A 42 DGND REF 43 13 V V (–)A REF PIN 1 CC IDENTIFIER 12 CLR V A 44 OUT 1 23 456789 1011 NC = NO CONNECT REV. A –5– DUTGND A DUTGND C V (+)B V (+)D REF REF V (–)B V (–)D REF REF V B V D OUT OUT DUTGND B DUTGND D A2 DB13 A1 DB12 A0 DB11 SEL DB10 CS DB9 WR DB8 AD7836 Full-Scale Error TERMINOLOGY This is the error in DAC output voltage when all 1s are loaded Relative Accuracy into the DAC latch. Ideally the output voltage, with all 1s Relative accuracy or endpoint linearity is a measure of the max- loaded into the DAC latch, should be 2 V (+) – 1 LSB. Full- imum deviation from a straight line passing through the endpoints REF scale error does not include zero-scale error. of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Zero-Scale Error Significant Bits or as a percentage of full-scale reading. Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally the output voltage, Differential Nonlinearity with all 0s in the DAC latch should be equal to 2 V (–). Zero- Differential nonlinearity is the difference between the measured REF scale error is mainly due to offsets in the output amplifier. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum Gain Error ensures monotonicity. Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error). DC Crosstalk GENERAL DESCRIPTION Although the common input reference voltage signals are inter- DAC Architecture—General nally buffered, small IR drops in the individual DAC reference Each channel consists of a segmented 14-bit R-2R voltage-mode inputs across the die can mean that an update to one channel DAC. The full-scale output voltage range is equal to twice the can produce a dc output change in one or other of the channel reference span of V (+) – V (–). The DAC coding is REF REF outputs. straight binary; all 0s produces an output of 2 V (–); all 1s REF produces an output of 2 V (+) – 1 LSB. The four DAC outputs are buffered by op amps that share com- REF mon V and V power supplies. If the dc load current changes DD SS The analog output voltage of each DAC channel reflects the in one channel (due to an update), this can result in a further dc contents of its own DAC latch. Data is transferred from the ex- change in one or other channel outputs. This effect is most ob- ternal bus to the input register of each DAC latch on a per vious at high load currents and reduces as the load currents are channel basis. The AD7836 has a feature whereby using the A2 reduced. With high impedance loads the effect is virtually pin, data can be transferred from the input data bus to all four unmeasurable. input registers simultaneously. Output Voltage Settling Time Bringing the CLR line low switches all the signal outputs, This is the amount of time it takes for the output to settle to a V A to V D, to the voltage level on the DUTGND pin. OUT OUT specified level for a full-scale input change. When CLR signal is brought back high the output voltages from the DACs will reflect the data stored in the relevant DAC Digital-to-Analog Glitch Impulse registers. This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in Data Loading to the AD7836 nV-secs. It is measured with V (+) = +5 V and V (–) = –5 V REF REF Data is loaded into the AD7836 in straight parallel 14-bit wide and the digital inputs toggled between 1FFFHEX and 8000H. words. Channel-to-Channel Isolation The DAC output voltages, V A–V D are updated to OUT OUT Channel-to-channel isolation refers to the proportion of input reflect new data in the DAC input registers. signal from one DACs reference input that appears at the output The actual DAC input register that is being written to is deter- of the other DAC. It is expressed in dBs. mined by the logic levels present on the devices address lines, as DAC-to-DAC Crosstalk shown in Table I. DAC-to-DAC crosstalk is defined as the glitch impulse that ap- pears at the output of one converter due to both the digital Table I. Address Line Truth Table change and subsequent analog O/P change at another converter. A2 A1 A0 DAC Selected It is specified in nV-s. Digital Crosstalk 0 0 0 DATA REG A (DAC A) The glitch impulse transferred to the output of one converter 0 0 1 DATA REG B (DAC B) due to a change in digital input code to the other converter is 0 1 0 DATA REG C (DAC C) defined as the digital crosstalk and is specified in nV-s. 0 1 1 DATA REG D (DAC D) 1 0 0 DATA REG E Digital Feedthrough 1 1 1 DATA REG A–D When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the V OUT pins. This noise is digital feedthrough. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. REV. A –6– Typical Performance Characteristics–AD7836 1.0 0.9 2 V = 15V DD 0.8 V = –15V SS 0.6 V (+) = +5V 0.6 REF 1 0.4 V (–) = –5V REF 0.4 0.2 0.2 0.0 0.0 0 –0.2 –0.2 –0.4 –0.4 –1 –0.6 –0.6 –0.8 –0.9 –1.0 –2 02 46 8 10 12 14 16 –40 –20 0 20 40 60 80 90 02 4 6 8 10 12 14 16 INPUT CODE/1000 TEMPERATURE – °C INPUT CODE/1000 Figure 4. Typical INL Error vs. Figure 2. Typical INL Plot Figure 3. Typical DNL Plot Temperature 6 1.0 2 DIGITAL INPUTS @ THRESHOLDS V = 15V DD V = 15V DD V = –15V 5 SS V = –15V SS V (+) = +5V REF V (+) = +5V REF 0.5 1 V (–) = –5V REF V (–) = –5V 4 REF V = 5V CC V = 15V DD FULL-SCALE ERROR 3 V = –15V SS 0 0 2 OFFSET ERROR 1 –0.5 –1 DIGITAL INPUTS @ SUPPLIES 0 –1 –1.0 –2 –40 –20 0 20406080 90 –40 –20 0 20 40 60 80 90 –40 –20 0 20 40 60 80 90 TEMPERATURE – °C TEMPERATURE – °C TEMPERATURE – °C Figure 7. I vs. Temperature Figure 5. Typical DNL Error vs. CC Figure 6. Offset and Full-Scale Error Temperature vs. Temperature 8 0.7 10.2 VERT = 100mV/DIV 0.6 HORIZ = 1�s/DIV 10.0 0.5 7 0.4 V = 15V DD 9.8 V = –15V SS 0.3 6 V (+) = +5V REF 0.2 V (–) = –5V REF 9.6 0.1 5 0 9.4 –0.1 4 –0.2 9.2 –40 –20 0 20 40 60 80 90 11 12 13 14 TEMPERATURE – °C SETTLING TIME – �s Figure 10. I /I vs. Temperature DD SS Figure 8. Typical Digital/Analog Figure 9. Settling Time (+) Glitch Impulse REV. A –7– DNL ERROR – LSB INL ERROR – LSBs DNL ERROR – LSBs V – V OUT ERROR – LSB I /I – mA I – mA INL ERROR – LSB DD SS CC AD7836 When bipolar-zero and full-scale adjustment are not needed, Unipolar Configuration R2 and R3 can be omitted. Pin 12 on the AD588 should be Figure 11 shows the AD7836 in the unipolar binary circuit con- connected to Pin 11 and Pin 5 should be left floating. figuration. The V (+) input of the DAC is driven by the REF AD586, a +5 V reference. V (–) is tied to ground. Table II REF +15V +5V gives the code table for unipolar operation of the AD7836. Other suitable references include the REF02, a precision 5 V R1 reference, and the REF195, a low dropout, micropower preci- 39k� sion +5 V reference. 4 6 V V 7 DD CC 2 V C1 V OUT OUT +15V +5V 3 1�F (–10V TO +10V) 9 V (+) REF 1 AD7836* AD588 5 14 R2 DUTGND 2 V V DD CC 100k� 10 15 6 AGND V (–) V REF V (+) V OUT REF OUT 16 11 8 DGND (0 TO +10V) V AD586 SS AD7836* 5 R1 12 8 13 10k� R3 DUTGND C1 SIGNAL 100k� 1nF 4 AGND GND –15V V (–) REF DGND *ADDITIONAL PINS OMITTED FOR CLARITY V SS SIGNAL SIGNAL Figure 12. Bipolar ±5 V Operation GND GND –15V Table III. Code Table for Bipolar Operation *ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. Unipolar +5 V Operation Binary Number in DAC Latch Analog Output Offset and gain may be adjusted in Figure 2 as follows: To ad- MSB LSB (V ) OUT just offset, disconnect the V (–) input from 0 V, load the DAC REF 11 1111 1111 1111 2[V (–) + V (16383/16384)] V REF REF with all 0s and adjust the V (–) voltage until V = 0 V. For REF OUT 10 0000 0000 0001 2[V (–) + V (8193/16384)] V REF REF gain adjustment, the AD7836 should be loaded with all 1s and 10 0000 0000 0000 2[V (–) + V (8192/16384)] V REF REF R1 adjusted until V = 10 V(16383/16384) = 9.999389. OUT 01 1111 1111 1111 2[V (–) + V (8191/16384)] V REF REF Many circuits will not require these offset and gain adjustments. In 00 0000 0000 0001 2[V (–) + V (1/16384)] V REF REF these circuits R1 can be omitted. Pin 5 of the AD586 may be left 00 0000 0000 0000 2[V (–)] V REF open circuit and Pin 2 (V (–)) of the AD7836 tied to 0 V. REF NOTE V = (V (+) – V (–)). REF REF REF Table II. Code Table for Unipolar Operation 14 For V (+) = +5 V, and V (–) = –5 V, V =10 V, 1 LSB = 2 VREF V/2 REF REF REF = 20 V/16384 = 1220 µV. Binary Number in DAC Latch Analog Output MSB LSB (V ) OUT CONTROLLED POWER-ON OF THE OUTPUT STAGE A block diagram of the output stage of the AD7836 is shown in 11 1111 1111 1111 2 V (16383/16384) V REF Figure 13. It is capable of driving a load of 5 kΩ in parallel 10 0000 0000 0000 2 V (8192/16384) V REF with 50 pF. G to G are transmission gates that are used to 1 6 01 1111 1111 1111 2 V (8191/16384) V REF control the power on voltage present at V . On power up G OUT 1 00 0000 0000 0001 2 V (1/16384) V REF and G are also used in conjunction with the CLR input to set 2 00 0000 0000 0000 0 V V to the user defined voltage present at the DUTGND pin. OUT NOTE When CLR is taken back high the DAC outputs reflect the data V = V (+); V (–) = 0 V for unipolar operation. REF REF REF 14 in the DAC registers. For V (+) = +5 V, 1 LSB = +10 V/2 = +10 V/16384 = 610 µV. REF Bipolar Configuration G 1 Figure 12 shows the AD7836 set up for ±10 V operation. The G 6 DAC AD588 provides precision ±5 V tracking outputs that are fed to V OUT the V (+) and V (–) inputs of the AD7836. The code table G REF REF 3 for bipolar operation of the AD7836 is shown in Table III. G G 2 4 In Figure 12, full-scale and bipolar zero adjustments are pro- R = 13.5k� vided by varying the gain and balance on the AD588. R2 varies R G the gain on the AD588 while R3 adjusts the offset of both the 5 6k� +5 V and –5 V outputs together with respect to ground. DUTGND For bipolar-zero adjustment, the DAC is loaded with 1000 . . . 0000 and R3 is adjusted until V = 0 V. Full scale OUT Figure 13. Block Diagram of AD7836 Output Stage is adjusted by loading the DAC with all 1s and adjusting R2 un- til V = 10(8191/8192) V = 9.998779 V. OUT REV. A –8– AD7836 Power-On with CLR Low G 1 G 6 DAC The output stage of the AD7836 has been designed to allow V OUT output stability during power-on. If CLR is kept low during G 3 power-on, then just after power is applied to the AD7836, the situation is as depicted in Figure 14. G , G and G are open 1 4 6 G G 2 4 while G , G and G are closed. 2 3 5 R R G 1 G 5 6k� G 6 DAC V OUT DUTGND G 3 Figure 16. Output Stage After CLR Is Taken High G G 2 4 R Power-On with CLR High If CLR is high on the application of power to the device, the R G 5 6k� output stages of the AD7836 are configured as in Figure 17 while V /V are less than ±10 V. G is closed and G is open DD SS 1 2 DUTGND thereby connecting the output of the DAC to the input of its output amplifier. G and G are closed while G and G are 3 5 4 6 Figure 14. Output Stage with V < 10 V DD open thus connecting the output amplifier as a unity gain V is kept within a few hundred millivolts of DUTGND via OUT buffer. V is connected to DUTGND via G through a 6 kΩ OUT 5 G and a 6kΩ resistor. This thin-film resistor is connected in 5 resistor until V and V reach approximately ±10 V. DD SS parallel with the gain resistors of the output amplifier. The out- put amplifier is connected as a unity gain buffer via G , and the G 3 1 G 6 DAC DUTGND voltage is applied to the buffer input via G . The 2 V OUT amplifier’s output is thus at the same voltage as the DUTGND G 3 pin. The output stage remains configured as in Figure 14 until the voltage at V and V reaches approximately ±10 V. By DD SS G G 2 4 now the output amplifier has enough headroom to handle sig- R nals at its input and has also had time to settle. The internal R G power-on circuitry opens G and G and closes G and G . This 5 3 5 4 6 6k� situation is shown in Figure 15. Now the output amplifier is configured in its noise gain configuration via G and G . The 4 6 DUTGND DUTGND voltage is still connected to the noninverting input Figure 17. Output Stage Powering Up with CLR High via G2 and this voltage appears at V . OUT While V /V < ±10 V DD SS G 1 When the supplies reach ±10 V, the internal power on circuitry G 6 DAC opens G and G and closes G and G configuring the output 3 5 4 6 V OUT stage as shown in Figure 18. G 3 G 1 G G G 2 4 6 DAC R V OUT R G G 3 5 6k� G G 2 4 R DUTGND Figure 15. Output Stage with V > 10 V and CLR Low DD R G 5 6k� V has been disconnected from the DUTGND pin by the OUT opening of G but will track the voltage present at DUTGND 5 DUTGND via the configuration shown in Figure 15. Figure 18. Output Stage Powering Up with CLR High When CLR is taken back high, the output stage is configured as When V /V > ±10 V DD SS shown in Figure 16. The internal control logic closes G and 1 opens G . The output amplifier is connected in a noninverting 2 gain of two configuration. The voltage that appears on the Vout pins is determined by the data present in the DAC registers. To set all output voltages to the same known state, a write to DATA REG E with the SEL pin high allows all DAC registers to be updated with the same data. REV. A –9– AD7836 DUTGND Voltage Range APPLICATIONS During power-on, the V pins of the AD7836 are connected OUT Power Supply Bypassing and Grounding to the relevant DUTGND pins via G and the 6 kΩ thin-film 6 In any circuit where accuracy is important, careful consider- resistor. The DUTGND potential must obey the max ratings at ation of the power supply and ground return layout helps to all times. Thus, the voltage at DUTGND must always be ensure the rated performance. The printed circuit board on within the range V – 0.3 V, V + 0.3 V. However, in order SS DD which the AD7836 is mounted should be designed such that that the voltages at the V pins of the AD7836 stay within OUT the analog and digital sections are separated and confined to ±2 V of the relevant DUTGND potential during power-on, the certain areas of the board. This facilitates the use of ground voltage applied to DUTGND should also be kept within the planes that can be separated easily. A minimum etch tech- range AGND – 2 V, AGND + 2 V. nique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be Once the AD7836 has powered on and the on-chip amplifiers joined at one place. If the AD7836 is the only device requiring have settled, any voltage that is now applied to the DUTGND an AGND to DGND connection, then the ground planes pin is subtracted from the DAC output which has been gained should be connected at the AGND and DGND pins of the up by a factor of two. Thus, for specified operation, the maxi- AD7836. If the AD7836 is in a system where multiple devices mum voltage that can be applied to the DUTGND pin increases require an AGND to DGND connection, the connection to the maximum allowable 2 × V (+) voltage, and the mini- REF should still be made at one point only, a star ground point mum voltage that can be applied to DUTGND is the minimum which should be established as close as possible to the 2 × V (–) voltage. After the AD7836 has fully powered on, REF AD7836. the outputs can track any DUTGND voltage within this minimum/maximum range. Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane MICROPROCESSOR INTERFACING should be allowed to run under the AD7836 to avoid noise Interfacing the AD7836—16-Bit Interface coupling. The power supply lines of the AD7836 should use The AD7836 can be interfaced to a variety of 16-bit micro- as large a trace as possible to provide low impedance paths and controllers or DSP processors. Figure 19 shows the AD7836 reduce the effects of glitches on the power supply line. Fast interfaced to a generic 16-bit microcontroller/DSP processor. switching signals like clocks should be shielded with digital The lower address lines from the processor are connected to ground to avoid radiating noise to other parts of the board and A0, A1 and A2 on the AD7836 as shown. The upper address should never be run near the analog inputs. lines are decoded to provide a chip select signal for the AD7836. They are also decoded (in conjunction with the lower Avoid crossover of digital and analog signals. Traces on oppo- address lines if need be) to provide a SEL signal. The fast inter- site sides of the board should run at right angles to each other. face timing of the AD7836 allows direct interface to a wide vari- This reduces the effects of feedthrough through the board. A ety of microcontrollers and DSPs as shown in Figure 19. microstrip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal �CONTROLLER/ * AD7836 DSP traces are placed on the solder side. PROCESSOR* The AD7836 should have ample supply bypassing located as D13 D13 • DATA • • close to the package as possible, ideally right up against the • BUS • • device. Figure 20 shows the recommended capacitor values of D0 D0 10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF UPPER BITS OF ADDRESS CS capacitors are the tantalum bead type. The 0.1 µF capacitor ADDRESS BUS DECODE should have low Effective Series Resistance (ESR) and Effec- tive Series Inductance (ESI), such as the common ceramic A2 A2 types, which provide a low impedance path to ground at high A1 A1 A0 A0 frequencies to handle transient currents due to internal logic R/W WR switching. *ADDITIONAL PINS OMITTED FOR CLARITY V V Figure 19. AD7836 Parallel Interface CC DD 0.1�F 10�F 10�F 0.1�F AD7836 V SS 10�F 0.1�F Figure 20. Recommended Decoupling Scheme for AD7836 REV. A –10– AD7836 Automated Test Equipment Programmable Reference Generation for the AD7836 in an The AD7836 is particularly suited for use in an automated test ATE Application environment. Figure 21 shows the AD7836 providing the nec- The AD7836 is particularly suited for use in an automated test essary voltages for the pin driver and the window comparator in environment. The reference input for the AD7836 quad 14-bit a typical ATE pin electronics configuration. AD588s are used DAC requires two references for each DAC. Programmable to provide reference voltages for the AD7836. In the configu- references may be a requirement in some ATE applications as ration shown, the AD588s are configured so that the voltage at the offset and gain errors at the output of each DAC can be ad- Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at justed by varying the voltages on the reference pins of the DAC. Pin 15 is 5 V less than the voltage at Pin 9. To trim offset errors, the DAC is loaded with the digital code 000 . . . 000 and the voltage on the V (–) pin is adjusted until REF +15V –15V V OFFSET the desired negative output voltage is obtained. To trim out 2 16 gain errors, first the offset error is trimmed. Then the DAC is 4 3 +15V loaded with the code 111 . . . 111 and the voltage on the 6 1 V (+)A/B REF V (+) pin is adjusted until the desired full scale voltage REF 8 V A OUT 15 AD588 PIN 13 V (–)A/B minus one LSB is obtained. REF 14 DRIVER 7 V B It is not uncommon in ATE design, to have other circuitry at OUT 9 1�F DUTGND A/B the output of the AD7836 that can have offset and gain errors 0.1�F –15V AD7836* of up to say ±300 mV. These offset and gain errors can be eas- 10 11 12 ily removed by adjusting the reference voltages of the AD7836. DUTGND C/D V +15V –15V OUT DEVICE The AD7836 uses nominal reference values of ±5 V to achieve GND 2 16 an output span of ±10 V. Since the AD7836 has a gain of two V C 4 OUT 3 from the reference inputs to the DAC output, adjusting the ref- 6 1 DEVICE V (+)C/D REF 8 GND erence voltages by ±150 mV will adjust the DAC offset and V D OUT 15 13 V (–)C/D AD588 REF gain by ±300 mV. 14 10 11 There are a number of suitable 8- and 10-bit DACs available AGND 12 that would be suitable to drive the reference inputs of the 7 WINDOW 8 AD7836, such as the AD7804 which is a quad 10-bit digital-to- 1�F DEVICE COMPARATOR GND TO TESTER analog converter with serial load capabilities. The voltage out- put from this DAC is in the form of V ± V and rail to BIAS SWING *ADDITIONAL PINS OMITTED FOR CLARITY rail operation is achievable. The voltage reference for this DAC Figure 21. ATE Application can be internally generated or provided externally. This DAC One of the AD588s is used as a reference for DACs 1 and 2. also contains an 8-bit SUB DAC which can be used to shift the These DACs are used to provide high and low levels for the pin complete transfer function of each DAC around the V BIAS driver. The pin driver may have an associated offset. This can point. This can be used as a fine trim on the output voltage. In be nulled by applying an offset voltage to Pin 9 of the AD588. this Application two AD7804s are required to provide program- First, the code 1000 . . . 0000 is loaded into the DACA latch mable reference capability for all four DACs. One AD7804 is and the pin driver output is set to the DACA output. The used to drive the V (+) pins and the second package used to REF V voltage is adjusted until 0 V appears between the pin OFFSET drive the V (–) pins. REF driver output and DUT GND. This causes both V (+) and REF Another suitable DAC for providing programmable reference V (–) to be offset with respect to AGND by an amount equal REF ® capability is the AD8803. This is an octal 8-bit trimDAC and to V . However, the output of the pin driver will vary OFFSET provides independent control of both the top and bottom ends from –10 V to +10 V with respect to DUT GND as the DAC of the trimDAC. This is helpful in maximizing the resolution of input code varies from 000 . . . 000 to 111 . . . 111. The devices with a limited allowable voltage control range. V voltage is also applied to the DUTGND pins. When a OFFSET The AD8803 has an output voltage range of GND to V (0 V to DD clear is performed on the AD7836, the output of the pin driver +5 V). To trim the V (+) input, the appropriate trim range REF will be 0 V with respect to Device GND. on the AD8803 DAC can be set using the V and V REFL REFH The other AD588 is used to provide a reference voltage for pins allowing 8 bits of resolution between the two points. This DACs C and D. These provide the reference voltages for the will allow the V (+) pin to be adjusted to remove gain errors. REF window comparator shown in the diagram. Note that Pin 9 of To trim the V (–) voltage, some method of providing a trim REF this AD588 is connected to Device GND. This causes voltage in the required negative voltage range is required. Nei- V (+)C & D and V (–)C & D to be referenced to Device REF REF ther the AD7804 or the AD8803 can provide this range in nor- GND. As DAC 3 and DAC 4 input codes vary from mal operation as their output range is 0 V to +5 V. There are 000 . . . 000 to 111 . . . 111, V 3 and V 4 vary from –10 V OUT OUT two methods of producing this negative voltage. One method is to +10 V with respect to Device GND. Device GND is also to provide a positive output voltage and then to level shift that connected to DUTGND. When the AD7836 is cleared, analog voltage to the required negative range. Alternatively V C and V D are cleared to 0 V with respect to DEVICE OUT OUT GND. TrimDAC is a registered trademark of Analog Devices, Inc. REV. A –11– AD7836 the digital signals driving the DACs need to be level shifted these DACs can be operated with supplies of 0 V and a –5 V, from the 0 V to +5 V range to the –5 V to 0 V range. Figure 22 with the V pin connected to 0 V and the GND pin connected DD shows a typical application circuit to provide programmable ref- to –5 V. Now these can be used to provide the negative refer- erence capabilities for the AD7836. ence voltages for the V (–) inputs on the AD7836. However, REF ADDR BUS +5V ADDR DECODER 8/10-BIT V DD DAC FSIN/CS A0,A1,A2 DIN 0V to 5V V (+)A SDATA REF V V A OUT OUT SCLK SCLK GND LOGIC LEVEL AD7836* SHIFT CONTROLLER 8/10-BIT V DD DAC FSIN/CS 0V to -5V DIN V (–) A REF SCLK GND –5V DATA BUS DATA BUS AGND *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Programmable Reference Generation for the AD7836 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead MQFP (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8� 0.025 (0.64) 33 23 0.8� 34 22 SEATING PLANE TOP VIEW (PINS DOWN) 44 12 1 11 0.040 (1.02) 0.040 (1.02) 0.032 (0.81) 0.032 (0.81) 0.033 (0.84) 0.016 (0.41) 0.083 (2.11) 0.029 (0.74) 0.012 (0.30) 0.077 (1.96) REV. A –12– PRINTED IN U.S.A. C2163a–0–9/99