ANALOG DEVICES AD7834

2 LC MOS Quad 14-Bit DACs AD7834/AD7835 into one via DIN, SCLK, and FSYNC. The AD7834 has five FEATURES dedicated package address pins, PA0 to PA4, that can be wired Four 14-bit DACs in one package to AGND or V to permit up to 32 AD7834s to be individually CC AD7834—serial loading addressed in a multipackage application. AD7835—parallel 8-bit/14-bit loading Voltage outputs The AD7835 can accept either 14-bit parallel loading or double- Power-on reset function byte loading, where right-justified data is loaded in one 8-bit Maximum/minimum output voltage range of ±8.192 V byte and one 6-bit byte. Data is loaded from the external bus Maximum output voltage span of 14 V into one of the input latches under the control of the WR, CS, Common voltage reference inputs BYSHF, and DAC channel address pins, A0 to A2. User-assigned device addressing With each device, the LDAC signal is used to update all four Clear function to user-defined voltage DAC outputs simultaneously, or individually, on reception of Surface-mount packages CLR new data. In addition, for each device, the asynchronous AD7834—28-lead SOIC and PDIP input can be used to set all signal outputs, V 1 to V 4, to OUT OUT AD7835—44-lead MQFP and PLCC the user-defined voltage level on the device sense ground pin, APPLICATIONS DSG. On power-on, before the power supplies have stabilized, Process control internal circuitry holds the DAC output voltage levels to within Automatic test equipment ±2 V of the DSG potential. As the supplies stabilize, the DAC General-purpose instrumentation output levels move to the exact DSG potential (assuming CLR is exercised). GENERAL DESCRIPTION The AD7834 is available in a 28-lead 0.3" SOIC package and a The AD7834 and AD7835 contain four 14-bit DACs on one 28-lead 0.6" PDIP package, and the AD7835 is available in a monolithic chip. The AD7834 and AD7835 have output 44-lead MQFP package and a 44-lead PLCC package. voltages in the range ±8.192 V with a maximum span of 14 V. The AD7834 is a serial input device. Data is loaded in 16-bit format from the external serial bus, MSB first after two leading 0s, FUNCTIONAL BLOCK DIAGRAMS V V (–)A V V V V (–) V (+) V V V (+)A CC DD SS REF REF CC DD SS REF REF DSGA AD7835 INPUT AD7834 INPUT DAC 1 DAC 1 DAC 1 REGISTER DAC 1 REGISTER LATCH LATCH BYSHF 1 PAEN 1 ×1 V 1 ×1 V 1 OUT OUT 14 DB13 INPUT PA0 INPUT INPUT DAC 2 BUFFER DAC 2 DB0 REGISTER DAC 2 REGISTER DAC 2 LATCH PA1 CONTROL LATCH 2 2 ×1 LOGIC V 2 OUT ×1 V 2 OUT WR PA2 AND ADDRESS PA3 DECODE INPUT CS DAC 3 INPUT DAC 3 DAC 3 REGISTER PA4 LATCH REGISTER DAC 3 LATCH 3 3 ×1 V 3 OUT ×1 V 3 OUT A0 FSYNC INPUT ADDRESS DAC 4 INPUT A1 REGISTER DAC 4 DAC 4 DECODE LATCH SERIAL-TO- REGISTER DAC 4 4 LATCH ×1 DIN 4 V 4 PARALLEL A2 OUT ×1 V 4 OUT CONVERTER CLR SCLK CLR AGND DGND V (+)B DSGB AGND DGND LDAC DSG LDAC V (–)B REF REF Figure 1. AD7834 Figure 2. AD7835 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01006-001 01006-002 AD7834/AD7835 TABLE OF CONTENTS Power-On with CLR Low, LDAC High ................................... 17 Features .............................................................................................. 1 Power-On with LDAC Low, CLR High ................................... 17 Applications....................................................................................... 1 Loading the DAC and Using the CLR Input .......................... 17 General Description ......................................................................... 1 DSG Voltage Range.................................................................... 18 Functional Block Diagrams............................................................. 1 Power-On of the AD7834/AD7835.............................................. 19 Revision History ............................................................................... 2 Microprocessor Interfacing........................................................... 20 Specifications..................................................................................... 3 AD7834 to 80C51 Interface ...................................................... 20 AC Performance Characteristics ................................................ 5 AD7834 to 68HC11 Interface ................................................... 20 Timing Specifications .................................................................. 6 AD7834 to ADSP-2101 Interface ............................................. 20 Absolute Maximum Ratings............................................................ 7 AD7834 to DSP56000/DSP56001 Interface............................ 21 Thermal Resistance ...................................................................... 7 AD7834 to TMS32020/TMS320C25 Interface....................... 21 ESD Caution.................................................................................. 7 Interfacing the AD7835—16-Bit Interface.............................. 21 Pin Configurations and Function Descriptions ........................... 8 Interfacing the AD7835—8-Bit Interface................................ 22 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 23 Terminology .................................................................................... 13 Serial Interface to Multiple AD7834s ...................................... 23 Theory of Operation ...................................................................... 14 Opto-Isolated Interface ............................................................. 23 DAC Architecture....................................................................... 14 Automated Test Equipment ...................................................... 23 Data Loading—AD7834 Serial Input Device ......................... 14 Power Supply Bypassing and Grounding................................ 24 Data Loading—AD7835 Parallel Loading Device ................. 14 Outline Dimensions....................................................................... 25 Unipolar Configuration............................................................. 15 Ordering Guide .......................................................................... 27 Bipolar Configuration................................................................ 16 Controlled Power-On of the Output Stage.................................. 17 REVISION HISTORY 8/07—Rev. C to Rev. D Changes to Table 5 ........................................................................... 7 Added Table 6.................................................................................... 7 Changes to Table 8............................................................................ 9 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 27 7/05—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Figure 40...................................................................... 25 Changes to Ordering Guide .......................................................... 27 7/03—Rev. A to Rev. B Revision 0: Initial Version Rev. D | Page 2 of 28 AD7834/AD7835 SPECIFICATIONS 1 VCC = 5 V ± 5%; VDD = 15 V ± 5%; VSS = −15 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter A B S Unit Test Conditions/Comments ACCURACY Resolution 14 14 14 Bits Relative Accuracy ±2 ±1 ±2 LSB max Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed monotonic over temperature. Full-Scale Error VREF(+) = +7 V, VREF(−) = −7 V. T to T ±5 ±5 ±8 mV max MIN MAX Zero-Scale Error ±4 ±4 ±5 mV max V (+) = +7 V, V (−) = −7 V. REF REF Gain Error ±0.5 ±0.5 ±0.5 mV typ V (+) = +7 V, V (−) = −7 V. REF REF Gain Temperature 4 4 4 ppm FSR/°C typ 2 Coefficient 20 20 20 ppm FSR/°C max 2 DC Crosstalk 50 50 50 μV max See the Terminology section. R = 10 kΩ. L REFERENCE INPUTS DC Input Resistance 30 30 30 MΩ typ Input Current ±1 ±1 ±1 μA max Per input. V (+) Range 0/8.192 0/8.192 0/8.192 V min/max REF VREF(−) Range −8.192/0 −8.192/0 −8.192/0 V min/max VREF(+) − VREF(−) 5/14 7/14 5/14 V min/max For specified performance. Can go as low as 0 V, but performance is not guaranteed. DEVICE SENSE GROUND INPUTS Input Current ±2 ±2 ±2 μA max Per input. V = −2 V to +2 V. DSG DIGITAL INPUTS VINH, Input High Voltage 2.4 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 0.8 V max I , Input Current ±10 ±10 ±10 μA max INH C , Input Capacitance 10 10 10 pF max IN POWER REQUIREMENTS VCC 5.0 5.0 5.0 V nom ±5% for specified performance. VDD 15.0 15.0 15.0 V nom ±5% for specified performance. VSS −15.0 −15.0 −15.0 V nom ±5% for specified performance. Power Supply Sensitivity ΔFull Scale/ΔV 110 110 110 dB typ DD ΔFull Scale/ΔV 100 100 100 dB typ SS ICC 0.2 0.2 0.5 mA max VINH = VCC, VINL = DGND. 3 3 3 mA max AD7834: VINH = 2.4 V min, VINL = 0.8 V max. 6 6 6 mA max AD7835: VINH = 2.4 V min, VINL = 0.8 V max. I 13 13 15 mA max AD7834: outputs unloaded. DD 15 15 15 mA max AD7835: outputs unloaded. I 13 13 15 mA max Outputs unloaded. SS 1 Temperature range for A, B, and C versions is −40°C to +85°C. 2 Guaranteed by design. Rev. D | Page 3 of 28 AD7834/AD7835 1 V = 5 V ± 5%; V = 12 V ± 5%; V = −12 V ± 5%; AGND = DGND = 0 V; T = T to T , unless otherwise noted. CC DD SS A MIN MAX Table 2. Parameter A B S Unit Test Conditions/Comments ACCURACY Resolution 14 14 14 Bits Relative Accuracy ±2 ±1 ±2 LSB max Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed monotonic over temperature. Full-Scale Error VREF(+) = +5 V, VREF(−) = –5 V. TMIN to TMAX ±5 ±5 ±8 mV max Zero-Scale Error ±4 ±4 ±5 mV max VREF(+) = +5 V, VREF(−) = −5 V. Gain Error ±0.5 ±0.5 ±0.5 mV typ V (+) = +5 V, V (−) = −5 V. REF REF 2 Gain Temperature Coefficient 4 4 4 ppm FSR/°C typ 20 20 20 ppm FSR/°C max 2 DC Crosstalk 50 50 50 μV max See the Terminology section. RL = 10 kΩ. REFERENCE INPUTS DC Input Resistance 30 30 30 MΩ typ Input Current ±1 ±1 ±1 μA max Per input. VREF(+) Range 0/8.192 0/8.192 0/8.192 V min/max V (−) Range −5/0 −5/0 −5/0 V min/max REF V (+) − V (−) 5/13.192 7/13.192 5/13.192 V min/max For specified performance. Can go as low as REF REF 0 V, but performance is not guaranteed. DEVICE SENSE GROUND INPUTS Input Current ±2 ±2 ±2 μA max Per input. VDSG = −2 V to +2 V. DIGITAL INPUTS V , Input High Voltage 2.4 2.4 2.4 V min INH VINL, Input Low Voltage 0.8 0.8 0.8 V max IINH, Input Current ±10 ±10 ±10 μA max CIN, Input Capacitance 10 10 10 pF max POWER REQUIREMENTS VCC 5.0 5.0 5.0 V nom ±5% for specified performance. V 15.0 15.0 15.0 V nom ±5% for specified performance. DD V −15.0 −15.0 −15.0 V nom ±5% for specified performance. SS Power Supply Sensitivity ΔFull Scale/ΔVDD 110 110 110 dB typ ΔFull Scale/ΔVSS 100 100 100 dB typ ICC 0.2 0.2 0.5 mA max VINH = VCC, VINL = DGND. 3 3 3 mA max AD7834: V = 2.4 V min, V = 0.8 V max. INH INL 6 6 6 mA max AD7835: V = 2.4 V min, V = 0.8 V max. INH INL IDD 13 13 15 mA max AD7834: outputs unloaded. 15 15 15 mA max AD7835: outputs unloaded. ISS 13 13 15 mA max Outputs unloaded. 1 Temperature range for A, B, and C versions is −40°C to +85°C. 2 Guaranteed by design. Rev. D | Page 4 of 28 AD7834/AD7835 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are not subject to production testing. Table 3. Parameter A B S Unit (typ) Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 10 10 μs Full-scale change to ±1/2 LSB. DAC latch contents alternately loaded with all 0s and all 1s. Digital-to-Analog Glitch Impulse 120 120 120 nV-s Measured with V (+) = V (−) = 0 V. DAC latch REF REF alternately loaded with all 0s and all 1s. DC Output Impedance 0.5 0.5 0.5 Ω See the Terminology section. Channel-to-Channel Isolation 100 100 100 dB See the Terminology section; applies to the AD7835 only. DAC-to-DAC Crosstalk 25 25 25 nV-s See the Terminology section. Digital Crosstalk 3 3 3 nV-s Feedthrough to DAC output under test due to change in digital input code to another converter. Digital Feedthrough—AD7834 0.2 0.2 0.2 nV-s Effect of input bus activity on DAC output under test. Digital Feedthrough—AD7835 1.0 1.0 1.0 nV-s Output Noise Spectral Density at 1 kHz 40 40 40 nV/√Hz All 1s loaded to DAC. VREF(+) = VREF(−) = 0 V. Rev. D | Page 5 of 28 AD7834/AD7835 TIMING SPECIFICATIONS 1 VCC = 5 V ± 5%; VDD = 11.4 V to 15.75 V; VSS = −11.4 V to −15.75 V; AGND = DGND = 0 V . Table 4. Parameter Limit at TMIN, TMAX Unit Description AD7834-SPECIFIC 2 t 100 ns min SCLK cycle time 1 2 t2 50 ns min SCLK low 2 t3 30 ns min SCLK high time t4 30 ns min FSYNC, PAEN setup time t 40 ns min FSYNC, PAEN hold time 5 t 30 ns min Data setup time 6 t7 10 ns min Data hold time t8 0 ns min LDAC to FSYNC setup time t9 40 ns min LDAC to FSYNC hold time t 20 ns min Delay between write operations 21 AD7835-SPECIFIC t11 15 ns min A0, A1, A2, BYSHF to CS setup time t 15 ns min A0, A1, A2, BYSHF to CS hold time 12 t 0 ns min CS to WR setup time 13 t 0 ns min 14 CS to WR hold time t15 40 ns min WR pulse width t16 40 ns min Data setup time t17 10 ns min Data hold time t 0 ns min LDAC to CS setup time 18 t 0 ns min CS to LDAC setup time 19 t20 0 ns min LDAC to CS hold time GENERAL t 40 ns min LDAC, CLR pulse width 10 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and time from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. 1ST 2ND 24TH t 1 A0 A1 A2 CLK CLK CLK BYSHF SCLK t t 11 12 t t t t 5 4 2 3 CS FSYNC t 21 t t t 6 13 14 t 15 t 7 MSB LSB WR DIN D23 D22 D1 D0 t 10 t t 16 17 LDAC (SIMULTANEOUS UPDATE) DB0 TO DB13 t 8 t LDAC 9 t (PER-CHANNEL 10 LDAC UPDATE) (SIMULTANEOUS t UPDATE) 19 t 18 t 20 LDAC (PER-CHANNEL UPDATE) Figure 3. AD7834 Timing Diagram Figure 4. AD7835 Timing Diagram Rev. D | Page 6 of 28 01006-003 01006-004 AD7834/AD7835 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen during power supply sequencing, the diode protection scheme shown in Figure 5 can be used to provide protection. V V DD CC Table 5. IN4148 Parameter Rating SD103C V to DGND −0.3 V to +7 V, or V + 0.3 V CC DD V V DD CC (whichever is lower) AD7834/ VDD to AGND −0.3 V to +17 V AD7835 V to AGND +0.3 V to –17 V SS Figure 5. Diode Protection AGND to DGND −0.3 V to +0.3 V Digital Inputs to DGND −0.3 V to V + 0.3 V CC THERMAL RESISTANCE VREF(+) to VREF(–) −0.3 V to +18 V θ is specified for the worst-case conditions, that is, a device JA VREF(+) to AGND VSS – 0.3 V to VDD + 0.3 V soldered in a circuit board for surface-mount packages. VREF(–) to AGND VSS – 0.3 V to VDD + 0.3 V DSG to AGND V – 0.3 V to V + 0.3 V SS DD Table 6. Thermal Resistance V (1–4) to AGND V – 0.3 V to V + 0.3 V OUT SS DD Package Type θ Unit JA Operating Temperature Range, T A PDIP 75 °C/W Industrial (A Version) −40°C to +85°C SOIC 75 °C/W Storage Temperature Range −65°C to +150°C MQFP 95 °C/W Junction Temperature, T (max) 150°C J PLCC 55 °C/W Power Dissipation, P (max) (T − T )/θ D J A JA Lead Temperature JEDEC Industry Standard ESD CAUTION Soldering J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 7 of 28 01006-005 AD7834/AD7835 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 28 AGND SS DSG 2 27 NC V (–) REF 3 26 NC V (+) 4 25 NC REF NC 5 24 NC AD7834 V 2 6 23 OUT V TOP VIEW DD (Not to Scale) V 4 7 22 V 1 OUT OUT DGND 8 21 V 3 OUT V 9 20 CLR CC SCLK 10 19 LDAC DIN 11 18 FSYNC PA0 12 17 PAEN PA1 13 16 PA4 PA2 14 15 PA3 NC = NO CONNECT Figure 6. AD7834 PDIP and SOIC Pin Configuration Table 7. AD7834 Pin Function Descriptions Pin No. Pin Mnemonic Description 1 V Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%. SS 2 DSG Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin. 3 VREF(−) Negative Reference Input. The negative reference voltage is referred to AGND. 4 V (+) Positive Reference Input. The positive reference voltage is referred to AGND. REF 5, 24, 25, 26, 27 NC No Connect. 22, 6, 21, 7 V 1 to V 4 DAC Outputs. OUT OUT 8 DGND Digital Ground. 9 VCC Logic Power Supply: 5 V ± 5%. 10 SCLK Clock Input. Used for writing data to the device; data is clocked into the input register on the falling edge of SCLK. 11 DIN Serial Data Input. 12,13,14,15,16 PA0 to PA4 Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated package addresses in a multipackage environment. 17 PAEN Package Address Enable Input. When low, this input allows normal operation of the device. When high, the device ignores the package address, but not the channel address, in the serial data stream and loads the serial data into the input registers. This feature is useful in a multipackage application where it can be used to load the same data into the same channel in each package. 18 FSYNC Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input register are transferred on the rising edge of this signal. 19 LDAC Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal, determines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four input registers are transferred into their respective DAC latches, updating all of the analog outputs simultaneously. 20 CLR Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs remain switched to the potential on the DSG pin. 23 V Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%. DD 28 AGND Analog Ground. Rev. D | Page 8 of 28 01006-006 AD7834/AD7835 44 43 42 41 40 39 38 37 36 35 34 64 5 4 324 14 4324140 PIN 1 NC NC 7 39 NC 1 33 NC IDENTIFIER PIN 1 DSGA 8 DSGA IDENTIFIER 32 38 DSGB 2 DSGB V 1 V 1 9 37 V 3 3 31 V 3 OUT OUT OUT OUT V 2 10 V 2 36 V 4 OUT 4 30 V 4 OUT OUT OUT NC NC 11 35 DB13 5 29 DB13 AD7835 AD7835 A2 12 34 A2 TOP VIEW DB12 6 TOP VIEW 28 DB12 (Not to Scale) (Not to Scale) 13 33 A1 27 A1 DB11 7 DB11 32 DB10 26 DB10 A0 14 A0 8 CLR 15 31 DB9 CLR 25 DB9 9 LDAC 30 DB8 LDAC 10 24 DB8 16 BYSHF 17 29 DB7 BYSHF 11 23 DB7 19 26 12 13 14 15 16 17 18 19 21 22 18 20 21 22 23 24 25 27 28 20 NC = NO CONNECT NC = NO CONNECT Figure 7. AD7835 MQFP Pin Configuration Figure 8. AD7835 PLCC Pin Configuration Table 8. AD7835 Pin Function Descriptions Pin No. MQFP Pin No. PLCC Pin Mnemonic Description 1, 5, 33, 34, 3, 6, 7, 11, 39, NC No Connect. 37, 41, 44 40, 43 2 8 DSGA Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, DAC outputs V 1 and V 2 are forced to the OUT OUT potential on the DSGA pin. 3, 4, 31, 30 9, 10, 37, 36 V 1 to V 4 DAC Outputs. OUT OUT 8, 7, 6 14, 13, 12 A0, A1, A2 Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is used to select all four DACs simultaneously. 9 15 CLR Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog outputs are switched to the externally set potentials on the DSG pins (V 1 OUT and V 2 follow DSGA, and V 3 and V 4 follow DSGB). When CLR is brought high, the OUT OUT OUT signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs remain switched to the potential on the DSG pins. 10 16 LDAC Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS input signals, determines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs simultaneously. Alternatively, if LDAC is brought low while new data is being entered, the addressed DAC latch and corresponding analog output are updated immediately on the rising edge of WR. 11 17 BYSHF Byte Shift Input. When low, it shifts the data on DB0 to DB7 into the DB8 to DB13 half of the input register. 12 18 CS Level-Triggered Chip Select Input (Active Low). The device is selected when this input is low. 13 19 WR Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS to write data over the input databus. 14 20 VCC Logic Power Supply: 5 V ± 5%. 15 21 DGND Digital Ground. Rev. D | Page 9 of 28 CS NC WR V (–)A REF V (+)A V CC REF DGND NC DB0 V SS V DB1 DD AGND DB2 NC DB3 DB4 V (+)B REF V (–)B DB5 REF DB6 NC 01006-007 CS NC V WR (–)A REF V CC V (+)A REF DGND NC DB0 V SS DB1 V DD DB2 AGND NC DB3 V (+)B DB4 REF DB5 V (–)B REF DB6 NC 01006-008 AD7834/AD7835 Pin No. MQFP Pin No. PLCC Pin Mnemonic Description 16 to 29 22 to 35 DB0 to DB13 Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the bottom eight data inputs, DB0 to DB7, are used for data loading, and the top six data inputs, DB8 to DB13, should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data are being loaded into the device. 32 38 DSGB Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, DAC outputs V 3 and V 4 are forced to the OUT OUT potential on the DSGB pin. 36, 35 42, 41 VREF(+)B, VREF(−)B Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND. 38 44 AGND Analog Ground. 39 1 VDD Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%. 40 2 V Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%. SS 42, 43 4, 5 V (+)A, V (−)A Reference Inputs for DAC 1 and DAC 2. These reference voltages are referred to AGND. REF REF Rev. D | Page 10 of 28 AD7834/AD7835 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.50 0.8 0.45 DAC 1 0.6 0.40 0.4 0.35 DAC 3 DAC 4 0.2 0.30 0 0.25 DAC 2 –0.2 0.20 0.15 –0.4 –0.6 0.10 –0.8 0.05 TEMP = 25°C ALL DACs FROM 1 DEVICE 0 –1.0 01 2 4 6 8 10 12 146 0 2.5 5.0 8.0 CODE/1000 V (+) (V) REF Figure 9. Typical INL Plot Figure 12. Typical INL vs. V (+), V (+) – V (−) = 5 V REF REF REF 0.5 0.8 ALL DACs FROM ONE DEVICE 0.4 0.7 0.3 0.6 DAC 1 0.2 DAC 3 0.5 0.1 DAC 4 0 0.4 –0.1 DAC 2 0.3 –0.2 0.2 –0.3 0.1 –0.4 –0.5 0 01 2 4 6 8 10 12 146 –40 25 85 CODE/1000 TEMPERATURE (°C) Figure 13. Typical INL vs. Temperature Figure 10. Typical DNL Plot 1.0 0.9 0.8 0.8 0.6 0.7 0.4 0.6 0.2 0.5 0 0.4 –0.2 0.3 –0.4 0.2 –0.6 0.1 –0.8 0 –1.0 0217 3456 8 01 2 4 6 8 10 12 146 CODE/1000 V (+) (V) REF Figure 11. Typical INL vs. V (+), V (−) = −6 V REF REF Figure 14. Typical DAC-to-DAC Matching Rev. D | Page 11 of 28 INL (LSB) INL (LSB) DNL (LSB) 01006-011 01006-010 01006-009 DAC (LSB) INL (LSB) INL (LSB) 01006-013 01006-014 01006-012 AD7834/AD7835 –2.985 0.7 8 VERT = 100mV/DIV VERT = 10mV/DIV HORIZ = 1μs/DIV 0.6 HORIZ = 1µs/DIV –3.005 6 0.5 4 –3.025 0.4 0.3 V (+) = +7V REF 2 –3.045 V (–) = –3V REF 0.2 0 –3.065 0.1 0 –2 –3.085 –0.1 VERT = 2V/DIV HORIZ = 1µs/DIV –0.2 –4 –3.105 Figure 15. Typical Digital/Analog Glitch Impulse Figure 17. Settling Time(−) 7.250 8 VERT = 2V/DIV HORIZ = 1.2μs/DIV 7.225 6 7.200 4 V (+) = +7V REF 7.175 2 V (–) = –3V REF 0 7.150 –2 7.125 VERT = 25mV/DIV HORIZ = 2.5μs/DIV –4 7.100 Figure 16. Settling Time(+) Rev. D | Page 12 of 28 VOLTS VOLTS 01006-015 VOLTS 01006-016 VOLTS VOLTS 01006-017 AD7834/AD7835 TERMINOLOGY DAC-to-DAC Crosstalk Relative Accuracy DAC-to-DAC crosstalk is defined as the glitch impulse that Relative accuracy or endpoint linearity is a measure of the appears at the output of one converter due to both the digital maximum deviation from a straight line passing through the change and the subsequent analog output (O/P) change at endpoints of the DAC transfer function. It is measured after another converter. It is specified in nV-secs. adjusting for zero error and full-scale error. It is normally expressed in LSBs or as a percentage of full-scale reading. Digital Crosstalk The glitch impulse transferred to the output of one converter Differential Nonlinearity due to a change in digital input code to the other converter is Differential nonlinearity is the difference between the measured defined as the digital crosstalk and is specified in nV-secs. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum Digital Feedthrough ensures monotonicity. When the device is not selected, high frequency logic activity on its digital inputs can be capacitively coupled both across and DC Crosstalk through the device to show up as noise on the V pins. This OUT Although the common input reference (IR) voltage signals are noise is digital feedthrough. internally buffered, small IR drops in individual DAC reference inputs across the die mean that an update to one channel DC Output Impedance produces a dc output change in one or more channel outputs. DC output impedance is the effective output source resistance. It is dominated by package lead resistance. The four DAC outputs are buffered by op amps sharing common VDD and VSS power supplies. If the dc load current Full-Scale Error changes in one channel due to an update, a further dc change Full-scale error is the error in DAC output voltage when all 1s occurs in one or more of the channel outputs. This effect is are loaded into the DAC latch. Ideally, the output voltage, with most obvious at high load currents and is reduced as the load all 1s loaded into the DAC latch, should be V (+) – 1 LSB. REF currents are reduced. With high impedance loads, the effect is Full-scale error does not include zero-scale error. virtually unmeasurable. Zero-Scale Error Output Voltage Settling Time Zero-scale error is the error in the DAC output voltage when This is the amount of time it takes for the output to settle to a all 0s are loaded into the DAC latch. Ideally, the output voltage, specified level for a full-scale input change. with all 0s in the DAC latch, is equal to VREF(−). Zero-scale error is due mainly to offsets in the output amplifier. Digital-to-Analog Glitch Impulse This is the amount of charge injected into the analog output Gain Error when the inputs change state. It is specified as the area of the Gain error is defined as (full-scale error) − (zero-scale error). glitch in nV-secs. It is measured with the reference inputs connected to 0 V and the digital inputs toggled between all 1s and all 0s. Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from the reference input of one DAC that appears at the output of the other DAC. It is expressed in decibels (dB). The AD7834 has no specification for channel-to-channel isolation because it has one reference for all DACs. Channel-to-channel isolation is specified for the AD7835. Rev. D | Page 13 of 28 AD7834/AD7835 THEORY OF OPERATION DAC ARCHITECTURE Table 9. D23 Control Each channel consists of a segmented 14-bit R-2R voltage-mode D23 Control Function DAC. The full-scale output voltage range is equal to the entire 0 Ignore the following 23 bits of information. reference span of V (+) – V (−). The DAC coding is straight REF REF 1 Use the following 23 bits of address and data as normal. binary; all 0s produce an output of VREF(−); all 1s produce an D22 and D21 output of VREF(+) − 1 LSB. D22 and D21 are decoded to select one of the four DAC chan- The analog output voltage of each DAC channel reflects the nels within a device, as shown in Table 10. contents of its own DAC latch. Data is transferred from the external bus to the input register of each DAC latch on a per Table 10. D22, D21 Control channel basis. The AD7835 has a feature whereby the A2 pin D22 D21 Control Function data can be transferred from the input databus to all four input 0 0 Select Channel 1 registers simultaneously. 0 1 Select Channel 2 Bringing the CLR line low switches all the signal outputs, V 1 1 0 Select Channel 3 OUT to VOUT4, to the voltage level on the DSG pin. The signal 1 1 Select Channel 4 outputs are held at this level after the removal of the CLR signal D20 to D16 LDAC and do not switch back to the DAC outputs until the D20 and D16 determine the package address. The five address signal is exercised. bits allow up to 32 separate packages to be individually decoded. DATA LOADING—AD7834 SERIAL INPUT DEVICE Successful decoding is accomplished when these five bits match up with the five hardwired pins on the physical package. A write operation transfers 24 bits of data to the AD7834. The first 8 bits are control data and the remaining 16 bits are DAC D15 to D0 data (see Figure 18). The control data identifies the DAC chan- D15 and D0 provide DAC data to be loaded into the identified nel to be updated with new data and which of 32 possible DAC input register. This data must have two leading 0s followed packages the DAC resides in. In any communication with the by 14 bits of data, MSB first. The MSB is in location D13 of the device, the first 8 bits must always be control data. 24-bit data stream. The DAC output voltages, VOUT1 to VOUT4, can be updated to DATA LOADING—AD7835 PARALLEL LOADING reflect new data in the DAC input registers in one of two ways. DEVICE The first method normally keeps LDAC high and only pulses Data is loaded into the AD7835 in either straight 14-bit wide LDAC low momentarily to update all DAC latches simultan- words or in two 8-bit bytes. eously with the contents of their respective input registers. The LDAC second method ties low and channel updating occurs on BYSHF In systems that transfer 14-bit wide data, the input a per channel basis after new data has been clocked into the should be hardwired to V . This sets up the AD7835 as a CC AD7834. With LDAC low, the rising edge of FSYNC transfers straight 14-bit parallel-loading DAC. the new data directly into the DAC latch, updating the analog In 8-bit bus systems where it is required to transfer data in two output voltage. bytes, it is necessary to have the BYSHF input under logic control. Data being shifted into the AD7834 enters a 24-bit long shift In such a system, the top six pins of the device databus, DB8 to FSYNC register. If more than 24 bits are clocked in before goes DB13, must be hardwired to DGND. New low byte data is high, the last 24 bits transmitted are used as the control data loaded into the lower eight places of the selected input register and DAC data. BYSHF by carrying out a write operation while holding high. BYSHF A second write operation is subsequently executed with Individual bit functions are shown in Figure 18. low and the 6 MSBs on the DB0 to DB5 inputs (DB5 = MSB). D23 D23 determines whether the following 23 bits of address and data should be used or ignored. This is effectively a software chip select bit. D23 is the first bit to be transmitted in the 24-bit long word. Rev. D | Page 14 of 28 AD7834/AD7835 NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD. D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB, DB0 CONTROL BIT TO USE/IGNORE SECOND LSB, DB1 FOLLOWING 23 BITS OF INFORMATION THIRD LSB, DB2 DB3 CHANNEL ADDRESS MSB, D1 DB4 CHANNEL ADDRESS LSB, D2 DB5 DB6 PACKAGE ADDRESS MSB, PA4 DB7 DB8 PACKAGE ADDRESS, PA3 DB9 PACKAGE ADDRESS, PA2 DB10 THIRD MSB, DB11 PACKAGE ADDRESS, PA1 SECOND MSB, DB12 PACKAGE ADDRESS LSB, PA0 MSB, DB13 SECOND LEADING ZERO FIRST LEADING ZERO Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834 When 14-bit transfers are being used, the DAC output voltages, gives the code table for unipolar operation of the AD7834/ 1 to V 4, can be updated to reflect new data in the DAC AD7835. VOUT OUT input registers in one of two ways. The first method normally +15V +5V keeps LDAC high and only pulses LDAC low momentarily to update all DAC latches simultaneously with the contents of 2 V V CC DD LDAC 6 their respective input registers. The second method ties V OUT V (+) V REF OUT 8 (0V TO 5V) AD586 low, and channel updating occurs on a per channel basis after 5 R1 AD7834/ 10kΩ 1 AD7835 C1 new data is loaded to an input register. 1nF 4 AGND V (–) REF DGND To avoid the DAC output going to an intermediate value during V SS SIGNAL a 2-byte transfer, LDAC should not be tied low permanently but SIGNAL GND GND should be held high until the two bytes are written to the input –15V 1 ADDITIONAL PINS OMITTED FOR CLARITY register. When the selected input register has been loaded with Figure 19. Unipolar 5 V Operation the two bytes, LDAC should then be pulsed low to update the DAC latch and, consequently, perform the digital-to-analog Offset and gain can be adjusted in Figure 19 as follows: conversion. • To adjust offset, disconnect the V (−) input from 0 V, REF In many applications, it may be acceptable to allow the DAC load the DAC with all 0s, and adjust the V (−) voltage REF output to go to an intermediate value during a 2-byte transfer. until V = 0 V. OUT In such applications, LDAC can be tied low, thus using one less • To adjust gain, load the AD7834/AD7835 with all 1s and control line. adjust R1 until V = 5 V(16383/16384) = 4.999695 V. OUT The actual DAC input register that is being written to is deter- Many circuits do not require these offset and gain adjustments. mined by the logic levels present on the device address lines, as In these circuits, R1 can be omitted. Pin 5 of the AD586 can be shown in Table 11. left open circuit, and Pin 2 (VREF(−)) of the AD7834/AD7835 is tied to 0 V. Table 11. AD7835—Address Line Truth Table A2 A1 A0 DAC Selected 1 , 2 Table 12. Code Table for Unipolar Operation 0 0 0 DAC 1 Binary Number in DAC Latch 0 0 1 DAC 2 MSB LSB Analog Output (V ) OUT 0 1 0 DAC 3 11 1111 1111 1111 VREF (16383/16384) V 0 1 1 DAC 4 10 0000 0000 0000 VREF (8192/16384) V 1 X X All DACs selected 01 1111 1111 1111 V (8191/16384) V REF 00 0000 0000 0001 V (1/16384) V REF UNIPOLAR CONFIGURATION 00 0000 0000 0000 0 V Figure 19 shows the AD7834/AD7835 in the unipolar binary circuit configuration. The V (+) input of the DAC is driven by 1 REF V = V (+); VREF(−) = 0 V for unipolar operation. REF REF 2 14 For VREF(+) = 5 V, 1 LSB = 5 V/2 = 5 V/16384 = 305 μV. the AD586, a 5 V reference. VREF(−) is tied to ground. Table 12 Rev. D | Page 15 of 28 01006-018 01006-019 AD7834/AD7835 BIPOLAR CONFIGURATION In Figure 20, full-scale and bipolar zero adjustments are +15V +5V provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the offset of both R1 39kΩ the +5 V and –5 V outputs together with respect to ground. 4 6 For bipolar-zero adjustment, the DAC is loaded with 7 V V 2 CC DD C1 1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale 3 1μF V OUT 9 V (+) V REF OUT (–5V TO +5V) 1 is adjusted by loading the DAC with all 1s and adjusting R2 AD588 AD7834/ 5 14 1 R2 AD7835 until VOUT = 5(8191/8192) V = 4.99939 V. 100kΩ 10 15 AGND V (–) REF 11 16 DGND When bipolar zero and full-scale adjustment are not needed, R2 V SS and R3 are omitted. Pin 12 on the AD588 should be connected to 12 8 13 R3 SIGNAL 100kΩ GND Pin 11, and Pin 5 should be left floating. –15V 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. Bipolar ±5 V Operation Figure 20 shows the AD7834/AD7835 setup for ±5 V operation. The AD588 provides precision ±5 V tracking outputs that are fed to the V (+) and V (−) inputs of the AD7834/AD7835. REF REF The code table for bipolar operation of the AD7834/AD7835 is shown in Table 13. 1, 2 Table 13. Code Table for Bipolar Operation Binary Number in DAC Latch MSB LSB Analog Output (VOUT) 11 1111 1111 1111 VREF(−) + VREF (16383/16384) V 10 0000 0000 0001 V (−) + V (8193/16384) V REF REF 10 0000 0000 0000 VREF(−) + VREF (8192/16384) V 01 1111 1111 1111 V (−) + V (8191/16384) V REF REF 00 0000 0000 0001 VREF(−) + VREF (1/16384) V 00 0000 0000 0000 V (−) V REF 1 V = V (+) – V (−). REF REF REF 2 14 For VREF(+) = +5 V and VREF(−) = –5 V, 1 LSB = 10 V/2 = 10 V/16384 = 610 μV. Rev. D | Page 16 of 28 01006-020 AD7834/AD7835 CONTROLLED POWER-ON OF THE OUTPUT STAGE G 1 A block diagram of the output stage of the AD7834/AD7835 is G 6 DAC shown in Figure 21. It is capable of driving a load of 10 kΩ in V OUT parallel with 200 pF. G1 to G6 are transmission gates used to G 3 control the power-on voltage present at VOUT. G1 and G2 are also G 4 G CLR 2 used in conjunction with the input to set VOUT to the user- G 5 R defined voltage present at the DSG pin. G 1 G 6 DAC DSG V OUT CLR Figure 23. Output Stage with VDD > 10 V and Low G 3 G 4 VOUT is disconnected from the DSG pin by the opening of G5 G 2 but tracks the voltage present at DSG via the unity gain buffer. G 5 R POWER-ON WITH LDAC LOW, CLR HIGH DSG In many applications of the AD7834/AD7835, LDAC is kept continuously low, updating the DAC after each valid data Figure 21. Block Diagram of AD7834/AD7835 Output Stage LDAC transfer. If is low when power is applied, G1 is closed and POWER-ON WITH CLR LOW, LDAC HIGH G is open, connecting the output of the DAC to the input of the 2 The output stage of the AD7834/AD7835 is designed to allow output amplifier. G and G are closed and G and G are open, 3 5 4 6 CLR output stability during power-on. If is kept low during connecting the amplifier as a unity gain buffer, as before. VOUT is power-on, and power is applied to the part, G , G , and G are 1 4 6 connected to DSG via G5 and R (a thin-film resistance between open while G , G , and G are closed (see Figure 22). 2 3 5 DSG and VOUT) until VDD and VSS reach approximately ±10 V. Then, the internal power-on circuitry opens G3 and G5 and G 1 G 6 DAC closes G and G . This is the situation shown in Figure 24. At 4 6 V OUT this point, V is at the same voltage as the DAC output. OUT G 3 G 1 G 4 G 6 DAC G 2 V OUT G 5 R G 3 G 4 G 2 DSG G 5 R Figure 22. Output Stage with V < 10 V DD VOUT is kept within a few hundred millivolts of DSG via G5 DSG and R. R is a thin-film resistor between DSG and V . The OUT LDAC Figure 24. Output Stage with Low output amplifier is connected as a unity gain buffer via G , and 3 the DSG voltage is applied to the buffer input via G . The 2 LOADING THE DAC AND USING THE CLR INPUT amplifier output is thus at the same voltage as the DSG pin. The LDAC When goes low, it closes G1 and opens G2 as in Figure 24. output stage remains configured as in Figure 22 until the The voltage at VOUT now follows the voltage present at the out- voltage at VDD and VSS reaches approximately ±10 V. At this put of the DAC. The output stage remains connected in this point, the output amplifier has enough headroom to handle manner until a CLR signal is applied. Then, the situation reverts signals at its input and has also had time to settle. The internal (see Figure 23). Once again, VOUT remains at the same voltage as power-on circuitry opens G and G and closes G and G (see 3 5 4 6 LDAC DSG until goes low. This reconnects the DAC output to Figure 23). As a result, the output amplifier is connected in the unity gain buffer. unity gain mode via G and G . The DSG voltage is still applied 4 6 to the noninverting input via G . This voltage appears at V . 2 OUT Rev. D | Page 17 of 28 01006-022 01006-021 01006-024 01006-023 AD7834/AD7835 Once the AD7834/AD7835 have powered on and the on-chip DSG VOLTAGE RANGE amplifiers have settled, the situation is as shown in Figure 23. During power-on, the VOUT pins of the AD7834/AD7835 are Any voltage subsequently applied to the DSG pin is buffered by connected to the relevant DSG pins via G6 and the thin-film the same amplifier that buffers the DAC output voltage in resistor, R. The DSG potential must obey the maximum ratings normal operation. Thus, for specified operations, the maximum at all times. Thus, the voltage at DSG must always be within the voltage applied to the DSG pin increases to the maximum range V – 0.3 V to V + 0.3 V. However, to keep the voltages SS DD allowable VREF(+) voltage, and the minimum voltage applied to at the V pins of the AD7834/AD7835 within ±2 V of the OUT DSG is the minimum V (−) voltage. After the AD7834 or REF relevant DSG potential during power-on, the voltage applied to AD7835 has fully powered on, the outputs can track any DSG DSG should also be kept within the range AGND – 2 V to voltage within this minimum/maximum range. AGND + 2 V. Rev. D | Page 18 of 28 AD7834/AD7835 POWER-ON OF THE AD7834/AD7835 Power is normally applied to the AD7834/AD7835 in the V (+) REF following sequence: first VDD and VSS, then VCC, and then SD103C 1 AD7834 1N5711 VREF(+) and VREF(−). The VREF pins are not allowed to float when 1N5712 power is applied to the part. VREF(+) is not allowed to go below V (–) REF V (−) − 0.3 V. V (−) is not allowed to go below V − 0.3 V. REF REF SS 1 ADDITIONAL PINS OMITTED FOR CLARITY V is not allowed to go below V − 0.3 V. DD CC Figure 25. Power-On Protection In some systems, it is necessary to introduce one or more Schottky diodes between pins to prevent the above situations arising at power-on. These diodes are shown in Figure 25. However, in most systems, with careful consideration given to power supply sequencing, the above rules are adhered to, and protection diodes are not necessary. Rev. D | Page 19 of 28 01006-025 AD7834/AD7835 MICROPROCESSOR INTERFACING To load data to the AD7834, PC7 is left low after the first eight AD7834 TO 80C51 INTERFACE bits are transferred. A second byte of data is then transmitted A serial interface between the AD7834 and the 80C51 micro- serially to the AD7834. Then, a third byte is transmitted and, controller is shown in Figure 26. TXD of the 80C51 drives SCLK when this transfer is complete, the PC7 line is taken high. of the AD7834, while RXD drives the serial data line of the part. 1 1 68HC11 AD7834 The 80C51 provides the LSB of its SBUF register as the first bit PC5 CLR in the serial data stream. The AD7834 expects the MSB of the PC6 LDAC 24-bit write first. Therefore, the user has to ensure that data in the SBUF register is arranged correctly so the data is received PC7 FSYNC MSB first by the AD7834/AD7835. When data is to be trans- SCLK SCK mitted to the part, P3.3 is taken low. Data on RXD is valid on MOSI DIN the falling edge of TXD. The 80C51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the trans- 1 ADDITIONAL PINS OMITTED FOR CLARITY mit cycle. To load data to the AD7834, P3.3 is left low after the Figure 27. AD7834 to 68HC11 Interface first 8 bits are transferred. A second byte is then transferred, LDAC CLR In Figure 27, and are controlled by the PC6 and PC5 with P3.3 still kept low. After the third byte has been trans- port outputs, respectively. As with the 80C51, each DAC of the ferred, the P3.3 line is taken high. AD7834 can be updated after each 3-byte transfer, or all DACs 1 1 80C51 AD7834 can be simultaneously updated after 12 bytes are transferred. P3.5 CLR AD7834 TO ADSP-2101 INTERFACE P3.4 LDAC An interface between the AD7834 and the ADSP-2101 is shown P3.3 FSYNC in Figure 28. In the interface shown, SPORT0 is used to transfer TXD SCLK data to the part. SPORT1 is configured for alternate functions. RXD DIN FO, the flag output on SPORT0, is connected to LDAC and is used to load the DAC latches. In this way, data is transferred 1 ADDITIONAL PINS OMITTED FOR CLARITY from the ADSP-2101 to all the input registers in the DAC, and Figure 26. AD7834 to 80C51 Interface the DAC latches are updated simultaneously. In the application CLR LDAC CLR shown, the pin on the AD7834 is controlled by circuitry and on the AD7834 are also controlled by 80C51 that monitors the power in the system. LDAC port outputs. The user can bring low after every three bytes have been transmitted to update the DAC, which has been POWER MONITOR programmed. Alternatively, it is possible to wait until all the 1 1 ADSP-2101 AD7834 input registers have been loaded (12-byte transmits) and then CLR update the DAC outputs. FO LDAC AD7834 TO 68HC11 INTERFACE TFS FSYNC Figure 27 shows a serial interface between the AD7834 and the SCK SCLK 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of DT DIN the AD7834, while the MOSI output drives the serial data line, 1 DIN, of the AD7834. The FSYNC signal is derived from Port ADDITIONAL PINS OMITTED FOR CLARITY Line PC7. Figure 28. AD7834 to ADSP-2101 Interface For correct operation of this interface, the 68HC11 should be The AD7834 requires 24 bits of serial data framed by a single configured so that its CPOL bit is 0 and its CPHA bit is 1. When FSYNC FSYNC pulse. It is necessary that this pulse stay low until data is to be transferred to the part, PC7 is taken low. When the all the data is transferred. This can be provided by the ADSP-2101 68HC11 is configured like this, data on MOSI is valid on the in one of two ways. Both require setting the serial word length of falling edge of SCK. The 68HC11 transmits its serial data in 8-bit the SPORT to 12 bits, with the following conditions: internal bytes, MSB first. The AD7834 also expects the MSB of the 24-bit SCLK, alternate framing mode, and active low framing signal. write first. Eight falling clock edges occur in the transmit cycle. Rev. D | Page 20 of 28 01006-026 01006-028 01006-027 AD7834/AD7835 First, data can be transferred using the autobuffering feature of CLOCK/ TIMER 1 the ADSP-2101, sending two 12-bit words directly after each TMS32020/ AD7834 1 TMS320C25 other. This ensures a continuous transmit frame synchron- LDAC ization (TFS ) pulse. Second, the first data word is loaded to the XF CLR serial port, the subsequent generated interrupt is trapped, and FSX FSYNC then the second data word is sent immediately after the first. SCLK CLKX Again, this produces a continuous TFS pulse that frames the DX DIN 24 data bits. 1 AD7834 TO DSP56000/DSP56001 INTERFACE ADDITIONAL PINS OMITTED FOR CLARITY Figure 29 shows a serial interface between the AD7834 and the Figure 30. AD7834 to TMS32020/TMS320C25 Interface DSP56000/DSP56001. The serial port is configured for a word INTERFACING THE AD7835—16-BIT INTERFACE length of 24 bits, gated clock, and FSL0 and FSL1 control bits The AD7835 can be interfaced to a variety of microcontrollers each set to 0. Normal mode synchronous operation is selected, or DSP processors, both 8-bit and 16-bit. Figure 31 shows the which allows the use of SC0 and SC1 as outputs controlling AD7835 interfaced to a generic 16-bit microcontroller/DSP CLR LDAC and , respectively. The framing signal on SC2 has to processor. BYSHF is tied to V in this interface. The lower CC be inverted before being applied to FSYNC. SCK is internally address lines from the processor are connected to A0, A1, and generated on the DSP56000/DSP56001 and is applied to SCLK A2 on the AD7835 as shown. The upper address lines are on the AD7834. Data from the DSP56000/DSP56001 is valid on decoded to provide a chip select signal for the AD7835. They the falling edge of SCK. are also decoded, in conjunction with the lower address lines if DSP56000/ 1 AD7834 1 need be, to provide an LDAC signal. Alternatively, LDAC can be DSP56001 SC0 CLR driven by an external timing circuit or just tied low. The data lines of the processor are connected to the data lines of the SC1 LDAC AD7835. Selection options available for the DACs are provided SC2 FSYNC in Table 11. SCK SCLK 1 MICROCONTROLLER/ AD7835 STD DIN V CC DSP 1 PROCESSOR 1 ADDITIONAL PINS OMITTED FOR CLARITY BYSHF D13 D13 Figure 29. AD7834 to DSP56000/DSP56001 Interface DATABUS AD7834 TO TMS32020/TMS320C25 INTERFACE D0 D0 A serial interface between the AD7834 and the TMS32020/ UPPER BITS OF CS ADDRESS ADDRESS BUS DECODE TMS320C25 DSP processor is shown in Figure 30. The LDAC CLKX and FSX signals for the TMS32020/TMS32025 are A2 A2 generated using an external clock/timer circuit. The CLKX and A1 A1 A0 A0 FSX pins are configured as inputs. The TMS32020/ TMS320C25 R/W WR are set up for an 8-bit serial data length. Data can then be written to the AD7834 by writing three bytes to the serial port of the 1 ADDITIONAL PINS OMITTED FOR CLARITY TMS32020/TMS320C25. In the configuration shown in Figure Figure 31. AD7835 16-Bit Interface 30, the CLR input on the AD7834 is controlled by the XF output on the TMS32020/TMS320C25. The clock/timer circuit controls the LDAC input on the AD7834. Alternatively, LDAC can also be tied to ground to allow automatic update of the DAC latches after each transfer. Rev. D | Page 21 of 28 01006-029 01006-030 01006-031 AD7834/AD7835 When writing to the DACs, the lower eight bits must be written INTERFACING THE AD7835—8-BIT INTERFACE first, followed by the upper six bits. The upper six bits should be Figure 32 shows an 8-bit interface between the AD7835 and output on data lines D0 to D5. Once again, the upper address a generic 8-bit microcontroller/DSP processor. Pin D13 to lines of the processor are decoded to provide a CS signal. They Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the are also decoded in conjunction with lines A3 to A0 to provide processor are connected to Pin D7 to Pin D0 of the AD7835. an LDAC signal. Alternatively, LDAC can be driven by an exter- BYSHF is driven by the A0 line of the processor. This maps the nal timing circuit or, if it is acceptable to allow the DAC output DAC upper bits and lower bits into adjacent bytes in the proces- LDAC to go to an intermediate value between 8-bit writes, can sor address space. Table 14 shows the truth table for addressing be tied low. the DACs in the AD7835. For example, if the base address for the DACs in the processor address space is decoded by the upper Table 14. DAC Channel Decoding, 8-Bit Interface address bits to location HC000, then the upper and lower bits of Processor Address Lines the first DAC are at locations HC000 and HC001, respectively. A3 A2 A1 A0 DAC Selected D13 MICROCONTROLLER/ x X X 0 Upper 6 bits of all DACs DSP 1 X X 1 Lower 8 bits of all DACs 1 PROCESSOR D8 1 AD7835 0 0 0 0 Upper 6 bits, DAC 1 DGND D7 D7 0 0 0 1 Lower 8 bits, DAC 1 DATABUS 0 0 1 0 Upper 6 bits, DAC 2 D0 D0 0 0 1 1 Lower 8 bits, DAC 2 UPPER BITS OF CS ADDRESS ADDRESS BUS 0 1 0 0 Upper 6 bits, DAC 3 DECODE LDAC 0 1 0 1 Lower 8 bits, DAC 3 0 1 1 0 Upper 6 bits, DAC 4 A3 A2 A2 A1 0 1 1 1 Lower 8-bits, DAC 4 A1 A0 A0 BYSHF R/W WR 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 32. AD7835 8-Bit Interface Rev. D | Page 22 of 28 01006-032 AD7834/AD7835 APPLICATIONS INFORMATION Figure 34 shows a 5-channel isolated interface to the AD7834. SERIAL INTERFACE TO MULTIPLE AD7834S Multiple devices are connected to the outputs of the opto-coupler Figure 33 shows how the package address pins of the AD7834 and controlled as for serial interfacing. To reduce the number of are used to address multiple AD7834s. This figure shows only opto-isolators, the PAEN line doesn’t need to be controlled if it 10 devices, but up to 32 AD7834s can each be assigned a unique PAEN is not used. If the line is not controlled by the microcon- address by hardwiring each of the package address pins to VCC troller, it should be tied low at each device. If simultaneous updat- or DGND. Normal operation of the device occurs when PAEN LDAC ing of the DACs is not required, the pin on each part can is low. When serial data is being written to the AD7834s, only be tied permanently low and another opto-isolator is not needed. the device with the same package address as the package address V CC contained in the serial data accepts data into the input registers. MICROCONTROLLER PAEN Conversely, if is high, the package address is ignored, and the data is loaded into the same channel on each package. CONTROL OUT TO PAENs The primary limitation with multiple packages is the output TO LDACs CONTROL OUT update rate. For example, if an output update rate of 10 kHz is SYNC OUT TO FSYNCs required, 100 μs are available to load all DACs. Assuming a TO SCLKs serial clock frequency of 10 MHz, it takes 2.5 μs to load data to SERIAL CLOCK OUT one DAC. Thus, 40 DACs or 10 packages can be updated in this SERIAL DATA OUT TO DINs time. As the update rate requirement decreases, the number of possible packages increases. OPTO-COUPLER 1 Figure 34. Opto-Isolated Interface MICROCONTROLLER AD7834 DEVICE 0 AUTOMATED TEST EQUIPMENT CONTROL OUT PAEN PA0 CONTROL OUT LDAC PA1 The AD7834/AD7835 are particularly suited for use in an SYNC OUT FSYNC PA2 automated test environment. Figure 35 shows the AD7835 SCLK PA3 SERIAL CLOCK OUT PA4 SERIAL DATA OUT DIN providing the necessary voltages for the pin driver and the window comparator in a typical ATE pin electronics configur- 1 ation. Two AD588s are used to provide reference voltages for AD7834 DEVICE 1 V CC the AD7835. In the configuration shown, the AD588s are PAEN PA0 configured so that the voltage at Pin 1 is 5 V greater than the LDAC PA1 voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the FSYNC PA2 SCLK PA3 voltage at Pin 9. PA4 DIN One AD588 is used as a reference for DAC 1 and DAC 2. These DACs are used to provide high and low levels for the pin driver. The pin driver can have an associated offset. This can be nulled 1 AD7834 by applying an offset voltage to Pin 9 of the AD588. First, the DEVICE 9 V CC code 1000 . . . 0000 is loaded into the DAC 1 latch, and the pin PAEN PA0 driver output is set to the DAC 1 output. The V voltage is OFFSET LDAC PA1 FSYNC PA2 adjusted until 0 V appears between the pin driver output and SCLK PA3 DUT GND. This causes both VREF(+)A and VREF(−)A to be off- PA4 DIN set with respect to AGND by an amount equal to VOFFSET. 1 ADDITIONAL PINS OMITTED FOR CLARITY However, the output of the pin driver varies from −5 V to +5 V Figure 33. Serial Interface to Multiple AD7834s with respect to DUT GND as the DAC input code varies from OPTO-ISOLATED INTERFACE 000 . . . 000 to 111 . . . 111. The V voltage is also applied to OFFSET In many process control applications, it is necessary to provide the DSGA pin. When a clear is performed on the AD7835, the output of the pin driver is 0 V with respect to DUT GND. an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD7834 makes it ideal for opto-isolated interfaces because the number of interface lines is kept to a minimum. Rev. D | Page 23 of 28 01006-033 01006-034 AD7834/AD7835 +15V –15V V OFFSET If the AD7834/AD7835 are the only devices requiring an AGND 2 16 to DGND connection, then the ground planes should be connected 3 4 +15V at the AGND and DGND pins of the AD7834/ AD7835. If the 6 1 V (+)A REF 8 V 1 OUT AD7834/AD7835 are in a system where multiple devices require 15 AD588 13 V (–)A PIN REF 14 DRIVER an AGND to DGND connection, the connection can still be made 7 VOUT2 9 at one point only, a star ground point, which can be established as 1µF DSG A 0.1µF –15V close as possible to the AD7834/AD7835. 1 AD7835 10 11 12 Digital lines running under the device must be avoided because DSG B +15V –15V DUT V DUT they couple noise onto the die. The analog ground plane can run GND 2 16 V 3 under the AD7834/AD7835 to avoid noise coupling. The power OUT 4 3 6 1 DUT supply lines of the AD7834/AD7835 can use as large a trace as V (+)B REF GND 8 V 4 OUT 15 possible to provide low impedance paths and reduce the effects of 13 V (–)B AD588 REF 14 10 glitches on the power supply line. Fast switching signals, such as 11 AGND clocks, should be shielded with digital ground to avoid radiating 12 noise to other parts of the board. These signals should never be 7 9 WINDOW 1µF COMPARATOR run near the analog inputs. Avoid crossover of digital and analog DUT TO TESTER GND signals. Traces on opposite sides of the board should run at right 1 ADDITIONAL PINS OMITTED FOR CLARITY angles to each other. This reduces the effects of feedthrough Figure 35. ATE Application through the board. A microstrip method is best but not always The other AD588 provides a reference voltage for DAC 3 and possible with a double-sided board. With this method, the DAC 4. These provide the reference voltages for the window component side of the board is dedicated to ground plane while comparator shown in Figure 35. Pin 9 of this AD588 is con- signal traces are placed on the solder side. nected to DUT GND. This causes V (+)B and V (−)B to be REF REF The AD7834/AD7835 must have ample supply bypassing located referenced to DUT GND. As DAC 3 and DAC 4 input codes vary as close as possible to the package, ideally right up against the from 000 . . . 000 to 111 . . . 111, V 3 and V 4 vary from −5 V OUT OUT device. Figure 36 shows the recommended capacitor values of to +5 V with respect to DUT GND. DUT GND is also connected 10 μF in parallel with 0.1 μF on each of the supplies. The 10 μF to DSGB. When the AD7835 is cleared, VOUT3 and VOUT4 are capacitors are the tantalum bead type. The 0.1 μF capacitor can cleared to 0 V with respect to DUT GND. have low effective series resistance (ESR) and effective series Care must be taken to ensure that the maximum and minimum inductance (ESI), such as the common ceramic types, which voltage specifications for the AD7835 reference voltages are provide a low impedance path to ground at high frequencies to followed as shown in Figure 35. handle transient currents due to internal logic switching. POWER SUPPLY BYPASSING AND GROUNDING V V CC DD In any circuit where accuracy is important, careful considera- 0.1μF 10μF 0.1μF 10μF tion of the power supply and ground return layout helps to AD7834/ DGND 1 AD7835 AGND ensure the rated performance. The printed circuit boards on V which the AD7834/AD7835 are mounted should be designed so SS 0.1μF 10μF the analog and digital sections are separated and confined to certain areas of the boards. This facilitates the use of ground 1 ADDITIONAL PINS OMITTED FOR CLARITY planes that can be easily separated. A minimum etch technique Figure 36. Power Supply Decoupling is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined at only one place. Rev. D | Page 24 of 28 01006-035 01006-036 AD7834/AD7835 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 14 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.10 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 37. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 114 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.195 (4.95) 0.250 (6.35) 0.015 (0.38) 0.125 (3.17) MAX GAUGE PLANE 0.015 (0.38) 0.200 (5.08) MIN 0.115 (2.92) 0.015 (0.38) SEATING PLANE 0.008 (0.20) 0.700 (17.78) 0.022 (0.56) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev. D | Page 25 of 28 0.75 (0.0295) 0.25 (0.0098) 060706-A 071006-A AD7834/AD7835 0.180 (4.57) 0.048 (1.22) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.020 (0.51) 0.042 (1.07) MIN 6 40 0.048 (1.22) 7 39 0.021 (0.53) PIN 1 0.042 (1.07) 0.013 (0.33) IDENTIFIER 0.630 (16.00) BOTTOM VIEW 0.050 TOP VIEW 0.590 (14.99) (PINS UP) (1.27) (PINS DOWN) BSC 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.045 (1.14) R 0.656 (16.66) 0.120 (3.05) 0.025 (0.64) SQ 0.650 (16.51) 0.090 (2.29) 0.695 (17.65) SQ 0.685 (17.40) COMPLIANT TO JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. 44-Lead Plastic Leaded Chip Carrier [PLCC} (P-44A) Dimensions shown in inches and (millimeters) 14.15 1.03 13.90 SQ 2.45 0.88 MAX 13.65 0.73 34 44 1 33 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 2.20 0.23 2.00 0.11 1.80 23 11 7° 12 22 0.25 MIN 0° 0.10 0.45 COPLANARITY 0.30 0.80 BSC LEAD WIDTH LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Figure 40. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions show in millimeters Rev. D | Page 26 of 28 1.95 REF SEATING PLANE VIEW A 041807-A AD7834/AD7835 ORDERING GUIDE Model Temperature Range Linearity Error (LSBs) DNL (LSBs) Package Description Package Option AD7834AR −40°C to +85°C ±2 ±0.9 28-Lead SOIC_W RW-28 AD7834AR-REEL −40°C to +85°C ±2 ±0.9 28-Lead SOIC_W RW-28 1 AD7834ARZ −40°C to +85°C ±2 ±0.9 28-Lead SOIC_W RW-28 1 AD7834ARZ-REEL −40°C to +85°C ±2 ±0.9 28-Lead SOIC_W RW-28 AD7834BR −40°C to +85°C ±1 ±0.9 28-Lead SOIC_W RW-28 AD7834BR-REEL −40°C to +85°C ±1 ±0.9 28-Lead SOIC_W RW-28 1 AD7834BRZ −40°C to +85°C ±1 ±0.9 28-Lead SOIC_W RW-28 1 AD7834BRZ-REEL −40°C to +85°C ±1 ±0.9 28-Lead SOIC_W RW-28 AD7834AN −40°C to +85°C ±2 ±0.9 28-Lead PDIP N-28-2 1 AD7834ANZ −40°C to +85°C ±2 ±0.9 28-Lead PDIP N-28-2 AD7834BN −40°C to +85°C ±1 ±0.9 28-Lead PDIP N-28-2 1 AD7834BNZ −40°C to +85°C ±1 ±0.9 28-Lead PDIP N-28-2 AD7835AP −40°C to +85°C ±2 ±0.9 44-Lead PLCC P-44A AD7835AP-REEL −40°C to +85°C ±2 ±0.9 44-Lead PLCC P-44A 1 AD7835APZ −40°C to +85°C ±2 ±0.9 44-Lead PLCC P-44A 1 AD7835APZ-REEL −40°C to +85°C ±2 ±0.9 44-Lead PLCC P-44A AD7835AS −40°C to +85°C ±2 ±0.9 44-Lead-MQFP S-44-2 AD7835AS-REEL −40°C to +85°C ±2 ±0.9 44-Lead-MQFP S-44-2 1 AD7835ASZ −40°C to +85°C ±2 ±0.9 44-Lead-MQFP S-44-2 1 AD7835ASZ-REEL −40°C to +85°C ±2 ±0.9 44-Lead-MQFP S-44-2 1 Z = RoHS Compliant Part. Rev. D | Page 27 of 28 AD7834/AD7835 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01006-0-8/07(D) Rev. D | Page 28 of 28