ANALOG DEVICES AD7827

3 V/5 V, 1 MSPS, 8-Bit, Serial Interface a Sampling ADC AD7827 FEATURES FUNCTIONAL BLOCK DIAGRAM 8-Bit Half-Flash ADC with 420 ns Conversion Time V /V V REFIN REFOUT DD GND 200 ns Acquisition Time 8-Lead Package 2.5V V AD7827 DD On-Chip Track-and-Hold REF DETECT On-Chip 2.5 V Reference with 2% Tolerance CONTROL Operating Supply Range: 3 V 6 10% and 5 V 6 10% COMP CONVST LOGIC BUF Specifications @ 3 V and 5 V DSP/Microcontroller Compatible Serial Interface SCLK Automatic Power-Down at End of Conversion 8-BIT SERIAL V T/H IN Input Ranges HALF-FLASH D OUT PORT ADC 0 V to 2 V, V = 3 V DD RFS 0 V to 2.5 V, V = 5 V DD GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7827 is a high speed, single channel, low power, analog- 1. Fast Conversion Time to-digital converter with a maximum throughput of 1 MSPS that The AD7827 has a conversion time of 420 ns. Faster conver- operates from a single 3 V or 5 V supply. The AD7827 contains sion times maximize the DSP processing time in a real time a track/hold amplifier, an on-chip 2.5 V reference (2% toler- system. ance), a 420 ns 8-bit half-flash ADC and a serial interface. The 2. Built-In Track-and-Hold serial interface is compatible with the serial interfaces of most The analog input signal is held and a new conversion is initi- DSPs (Digital Signal Processors). The throughput rate of the ated on the falling edge of the CONVST signal. The CONVST AD7827 is dependent on the clock speed of the DSP serial signal allows the sampling instant to be exactly controlled. interface. This feature is a requirement in many DSP applications. The AD7827 combines the Convert Start and Power Down 3. Automatic Power-Down signals at one pin, i.e., the CONVST pin. This allows a unique The CONVST signal is sampled approximately 100 ns after automatic power-down at the end of a conversion to be imple- the end of conversion and depending on its state the AD7827 mented. The logic level on the CONVST pin is sampled at the is powered down. end of a conversion and, depending on its state, the AD7827 4. An easy to use, fast serial interface allows direct interfacing to powers down. most popular DSPs with no external circuitry. The AD7827 has one single-ended analog input with an input span determined by the supply voltage. With a V of 3 V, the DD input range of the AD7827 is 0 V to 2 V and with V equal to DD 5 V, the input range is 0 V to 2.5 V. The parts are available in a small, 8-lead, 0.3" wide, plastic dual-in-line package (DIP) and an 8-lead, small outline IC (SOIC). REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 (V = +3 V 6 10%, V = +5 V 6 10%, GND = 0 V, V = 2.5 V. All DD DD REFIN/REFOUT specifications –408C to +1058C unless otherwise noted.) AD7827–SPECIFICATIONS Parameter Version B Units Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz; f = 1 MHz IN SAMPLE 1 Signal-to-(Noise + Distortion) Ratio 48 dB min 1 Total Harmonic Distortion –55 dB max 1 Peak Harmonic or Spurious Noise –55 dB max 1 Intermodulation Distortion fa = 29.1 kHz; fb = 29.9 kHz 2nd Order Terms –65 dB typ 3rd Order Terms –65 dB typ DC ACCURACY Resolution 8 Bits 1 Integral Nonlinearity (INL) ±0.5 LSB max 1 Differential Nonlinearity (DNL) ±0.5 LSB max 1 Offset Error ±1.5 LSB max 1 Gain Error ±2 LSB max Minimum Resolution for Which No Missing Codes are Guaranteed 8 Bits 2 ANALOG INPUT Input Voltage Range 0 V min V = 5 V DD 2.5 V max 0 V min V = 3 V DD 2 V max Input Leakage Current ±1 μA max Input Capacitance 10 pF max REFERENCE INPUT V / Input Voltage Range 2.55 V max REFIN REFOUT 2.45 V min Input Current ±1 μA typ ±50 μA max LOGIC INPUTS CONVST, SCLK V Input High Voltage 2.4 V min V = 5 V ± 10% INH, DD V Input Low Voltage 0.8 V max V = 5 V ± 10% INL, DD V Input High Voltage 2.0 V min V = 3 V ± 10% INH, DD V Input Low Voltage 0.4 V max V = 3 V ± 10% INL, DD Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V INH IN DD Input Capacitance 10 pF max LOGIC OUTPUTS D , RFS OUT V Output High Voltage I = 200 μA OH, SOURCE 4 V max V = 5 V ± 10% DD 2.4 V min V = 3 V ± 10% DD V Output Low Voltage I = 200 μA OL, SINK 0.4 V max V = 5 V ± 10% DD 0.2 V min V = 3 V ± 10% DD High Impedance Leakage Current ±1 μA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 420 ns max Track/Hold Acquisition Time 200 ns max –2– REV. 0 AD7827 Parameter Version B Units Test Conditions/Comments POWER SUPPLY V 4.5 V min 5 V ± 10% For Specified Performance DD 5.5 V max 2.7 V min 3 V ± 10% For Specified Performance 3.3 V max I DD Normal Operation 10 mA max 8 mA Typically Power-Down 1 μA max Logic Inputs = 0 V or V DD Power Dissipation V = 3 V DD Normal Operation 30 mW max Typically 24 mW Power-Down 200 kSPS 9.58 mW max 1 MSPS 47.88 mW max NOTES 1 See Terminology section of this data sheet. 2 Refer to the Analog Input section for an explanation of the Analog Input(s). Specifications subject to change without notice. 1, 2 TIMING CHARACTERISTICS (V = 2.5 V, all specifications –408C to +1058C, unless otherwise noted) REFIN/REFOUT Parameter 5 V 6 10% 3 V 6 10% Units Conditions/Comments t 420 420 ns max Conversion Time. CONVERT t 20 20 ns min Minimum CONVST Pulsewidth. 1 t t +t t +t ns min Falling edge of CONVST to falling edge of RFS. 2 CONVERT 3 CONVERT 3 t +t +t +t t +t +t +t ns max CONVERT 3 7 8 CONVERT 3 7 8 3 t 14 18 ns max Rising edge of SCLK to falling edge of RFS. 3 t 14 18 ns max Rising edge of SCLK to rising edge of RFS. 4 3 t 20 20 ns max Rising edge of SCLK to high impedance disabled. 5 3 t 14 18 ns max Rising edge of SCLK to D valid delay. 6 OUT t 25 25 ns min Minimum high SCLK pulse duration. 7 t 25 25 ns min Minimum low SCLK pulse duration. 8 4 t 20 20 ns min Bus relinquish time after SCLK falling edge. 9 35 35 ns max t 20 20 ns max Maximum delay from falling edge CONVST to rising edge RFS if 10 RFS reset by CONVST. t 30 30 ns min Minimum time between end of serial read and next falling edge of 11 CONVST. t 11 μs max Power-up time from rising edge of CONVST using external 2.5 V POWER-UP reference. t 25 25 μs max Power-up time from rising edge of CONVST using on-chip reference. POWER-UP NOTES 1 Sample tested to ensure compliance. 2 See Figures 13, 14 and 15. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V = 5 V ± 10% and time required for an DD output to cross 0.4 V or 2.0 V with V = 3 V ± 10%. DD 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time of 9 the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. 200mA I OL TO +2.1V OUTPUT C PIN L 50pF 200mA I OH Figure 1. Load Circuit for Digital Output Timing Specifications REV. 0 –3– AD7827 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Pin No. Mnemonic Description Digital Input Voltage to GND (CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD 1 CONVST Convert Start. Puts the track-and- Digital Output Voltage to GND hold into hold mode and initiates a (D , RFS) . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V OUT DD conversion. V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V REF DD The state of this pin at the end of Analog Input Voltage to AGND . . . . . . –0.3 V, V + 0.3 V DD conversion also determines whether Operating Temperature Range or not the part is powered down. Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C 2V Analog Input is applied here. IN Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 3 RFS Receive Frame Sync. This is an Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C output. When this signal goes logic Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW high at the end of a conversion, the θ Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W JA Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C DSP starts latching in data on the SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW next cycle of SCLK. θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . +75°C/W JA 4 GND Ground reference for analog and Lead Temperature, Soldering digital circuitry. Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C 5V Reference Input. REF Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C 6D Serial Data is shifted out on this pin. OUT ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 kV Data is clocked out by the rising *Stresses above those listed under Absolute Maximum Ratings may cause perma- edges of SCLK. nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational 7 SCLK Serial Clock. An external serial clock sections of this specification is not implied. Exposure to absolute maximum rating is applied here. The clock must be conditions for extended periods may affect device reliability. continuous so the RFS (frame SYNC) can be synchronized to the clock for ORDERING GUIDE high speed data transfers. (See Linearity Microprocessor Interfacing section.) Error Package Package 8V Positive Supply Voltage 3 V/5 V ± 10%. DD Model (LSB) Description Option AD7827BN ±0.5 LSB Plastic DIP N-8 PIN CONFIGURATION AD7827BR ±0.5 LSB Small Outline IC SO-8 1 8 V CONVST DD AD7827 V 2 7 SCLK IN TOP VIEW RFS 3 6 D OUT (Not to Scale) GND 4 5 V REF CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7827 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 AD7827 TERMINOLOGY order terms are usually at a frequency close to the input fre- Signal-to-(Noise + Distortion) Ratio quencies. As a result, the second and third order terms are This is the measured ratio of signal-to-(noise + distortion) at specified separately. The calculation of the intermodulation the output of the A/D converter. The signal is the rms amplitude distortion is as per the THD specification where it is the ratio of the fundamental. Noise is the rms sum of all nonfundamental of the rms sum of the individual distortion products to the rms signals up to half the sampling frequency (f /2), excluding dc. S amplitude of the fundamental expressed in dBs. The ratio is dependent upon the number of quantization levels in Relative Accuracy the digitization process; the more levels, the smaller the quantiza- Relative accuracy or endpoint nonlinearity is the maximum tion noise. The theoretical signal-to-(noise + distortion) ratio for deviation from a straight line passing through the endpoints of an ideal N-bit converter with a sine wave input is given by: the ADC transfer function. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Differential Nonlinearity Thus for an 8-bit converter, this is 50 dB. This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of Offset Error harmonics to the fundamental. For the AD7827 it is defined as: This is the deviation of the 128th code transition (01111111) to (10000000) from the ideal, i.e., V /2 (V = 5 V), 0.8 V /2 REF DD REF 2 2 2 2 2 V +V +V +V +V (V = 3 V). DD 2 3 4 5 6 THD (dB) = 20 log V 1 Zero Scale Error This is the deviation of the first code transition (00000000) to where V is the rms amplitude of the fundamental and V , V , V , 1 2 3 4 (00000001) from the ideal, i.e., V /2 –1.25 V + 1 LSB (V = REF DD V and V are the rms amplitudes of the second through the sixth 5 6 5 V ± 10%), or 0.8 V /2 –1.0 V + 1 LSB (V = 3 V ± 10%). REF DD harmonics. Full-Scale Error Peak Harmonic or Spurious Noise This is the deviation of the last code transition (11111110) to Peak harmonic or spurious noise is defined as the ratio of the (11111111) from the ideal, i.e., V + 1.25 V – 1 LSB (V = MID DD rms value of the next largest component in the ADC output 5 V ± 10%), or V + 1.0 V – 1 LSB (V = 3 V ± 10%). MID DD spectrum (up to f /2 and excluding dc) to the rms value of the S fundamental. Normally, the value of this specification is deter- Gain Error mined by the largest harmonic in the spectrum, but for parts This is the deviation of the last code transition (1111 . . . 110) to where the harmonics are buried in the noise floor, it will be a (1111 . . . 111) from the ideal, i.e., V – 1 LSB, after the offset REF noise peak. error has been adjusted out. Intermodulation Distortion Track/Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and Track/hold acquisition time is the time required for the output fb, any active device with nonlinearities will create distortion of the track/hold amplifier to reach its final value, within products at sum and difference frequencies of mfa ± nfb where ±1/2 LSB, after the point at which the track/hold returns to m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for track mode. This happens approximately 120 ns after the falling which neither m nor n are equal to zero. For example, the sec- edge of CONVST. ond order terms include (fa + fb) and (fa – fb), while the third It also applies when there is a step input change on the input order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). voltage applied to the V input of the AD7827. It means that IN The AD7827 is tested using the CCIF standard where two the user must wait for the duration of the track/hold acquisition input frequencies near the top end of the input bandwidth are time after the end of conversion or after a step input change to used. In this case, the second and third order terms are of dif- V before starting another conversion, to ensure that the part IN ferent significance. The second order terms are usually dis- operates to specification. tanced in frequency from the original sine waves while the third REV. 0 –5– AD7827 CIRCUIT DESCRIPTION of the second flash, and hence the 8-bit conversion result, is The AD7827 consists of a track-and-hold amplifier followed by available at 330 ns. As shown in Figure 4 the track-and-hold a half-flash analog-to-digital converter. This device uses a half- returns to track mode after 120 ns, and so starts the next acqui- flash conversion technique where one 4-bit flash ADC is used to sition before the end of the current conversion. Figure 6 shows achieve an 8-bit result. The 4-bit flash ADC contains a sampling the ADC transfer function. capacitor followed by 15 comparators that compare the unknown input to a reference ladder to get a 4-bit result. This first flash, 120ns i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit TRACK HOLD TRACK HOLD reading to be realized, a second flash, i.e., a fine conversion, t 1 must be performed to provide the 4 LSBs. The 8-bit word is CONVST then placed in the serial shift register. t 2 t 10 Figures 2 and 3 below show simplified schematics of the ADC. RFS t t t 7 4 When the ADC starts a conversion, the track-and-hold goes into 3 t 8 hold mode and holds the analog input for 120 ns. This is the SCLK 1 2 345 6 7 8 acquisition phase as shown in Figure 2 when Switch 2 is in Position A. At the point when the track-and-hold returns to its D DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OUT track mode, this signal is sampled by the sampling capacitor as Switch 2 moves into Position B. The first flash occurs at this Figure 4. Track-and-Hold Timing instant and is then followed by the second flash. Typically the first flash is complete after 100 ns, i.e., at 220 ns, while the end TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7827. The serial interface is implemented using three wires; the RFS is REFERENCE a logic output and the serial clock is continuous. The Receive Frame Sync signal (RFS) idles high, the falling edge of CONVST R16 15 initiates a conversion and the first rising edge of the serial clock SAMPLING R15 after the end of conversion causes the RFS signal to go low. CAPACITOR A 14 V T/H IN This falling edge of RFS is used to drive the RFS on a micro- SW2 B processor—see Serial Interface section for more details. V is HOLD R14 REF D OUT 13 connected to a voltage source such as the AD780, while V is DD . . connected to a voltage source of 3 V ± 10% or 5 V ± 10%. Due R13 . to the proximity of the CONVST and V pins, it is recom- IN . mended to use a 10 nF decoupling capacitor on V . When V IN DD 1 is first connected the AD7827 powers up in a low current mode, R1 i.e., power-down. A rising edge on the CONVST pin will cause TIMING AND the AD7827 to fully power up. For applications where power CONTROL LOGIC consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power perfor- mance. See the Power-Down Options section of this data sheet. Figure 2. ADC Acquisition Phase 2.5V AD780 SUPPLY REFERENCE THREE-WIRE +3V 610% OR 10mF 0.1mF SERIAL INTERFACE +5V 610% R16 15 V V DD REF SAMPLING R15 CAPACITOR A SCLK 14 V T/H IN SW2 0V TO 2.5V (V = 5V) V D DD IN OUT mC/mP B AD7827 HOLD R14 0V TO 2V (V = 3V) DD D OUT RFS 13 INPUT . GND . CONVST R13 . . Figure 5. Typical Connection Diagram 1 R1 TIMING AND CONTROL LOGIC Figure 3. ADC Conversion Phase –6– REV. 0 DECODE LOGIC DECODE LOGIC OUTPUT REGISTER OUTPUT REGISTER OUTPUT DRIVER OUTPUT DRIVER AD7827 ADC TRANSFER FUNCTION that of the multiplexer and the track-and-hold. This resistor is The output coding of the AD7827 is straight binary. The typically about 310 Ω. The capacitor C1 is the track-and-hold designed code transitions occur at successive integer LSB capacitor and has a capacitance of 0.5 pF. Switch 1 is the track- values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V /256 and-hold switch, while Switch 2 is that of the sampling capaci- REF (V = 5 V) or the LSB size = (0.8 V )/256 (V = 3 V). The tor as shown in Figures 2 and 3. DD REF DD ideal transfer characteristic for the AD7827 is shown in Figure 6 When in track phase, Switch 1 is closed and Switch 2 is in below. Position A. When in hold mode, Switch 1 opens while Switch 2 remains in Position A. The track-and-hold remains in hold (V = 5V) DD mode for 120 ns—see Circuit Description, after which it returns 1LSB = V /256 REF 11111111 to track mode and the ADC enters its conversion phase. At this 111....110 point Switch 1 opens and Switch 2 moves to Position B. At the 111....000 end of the conversion Switch 2 moves back to Position A. (V = 3V) DD 10000000 1LSB = 0.8V /256 REF V DD 000....111 C1 D1 000....010 R1 0.5pF SW2 310V A 000....001 V IN 00000000 SW1 C2 B 1LSB (V = 5V) V /2 DD REF D2 4pF (V = 3V) 0.8V /2 DD REF (V = 5V) V /2 – 1.25V V /2+1.25V – 1LSB DD REF REF (V = 3V) 0.8V /2 – 1V 0.8V /2+1V – 1LSB DD REF REF Figure 7. Equivalent Analog Input Circuit Figure 6. Transfer Characteristic The on-chip track-and-hold can accommodate input frequen- cies to 10 MHz, making the AD7827 ideal for subsampling ANALOG INPUT applications. When the AD7827 is converting a 10 MHz input The AD7827 has a single input channel with an input range of signal at a sampling rate of 1 MSPS, the effective number of 0 V to 2.5 V or 0 V to 2.0 V, depending on the supply voltage (V ). This input range is automatically set up by an on-chip bits typically remains above seven corresponding to a signal-to- DD “V detector” circuit. 5 V operation of the ADC is detected noise ratio of 42 dBs as shown in Figure 8. DD when V exceeds 4.1 V and 3 V operation is detected when DD 50 V falls below 3.8 V. This circuit also possesses a degree of DD F = 1MHz SAMPLE glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to 60 ns wide will not trip the V detector. 48 DD Note: Although there is a V pin from which a voltage refer- REF 46 ence of 2.5 V may be sourced, or to which an external reference may be applied, this does not provide an option of varying the value of the voltage reference. As stated in the specifications for the 44 AD7827, the input voltage range at this pin is 2.5 V ± 2%. 42 Analog Input Structure Figure 7 shows an equivalent circuit of the analog input struc- ture of the AD7827. The two diodes, D1 and D2, provide ESD 40 protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by 38 0.2 134 5 6 8 10 more than 200 mV. This will cause these diodes to become INPUT FREQUENCY – MHz forward biased and start conducting current into the substrate. Figure 8. SNR vs. Input Frequency On the AD7827 The maximum current these diodes can conduct without caus- ing irreversible damage to the part is 20 mA. The capacitor C2 in Figure 7 is typically about 4 pF and can mostly be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of several components including REV. 0 –7– ADC CODE SNR – dB AD7827 POWER-UP TIMES For example, if the AD7827 is operated in a continuous sam- The AD7827 has a 1 μs power-up time when using an external pling mode, with a throughput rate of 100 kSPS and using an reference and a 25 μs power-up time when using the on-chip external reference, the power consumption is calculated as reference. When V is first connected, the AD7827 is in a low DD follows. The power dissipation during normal operation is current mode of operation. In order to carry out a conversion 30 mW, V = 3 V. DD the AD7827 must first be powered up. The AD7827 is pow- ered up by a rising edge on the CONVST pin and a conversion t t POWER-UP CONVERT 1ms 330ns is initiated on the falling edge of CONVST. Figure 9 shows POWER-DOWN how to power up the AD7827 when V is first connected or DD CONVST after the ADC has been powered down using the CONVST pin when using either the on-chip, or an external, reference. When t CYCLE using an external reference the falling edge of CONVST may 10ms @ 100kSPS occur before the required power-up time has elapsed; however, Figure 10. Automatic Power-Down the conversion will not be initiated on the falling edge of CONVST but rather at the moment when the part has com- If the power-up time is 1 μs and the conversion time is 330 ns pletely powered up, i.e., after 1 μs. If the falling edge of (@ 25°C), the AD7827 can be said to dissipate 30 mW for 1.33 μs CONVST occurs after the required power-up time has elapsed, (worst case) during each conversion cycle. If the throughput it is upon this falling edge that a conversion is initiated. When rate is 100 kSPS, the cycle time is 10 μs and the average power using the on-chip reference, it is necessary to wait the required dissipated during each cycle is (1.33/10) × (30 mW) = 3.99 mW. power-up time of approximately 25 μs before initiating a con- version, i.e., a falling edge on CONVST may not occur before Figure 11 shows the Power vs. Throughput rate for automatic the required power-up time has elapsed, when V is first con- DD full power-down. nected or after the AD7827 has been powered down using the CONVST pin as shown in Figure 9. 100 EXTERNAL REFERENCE V DD t POWER-UP 1ms 10 CONVST CONVERSION INITIATED HERE 1 ON-CHIP REFERENCE V DD t POWER-UP 25ms 0.1 0 50 100 150 200 250 300 350 400 450 500 CONVST THROUGHPUT – kSPS Figure 11. Power vs. Throughput CONVERSION INITIATED HERE Figure 9. Power-Up Time 0 2048 POINT FFT SAMPLING –10 POWER VS. THROUGHPUT 1MSPS F = 30kHz IN Superior power performance can be achieved by using the –20 automatic power-down (Mode 2) at the end of a conversion (see Operating Modes section of this data sheet). –30 Figure 10 shows how the automatic power-down is implemented –40 using the CONVST signal to achieve the optimum power per- formance for the AD7827. The duration of the CONVST pulse –50 is set to be equal to or less than the power-up time of the de- –60 vices (see Operating Modes section). As the throughput rate is reduced, the device remains in its power-down state for longer and –70 the average power consumption over time drops accordingly. –80 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY – Hz Figure 12. AD7827 SNR –8– REV. 0 dB POWER – mW AD7827 OPERATING MODES Mode 2 Operation (Automatic Power-Down) The AD7827 has two possible modes of operation depending on When the AD7827 is operated in Mode 2 (see Figure 14) it the state of the CONVST pulse at the end of a conversion. automatically powers down 530 ns after the falling edge of CONVST. The CONVST signal is brought low to initiate a Mode 1 Operation (High Speed Sampling) conversion and is left logic low until 530 ns has elapsed after the When the AD7827 is operated in Mode 1 the device is not falling edge of the CONVST pulse, i.e., before Point A or Point powered down between conversions. This mode of operation B in Figure 14, depending on the actual value of t (see Timing 2 allows high throughput rates to be achieved. Figure 13 shows Characteristics). The state of the CONVST signal is sampled at how this optimum throughput rate is achieved by bringing this point (i.e., 530 ns after CONVST falling edge) and the CONVST high before the end of the conversion. When operat- AD7827 will power down as long as the CONVST is low. The ing in this mode, a new conversion should not be initiated until ADC is powered up again on the rising edge of the CONVST 30 ns after the end of a read operation. This is to allow the signal. The CONVST pulse width does not have to be as long as track/hold to acquire the analog signal to 0.5 LSB accuracy. the power-up time if an external reference is used (see Power-Up Times section). Superior power performance can be achieved in this mode of operation by powering up the AD7827 to only carry out a conversion. The serial interface of the AD7827 is still fully operational while the device is powered down. t 2 CONVST t 1 RFS SCLK CURRENT CONVERSION D OUT RESULT Figure 13. Mode 1 Operation Timing Diagram t POWER-UP t 2 CONVST A B RFS SCLK CURRENT CONVERSION D OUT RESULT Figure 14. Mode 2 Operation Timing Diagram REV. 0 –9– AD7827 AD7827 SERIAL INTERFACE synchronize the data with a continuous serial clock. The data In order to achieve a high throughput rate, the serial port of the output pin (D ) is a logic output and serial data is shifted OUT AD7827 has been optimized for high speed serial protocols. out onto this pin on the rising edge of the serial clock. The first Many high speed serial protocols use a continuous serial clock rising edge of the serial clock after the end of a conversion causes to transfer data, e.g., the serial ports of many popular DSPs like the RFS pin to go logic low. (See Figure 15 below.) The D pin OUT the TMS320C5x, ADSP-21xx and DSP560xx. The serial inter- leaves its high impedance state and the first MSB is shifted out face of the AD7827 is optimized for communication with such on the first SCLK rising edge after the end of conversion. The devices. remaining seven data bits are shifted out on subsequent SCLK rising edges. The D pin enters its high impedance state again OUT The serial interface of the AD7827 uses a three-wire interface to on the falling edge of the eighth SCLK after RFS goes low. The communicate with a Master. The serial clock pin (SCLK) is a RFS output goes high again on the rising edge of the ninth SCLK. logic input and determines the bit transfer rate. The Receive If the AD7827 does not receive a ninth SCLK, the RFS will be Frame Synchronization pin (RFS) is a logic output and used to reset logic high by the next falling edge of CONVST. t 1 CONVST t 2 t 10 RFS t t t 7 8 t 4 3 1 2345 6 7 8 SCLK t t 5 6 t 11 D DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OUT t 9 Figure 15. Serial Timing –10– REV. 0 AD7827 MICROPROCESSOR INTERFACING AD7827 to DSP56xxx The Serial Interface on the AD7827 allows the part to be con- The connection diagram in Figure 18 shows how the AD7827 nected directly to a range of many different microprocessors and can be connected to the SSI (Synchronous Serial Interface) of microcontrollers. This section explains how to interface the the DSP56xxx family of DSPs from Motorola. The SSI is oper- AD7827 with some of the more common DSP serial interface ated in Synchronous Mode (SYN bit in CRB = 1) with inter- protocols. nally generated 1-bit clock period frame sync for both TX and RX (FSL1 and FSL0 bits in CRB = 1 and 0 respectively). AD7827 to TMS320C5x The serial interface on the TMS320C5x uses a continuous serial DSP56xxx* AD7827* clock and frame synchronization signals to synchronize the data SCLK SCLK transfer operations with peripheral devices such as the AD7827. A receive frame synchronization output has been supplied on D SRD OUT the AD7827 to allow easy interfacing with no extra gluing logic. RFS SC2 The serial port of the TMS320C5x is set up to operate in Burst Mode with internal CLKX (TX serial clock) and FSR (RX *ADDITIONAL PINS OMITTED FOR CLARITY frame sync). The Serial Port Control register (SPC) must have the following setup: F0 = 1, FSM = 1, MCM = 1. The connec- Figure 18. Interfacing to the DSP56xxx tion diagram is shown in Figure 16. Microcontrollers The AD7827 may also be interfaced to many microcontrollers, TMS320C5x* AD7827* as a continuous serial clock is not essential. However, enough SCLK CLKX time must be left for the conversion to be complete before CLKR applying a burst of serial clocks to read out the data. D DR OUT RFS FSR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 16. Interfacing to the TMS320C5x AD7827 to ADSP-21xx The ADSP-21xx family of DSPs are easily interfaced to the AD7827 without the need for any extra gluing logic. The SPORT is operated in alternate framing mode. The SPORT control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 0111, 8-Bit Data Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0, External Framing Signal ITFS = 1, Internal Framing Signal The 8-bit data words will be right justified in the 16-bit serial data registers when using this configuration. Figure 17 shows the connection diagram. ADSP-21xx* AD7827* SCLK SCLK D DR OUT RFS RFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. Interfacing to the ADSP-21xx REV. 0 –11– AD7827 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 14 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) PIN 1 0.015 (0.38) 0.195 (4.95) 0.210 (5.33) 0.115 (2.93) MAX 0.130 0.160 (4.06) (3.30) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.100 0.022 (0.558) 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 8-Lead Small Outline Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.1574 (4.00) 0.2440 (6.20) 1 4 0.1497 (3.80) 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0098 (0.25) 0.0500 (1.27) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) –12– REV. 0 PRINTED IN U.S.A. C3215–8–1/98