ANALOG DEVICES AD7823

2.7 V to 5.5 V, 5 �s, 8-Bit a ADC in 8-Lead microSOIC/DIP AD7823 FEATURES FUNCTIONAL BLOCK DIAGRAM 8-Bit ADC with 4 �s Conversion Time V V Small Footprint 8-Lead microSOIC Package DD AGND REF Specified Over a –40�C to +125�C Temperature Range Inherent Track-and-Hold Functionality AD7823 CHARGE D OUT SERIAL REDISTRIBUTION PORT Operating Supply Range: 2.7 V to 5.5 V DAC SCLK Specifications at 2.7 V to 5.5 V and 5 V � 10% CLOCK Microcontroller Compatible Serial Interface OSC Optional Automatic Power-Down V IN+ Low Power Operation: CONTROL COMP 570 �W at 10 kSPS Throughput Rate V IN– LOGIC V /3 DD 2.9 mW at 50 kSPS Throughput Rate Analog Input Range: 0 V to V REF Reference Input Range: 0 V to V DD CONVST “Drop In” Upgrade to 10 Bits Available (AD7810) APPLICATIONS Low Power, Hand-Held Portable Applications Requiring Analog-to-Digital Conversion with 8-Bit Accuracy, e.g., Battery-Powered Test Equipment Battery-Powered Communications Systems PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. Complete, 8-Bit ADC in 8-Lead Package The AD7823 is a high speed, low power, 8-bit A/D converter The AD7823 is an 8-bit 4 µs typ ADC with inherent track- that operates from a single 2.7 V to 5.5 V supply. The part con- and-hold functionality and a high speed serial interface—all tains a 4 µs typ successive approximation A/D converter, inherent in an 8-lead microSOIC package. V may be connected to track-and-hold functionality (with a pseudo differential input) REF V to eliminate the need for an external reference. The result and a high speed serial interface that interfaces to most microcon- DD is a high speed, low power, space saving ADC solution. trollers. The AD7823 is fully specified over a temperature range of –40°C to +125°C. 2. Low Power, Single Supply Operation The AD7823 operates from a single 2.7 V to 5.5 V supply and By using a technique that samples the state of the CONVST typically consumes only 9 mW of power. The power dissipa- (convert start) signal at the end of a conversion, the AD7823 tion can be significantly reduced at lower throughput rates by may be used in an automatic power-down mode. When used in using the automatic power-down mode, e.g., at a throughput this mode, the AD7823 powers down automatically at the end rate of 10 kSPS the power consumption is only 570µW. of a conversion and “wakes up” at the start of a new conversion. This feature significantly reduces the power consumption of the 3. Automatic Power-Down part at lower throughput rates. The AD7823 can also operate in The automatic power-down mode, whereby the AD7823 a high speed mode where the part is not powered down between “powers down” at the end of a conversion and “wakes up” conversions. In this high speed mode of operation, the conver- before the next conversion, means the AD7823 is ideal for sion time of the AD7823 is 4 µs typ. The maximum throughput battery powered applications. See Power vs. Throughput rate is dependent on the speed of the serial interface of the Rate section. microcontroller. 4. Serial Interface The part is available in a small, 8-lead 0.3" wide, plastic dual-in- An easy to use, fast serial interface allows connection to most line package (mini-DIP); in an 8-lead, small outline IC (SOIC); popular microprocessors with no external circuitry. and in an 8-lead microSOIC package. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD7823–SPECIFICATIONS (GND = 0 V, V = V . All specifications –40�C to +125�C unless otherwise noted.) REF DD Parameter Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz, f = 133 kHz IN SAMPLE 1, 2 Signal to (Noise + Distortion) Ratio 48 dB min 1 Total Harmonic Distortion –70 dB typ 1 Peak Harmonic or Spurious Noise –70 dB typ 2 Intermodulation Distortion fa = 48 kHz, fb = 48.5 kHz 2nd Order Terms –77 dB typ 3rd Order Terms –77 dB typ DC ACCURACY Resolution 8 Bits 1 Relative Accuracy ±0.5 LSB max 1 Differential Nonlinearity (DNL) ±0.5 LSB max 1 Gain Error ±1LSB max 1 Offset Error ±1LSB max 1 Total Unadjusted Error ±1LSB max Minimum Resolution for Which No Missing Codes Are Guaranteed 8 Bits ANALOG INPUT Input Voltage Range 0 V min V V max REF 2 ±1 µA max Input Leakage Current 2 Input Capacitance 15 pF max 2 REFERENCE INPUTS V Input Voltage Range 1.2 V min REF V V max DD Input Leakage Current ±1 µA max Input Capacitance 20 pF max 2 LOGIC INPUTS V , Input High Voltage 2.0 V min INH V , Input Low Voltage 0.4 V max INL Input Current, I ±1 µA max Typically 10 nA, V = 0 V to V IN IN DD Input Capacitance, C 8 pF max IN LOGIC OUTPUTS Output High Voltage, V 2.4 V min I = 200 µA OH SOURCE Output Low Voltage, V 0.4 V max I = 200 µA OL SINK High Impedance Leakage Current ±1 µA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 4 µs typ 1 Track/Hold Acquisition Time 100 ns max See DC Acquisition Section POWER SUPPLY V 2.7–5.5 Volts For Specified Performance DD I 3.5 mA max Sampling at 133 kSPS and Logic DD Inputs @ V or 0 V. V = 5 V DD DD Power Dissipation 17.5 mW max Nominal Supplies Power-Down Mode I 1 µA max DD Power Dissipation 5 µW max Nominal Supplies Automatic Power Down V = 3 V DD 1 kSPS Throughput 54 µW max 10 kSPS Throughput 540 µW max 50 kSPS Throughput 2.7 mW max NOTES 1 See Terminology. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. REV. C –2– AD7823 1, 2 (–40�C to +125�C, unless otherwise noted) TIMING CHARACTERISTICS Parameter V = 5 V � 10% V = 3 V � 10% Unit Conditions/Comments DD DD t 55 µs (max) Conversion Time Mode 1 Operation (High Speed Mode) 1 t 20 20 ns (min) CONVST Pulsewidth 2 t 25 25 ns (min) SCLK High Pulsewidth 3 t 25 25 ns (min) SCLK Low Pulsewidth 4 3 t 5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time 5 3 t 10 10 ns (max) SCLK Rising Edge to D Data Valid Delay 6 OUT 3 t 5 5 ns (max) Data Hold Time after Rising Edge SCLK 7 3, 4 t 20 20 ns (max) Bus Relinquish Time after Falling Edge of SCLK 8 10 10 ns (min) t 1.5 1.5 µs (max) Power-Up Time POWERUP NOTES 1 Sample tested to ensure compliance. 2 See Figures 14, 15 and 16. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V = 5 V ± 10% and DD 0.4 V or 2 V for V = 3 V ± 10%. DD 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t , is the true bus relinquish time 8 of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW (T = 25°C unless otherwise noted) A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W JA V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W JC Digital Input Voltage to GND Lead Temperature, Soldering (CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Digital Output Voltage to GND Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C (D ) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V OUT DD MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V REF DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W JA Analog Inputs θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W JC (V , V ) . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN+ IN– DD Lead Temperature, Soldering Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW *Stresses above those listed under Absolute Maximum Ratings may cause perma- θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W JA nent damage to the device. This is a stress rating only; functional operation of the θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W device at these or any other conditions above those listed in the operational JC sections of this specification is not implied. Exposure to absolute maximum rating Lead Temperature, Soldering (10 sec) . . . . . . . . . . . 260°C conditions for extended periods may affect device reliability. ORDERING GUIDE Linearity Temperature Branding Package Model Error Range Information Option* AD7823YN ±1 LSB –40°C to +125°C N-8 AD7823YR ±1 LSB –40°C to +125°C SO-8 AD7823YRM ±1 LSB –40°C to +125°C C2Y RM-8 *N = plastic DIP; RM = microSOIC; SO = small outline IC (SOIC). I OL 200mA TO OUTPUT 1.6V PIN C L 50pF I OH 200�A Figure 1. Load Circuit for Digital Output Timing Specifications REV. C –3– AD7823 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion. A rising edge on the CONVST pin enables the serial port of the AD7823. This is useful in multipackage applications where a number of devices share the same serial bus. The state of this pin at the end of conversion also determines whether the part is powered down or not. See Operating Modes section of this data sheet. 2V Positive input of the pseudo differential analog input. IN+ 3V Negative input of the pseudo differential analog input. IN– 4 GND Ground reference for analog and digital circuitry. 5V External reference is connected here. REF 6D Serial data is shifted out on this pin. OUT 7 SCLK Serial Clock. An external serial clock is applied here. 8V Positive Supply Voltage 2.7 V to 5.5 V. DD PIN CONFIGURATION DIP/SOIC/microSOIC CONVST 1 8 V DD V SCLK 2 7 IN+ AD7823 TOP VIEW V 3 6 D OUT IN– (Not to Scale) 5 GND 4 V REF REV. C –4– AD7823 TERMINOLOGY The AD7823 is tested using the CCIF standard where two input Signal to (Noise + Distortion) Ratio frequencies near the top end of the input bandwidth are used. This is the measured ratio of signal to (noise + distortion) at the In this case, the second and third order terms are of different output of the A/D converter. The signal is the rms amplitude of significance. The second order terms are usually distanced in the fundamental. Noise is the rms sum of all nonfundamental frequency from the original sine waves while the third order signals up to half the sampling frequency (f /2), excluding dc. terms are usually at a frequency close to the input frequencies. S The ratio is dependent upon the number of quantization levels As a result, the second and third order terms are specified sepa- in the digitization process; the more levels, the smaller the rately. The calculation of the intermodulation distortion is as quantization noise. The theoretical signal to (noise + distortion) per the THD specification where it is the ratio of the rms sum of ratio for an ideal N-bit converter with a sine wave input is the individual distortion products to the rms amplitude of the given by: fundamental expressed in dBs. Signal to (Noise + Distortion) = (6.02N + 1.76) dB Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum Thus for an 8-bit converter, this is 50 dB. deviation from a straight line passing through the endpoints of Total Harmonic Distortion the ADC transfer function. Total harmonic distortion (THD) is the ratio of the rms sum of Differential Nonlinearity harmonics to the fundamental. For the AD7823 it is defined as: This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD (dB)= 20 log Offset Error V 1 This is the deviation of the first code transition (0000 . . . 000) where V is the rms amplitude of the fundamental and V , V , 1 2 3 to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB. V , V and V are the rms amplitudes of the second through the 4 5 6 Gain Error sixth harmonics. This is the deviation of the last code transition (1111 . . . 110) Peak Harmonic or Spurious Noise to (1111 . . . 111) from the ideal (i.e., V – 1 LSB) after the REF Peak harmonic or spurious noise is defined as the ratio of the offset error has been adjusted out. rms value of the next largest component in the ADC output Track/Hold Acquisition Time spectrum (up to f /2 and excluding dc) to the rms value of S Track/hold acquisition time is the time required for the output the fundamental. Normally, the value of this specification is of the track/hold amplifier to reach its final value, within determined by the largest harmonic in the spectrum, but for ±1/2 LSB, after the end of conversion (the point at which the parts where the harmonics are buried in the noise floor, it track/hold returns to track mode). It also applies to situations will be a noise peak. where there is a step input change on the input voltage applied Intermodulation Distortion to the V input of the AD7823. It means that the user must IN+ With inputs consisting of sine waves at two frequencies, fa and wait for the duration of the track/hold acquisition time, after the fb, any active device with nonlinearities will create distortion end of conversion or after a step input change to V , before IN products at sum and difference frequencies of mfa ± nfb where starting another conversion to ensure that the part operates to m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which specification. neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Typical Performance Characteristics 10 0 AD7823 –10 2048 POINT FFT SAMPLING 136.054 –20 f 29.961 IN –30 0 –40 –50 –60 0.1 –70 –80 –90 0.01 –100 03 10 200 40 50 THROUGHPUT – kSPS FREQUENCY BINS Figure 2. Power vs. Throughput Figure 3. AD7823 SNR REV. C –5– POWER – mW dBs 1 23 45 67 89 111 133 155 177 199 221 243 265 287 309 331 353 375 397 419 441 463 485 507 529 551 573 595 617 639 661 683 705 727 749 771 793 815 837 859 881 903 925 947 969 991 1013 AD7823 SUPPLY CIRCUIT DESCRIPTION 2.7V TO 5.5V TWO-WIRE 10�F 0.1�F Converter Operation SERIAL INTERFACE The AD7823 is a successive approximation analog-to-digital converter based around a charge redistribution DAC. The ADC V V DD REF 0V TO V REF V SCLK can convert analog input signals in the range 0 V to V . Figures IN+ DD INPUT 4 and 5 below show simplified schematics of the ADC. Figure 4 AD7823 �C/�P V D IN– OUT shows the ADC during its acquisition phase. SW2 is closed and CONVST AGND SW1 is in Position A; the comparator is held in a balanced condi- tion; and the sampling capacitor acquires the signal on V . IN+ Figure 6. Typical Connection Diagram CHARGE Analog Input REDISTRIBUTION Figure 7 shows an equivalent circuit of the analog input struc- DAC SAMPLING ture of the AD7823. The two diodes, D1 and D2, provide ESD CAPACITOR A V IN+ protection for the analog inputs. Care must be taken to ensure CONTROL SW1 LOGIC that the analog input signal never exceeds the supply rails by B ACQUISITION SW2 PHASE more than 200 mV. This will cause these diodes to become COMPARATOR CLOCK forward biased and start conducting current into the substrate. V V /3 IN– OSC DD The maximum current these diodes can conduct without caus- ing irreversible damage to the part is 20 mA. The capacitor C2 Figure 4. ADC Acquisition Phase is typically about 4 pF and can be primarily attributed to pin When the ADC starts a conversion (see Figure 5) SW2 will capacitance. The resistor R1 is a lumped component made up of open, and SW1 will move to Position B causing the comparator the on resistance of a multiplexer and a switch. This resistor is to become unbalanced. The control logic and the charge redis- typically about 125 Ω. The capacitor C1 is the ADC sampling tribution DAC are used to add and subtract fixed amounts of capacitor and has a capacitance of 3.5 pF. charge from the sampling capacitor in order to bring the com- parator back into a balanced condition. When the comparator V DD is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 11 shows the ADC D1 C1 R1 3.5pF transfer function. 125� V V /3 IN+ DD C2 D2 4pF CHARGE REDISTRIBUTION CONVERT PHASE – SWITCH OPEN DAC SAMPLING ACQUISITION PHASE – SWITCH CLOSED CAPACITOR A V IN+ CONTROL Figure 7. Equivalent Analog Input Circuit SW1 LOGIC B CONVERSION SW2 PHASE The analog input of the AD7823 is made up of a pseudo dif- COMPARATOR ferential pair, V pseudo differential with respect to V . The CLOCK IN+ IN– V V /3 IN– DD OSC signal is applied to V but in the pseudo differential scheme IN+ the sampling capacitor is connected to V during conversion— IN– Figure 5. ADC Conversion Phase see Figure 8. This input scheme can be used to remove offsets that exist in a system. For example, if a system had an offset of TYPICAL CONNECTION DIAGRAM 0.5 V, the offset could be applied to V and the signal applied IN– Figure 6 shows a typical connection diagram for the AD7823. to V . This has the effect of offsetting the input span by 0.5 V. IN+ The serial interface is implemented using two wires; the rising It is only possible to offset the input span when the reference volt- edge of CONVST enables the serial interface—see Serial age (V ) is less than V – V . REF DD OFFSET Interface section for more details. V is connected to a well REF decoupled V pin to provide an analog input range of 0 V to DD CHARGE V . When V is first connected, the AD7823 powers up in DD DD REDISTRIBUTION a low current mode, i.e., power-down. A rising edge on the DAC SAMPLING CONVST input will cause the part to power up—see Operating COMPARATOR CAPACITOR Modes. If power consumption is of concern, the automatic power- V IN+ CONTROL V (+) IN down at the end of a conversion should be used to improve LOGIC CONVERSION V OFFSET SW2 power performance. See Power vs. Throughput Rate section of PHASE the data sheet. V IN– CLOCK V /3 OSC DD V OFFSET Figure 8. Pseudo Differential Input Scheme REV. C –6– AD7823 When using the pseudo differential input scheme the signal on For small values of source impedance, the settling time associated V must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition IN– sion process. If the signal on V varies during conversion, the time of the ADC. For example, with a source impedance (R2) IN– conversion result will be incorrect. For single ended operation, V of 10 Ω, the charge time for the sampling capacitor is approxi- IN– is always connected to AGND. Figure 9 shows the AD7823 pseudo mately 2 ns. The charge time becomes significant for source differential input being used to make a unipolar dc current mea- impedances of 4.6 kΩ and greater. surement. A sense resistor is used to convert the current to a AC Acquisition Time voltage, and the voltage is applied to the differential input as In ac applications it is recommended to always buffer analog shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of V DD the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor- V IN+ mance can generally be achieved by using an external 1 nF R SENSE AD7823 capacitor on V . IN+ V IN– R L ADC TRANSFER FUNCTION The output coding of the AD7823 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V /256. The ideal trans- REF Figure 9. DC Current Measurement Scheme fer characteristic for the AD7823 is shown in Figure 11 below. DC Acquisition Time The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the 111...111 end of a conversion there is a settling time associated with the 111...110 sampling circuit. This settling time lasts approximately 100 ns. The analog signal on V is also being acquired during this IN+ settling time; therefore, the minimum acquisition time needed is approximately 100 ns. 111...000 Figure 10 shows the equivalent charging circuit for the sampling 011...111 capacitor when the ADC is in its acquisition phase. R2 represents 1LSB = V /256 REF the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance and C1 is the sampling 000...010 capacitor. 000...001 000...000 R1 V 0V 1LSB +V –1LSB 125� REF R2 IN+ ANALOG INPUT C1 3.5�F Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (t ) is given by the follow- CHARGE ing formula: t = 6.2 × (R2 + 125 Ω) × 3.5 pF CHARGE REV. C –7– ADC CODE AD7823 POWER-UP TIMES OPERATING MODES The AD7823 has a 1.5 µs power-up time. When V is first Mode 1 Operation (High Speed Sampling) DD connected, the AD7823 is in a low current mode of operation. When the AD7823 is used in this mode of operation, the part is In order to carry out a conversion, the AD7823 must first be not powered down between conversions. This mode of opera- powered up. The ADC is powered up by a rising edge on the tion allows high throughput rates to be achieved. The timing CONVST pin. A conversion is initiated on the falling edge of diagram in Figure 14 shows how this optimum throughput rate CONVST. Figure 12 shows how to power up the AD7823 when is achieved by bringing the CONVST signal high before the end V is first connected or after the AD7823 is powered down of the conversion. It is recommended that the CONVST signal DD using the CONVST pin. should go high within 3 µs of conversion starting. This ensures that the CONVST signal does not go high at the same time the Care must be taken to ensure that the CONVST pin of the part is attempting to power down. The AD7823 leaves its tracking AD7823 is logic low when V is first applied. DD mode and goes into hold on the falling edge of CONVST. A conversion is also initiated at this time and takes 4 µs typ to MODE 1 (CONVST IDLES HIGH) complete. At this point, the result of the current conversion is V t DD 1µs latched into the serial shift register, and the state of the CONVST POWER-UP 1.5�s signal is checked. The CONVST signal should be high at the CONVST end of the conversion to prevent the part from powering down. MODE 2 (CONVST IDLES LOW) t 1 V DD t POWER-UP CONVST 1.5�s A t B 2 CONVST SCLK Figure 12. Power-Up Times CURRENT CONVERSION D OUT RESULT POWER VS. THROUGHPUT RATE By operating the AD7823 in Mode 2, the average power con- Figure 14. Mode 1 Operation Timing sumption of the AD7823 decreases at lower throughput rates. The serial port on the AD7823 is enabled on the rising edge of Figure 13 shows how the automatic power-down is implemented the CONVST signal–see Serial Interface section. As explained using the CONVST signal to achieve the optimum power per- earlier, this rising edge should occur before the end of the con- formance for the AD7823. The AD7823 is operated in Mode 2. version process if the part is not to be powered down. A serial As the throughput rate is reduced, the device remains in its read can take place at any stage after the rising edge of CONVST. power-down state for longer, and the average power consump- If a serial read is initiated before the end of the current conver- tion over time drops accordingly. sion process (i.e., at time “A”), then the result of the previous conversion is shifted out on the D pin. It is possible to allow t OUT CONVERT 5�s the serial read to extend beyond the end of a conversion. In this t POWER-UP 1.5�s POWER-DOWN case, the new data will not be latched into the output shift regis- ter until the read has finished. If the user waits until the end of CONVST the conversion process, i.e., 4 µs typ after falling edge of CONVST t CYCLE (Point “B”), before initiating a read, the current conversion 100�s @ 10kSPS result is shifted out. Figure 13. Automatic Power-Down For example, if the AD7823 is operated in a continuous sampling mode with a throughput rate of 10 kSPS, the power consumption is calculated as follows. The power dissipation during normal operation is 10.5 mW, V = 3 V. If the power-up time is 1.5 µs DD and the conversion time is 5 µs, then the AD7823 can be said to dissipate 10.5 mW for 6.5 µs (worst case) during each conver- sion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs, and the average power dissipated during each cycle is (6.5/100) × (10.5 mW) = 683 µW. Figure 2 shows a graph of Power vs. Throughput. REV. C –8– AD7823 Mode 2 Operation (Automatic Power-Down) high for 1.5µs after the rising edge before bringing it low to When used in this mode of operation, the part automatically initiate a conversion. If the CONVST signal goes low before powers down at the end of a conversion. This is achieved by 1.5µs in time has elapsed, the power-up time is timed out inter- leaving the CONVST signal low until the end of the conversion. nally and a conversion is initiated. Hence the AD7823 is guaran- The timing diagram in Figure 15 shows how to operate the part teed to have always powered up before a conversion is initiated— in this mode. If the AD7823 is powered down, the rising edge of even if the CONVST pulsewidth is <1.5µs. If the CONVST width is >1.5µs a conversion is initiated on the falling edge. the CONVST pulse causes the part to power up. When the part has powered up (≈ 1.5 µs after the rising edge of CONVST), the CONVST signal is brought low, and a conversion is initiated SERIAL INTERFACE The serial interface of the AD7823 consists of three wires, a on this falling edge of the CONVST signal. The conversion takes 5 µs max and after this time, the conversion result is latched serial clock input SCLK, serial port enable CONVST and a into the serial shift register and the part powers down. Therefore, serial data output D , see Figure 16 below. The serial inter- OUT face is designed to allow easy interfacing to most microcontrollers, when the part is operated in Mode 2, the effective conversion time is equal to the power-up time (1.5 µs) and the SAR conver- e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any sion time (5 µs), i.e., 6.5µs. gluing logic. When interfacing to the 8051, the SCLK must be inverted. The “Microprocessor Interface” section explains how As in the case of Mode 1 operation, the rising edge of the to interface to some popular microcontrollers. CONVST pulse enables the serial port of the AD7823—see Serial Interface section. If a serial read is initiated soon after this Figure 16 shows the timing diagram for a serial read from the rising edge (Point “A”), i.e., before the end of the conversion, AD7823. The serial interface works with both a continuous and a noncontinuous serial clock. The rising edge of the CONVST then the result of the previous conversion is shifted out on pin D . In order to read the result of the current conversion, the signal RESETS a counter, which counts the number of serial OUT user must wait at least 5 µs max after the falling edge of CONVST clocks to ensure the correct number of bits are shifted out of the before initiating a serial read. The serial port of the AD7823 is serial shift registers. The SCLK is ignored once the correct still functional even though the AD7823 has been powered number of bits have been shifted out. In order for another serial down. Note: A serial read should not cross the reset rising edge transfer to take place, the counter must be reset by the falling edge of the eighth SCLK. Data is clocked out from the D of CONVST. OUT line on the first rising SCLK edge after the rising edge of the Because it is possible to do a serial read from the part while it is CONVST signal and on subsequent SCLK rising edges. The powered down, the AD7823 is powered up only to do the conver- D pin goes back into a high impedance state on the falling OUT sion and is immediately powered down at the end of a conversion. edge of the eighth SCLK. In multipackage applications, the This significantly improves the power consumption of the part CONVST signal can be used as a chip select signal. The serial at slower throughput rates—see Power vs. Throughput Rate interface will not shift data out until it receives a rising edge on section. the CONVST pin. Note: Although the AD7823 takes 1.5µs to power up after the rising edge of CONVST, it is not necessary to leave CONVST t POWER-UP t 1 1.5�s CONVST SCLK A B CURRENT CONVERSION D OUT RESULT Figure 15. Mode 2 Operation Timing t 3 SCLK 12 3 4 56 7 8 t t 4 5 CONVST t 7 t 8 t 6 D DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OUT Figure 16. Serial Interface Timing REV. C –9– AD7823 MICROPROCESSOR INTERFACING AD7823 to 8051 The serial interface on the AD7823 allows the parts to be directly The AD7823 requires a clock synchronized to the serial data; connected to a range of many different microprocessors. This therefore, the 8051 serial interface must be operated in Mode 0. section explains how to interface the AD7823 with some of the In this mode serial data enters and exits through RXD, and a serial more common microcontroller serial interface protocols. clock is output on TXD (half duplex). Figure 19 shows how the 8051 is connected to the AD7823. Here, because the AD7823 AD7823 to PIC16C6x/7x shifts data out on the rising edge of the serial clock, the serial The PIC16C6x Synchronous Serial Port (SSP) is configured clock must be inverted. as an SPI Master with the Clock Polarity Bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See PIC16/17 Microcontroller User Manual. Figure AD7823* 8051* 17 shows the hardware connections needed to interface to the SCLK TXD PIC16/PIC17. In this example I/O port RA1 is being used to D RXD OUT pulse CONVST and enable the serial port of the AD7823. CONVST P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY AD7823* PIC16C6x/7x* SCLK SCK/RC3 Figure 19. Interfacing to the 8051 Serial Port D SDO/RC5 OUT It is possible to implement a serial interface using the data ports CONVST RA1 on the 8051 (or any microcontroller). This would allow direct interfacing between the AD7823 and 8051 to be implemented *ADDITIONAL PINS OMITTED FOR CLARITY without the need for any “gluing” logic. The technique involves Figure 17. Interfacing to the PIC16/PIC17 “bit banging” an I/O port (e.g., P1.0) to generate a serial clock and using another I/O port (e.g., P1.1) to read in data, see AD7823 to MC68HC11 Figure 20. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 0), Clock Polarity Bit (CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is AD7823* 8051* configured by writing to the SPI Control Register (SPCR)—see SCLK P1.0 68HC11 User Manual. A connection diagram is shown in D P1.1 OUT Figure 18. CONVST P1.2 AD7823* MC68HC11* *ADDITIONAL PINS OMITTED FOR CLARITY SCLK SCLK/PD4 Figure 20. Interfacing to the 8051 Using I/O Ports D MISO/PD2 OUT CONVST PA0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 18. Interfacing to the MC68HC11 REV. C –10– AD7823 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 14 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) PIN 1 0.015 (0.38) 0.195 (4.95) 0.210 (5.33) 0.115 (2.93) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 8-Lead Small Outline Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.1574 (4.00) 0.2440 (6.20) 1 4 0.1497 (3.80) 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50) x 45� 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8� 0.0500 0.0192 (0.49) 0� SEATING 0.0098 (0.25) 0.0500 (1.27) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) 8-Lead microSOIC Package (RM-8) 0.122 (3.10) 0.114 (2.90) 85 0.122 (3.10) 0.199 (5.05) 0.114 (2.90) 0.187 (4.75) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.84) 0.112 (2.84) 0.043 (1.09) 0.006 (0.15) 0.037 (0.94) 0.002 (0.05) 33� 0.018 (0.46) 27� SEATING 0.011 (0.28) 0.028 (0.71) 0.008 (0.20) PLANE 0.003 (0.08) 0.016 (0.41) REV. C –11– C01322a–0–10/00 (rev. C) PRINTED IN U.S.A.