ANALOG DEVICES AD7813

2.7 V to 5.5 V, 400 kSPS a 8-/10-Bit Sampling ADC AD7813 FUNCTIONAL BLOCK DIAGRAM FEATURES 8-/10-Bit ADC with 2.3 �s Conversion Time On-Chip Track and Hold V V DD AGND REF Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V–3.6 V and 5 V � 10% DB7 AD7813 CHARGE 8-Bit Parallel Interface THREE- REDISTRIBUTION 8-Bit + 2-Bit Read STATE DAC DRIVERS Power Performance CLOCK DB0 Normal Operation OSC 10.5 mW, V = 3 V DD Automatic Power-Down CONTROL COMP V T/H IN LOGIC 34.6 �W @ 1 kSPS, V = 3 V DD Analog Input Range: 0 V to V REF Reference Input Range: 1.2 V to V DD BUSY CS RD CONVST GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7813 is a high-speed, microprocessor-compatible, 1. Low Power, Single Supply Operation 8-/10-bit analog-to-digital converter with a maximum through- The AD7813 operates from a single 2.7 V to 5.5 V supply put of 400 kSPS. The converter operates off a single 2.7 V to and typically consumes only 10.5 mW of power. The power 5.5 V supply and contains a 2.3 µs successive approximation dissipation can be significantly reduced at lower through- A/D converter, track/hold circuitry, on-chip clock oscillator and put rates by using the automatic power-down mode. 8-bit wide parallel interface. The parallel interface is designed to 2. Automatic Power-Down allow easy interfacing to microprocessors and DSPs. The 10-bit The automatic power-down mode, whereby the AD7813 conversion result is read by carrying out two 8-bit read opera- goes into power-down mode at the end of a conversion and tions. The first read operation accesses the 8 MSBs of the ADC powers up before the next conversion, means the AD7813 conversion result and the second read accesses the 2 LSBs. is ideal for battery powered applications; e.g., 34.6 µW Using only address decoding logic the AD7813 is easily mapped @ 1 kSPS. (See Power vs. Throughput Rate section.) into the microprocessor address space. 3. Parallel Interface When used in its power-down mode, the AD7813 automatically An easy to use 8-bit-wide parallel interface allows interfacing powers down at the end of a conversion and powers up at the to most popular microprocessors and DSPs with minimal start of a new conversion. This feature significantly reduces the external circuitry. power consumption of the part at lower throughput rates. The 4. Dynamic Specifications for DSP Users AD7813 can also operate in a high speed mode where the part is In addition to the traditional ADC specifications, the AD7813 not powered down between conversions. In this mode of opera- is specified for ac parameters, including signal-to-noise ratio tion the part is capable of providing 400 kSPS throughput. and distortion. The part is available in a small, 16-lead, 0.3" wide, plastic dual- in-line package (DIP), in a 16-lead, 0.15" wide, narrow body small outline IC (SOIC) and in a 16-lead thin shrink small outline package (TSSOP). REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 (GND = 0 V, V = V = 3 V � 10% to 5 V � 10%. All specifications –40�C to REF DD 1 +105�C unless otherwise noted.) AD7813–SPECIFICATIONS Parameter Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz, f = 350 kHz IN SAMPLE 1 Signal to (Noise + Distortion) Ratio 58 dB min 1 Total Harmonic Distortion (THD) –66 dB max 1 Peak Harmonic or Spurious Noise –66 dB max 2 Intermodulation Distortion fa = 29.1 kHz, fb = 29.8 kHz 2nd Order Terms –67 dB typ 3rd Order Terms –67 dB typ DC ACCURACY Resolution 10 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 10 Bits 1 Relative Accuracy ±1 LSB max 1 Differential Nonlinearity (DNL) ±1 LSB max 1 Gain Error ±2 LSB max 1 Offset Error ±2.0 LSB max ANALOG INPUT Input Voltage Range 0 V min V V max REF 2 Input Leakage Current ±1 µA max 2 Input Capacitance 20 pF max 2 REFERENCE INPUTS V Input Voltage Range 1.2 V min REF V V max DD Input Leakage Current ±3 µA max Input Capacitance 15 pF max 2 LOGIC INPUTS V Input High Voltage 2.0 V min INH, V Input Low Voltage 0.4 V max (0.8 V max, V = 5 V) INL, DD Input Current, I ±1 µA max Typically 10 nA, V = 0 V to V IN IN DD Input Capacitance, C 8 pF max IN LOGIC OUTPUTS Output High Voltage, V 2.4 V min I = 200 µA OH SOURCE Output Low Voltage, V 0.4 V max I = 200 µA OL SINK High Impedance Leakage Current ±1 µA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 2.3 µs max 1 Track/Hold Acquisition Time 100 ns max POWER SUPPLY V 2.7–5.5 Volts For Specified Performance DD I Digital Inputs = 0 V or V DD DD Normal Operation 3.5 mA max Power-Down 1 µA max V = 5 V DD Power Dissipation Normal Operation 17.5 mW max V = 5 V DD Power-Down 5 µW max Auto Power-Down V = 3 V DD 1 kSPS Throughput 34.6 µW max 10 kSPS Throughput 346.5 µW max 100 kSPS Throughput 3.46 mW max NOTES 1 See Terminology section. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. REV. C –2– AD7813 1, 2 (–40�C to +105�C, unless otherwise noted) TIMING CHARACTERISTICS Parameter V = 3 V � 10% V = 5 V � 10% Unit Conditions/Comments DD DD t 1.5 1.5 µs (max) Power-Up Time of AD7813 after Rising Edge of CONVST. POWER-UP t 2.3 2.3 µs (max) Conversion Time. 1 t 20 20 ns (min) CONVST Pulsewidth. 2 t 30 30 ns (max) CONVST Falling Edge to BUSY Rising Edge Delay. 3 t 0 0 ns (min) CS to RD Setup Time. 4 t 0 0 ns (min) CS Hold Time after RD High. 5 3 t 10 10 ns (max) Data Access Time after RD Low. 6 3, 4 t 10 10 ns (max) Bus Relinquish Time after RD High. 7 5 5 ns (min) t 10 10 ns (min) Minimum Time Between MSB and LSB Reads. 8 3 t 50 50 ns (min) Rising Edge of CS or RD to Falling Edge of CONVST Delay. 9 NOTES 1 Sample tested to ensure compliance. 2 See Figures 12, 13 and 14. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V = 5 V ± 10% and DD 0.4 V or 2 V for V = 3 V ± 10%. DD 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the Timing Characteristics is the true bus relinquish time 7 of the part and as such is independent of external bus loading capacitances. ABSOLUTE MAXIMUM RATINGS* V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V 200�AI DD OL Digital Input Voltage to DGND (CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD TO 1.6V OUTPUT Digital Output Voltage to DGND PIN C L (BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD 50pF REF to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN DD 200�A I OH Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Figure 1. Load Circuit for Digital Output Timing Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW Specifications θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W JA Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW ORDERING GUIDE θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W JA Linearity Package Package Lead Temperature, Soldering Model Error Description Option Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C AD7813YN ±1 LSB Plastic DIP N-16 SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW AD7813YR ±1 LSB Small Outline IC R-16A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W JA AD7813YRU ±1 LSB Thin Shrink Small Outline RU-16 Lead Temperature, Soldering (TSSOP) Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7813 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. C –3– AD7813 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1V Reference Input, 1.2 V to V . REF DD 2V Analog Input, 0 V to V . IN REF 3 GND Analog and Digital Ground. 4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an internally generated CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7813 automatically powers down. 5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs. 6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high impedance state and data is driven onto the data bus. 7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process. 8–15 DB0–DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible. 16 V Positive power supply voltage, 2.7 V to 5.5 V. DD PIN CONFIGURATION DIP/SOIC V 1 16 V REF DD V DB7 2 15 IN GND DB6 3 14 AD7813 CONVST DB5 4 13 TOP VIEW CS DB4 5 12 (Not to Scale) RD DB3 6 11 BUSY DB2 7 10 DB0 8 DB1 9 REV. C –4– AD7813 in frequency from the original sine waves, while the third order TERMINOLOGY terms are usually at a frequency close to the input frequencies. Signal to (Noise + Distortion) Ratio As a result, the second and third order terms are specified sepa- This is the measured ratio of signal to (noise + distortion) at the rately. The calculation of the intermodulation distortion is as output of the A/D converter. The signal is the rms amplitude of per the THD specification where it is the ratio of the rms sum the fundamental. Noise is the rms sum of all nonfundamental of the individual distortion products to the rms amplitude of the signals up to half the sampling frequency (f /2), excluding dc. S fundamental expressed in dBs. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- Relative Accuracy tization noise. The theoretical signal to (noise + distortion) ratio Relative accuracy or endpoint nonlinearity is the maximum for an ideal N-bit converter with a sine wave input is given by: deviation from a straight line passing through the endpoints of the ADC transfer function. Signal to (Noise + Distortion) = (6.02N + 1.76) dB Differential Nonlinearity Thus for an 10-bit converter, this is 62 dB. This is the difference between the measured and the ideal Total Harmonic Distortion 1 LSB change between any two adjacent codes in the ADC. Total harmonic distortion (THD) is the ratio of the rms sum of Offset Error harmonics to the fundamental. For the AD7813 it is defined as: This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB. 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD (dB)= 20 log Offset Error Match V 1 This is the difference in Offset Error between any two channels. where V is the rms amplitude of the fundamental and V , V , 1 2 3 Gain Error V , V and V are the rms amplitudes of the second through the 4 5 6 This is the deviation of the last code transition (1111 . . . 110) sixth harmonics. to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the Peak Harmonic or Spurious Noise offset error has been adjusted out. Peak harmonic or spurious noise is defined as the ratio of the Gain Error Match rms value of the next largest component in the ADC output This is the difference in Gain Error between any two channels. spectrum (up to f /2 and excluding dc) to the rms value of the S Track/Hold Acquisition Time fundamental. Normally, the value of this specification is deter- Track/hold acquisition time is the time required for the output mined by the largest harmonic in the spectrum, but for parts of the track/hold amplifier to reach its final value, within where the harmonics are buried in the noise floor, it will be a ±1/2 LSB, after the end of conversion (the point at which the noise peak. track/hold returns to track mode). It also applies to situations Intermodulation Distortion where a change in the selected input channel takes place or With inputs consisting of sine waves at two frequencies, fa and where there is a step input change on the input voltage applied fb, any active device with nonlinearities will create distortion to the selected V input of the AD7813. It means that the user IN products at sum and difference frequencies of mfa ± nfb where must wait for the duration of the track/hold acquisition time m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which after the end of conversion, or after a step input change to V , IN neither m nor n are equal to zero. For example, the second before starting another conversion, to ensure that the part order terms include (fa + fb) and (fa – fb), while the third order operates to specification. terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7813 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of differ- ent significance. The second order terms are usually distanced REV. C –5– AD7813 CIRCUIT DESCRIPTION SUPPLY 2.7V TO 5.5V Converter Operation 10�F 0.1�F The AD7813 is a successive approximation analog-to-digital PARALLEL converter based around a charge redistribution DAC. The ADC V V INTERFACE DD REF can convert analog input signals in the range 0 V to V . Fig- DB0-DB7 DD ures 2 and 3 below show simplified schematics of the ADC. AD7813 0V TO V REF BUSY V Figure 2 shows the ADC during its acquisition phase. SW2 is IN INPUT �C/�P RD closed and SW1 is in Position A, the comparator is held in a GND balanced condition and the sampling capacitor acquires the CS signal on V . IN+ CONVST CHARGE Figure 4. Typical Connection Diagram REDISTRIBUTION DAC SAMPLING Analog Input CAPACITOR A Figure 5 shows an equivalent circuit of the analog input struc- V + IN CONTROL SW1 ture of the AD7813. The two diodes, D1 and D2, provide ESD LOGIC B ACQUISITION protection for the analog inputs. Care must be taken to ensure SW2 PHASE COMPARATOR that the analog input signal never exceeds the supply rails by CLOCK AGND V /3 more than 200 mV. This will cause these diodes to become DD OSC forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without caus- Figure 2. ADC Track Phase ing irreversible damage to the part is 20 mA. The capacitor C2, When the ADC starts a conversion (see Figure 3), SW2 will in Figure 5, is typically about 4 pF and can be primarily attrib- open and SW1 will move to Position B, causing the comparator uted to pin capacitance. The resistor R1 is a lumped component to become unbalanced. The Control Logic and the Charge made up of the on resistance of a multiplexer and a switch. This Redistribution DAC are used to add and subtract fixed amounts resistor is typically about 125 Ω. The capacitor C1 is the ADC of charge from the sampling capacitor so as to bring the compara- sampling capacitor and has a capacitance of 3.5 pF. tor back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic gen- V DD erates the ADC output code. Figure 7 shows the ADC transfer function. D1 C1 R1 3.5pF 125� V /3 V IN DD CHARGE REDISTRIBUTION C2 CONVERT PHASE – SWITCH OPEN D2 DAC 4pF TRACK PHASE – SWITCH CLOSED SAMPLING CAPACITOR A V + IN CONTROL SW1 LOGIC SW2 B CONVERSION Figure 5. Equivalent Analog Input Circuit PHASE COMPARATOR DC Acquisition Time CLOCK AGND V /3 DD OSC The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the Figure 3. ADC Conversion Phase end of a conversion there is a settling time associated with the sampling circuit. This settling time lasts approximately 100 ns. TYPICAL CONNECTION DIAGRAM The analog signal on V is also being acquired during this settling IN Figure 4 shows a typical connection diagram for the AD7813. The time; therefore, the minimum acquisition time needed is parallel interface is implemented using an 8-bit data bus, the approximately 100 ns. falling edge of CONVST brings the BUSY signal high, and at Figure 6 shows the equivalent charging circuit for the sampling the end of conversion the falling edge of BUSY is used to ini- capacitor when the ADC is in its acquisition phase. R2 repre- tiate an Interrupt Service Routine (ISR) on a microprocessor— sents the source impedance of a buffer amplifier or resistive see Parallel Interface section for more details. V is connected REF network, R1 is an internal multiplexer resistance and C1 is the to a well decoupled V pin to provide an analog input range of DD sampling capacitor. 0 V to V . When V is first connected the AD7813 powers DD DD up in a low current mode, i.e., power-down. A rising edge on an R1 V IN internal CONVST input will cause the part to power up—see R2 125� Power-Up Times. If power consumption is of concern, the C1 automatic power-down at the end of a conversion should be 3.5pF used to improve power performance. See Power vs. Throughput Rate section of the data sheet. Figure 6. Equivalent Sampling Circuit REV. C –6– AD7813 During the acquisition phase the sampling capacitor must be MODE 1 charged to within a 1/2 LSB of its final value. The time it takes V DD to charge the sampling capacitor (T ) is given by the CHARGE following formula: EXT CONVST t T = 7.6 × (R2 + 125 Ω) × 3.5 pF POWER-UP CHARGE 1.5�s For small values of source impedance, the settling time associ- INT CONVST ated with the sampling circuit (100 ns) is, in effect, the acquisi- tion time of the ADC. For example, with a source impedance (R2) of 10 Ω the charge time for the sampling capacitor is MODE 2 approximately 4 ns. The charge time becomes significant for V DD source impedances of 2 kΩ and greater. AC Acquisition Time EXT CONVST t t POWER-UP In ac applications it is recommended to always buffer analog POWER-UP 1.5�s 1.5�s input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of INT CONVST the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. Figure 8. Power-Up Times ADC TRANSFER FUNCTION POWER VS. THROUGHPUT RATE The output coding of the AD7813 is straight binary. The By operating the AD7813 in Mode 2, the average power con- designed code transitions occur at successive integer LSB values sumption of the AD7813 decreases at lower throughput rates. (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V /1024. The REF Figure 9 shows how the Automatic Power-Down is implemented ideal transfer characteristic for the AD7813 is shown in Figure 7. using the external CONVST signal to achieve the optimum power performance for the AD7813. The AD7813 is operated in Mode 2, and the duration of the external CONVST pulse is 111...111 set to be equal to or less than the power-up time of the device. 111...110 As the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time 111...000 1LSB = V /1024 REF drops accordingly. 011...111 000...010 EXT CONVST 000...001 000...000 t POWER-UP 1LSB t +V –1LSB 1.5�s REF CONVERT 0V ANALOG INPUT POWER-DOWN 2.3�s INT CONVST Figure 7. Transfer Characteristic t CYCLE 100�s @ 10kSPS POWER-UP TIMES The AD7813 has a 1.5 µs power-up time. When V is first DD Figure 9. Automatic Power-Down connected, the AD7813 is in a low current mode of operation. For example, if the AD7813 is operated in a continuous sam- In order to carry out a conversion the AD7813 must first be pling mode, with a throughput rate of 10 kSPS, the power con- powered up. The ADC is powered up by a rising edge on an sumption is calculated as follows. The power dissipation during internally generated CONVST signal, which occurs as a result normal operation is 10.5 mW, V = 3 V. If the power-up time DD of a rising edge on the external CONVST pin. The rising edge is 1.5µs and the conversion time is 2.3 µs, the AD7813 can then of the external CONVST signal initiates a 1.5 µs pulse on the be said to dissipate 10.5 mW for 3.8 µs (worst-case) during each internal CONVST signal. This pulse is present to ensure the conversion cycle. If the throughput rate is 10 kSPS, the cycle part has enough time to power up before a conversion is initi- time is 100 µs and the average power dissipated during each ated, as a conversion is initiated on the falling edge of gated cycle is (3.8/100) × (10.5 mW) = 400 µW. CONVST. See Timing and Control section. Care must be taken to ensure that the CONVST pin of the AD7813 is logic low when V is first applied. DD When operating in Mode 2, the ADC is powered down at the end of each conversion and powered up again before the next conversion is initiated. (See Figure 8.) REV. C –7– ADC CODE AD7813 At the end of conversion the sampling circuit goes back into its Typical Performance Characteristics tracking mode again. The end of conversion is indicated by the BUSY signal going low. This signal may be used to initiate an 10 ISR on a microprocessor. At this point the conversion result is latched into the output register where it may be read. The AD7813 has an 8-bit wide parallel interface. The 10-bit conversion result is accessed by performing two successive read operations. The first 8-bit read accesses the 8 MSBs of the conversion result and 1 the second read accesses the 2 LSBs, as illustrated in Figure 13, where one performance of the two successive reads is highlighted after the falling edge of BUSY. The state of the external CONVST signal at the end of conversion also establishes the mode of opera- 0.1 tion of the AD7813. Mode 1 Operation (High Speed Sampling) If the external CONVST is logic high when BUSY goes low, the 0.01 part is said to be in Mode 1 operation. While operating in Mode 05 5 10152025 30 3540 450 1, the AD7813 will not power down between conversions. The THROUGHPUT – kSPS AD7813 should be operated in Mode 1 for high speed sampling Figure 10. Power vs. Throughput applications, i.e., throughputs greater than 100 kSPS. Figure 13 shows the timing for Mode 1 operation. From this diagram one 0 can see that a minimum delay of the sum of the conversion time AD7813 –10 2048 POINT FFT and read time must be left between two successive falling edges SAMPLING 357.142kHz –20 f 30.168kHz IN of the external CONVST. This is to ensure that a conversion is –30 not initiated during a read. –40 Mode 2 Operation (Automatic Power-Down) At slower throughput rates the AD7813 may be powered down –50 between conversions to give a superior power performance. –60 This is Mode 2 Operation and it is achieved by bringing the –70 CONVST signal logic low before the falling edge of BUSY. –80 Figure 14, overleaf, shows the timing for Mode 2 Operation. The falling edge of the external CONVST signal may occur –90 before or after the falling edge of the internal CONVST signal, –100 0 17 35 52 70 87 105 122 140 157 174 but it is the later occurring falling edge of both that controls FREQUENCY – kHz when the first conversion will take place. If the falling edge Figure 11. SNR of the external CONVST occurs after that of the internal CONVST, it means that the moment of the first conversion is TIMING AND CONTROL controlled exactly, regardless of any jitter associated with the The AD7813 has only one input for timing and control, i.e., internal CONVST signal. The parallel interface is still fully the CONVST (convert start signal). The rising edge of this operational while the AD7813 is powered down. The AD7813 CONVST signal initiates a 1.5 µs pulse on an internally gener- is powered up again on the rising edge of the CONVST signal. ated CONVST signal. This pulse is present to ensure the part The gated CONVST pulse will now remain high long enough has enough time to power up before a conversion is initiated. If for the AD7813 to fully power up, which takes about 1.5 µs. This the external CONVST signal is low, the falling edge of the is ensured by the internal CONVST signal, which will remain high internal CONVST signal will cause the sampling circuit to go for 1.5 µs. into hold mode and initiate a conversion. If, however, the exter- nal CONVST signal is high when the internal CONVST goes low, it is upon the falling edge of the external CONVST signal EXT CONVST that the sampling circuitry will go into hold mode and initiate a GATED (PIN 4) INT conversion. The use of the internally generated 1.5 µs pulse, as previously described, can be likened to the configuration 1.5�s shown in Figure 12. The application of a CONVST signal at the CONVST pin triggers the generation of a 1.5 µs pulse. Both Figure 12. the external CONVST and this internal CONVST are input to an OR gate. The resulting signal has the duration of the longer of the two input signals. Once a conversion has been initiated the BUSY signal goes high to indicate a conversion is in progress. REV. C –8– dBs POWER – mW AD7813 t 1 t 2 EXT CONVST t 3 t POWER-UP INT CONVST BUSY CS/RD DB7–DB0 8 MSBs 2 LSBs Figure 13. Mode 1 Operation EXT CONVST t POWER-UP t 1 INT CONVST t 3 BUSY CS/RD DB7–DB0 8 MSBs Figure 14. Mode 2 Operation PARALLEL INTERFACE Further read operations will access the 8 MSBs and 2 LSBs of The parallel interface of the AD7813 is eight bits wide. The the 10-bit ADC conversion result again. The parallel interface output data buffers are activated when both CS and RD are of the AD7813 is reset when BUSY goes logic high. This feature logic low. At this point the contents of the data register are allows the AD7813 to be used as an 8-bit converter if the user placed on the 8-bit data bus. Figure 15 shows the timing dia- only wishes to access the 8 MSBs of the conversion. Care must gram for the parallel port. As previously explained, two succes- be taken to ensure that a read operation does not occur while sive read operations must take place in order to access the 10-bit BUSY is high. Data read from the AD7813 while BUSY is high conversion result. The first read places the 8 MSBs on the data will be invalid. For optimum performance the read operation bus and the second read places the 2 LSBs on the data bus. The should end at least 100 ns (t ) prior to the falling edge of the 10 2 LSBs appear on DB7 and DB6, with DB5–DB0 set to logic zero. next CONVST. CONVST t 2 t 9 t 3 BUSY t 1 t 8 CS t t 4 5 RD t 7 t 6 DB7–DB0 8 MSBs 2 MSBs Figure 15. Parallel Port Timing REV. C –9– AD7813 MICROPROCESSOR INTERFACING The parallel port on the AD7813 allows the device to be inter- PSP0–PSP7 DB0–DB7 faced to a range of many different microcontrollers. This section explains how to interface the AD7813 with some of the more PIC16C6x/7x* AD7813* common microcontroller parallel interface protocols. AD7813 to 8051 CS CS Figure 16 shows a parallel interface between the AD7813 and the 8051 microcontroller. The BUSY signal on the AD7813 pro- vides an interrupt request to the 8051 when a conversion begins. RD RD Port 0 of the 8051 may serve as an input or output port, or as in INT BUSY this case when used together, may be used as a bidirectional low-order address and data bus. The address latch enable out- *ADDITIONAL PINS OMITTED FOR CLARITY put of the 8051 is used to latch the low byte of the address dur- ing accesses to the device, while the high-order address byte is Figure 17. Interfacing to the PIC16C6x/7x supplied from Port 2. Port 2 latches remain stable when the AD7813 to ADSP-21xx AD7813 is addressed, as they do not have to be turned around Figure 18 shows a parallel interface between the AD7813 and (set to 1) for data input as is the case for Port 0. the ADSP-21xx series of DSPs. As before, the BUSY signal on the AD7813 provides an interrupt request to the DSP when a conversion begins. DB0–DB7 8051* AD0–AD7 D7–D0 AD7813* DB0–DB7 LATCH DECODER A13–A0 ALE AD7813* CS ADSP-21xx* ADDRESS A8–A15 DECODE LOGIC RD RD CS DMS EN INT BUSY RD RD *ADDITIONAL PINS OMITTED FOR CLARITY IRQ BUSY Figure 16. Interfacing to the 8051 *ADDITIONAL PINS OMITTED FOR CLARITY AD7813 to PIC16C6x/7x Figure 17 shows a parallel interface between the AD7813 and the Figure 18. Interfacing to the ADSP-21xx PIC16C64/65/74. The BUSY signal on the AD7813 provides an interrupt request to the microcontroller when a conversion begins. Of the PIC16C6x/7x range of microcontrollers only the PIC16C64/65/74 can provide the option of a parallel slave port. Port D of the microcontroller will operate as an 8-bit wide parallel slave port when control bit PSPMODE in the TRISE register is set. Setting PSPMODE enables the port pin RE0 to be the RD output and RE2 to be the CS output. For this functionality, the corresponding data direction bits of the TRISE register must be configured as outputs (reset to 0). See PIC16/17 Microcontroller User Manual. REV. C –10– AD7813 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 16 9 0.280 (7.11) 0.240 (6.10) 18 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) PIN 1 0.060 (1.52) 0.115 (2.93) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.015 (0.381) 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 16-Lead Small Outline Package (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 9 0.1574 (4.00) 0.2550 (6.20) 1 8 0.1497 (3.80) 0.2284 (5.80) 0.0688 (1.75) PIN 1 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0099 (0.25) 0.0500 (1.27) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) 16-Lead Thin Shrink Small Outline Package (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0256 0.0118 (0.30) 0° 0.020 (0.50) SEATING 0.0079 (0.20) (0.65) 0.0075 (0.19) PLANE BSC 0.0035 (0.090) REV. C –11– 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) C01005–0–10/00 (rev. C) PRINTED IN U.S.A.