ANALOG DEVICES AD7811

2.7 V to 5.5 V, 350 kSPS, 10-Bit a 4-/8-Channel Sampling ADCs AD7811/AD7812 The control registers of the AD7811 and AD7812 allow the FEATURES input channels to be configured as single-ended or pseudo 10-Bit ADC with 2.3 �s Conversion Time differential. The control register also features a software convert The AD7811 has Four Single-Ended Inputs that start and a software power-down. Two of these devices can Can Be Configured as Three Pseudo Differential share the same serial bus and may be individually addressed in Inputs with Respect to a Common, or as Two Inde- a multipackage application by hardwiring the device address pin. pendent Pseudo Differential Channels The AD7811 is available in a small, 16-lead 0.3" wide, plastic The AD7812 has Eight Single-Ended Inputs that Can dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small Be Configured as Seven Pseudo Differential Inputs Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out- with Respect to a Common, or as Four Independent line Package (TSSOP). The AD7812 is available in a small, Pseudo Differential Channels 20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a Onboard Track and Hold 20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink Onboard Reference 2.5 V � 2.5% Small Outline Package (TSSOP). Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V–3.6 V and 5 V � 10% PRODUCT HIGHLIGHTS DSP-/Microcontroller-Compatible Serial Interface 1. Low Power, Single Supply Operation High Speed Sampling and Automatic Power-Down Modes Both the AD7811 and AD7812 operate from a single 2.7 V Package Address Pin on the AD7811 and AD7812 Allows to 5.5 V supply and typically consume only 10 mW of power. Sharing of the Serial Bus in Multipackage Applications The power dissipation can be significantly reduced at Input Signal Range: 0 V to V REF lower throughput rates by using the automatic power- Reference Input Range: 1.2 V to V DD down mode e.g., 315 µW @ 10 kSPS, V = 3 V—see DD GENERAL DESCRIPTION Power vs. Throughput. The AD7811 and AD7812 are high speed, low power, 10-bit 2. 4-/8-Channel, 10-Bit ADC A/D converters that operate from a single 2.7 V to 5.5 V supply. The AD7811 and AD7812 have four and eight single-ended The devices contain a 2.3 µs successive approximation A/D input channels respectively. These inputs can be configured converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer- as pseudo differential inputs by using the Control Register. ence and a high speed serial interface that is compatible with the serial interfaces of most DSPs (Digital Signal Processors) and 3. On-chip 2.5 V (±2.5%) reference circuit that is powered microcontrollers. The user also has the option of using an exter- down when using an external reference. nal reference by connecting it to the V pin and setting the REF 4. Hardware and Software Control EXTREF bit in the control register. The V pin may be tied REF The AD7811 and AD7812 provide for both hardware and to V . At slower throughput rates the power-down mode may DD software control of Convert Start and Power-Down. be used to automatically power down between conversions. FUNCTIONAL BLOCK DIAGRAMS C REF V V AGND DGND C REF REF IN DD DD AGND DGND REF IN 1.23V 1.23V REF AD7812 REF AD7811 CLOCK CLOCK OSC OSC BUF BUF DOUT DOUT V DIN DIN IN1 CHARGE CHARGE SERIAL SERIAL V RFS REDISTRIBUTION IN2 REDISTRIBUTION RFS PORT PORT DAC DAC V TFS IN3 TFS V IN4 SCLK V SCLK IN1 MUX V IN5 V IN2 MUX V IN6 V IN3 CONTROL CONTROL V IN7 LOGIC V LOGIC V /3 IN4 DD V /3 COMP DD V COMP IN8 A0 CONVST A0 CONVST REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 (V = 2.7 V to 3.6 V, V = 5 V � 10%, GND = 0 V, V = V DD DD REF DD [EXT]. All specifications –40�C to +105�C unless otherwise noted.) AD7811/AD7812–SPECIFICATIONS Parameter Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz Any Channel, f = 350 kHz IN SAMPLE 1 Signal to (Noise + Distortion) Ratio 58 dB min V Internal or External REF 1 Total Harmonic Distortion (THD) –66 dB max 1 Peak Harmonic or Spurious Noise –80 dB typ 1, 2 Intermodulation Distortion fa = 29 kHz, fb = 30 kHz Second Order Terms –67 dB max Third Order Terms –67 dB max 1, 2 Channel-to-Channel Isolation –80 dB typ f = 20 kHz IN DC ACCURACY Any Channel Resolution 10 Bits Minimum Resolution for Which No Missing Codes are Guaranteed 10 Bits 1 Relative Accuracy ±1 LSB max 1 Differential Nonlinearity ±1 LSB max 1 Gain Error ±2 LSB max 1 Gain Error Match ±0.75 LSB max 1 Offset Error ±2 LSB max 1 Offset Error Match ±0.75 LSB max ANALOG INPUT Input Voltage Range 0 V min V V max REF 2 Input Leakage Current ±1 µA max 2 Input Capacitance 20 pF max 2 REFERENCE INPUTS V Input Voltage Range 1.2 V min REF V V max DD Input Leakage Current ±3 µA max Input Capacitance 20 pF max ON-CHIP REFERENCE Nominal 2.5 V Reference Error ±2.5 % max Temperature Coefficient 50 ppm/°C typ 2 LOGIC INPUTS V , Input High Voltage 2.4 V min V = 5 V ± 10% INH DD V , Input Low Voltage 0.8 V max V = 5 V ± 10% INL DD V , Input High Voltage 2 V min V = 3 V ± 10% INH DD V , Input Low Voltage 0.4 V max V = 3 V ± 10% INL DD Input Current, I ±1 µA max Typically 10 nA, V = 0 V to V IN IN DD Input Capacitance, C 8 pF max IN LOGIC OUTPUTS Output High Voltage, V I = 200 µA OH SOURCE 4V min V = 5 V ± 10% DD 2.4 V min V = 3 V ± 10% DD Output Low Voltage, V I = 200 µA OL SINK 0.4 V max High Impedance Leakage Current ±1 µA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion time 2.3 µs max 1 Track/Hold Acquisition Time 200 ns max –2– REV. B AD7811/AD7812 Parameter Y Version Unit Test Conditions/Comments POWER SUPPLY V 2.7 V min For Specified Performance DD 5.5 V max I Digital Inputs = 0 V or V DD DD Normal Operation 3.5 mA max Power-Down Full Power-Down 1 µA max Partial Power-Down (Internal Ref) 350 µA max See Power-Up Times Section Power Dissipation V = 3 V DD Normal Operation 10.5 mW max Auto Full Power-Down See Power vs. Throughput Section Throughput 1 kSPS 31.5 µW max Throughput 10 kSPS 315 µW max Throughput 100 kSPS 3.15 mW max Partial Power-Down (Internal Ref) 1.05 mW max Full Power-Down 3 µW max NOTES 1 See Terminology. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. 1, 2 (V = 2.7 V to 5.5 V, V = V [EXT] unless otherwise noted) TIMING CHARACTERISTICS DD REF DD Parameter Y Version Unit Conditions/Comments t 1.5 µs (max) Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST POWER-UP t 2.3 µs (max) Conversion Time 1 t 20 ns (min) CONVST Pulsewidth 2 t 25 ns (min) SCLK High Pulsewidth 3 t 25 ns (min) SCLK Low Pulsewidth 4 3 t 5 ns (min) RFS Rising Edge to SCLK Rising Edge Setup Time 5 3 t 5 ns (min) TFS Falling Edge to SCLK Falling Edge Setup Time 6 3 t 10 ns (max) SCLK Rising Edge to Data Out Valid 7 t 10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time 8 t 5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time 9 3, 4 t 20 ns (max) SCLK Rising Edge to DOUT High Impedance 10 t 100 ns (min) DOUT High Impedance to CONVST Falling Edge 11 NOTES 1 Sample tested to ensure compliance. 2 See Figures 16, 17 and 18. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V = 5 V ± 10% and DD 0.4 V or 2 V for V = 3 V ± 10%. DD 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the Timing Characteristics is the true bus relinquish 11 time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. I 200�A OL TO OUTPUT 2.1V PIN C L 50pF I 200�A OH Figure 1. Load Circuit for Digital Output Timing Specifications REV. B –3– AD7811/AD7812 ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W JA Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS, Lead Temperature, Soldering DIN, A0) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Digital Output Voltage to DGND (DOUT) Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW REF to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W JA Analog Inputs Lead Temperature, Soldering V –V (AD7811) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN1 IN4 DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C V –V (AD7812) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN1 IN8 DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C nent damage to the device. This is a stress rating only; functional operation of the Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W JA conditions for extended periods may affect device reliability. Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C ORDERING GUIDE Linearity Package Package Model Error Descriptions Options AD7811YN ±1 LSB 16-Lead Plastic DIP N-16 AD7811YR ±1 LSB 16-Lead Small Outline IC (SOIC) R-16A AD7811YRU ±1 LSB 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD7812YN ±1 LSB 20-Lead Plastic DIP N-20 AD7812YR ±1 LSB 20-Lead Small Outline IC (SOIC) R-20A AD7812YRU ±1 LSB 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions ESD SENSITIVE DEVICE are recommended to avoid performance degradation or loss of functionality. –4– REV. B AD7811/AD7812 PIN CONFIGURATIONS DIP/SOIC/TSSOP V 1 16 V V 1 20 V REF DD REF DD C 2 C 15 CONVST 2 19 CONVST REF REF V 3 14 SCLK V 3 18 SCLK IN1 IN1 AD7811 AGND 4 DIN AGND 17 DIN 13 4 TOP VIEW V V 5 12 DOUT 5 AD7812 16 DOUT IN2 (Not to Scale) IN2 TOP VIEW V 6 11 RFS V 15 RFS IN3 6 IN3 (Not to Scale) V 10 TFS V 7 7 14 TFS IN4 IN4 DGND A0 8 9 V 13 DGND 8 IN5 V 9 12 A0 IN6 V 10 11 V IN7 IN8 PIN FUNCTION DESCRIPTIONS Pin(s) Pin(s) AD7811 AD7812 Mnemonic Description 11 V An external reference input can be applied here. When using an external precision REF reference or V the EXTREF bit in the control register must be set to logic one. The DD external reference input range is 1.2 V to V . DD 22 C Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise REF performance of the on-chip reference. 3, 5–7 3, 5–11 V –V Analog Inputs. The analog input range is 0 V to V . IN1 IN4(8) REF 4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. 8 12 A0 Package Address Pin. This Logic Input can be hardwired high or low. When used in conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. 9 13 DGND Digital Ground. Ground reference for digital circuitry. 10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. 11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. 12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. 13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted in—see Serial Interface section. 14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. 15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. 16 20 V Positive Supply Voltage 2.7 V to 5.5 V. DD REV. B –5– AD7811/AD7812 TERMINOLOGY usually distanced in frequency from the original sine waves Signal to (Noise + Distortion) Ratio while the third order terms are usually at a frequency close to This is the measured ratio of signal to (noise + distortion) at the the input frequencies. As a result, the second and third order output of the A/D converter. The signal is the rms amplitude of terms are specified separately. The calculation of the inter- the fundamental. Noise is the rms sum of all nonfundamental modulation distortion is as per the THD specification where it is signals up to half the sampling frequency (f /2), excluding dc. S the ratio of the rms sum of the individual distortion products to The ratio is dependent upon the number of quantization levels the rms amplitude of the fundamental expressed in dBs. in the digitization process; the more levels, the smaller the Channel-to-Channel Isolation quantization noise. The theoretical signal to (noise + distor- Channel-to-channel isolation is a measure of the level of tion) ratio for an ideal N-bit converter with a sine wave input crosstalk between channels. It is measured by applying a full- is given by: scale 20 kHz sine wave signal to all nonselected input channels Signal to (Noise + Distortion) = (6.02N + 1.76) dB and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four or Thus for a 10-bit converter, this is 62 dB. eight channels for the AD7811 and AD7812 respectively. Total Harmonic Distortion Relative Accuracy Total harmonic distortion (THD) is the ratio of the rms sum of Relative accuracy, or endpoint nonlinearity, is the maximum harmonics to the fundamental. For the AD7811 and AD7812 deviation from a straight line passing through the endpoints of it is defined as: the ADC transfer function. 2 2 2 2 2 Differential Nonlinearity V +V +V +V +V 2 3 4 5 6 THD (dB)= 20 log This is the difference between the measured and the ideal V 1 1 LSB change between any two adjacent codes in the ADC. where V is the rms amplitude of the fundamental and V , V , 1 2 3 Offset Error V , V and V are the rms amplitudes of the second through the 4 5 6 This is the deviation of the first code transition (0000 . . . 000) sixth harmonics. to (0000...001) from the ideal, i.e., AGND + 1 LSB. Peak Harmonic or Spurious Noise Offset Error Match Peak harmonic or spurious noise is defined as the ratio of the This is the difference in Offset Error between any two channels. rms value of the next largest component in the ADC output Gain Error spectrum (up to f /2 and excluding dc) to the rms value of the S This is the deviation of the last code transition (1111 . . . 110) fundamental. Normally, the value of this specification is to (1111...111) from the ideal, i.e., V – 1 LSB, after the REF determined by the largest harmonic in the spectrum, but for offset error has been adjusted out. parts where the harmonics are buried in the noise floor, it will be a noise peak. Gain Error Match This is the difference in Gain Error between any two channels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and Track/Hold Acquisition Time fb, any active device with nonlinearities will create distortion Track/hold acquisition time is the time required for the output products at sum and difference frequencies of mfa ± nfb where of the track/hold amplifier to reach its final value, within m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for ±1/2 LSB, after the end of conversion (the point at which the which neither m nor n are equal to zero. For example, the track/hold returns to track mode). It also applies to situations second order terms include (fa + fb) and (fa – fb), while the where a change in the selected input channel takes place or third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and where there is a step input change on the input voltage applied (fa – 2fb). to the selected V input of the AD7811 or AD7812. It means IN that the user must wait for the duration of the track/hold acquisi- The AD7811 and AD7812 are tested using the CCIF standard tion time after the end of conversion or after a channel change/ where two input frequencies near the top end of the input step input change to V before starting another conversion, to IN bandwidth are used. In this case, the second and third order ensure that the part operates to specification. terms are of different significance. The second order terms are –6– REV. B AD7811/AD7812 Control Register (AD7811) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7811 receives a falling edge on its TFS pin. The AD7811 will maintain the same configuration until a new control byte is written to the part. The control register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros; therefore, when the supplies are connected, the AD7811 is powered down by default. Control Register AD7811 9 0 X* A1 0 P0 D PV D /AGND DIFF/SGLC0 H1 CH CONVST EXTREF IN4 *This is a don’t care bit. A0 This is the package address bit. It is used in conjunction with the package address pin to allow two AD7811s to share the same serial bus. The AD7811 can also share the same serial bus with the AD7812. When a control word is written to the control register of the AD7811 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device that received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. PD1, PD0 These bits allow the AD7811 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7811 enters a power-down at the end of a conversion. There are two power-down modes—Full Power-Down and Partial Power-Down. See Power-Down Options section of this data sheet. PD1 PD0 Description 0 0 Full Power-Down of the AD7811 0 1 Partial Power-Down at the End of Conversion 1 0 Full Power-Down at the End of Conversion 1 1 Power-Up the AD7811 V /AGND The DIF/SGL bit in the control register must be set to 0 to use this option otherwise this bit is ignored. Setting IN4 V /AGND to 0 configures the analog inputs of the AD7811 as four single-ended analog inputs referenced to IN4 analog ground (AGND). By setting this bit to 1 the input channels V to V are configured as three pseudo- IN1 IN3 differential channels with respect to V —see Table I. IN4 DIF/SGL This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to V as explained above. Setting this bit to 1 configures the analog input channels as two pseudo differential pairs IN4 V /V and V /V —see Table I. IN1 IN2 IN3 IN4 CH1, CH0 These bits are used in conjunction with V /AGND and DIF/SGL to select an analog input channel. The table IN4 shows how the various channel selections are made—see Table I. CONVST Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initiated in the same serial write. The bit is reset after the end of a conversion. EXTREF This bit must be set to a logic one if the user wishes to use an external reference or use V as the reference. DD When the external reference is selected the on chip reference circuitry powers down. REV. B –7– AD7811/AD7812 Control Register (AD7812) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros; therefore, when the supplies are connected, the AD7812 is powered down by default. Control Register AD7812 9 0 A1 0 P0 D PV D /AGND DIFF/SGLC1 H2 C0 H CH CONVST EXTREF IN8 A0 This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word is written to the control register of the AD7812 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device which received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. PD1, PD0 These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down modes—Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet. PD1 PD0 Description 0 0 Full Power-Down of the AD7812 0 1 Partial Power-Down at the End of Conversion 1 0 Full Power-Down at the End of Conversion 1 1 Power-Up the AD7812 V /AGND The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored. IN8 Setting V /AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs IN8 referenced to analog ground (AGND). By setting this bit to 1 the input channels V to V are configured IN1 IN7 as seven pseudo differential channels with respect to V —see Table II. IN8 DIF/SGL This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to V as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs IN8 V /V , V /V , V /V and V /V —see Table II. IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 CH2, CH1, CH0 These bits are used in conjunction with V /AGND and DIF/SGL to select an analog input channel. Table II IN8 shows how the various channel selections are made. CONVST Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi- ated in the same write operation. The bit is reset after the end of a conversion. EXTREF This bit must be set to a logic one if the user wishes to use an external reference or use V as the reference. DD When the external reference is selected the on-chip reference circuitry powers down and the current consumption is reduced by about 1 mA. –8– REV. B AD7811/AD7812 Table I. AD7811 Channel Configurations V /AGND DIF/SGL CH1 CH0 Description IN4 00 0 0 V Single-Ended with Respect to AGND IN1 00 0 1 V Single-Ended with Respect to AGND IN2 00 1 0 V Single-Ended with Respect to AGND IN3 00 1 1 V Single-Ended with Respect to AGND IN4 10 0 0 V Pseudo Differential with Respect to V IN1 IN4 10 0 1 V Pseudo Differential with Respect to V IN2 IN4 10 1 0 V Pseudo Differential with Respect to V IN3 IN4 X1 0 0 V (+) Pseudo Differential with Respect to V (–) IN1 IN2 X1 0 1 V (+) Pseudo Differential with Respect to V (–) IN3 IN4 X 1 1 0 Internal Test. SAR Input Equal to V /2 REF X 1 1 1 Internal Test. SAR Input Equal to V REF Table II. AD7812 Channel Configurations V /AGND DIF/SGL CH2 CH1 CH0 Description IN8 0 0 000 V Single-Ended with Respect to AGND IN1 0 0 001 V Single-Ended with Respect to AGND IN2 0 0 010 V Single-Ended with Respect to AGND IN3 0 0 011 V Single-Ended with Respect to AGND IN4 0 0 100 V Single-Ended with Respect to AGND IN5 0 0 101 V Single-Ended with Respect to AGND IN6 0 0 110 V Single-Ended with Respect to AGND IN7 0 0 111 V Single-Ended with Respect to AGND IN8 1 0 000 V Pseudo Differential with Respect to V IN1 IN8 1 0 001 V Pseudo Differential with Respect to V IN2 IN8 1 0 010 V Pseudo Differential with Respect to V IN3 IN8 1 0 011 V Pseudo Differential with Respect to V IN4 IN8 1 0 100 V Pseudo Differential with Respect to V IN5 IN8 1 0 101 V Pseudo Differential with Respect to V IN6 IN8 1 0 110 V Pseudo Differential with Respect to V IN7 IN8 X 1 000 V (+) Pseudo Differential with Respect to V (–) IN1 IN2 X 1 001 V (+) Pseudo Differential with Respect to V (–) IN3 IN4 X 1 010 V (+) Pseudo Differential with Respect to V (–) IN5 IN6 X 1 011 V (+) Pseudo Differential with Respect to V (–) IN7 IN8 X 1 1 0 0 Internal Test. SAR Input Equal to V /2 REF X 1 1 0 1 Internal Test. SAR Input Equal to V REF REV. B –9– AD7811/AD7812 SUPPLY CIRCUIT DESCRIPTION 2.7V TO 5.5V Converter Operation THREE-WIRE SERIAL 10nF The AD7811 and AD7812 are successive approximation analog- 10�F 0.1�F INTERFACE to-digital converters based around a charge redistribution DAC. The ADCs can convert analog input signals in the range 0 V to V V C REF DD REF V . Figures 2 and 3 show simplified schematics of the ADC. DD SCLK Figure 2 shows the ADC during its acquisition phase. SW2 is V IN1 closed and SW1 is in position A, the comparator is held in a DOUT V IN2 balanced condition and the sampling capacitor acquires the AD7811/ 0V TO DIN µC/µP signal on V . V AD7812 IN REF INPUT V IN4(8) CONVST CHARGE REDISTRIBUTION RFS DAC SAMPLING AGND CAPACITOR TFS A V IN CONTROL DGND SW1 A0 LOGIC B ACQUISITION PHASE SW2 COMPARATOR Figure 4. Typical Connection Diagram AGND CLOCK OSC V /3 DD Analog Input Figure 5 shows an equivalent circuit of the analog input struc- Figure 2. ADC Acquisition Phase ture of the AD7811 and AD7812. The two diodes D1 and D2 When the ADC starts a conversion, see Figure 3, SW2 will provide ESD protection for the analog inputs. Care must be open and SW1 will move to position B causing the comparator taken to ensure that the analog input signal never exceeds the to become unbalanced. The Control Logic and the Charge supply rails by more than 200 mV. This will cause these diodes Redistribution DAC are used to add and subtract fixed amounts to become forward biased and start conducting current into of charge from the sampling capacitor to bring the comparator the substrate. 20 mA is the maximum current these diodes can back into a balanced condition. When the comparator is rebal- conduct without causing irreversible damage to the part. How- anced, the conversion is complete. The Control Logic generates ever, it is worth noting that a small amount of current (1 mA) the ADC output code. Figure 10 shows the ADC transfer being conducted into the substrate due to an overvoltage on an function. unselected channel can cause inaccurate conversions on a selected channel. The capacitor C2 in Figure 5 is typically about CHARGE 4 pF and can primarily be attributed to pin capacitance. The REDISTRIBUTION resistor R1 is a lumped component made up of the on resistance DAC SAMPLING of a multiplexer and a switch. This resistor is typically about CAPACITOR A V 125 Ω. The capacitor C1 is the ADC sampling capacitor and IN CONTROL SW1 LOGIC has a capacitance of 3.5 pF. B CONVERSION PHASE COMPARATOR V SW2 DD AGND CLOCK OSC V /3 DD D1 C1 R1 Figure 3. ADC Conversion Phase 3.5pF 125� V V /3 IN DD TYPICAL CONNECTION DIAGRAM C2 D2 4pF Figure 4 shows a typical connection diagram for the AD7811/ CONVERSION PHASE – SWITCH OPEN AD7812. The AGND and DGND are connected together at TRACK PHASE – SWITCH CLOSED the device for good noise suppression. The serial interface is implemented using three wires with RFS/TFS connected to CONVST see Serial Interface section for more details. V is REF Figure 5. Equivalent Analog Input Circuit connected to a well decoupled V pin to provide an analog DD The analog inputs on the AD7811 and AD7812 can be config- input range of 0 V to V . If the AD7811 or AD7812 is not DD ured as single ended with respect to analog ground (AGND), sharing a serial bus with another AD7811 or AD7812 then A0 as pseudo differential with respect to a common, and also as (package address pin) should be hardwired low. The default pseudo differential pairs—see Control Register section. power up value of the package address bit in the control register is 0. For applications where power consumption is of concern, the automatic power down at the end of a conversion should be used to improve power performance. See Power-Down Options section of the data sheet. –10– REV. B AD7811/AD7812 An example of the pseudo differential scheme using the AD7811 Figure 8 shows the equivalent charging circuit for the sampling is shown in Figure 6. The relevant bits in the AD7811 Control capacitor when the ADC is in its acquisition phase. R2 repre- Register are set as follows DIF/SGL = 1, CH1 = CH2 = 0, i.e., sents the source impedance of a buffer amplifier or resistive V pseudo differential with respect to V . The signal is network; R1 is an internal multiplexer resistance, and C1 is the IN1 IN2 applied to V but in the pseudo differential scheme the sam- sampling capacitor. During the acquisition phase the sampling IN1 pling capacitor is connected to V during conversion and not capacitor must be charged to within a 1/2 LSB of its final value. IN2 AGND as described in the Converter Operation section. This The time it takes to charge the sampling capacitor (T ) is CHARGE input scheme can be used to remove offsets that exist in a sys- given by the following formula: tem. For example, if a system had an offset of 0.5 V the offset T = 7.6 × (R2 + 125 Ω) × 3.5 pF CHARGE could be applied to V and the signal applied to V . This has IN2 IN1 the effect of offsetting the input span by 0.5 V. It is only pos- R1 V 125� IN+ R2 sible to offset the input span when the reference voltage is less than V –OFFSET. DD SAMPLING C1 CAPACITOR 3.5pF CHARGE REDISTRIBUTION Figure 8. Equivalent Sampling Circuit DAC SAMPLING For small values of source impedance, the settling time associ- V CAPACITOR V IN1 IN+ ated with the sampling circuit (100 ns) is, in effect, the acquisi- V IN1 CONTROL tion time of the ADC. For example, with a source impedance V LOGIC OFFSET CONVERSION (R2) of 10 Ω the charge time for the sampling capacitor is V COMPARATOR IN– PHASE approximately 4 ns. The charge time becomes significant for CLOCK V V OFFSET IN2 OSC source impedances of 2 kΩ and greater. V /3 DD AC Acquisition Time In ac applications it is recommended to always buffer analog Figure 6. Pseudo Differential Input Scheme input signals. The source impedance of the drive circuitry must When using the pseudo differential input scheme the signal on be kept as low as possible to minimize the acquisition time of V must not vary by more than a 1/2 LSB during the conver- IN2 the ADC. Large values of source impedance will cause the THD sion process. If the signal on V varies during conversion, the IN2 to degrade at high throughput rates. In addition, better perfor- conversion result will be incorrect. In single-ended mode the mance can generally be achieved by using an External 1 nF sampling capacitor is always connected to AGND during con- capacitor on V . IN version. Figure 7 shows the AD7811/AD7812 pseudo differen- tial input being used to make a unipolar dc current measurement. ON-CHIP REFERENCE A sense resistor is used to convert the current to a voltage and The AD7811 and AD7812 have an on-chip 2.5 V reference the voltage is applied to the differential input as shown. circuit. The schematic in Figure 9 shows how the reference circuit is implemented. A 1.23 V bandgap reference is gained up V DD to provide a 2.5 V ± 2% reference voltage. The on-chip refer- V ence is not available externally (SW2 is open). An external refer- IN+ ence (1.2 V to V ) can be applied at the V pin. However in AD7811/ R DD REF SENSE AD7812 order to use an external reference the EXTREF bit in the con- V IN– trol register (Bit 0) must first be set to a Logic 1. When EXTREF R L is set to a Logic 1 SW2 will close, SW3 will open and the ampli- fier will power down. This will reduce the current consumption of the part by about 1 mA. It is possible to use two different reference voltages by selecting the on-chip reference or external Figure 7. DC Current Measurement Scheme reference. DC Acquisition Time C REF The ADC starts a new acquisition phase at the end of a conver- EXTERNAL sion and ends on the falling edge of the CONVST signal. At the CAPACITOR V REF end of a conversion a settling time is associated with the sam- SW1 pling circuit. This settling time lasts approximately 100 ns. The SW2 analog signal on V is also being acquired during this settling IN+ 1.23V time. Therefore, the minimum acquisition time needed is 2.5V approximately 100 ns. 7pF SW3 AGND Figure 9. On-Chip Reference Circuitry REV. B –11– AD7811/AD7812 When using automatic power-down between conversions to POWER-ON-RESET improve the power performance of the part (see Power vs. If during normal operation, a power-save is performed by removing Throughput) the switch SW1 will open when the part enters its power from the AD7811 and AD7812; the user must be wary power-down mode if using the internal on-chip reference. This that a proper reset is done when power is applied to the part provides a high impedance discharge path for the external again. To ensure proper power-on-reset, we recommend that capacitor (see Figure 9). A typical value of external capacitance both PD bits are set to 0 and then set to 1. This procedure is 10 nF. When the part is in Mode 2 Full Power-Down, because causes an internal reset to occur. the external capacitor holds its charge during power-down, the internal bandgap reference will power up more quickly after POWER-UP TIMES relatively short periods of full power-down. When operating the The AD7811 and AD7812 have a 1.5 µs power-up time when part in Mode 2 Partial Power-Down the external capacitor is not using an external reference or when powering up from partial required as the on-chip reference stays powered up while the power-down. When V is first connected, the AD7811 and DD rest of the circuitry powers down. AD7812 are in a low current mode of operation. In order to carry out a conversion the AD7811 and AD7812 must first be ADC TRANSFER FUNCTION powered up by writing to the control register of each ADC to The output coding of the AD7811 and AD7812 is straight set the power-down bits (i.e., PD1 = 1, PD0 = 1) for a full binary. The designed code transitions occur at successive inte- power-up. See the Quick Evaluation Setup section on the fol- ger LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = lowing page. V /1024. The ideal transfer characteristic for the AD7811 and REF Mode 2 Full Power-Down (PD1 = 1, PD0 = 0) AD7812 is shown in Figure 10. The power-up time of the AD7811 and AD7812 after power is first connected, or after a long period of Full Power-Down, is the time it takes the on-chip 1.23 V reference to power up plus 111...111 the time it takes to charge the external capacitor C —see REF 111...110 Figure 9. The time taken to charge C to the 10-bit level is REF given by the equation (7.6 × 2 kΩ × C ). For C = 10 nF REF REF 111...000 1LSB = V /1024 REF the power-up time is approximately 152 µs. It takes 30 µs to 011...111 power up the on-chip reference so the total power-up time of either ADC in either of these conditions is 182 µs. However, 000...010 when powering down fully between conversions to achieve a 000...001 000...000 better power performance this power-up time reduces to 1.5 µs 1LSB +V –1LSB REF 0V after a relatively short period of power-down as C holds its REF ANALOG INPUT charge (see On-Chip Reference section). The AD7811 and Figure 10. AD7811 and AD7812 Transfer Characteristic AD7812 can therefore be used in Mode 2 with throughput rates of 250 kSPS and under. POWER-DOWN OPTIONS Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1) The AD7811 and AD7812 provide flexible power management The power-up time of the AD7811 and AD7812 from a Partial to allow the user to achieve the best power performance for a Power-Down is 1.5 µs maximum. When using a Partial Power- given throughput rate. Down between conversions, there is no requirement to connect The power management options are selected by programming an external capacitor to the C pin because the reference REF the power-down bits (i.e., PD1 and PD0) in the control register. remains powered up. This means that the AD7811 and AD7812 Table III below summarizes the options available. When the will power up in 30 µs after the supplies are first connected as power-down bits are programmed for Mode 2 Power Down (full there is no requirement to charge an external capacitor. and partial), a rising edge on the CONVST pin will power up the part. This feature is used when powering down between POWER VS. THROUGHPUT conversions—see Power vs. Throughput. When the AD7811 By using the Automatic Power-Down (Mode 2) at the end of a and AD7812 are placed in partial power-down the on-chip conversion—see Operating Modes section of the data sheet, reference does not power down. However, the part will power superior power performance can be achieved. up more quickly after long periods of power-down when using Figure 11 shows how the Automatic Power-Down is implemented partial power-down—see Power-Up Times section. using the CONVST signal to achieve the optimum power performance for the AD7811 and AD7812. The AD7811 and Table III. AD7811/AD7812 Power-Down Options AD7812 are operated in Mode 2 and the control register Bits PD1 and PD0 are set to 1 and 0 respectively for Full Power-Down, PD1 PD0 CONVST* Description or 0 and 1 for Partial Power-Down. The duration of the CONVST 1 1 x Full Power-Up pulse is set to be equal to or less than the power-up time of the 0 0 x Full Power-Down devices—see Operating Modes section. As the throughput rate 0 1 0 Mode 2 Partial Power-Down is reduced, the device remains in its power-down state longer (Reference Stays Powered-Up) and the average power consumption over time drops accordingly. 0 1 1 No Power-Down 1 0 0 Mode 2 Full Power-Down 1 0 1 No Power-Down *This refers to the state of the CONVST signal at the end of a conversion. –12– REV. B ADC CODE AD7811/AD7812 t CONVERT QUICK EVALUATION SETUP t POWER-UP 2.3�s 1.5�s The schematic shown in Figure 14 shows a suggested configura- POWER-DOWN CONVST tion of the AD7812 for a first look evaluation of the part. No external reference circuit is needed as the V pin can be REF t CYCLE connected to V . The CONVST signal is connected to TFS DD 100�s @ 10kSPS and RFS to enable the serial port. Also by selecting Mode 2 Figure 11. Automatic Power-Down operation (see Operating Modes section) the power performance For example, if the AD7811 is operated in a continuous sam- of the AD7812 can be evaluated. pling mode with a throughput rate of 10 kSPS, PD1 = 1, PD0 = 0 and using the on chip reference the power consump- SUPPLY V DD tion is calculated as follows. The power dissipation during nor- 0.1�F 10�F 10nF mal operation is 10.5 mW, V = 3 V. If the power-up time is DD 1.5 µs and the conversion time is 2.3 µs, the AD7811 can be V V C DD REF REF said to dissipate 10.5 mW for 3.8 µs (worst-case) during each SCLK conversion cycle. If the throughput rate is 10 kSPS, the cycle 0V TO V DD V IN1 INPUT time is 100 µs and the average power dissipated during each DOUT V IN2 cycle is (3.8/100) × (10.5 mW) = 400 µW. DIN AD7812 Figure 12 shows the Power vs. Throughput Rate for automatic full power-down. CONVST V IN7 10 RFS V IN8 AGND TFS A0 DGND 1 Figure 14. Evaluation Quick Setup The setup uses a full duplex, 16-bit, serial interface protocol, e.g., SPI. It is possible to use 8-bit transfers by carrying out two consecutive read/write operations. The MSB of data is trans- 0.1 ferred first. 1. When power is first connected to the device it is in a powered down mode of operation and is consuming only 1 µA. The AD7812 must first be configured by carrying out a serial 0.01 05 5 1015 20253 3054 4050 write operation. THROUGHPUT – kSPS 2. The CONVST signal is first pulsed to enable the serial port Figure 12. AD7811/AD7812 Power vs. Throughput (rising and falling edge on RFS and TFS respectively—see 0 Serial Interface section). AD7811/12 –10 3. Next, a 16-bit serial read/write operation is carried out. By 2048 POINT FFT writing 6040 Hex to the AD7812 the part is powered up, set SAMPLING 357.142kHz –20 f = 30.168kHz up to use external reference (i.e., V ) and the analog input IN DD –30 V is selected. The data read from the part during this read/ IN1 –40 write operation is invalid. –50 4. It is necessary to wait approximately 1.5 µs before pulsing CONVST again and initiating a conversion. The 1.5 µs is to –60 allow the AD7812 to power up correctly—see Power-Up –70 Times section. –80 5. Approximately 2.3 µs after the falling edge of CONVST, i.e., –90 after the end of the conversion, a serial read/write can take –100 place. This time 4040 Hex is written to the AD7812 and the 0 17 35 52 70 87 105 122 140 157 174 data read from the part is the result of the conversion. The FREQUENCY – kHz output code is in a straight binary format and will be left Figure 13. AD7811/AD7812 SNR justified in the 16-bit serial register (MSB clocked out first). 6. By idling the CONVST signal high or low it is possible to operate the AD7812 in Mode 1 and Mode 2 respectively. REV. B –13– dBs POWER – mV AD7811/AD7812 OPERATING MODES should occur before the end of the conversion process if the part The mode of operation of the AD7811 and AD7812 is selected is not to be powered down. A serial read can take place at any when the (logic) state of the CONVST is checked at the end of stage after the rising edge of CONVST. If a serial read is initi- a conversion. If the CONVST signal is logic high at the end ated before the end of the current conversion process (i.e., at of a conversion, the part does not power down and is operat- time “A”), the result of the previous conversion is shifted out on ing in Mode 1. If, however, the CONVST signal is brought the DOUT pin. It is possible to allow the serial read to extend logic low before the end of a conversion, the AD7811 and AD7812 beyond the end of a conversion. In this case the new data will will power down at the end of the conversion. This is Mode 2 not be latched into the output shift register until the read operation. has finished. The dynamic performance of the AD7811 and AD7812 typically degrades by up to 3 dBs while reading during Mode 1 Operation (High Speed Sampling) a conversion. If the user waits until the end of the conversion When the AD7811 and AD7812 are operated in Mode 1 they process, i.e., 2.3 µs after the falling edge of CONVST (Point are not powered down between conversions. This mode of opera- “B”) before initiating a read, the current conversion result is tion allows high throughput rates to be achieved. The timing shifted out. The serial read must finish at least 100 ns prior to diagram in Figure 16 shows how this optimum throughput rate the next falling edge of CONVST to allow the part to accurately is achieved by bringing the CONVST signal high before the end acquire the input signal. of the conversion. Mode 2 Operation (Automatic Power-Down) The sampling circuitry leaves its tracking mode and goes into When used in this mode of operation the part automatically hold on the falling edge of CONVST. A conversion is also initi- powers down at the end of a conversion. This is achieved by ated at this time. The conversion takes 2.3 µs to complete. At leaving the CONVST signal low until the end of the conversion. this point, the result of the current conversion is latched into the Because it takes approximately 1.5 µs for the part to power-up serial shift register and the state of the CONVST signal checked. after it has been powered down, this mode of operation is intended The CONVST signal should be logic high at the end of the to be used in applications where slower throughput rates are conversion to prevent the part from powering down. The serial required, i.e., in the order of 250 kSPS and improved power port on the AD7811 and AD7812 is enabled on the rising edge performance is required—see Power vs. Throughput section. of the first SCLK after the rising edge of the RFS signal—see There are two power-down modes the AD7811/AD7812 can Serial Interface section. As explained earlier, this rising edge V DD t t t CONVERT POWER-UP CONVERT 2.3�s 1.5�s 2.3�s CONVST 6040 HEX 4040 HEX 4040 HEX DIN NOT VALID VALID DATA VALID DATA DOUT Figure 15. Read/Write Sequence for AD7812 t 1 CONVST A B t 2 t 12 SCLK CURRENT CONVERSION DOUT RESULT Figure 16. Mode 1 Operation Timing Diagram –14– REV. B AD7811/AD7812 enter during automatic power-down. These modes are discussed (Point “B”), whichever occurs latest before initiating a serial in the Power-Up Times section of this data sheet. The timing read. The serial port of the AD7811 and AD7812 is still func- diagram in Figure 17 shows how to operate the part in Mode 2. tional even though the devices have been powered down. If the AD7811/AD7812 is powered down, the rising edge of the Because it is possible to do a serial read from the part while it is CONVST pulse causes the part to power-up. Once the part powered down, the AD7811 and AD7812 are powered up only has powered up (~1.5 µs after the rising edge of CONVST) to do the conversion and are immediately powered down at the the CONVST signal is brought low and a conversion is initiated end of a conversion. This significantly improves the power on this falling edge of the CONVST signal. The conversion consumption of the part at slower throughput rates—see Power takes 2.3 µs and after this time the conversion result is latched vs. Throughput section. into the serial shift register and the part powers down. There- fore, when the part is operated in Mode 2 the effective conver- SERIAL INTERFACE sion time is equal to the power-up time (1.5 µs) and the SAR The serial interface of the AD7811 and AD7812 consists of five conversion time (2.3 µs). wires, a serial clock input, SCLK, receive data to clock syn- NOTE: Although the AD7811 and AD7812 take 1.5 µs to chronization input RFS, transmit data to clock synchronization power up after the rising edge of CONVST, it is not necessary input TFS, a serial data output, DOUT, and a serial data to leave CONVST high for 1.5 µs after the rising edge before input, DIN, (see Figure 18). The serial interface is designed to bringing it low to initiate a conversion. If the CONVST signal allow easy interfacing to most microcontrollers and DSPs, goes low before 1.5 µs in time has elapsed, then the power-up e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320 time is timed out internally and a conversion is then initiated. and ADSP-21xx, without the need for any gluing logic. When Hence the AD7811 and AD7812 are guaranteed to have always interfacing to the 8051, the SCLK must be inverted. The powered-up before a conversion is initiated, even if the CONVST Microprocessor/Microcontroller Interface section explains pulsewidth is <1.5 µs. If the CONVST pulsewidth is > 1.5 µs, how to interface to some popular DSPs and microcontrollers. then a conversion is initiated on the falling edge. Figure 18 shows the timing diagram for a serial read and write As in the case of Mode 1 operation, the rising edge of the first to the AD7811 and AD7812. The serial interface works with SCLK after the rising edge of RFS enables the serial port of the both a continuous and a noncontinuous serial clock. The rising AD7811 and AD7812 (see Serial Interface section). If a serial edge of RFS and falling edge of TFS resets a counter that read is initiated soon after this rising edge (Point “A”), i.e., counts the number of serial clocks to ensure the correct number before the end of the conversion, the result of the previous con- of bits are shifted in and out of the serial shift registers. Once version is shifted out on pin DOUT. In order to read the result the correct number of bits have been shifted in and out, the of the current conversion, the user must wait at least 2.3 µs after SCLK is ignored. In order for another serial transfer to take power-up or at least 2.3 µs after the falling edge of CONVST, place the counter must be reset by the active edges of TFS and t POWER-UP t 1 1.5�s CONVST t 2 SCLK B A CURRENT CONVERSION DOUT RESULT Figure 17. Mode 2 Operation Timing Diagram t A 3 B SCLK 4 5 6 7 8 9 10 11 12 1 2 3 13 t 4 t 5 RFS t 6 TFS t t 7 10 DOUT DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 t 8 t 9 DIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Figure 18. Serial Interface Timing Diagram REV. B –15– AD7811/AD7812 RFS. The first rising SCLK edge after the rising edge of the AD7811/AD7812 to MC68HC11 RFS signal causes DOUT to leave its high impedance state and The Serial Peripheral Interface (SPI) on the MC68HC11 is data is clocked out onto the DOUT line and also on subsequent configured for Master Mode (MSTR = 0), Clock Polarity Bit SCLK rising edges. The DOUT pin goes back into a high (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is impedance state on the 11th SCLK rising edge—Point “A” on configured by writing to the SPI Control Register (SPCR)—see Figure 18. A minimum of 11 SCLKs are therefore needed to 68HC11 user manual. A connection diagram is shown in carry out a serial read. Data on the DIN line is latched in on Figure 20. the first SCLK falling edge after the falling edge of the TFS signal and on subsequent SCLK falling edges. The control register is updated on the 13th SCLK rising edge—point “B” on AD7811/AD7812* MC68HC11* Figure 18. A minimum of 13 SCLK pulses are therefore needed SCLK SCLK/PD4 to complete a serial write operation. In multipackage applications DOUT MISO/PD2 the RFS and TFS signals can be used as chip select signals. The serial interface will not shift data in or out until it receives the DIN MOSI/PD3 active edge of the RFS or TFS signal. Simplifying the Serial Interface CONVST PA0 The five-wire interface is designed to support many different RFS serial interface standards. However, it is possible to reduce the number of lines required to just three. By simply connecting the TFS TFS and RFS pins to the CONVST signal (see Figure 4), the *ADDITIONAL PINS OMITTED FOR CLARITY CONVST signal can be used to enable the serial port for read- ing and writing. This is only possible where a noncontinuous Figure 20. Interfacing to the MC68HC11 serial clock is being used. AD7811/AD7812 to 8051 MICROPROCESSOR INTERFACING The AD7811/AD7812 requires a clock synchronized to the The serial interface on the AD7811 and AD7812 allows the serial data. The 8051 serial interface must therefore be operated parts to be directly connected to a range of many different in Mode 0. In this mode serial data enters and exits through microprocessors. This section explains how to interface the RxD and a shift clock is output on TxD (half duplex). Figure 21 AD7811 and AD7812 with some of the more common micro- shows how the 8051 is connected to the AD7811/AD7812. controller and DSP serial interface protocols. However, because the AD7811/AD7812 shifts data out on the AD7811/AD7812 to PIC16C6x/7x rising edge of the shift clock and latches data in on the falling The PIC16C6x Synchronous Serial Port (SSP) is configured as edge, the shift clock must be inverted. an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register 8051* (SSPCON). See user PIC16/17 Microcontroller User Manual. AD7811/AD7812* Figure 19 shows the hardware connections needed to interface SCLK TxD to the PIC16/17. In this example I/O port RA1 is being used to DOUT RxD pulse CONVST and enable the serial port of the AD7811/ AD7812. This microcontroller transfers only eight bits of data DIN during each serial transfer operation; therefore, two consecutive read/write operations are needed. RFS P1.1 TFS PIC16C6x/7x* AD7811/AD7812* SCLK SCK/RC3 *ADDITIONAL PINS OMITTED FOR CLARITY DOUT SDO/RC5 Figure 21. Interfacing to the 8051 Serial Port DIN SDI/ RC4 CONVST RA1 RFS TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. Interfacing to the PIC16/17 –16– REV. B AD7811/AD7812 It is possible to implement a serial interface using the data ports AD7811/AD7812 to ADSP-21xx on the 8051. This would also allow a full duplex serial transfer The ADSP-21xx family of DSPs are easily interfaced to the to be implemented. The technique involves “bit banging” an AD7811/AD7812 without the need for extra gluing logic. The I/O port (e.g., P1.0) to generate a serial clock and using two SPORT is operated in normal framing mode. The SPORT other I/O ports (e.g., P1.1 and P1.2) to shift data in and out— control register should be set up as follows: see Figure 22. TFSW = RFSW = 0, Normal Framing INVRFS = INVTFS = 0, Active High Frame Signal DTYPE = 00, Right Justify Data AD7811/AD7812* 8051* SLEN = 1001, 10-Bit Data Words P1.0 SCLK ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word DOUT P1.1 IRFS = 0, External Framing Signal DIN P1.2 ITFS = 1, Internal Framing Signal The 10-bit data words will be right justified in the 16-bit serial RFS P1.3 data registers when using this configuration. Figure 24 shows the connection diagram. TFS AD7811/AD7812* ADSP-21xx* *ADDITIONAL PINS OMITTED FOR CLARITY SCLK SCLK Figure 22. Interfacing to the 8051 Using I/O Ports DOUT DR AD7811/AD7812 to TMS320C5x DIN DT The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize RFS RFS the data transfer operations with peripheral devices like the AD7811. Frame synchronization inputs have been supplied on TFS TFS the AD7811/AD7812 to allow easy interfacing with no extra gluing logic. The serial port of the TMS320C5x is set up to operate in Burst Mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The Serial Port Control register *ADDITIONAL PINS OMITTED FOR CLARITY (SPC) must have the following setup: F0 = 0, FSM = 1, Figure 24. Interfacing to the ADSP-21xx MCM = 1 and TXM = 1. The connection diagram is shown AD7811/AD7812 to DSP56xxx in Figure 23. The connection diagram in Figure 25 shows how the AD7811 and AD7812 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The AD7811/AD7812* TMS320C5x* SSI is operated in Synchronous Mode (SYN bit in CRB =1) SCLK CLKX with internally generated 1-bit clock period frame sync for both Tx and Rx (FSL1 and FSL0 bits in CRB = 1 and 0 respectively). CLKR DOUT DR DIN DT AD7811/AD7812* DSP56xxx* RFS FSX SCLK SCK DOUT SRD TFS FSR DIN STD *ADDITIONAL PINS OMITTED FOR CLARITY RFS SC2 Figure 23. Interfacing to the TMS320C5x TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. Interfacing to the DSP56xxx REV. B –17– AD7811/AD7812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 16 9 0.280 (7.11) 0.240 (6.10) 18 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) PIN 1 0.060 (1.52) 0.115 (2.93) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.015 (0.381) 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204) PLANE (2.54) 0.045 (1.15) 0.014 (0.356) BSC 16-Lead Small Outline Package (SOIC) (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 9 0.1574 (4.00) 0.2550 (6.20) 1 8 0.1497 (5.80) 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0500 (1.27) 0.0099 (0.25) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) 16-Lead Thin Shrink Outline Package (TSSOP) (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0256 0.0118 (0.30) 0° 0.020 (0.50) SEATING 0.0079 (0.20) (0.65) 0.0075 (0.19) PLANE BSC 0.0035 (0.090) –18– REV. B 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) AD7811/AD7812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 20 11 0.280 (7.11) 0.240 (6.10) 110 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) PIN 1 0.060 (1.52) 0.115 (2.93) 0.015 (0.38) 0.210 (5.33) MAX 0.130 0.160 (4.06) (3.30) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.045 (1.15) 0.014 (0.356) BSC 20-Lead Small Outline Package (SOIC) (R-20A) 0.5118 (13.00) 0.4961 (12.60) 20 11 1 10 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0500 0.0192 (0.49) 0.0118 (0.30) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 20-Lead Thin Shrink Outline Package (TSSOP) (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 1 10 0.006 (0.15) PIN 1 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0118 (0.30) 0.0256 (0.65) 0° 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) REV. B –19– 0.177 (4.50) 0.169 (4.30) 0.2992 (7.60) 0.256 (6.50) 0.2914 (7.40) 0.246 (6.25) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. C01312a–0–10/00 (rev. B)