ANALOG DEVICES AD7810

2.7 V to 5.5 V, 2.3 �s, 10-Bit a ADC in 8-Lead microSOIC/DIP AD7810 FUNCTIONAL BLOCK DIAGRAM FEATURES 10-Bit ADC with 2.3 �s Conversion Time V V DD AGND REF Small Footprint 8-Lead microSOIC Package Specified Over a –40�C to +105�C Temperature Range AD7810 Inherent Track-and-Hold Functionality CHARGE D OUT SERIAL REDISTRIBUTION PORT Operating Supply Range: 2.7 V to 5.5 V DAC SCLK Specifications at 2.7 V to 5.5 V CLOCK Microcontroller-Compatible Serial Interface OSC Optional Automatic Power-Down V + IN at End of Conversion CONTROL COMP V – Low Power Operation IN LOGIC 3 V / DD 270 �W at 10 kSPS Throughput Rate 2.7 mW at 100 kSPS Throughput Rate Analog Input Range: 0 V to V REF CONVST Reference Input Range: 0 V to V DD APPLICATIONS Low Power, Hand-Held Portable Applications that Require Analog-to-Digital Conversion with 10-Bit Accuracy; e.g., Battery Powered Test Equipment, Battery-Powered Communications Systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7810 is a high speed, low power, 10-bit A/D con- 1. Complete, 10-Bit ADC in 8-Lead Package verter that operates from a single 2.7 V to 5.5 V supply. The The AD7810 is a 10-bit 2.3 µs ADC with inherent track/hold part contains a 2.3 µs successive approximation A/D converter, functionality and a high speed serial interface—all in an with inherent track/hold functionality, a pseudo differential 8-lead microSOIC package. V may be connected to V REF DD input and a high speed serial interface that interfaces to most to eliminate the need for an external reference. The result is microcontrollers. The AD7810 is fully specified over a tem- a high speed, low power, space saving ADC solution. perature range of –40°C to +105°C. 2. Low Power, Single Supply Operation By using a technique that samples the state of the CONVST The AD7810 operates from a single 2.7 V to 5.5 V supply (convert start) signal at the end of a conversion, the AD7810 and typically consumes only 9 mW of power while convert- may be used in an automatic power-down mode. When used in ing. The power dissipation can be significantly reduced at this mode, the AD7810 automatically powers down at the end lower throughput rates by using the automatic power-down of a conversion and “wakes up” at the start of a new conversion. mode, e.g., at a throughput rate of 10 kSPS the power This feature significantly reduces the power consumption of the consumption is only 270 µW. part at lower throughput rates. The AD7810 can also operate in 3. Automatic Power-Down a high speed mode where the part is not powered down between The automatic power-down mode, whereby the AD7810 conversions. In this high speed mode of operation, the conver- powers down at the end of a conversion and “wakes up” sion time of the AD7810 is 2.3 µs. The maximum throughput before the next conversion, means the AD7810 is ideal for rate is dependent on the speed of the serial interface of the battery powered applications. See Power vs. Throughput microcontroller. Rate section. The part is available in a small 8-lead, 0.3" wide, plastic dual- 4. Serial Interface in-line package (mini-DIP); in an 8-lead, small outline IC An easy to use, fast serial interface allows connection to most (SOIC); and in an 8-lead microSOIC package. popular microprocessors with no external circuitry. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 (GND = 0 V, V = V . All specifications –40�C to +105�C unless otherwise noted.) AD7810–SPECIFICATIONS REF DD Parameter Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz, f = 350 kHz IN SAMPLE 1 Signal to (Noise + Distortion) Ratio 58 dB min 1 Total Harmonic Distortion –64 dB max Peak Harmonic or Spurious Noise –64 dB max 2 Intermodulation Distortion fa = 48 kHz, fb = 48.5 kHz 2nd Order Terms –67 dB typ 3rd Order Terms –67 dB typ DC ACCURACY Resolution 10 Bits 1 Relative Accuracy ±1 LSB max 1 Differential Nonlinearity (DNL) ±1 LSB max 1 Offset Error ±2 LSB max 1 Gain Error ±2 LSB max Minimum Resolution for Which No Missing Codes Are Guaranteed 10 Bits ANALOG INPUT Input Voltage Range 0 V min V V max REF 2 ±1 µA max Input Leakage Current 2 Input Capacitance 15 pF max 2 REFERENCE INPUTS V Input Voltage Range 1.2 V min REF V V max DD Input Leakage Current ±3 µA max Input Capacitance 20 pF max 2 LOGIC INPUTS V , Input High Voltage 2.0 V min INH V , Input Low Voltage 0.4 V max INL Input Current, I ±1 µA max Typically 10 nA, V = 0 V to V IN IN DD Input Capacitance, C 8 pF max IN LOGIC OUTPUTS Output High Voltage, V 2.4 V min I = 200 µA OH SOURCE Output Low Voltage, V 0.4 V max I = 200 µA OL SINK High Impedance Leakage Current ±10 µA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 2.3 µs max 1 Track/Hold Acquisition Time 100 ns max See DC Acquisition Time Section POWER SUPPLY V 2.7–5.5 Volts For Specified Performance DD I 3.5 mA max Sampling at 350 kSPS and Logic DD Power Dissipation 17.5 mW max Inputs at V or 0 V. V = 5 V DD DD Power-Down Mode I 1 µA max V = 5 V; V = 3 V DD DD DD Power Dissipation 5 µW max Automatic Power Down 1 kSPS Throughput 27 µW max 10 kSPS Throughput 270 µW max 100 kSPS Throughput 2.7 mW max NOTES 1 See Terminology section. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. REV. B –2– AD7810 1, 2 (–40�C to +105�C, V = V , unless otherwise noted) Timing Characteristics REF DD Parameter V = 5 V � 10% V = 3 V � 10% Unit Conditions/Comments DD DD t 2.3 2.3 µs (max) Conversion Time Mode 1 Operation (High Speed Mode) 1 t 20 20 ns (min) CONVST Pulsewidth 2 t 25 25 ns (min) SCLK High Pulsewidth 3 t 25 25 ns (min) SCLK Low Pulsewidth 4 3 t 5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time 5 3 t 10 10 ns (max) SCLK Rising Edge to D Data Valid Delay 6 OUT 3 t 5 5 ns (max) Data Hold Time after Rising Edge SCLK 7 3, 4 t 20 20 ns (max) Bus Relinquish Time after Falling Edge of SCLK 8 10 10 ns (min) t 1.5 1.5 µs (max) Power-Up Time after Rising Edge of CONVST POWER UP NOTES 1 Sample tested to ensure compliance. 2 See Figures 14, 15 and 16. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V = 5 V ± 10% and DD 0.4 V or 2 V for V = 3 V ± 10%. DD 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the Timing Characteristics is the true bus relinquish time 8 of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW (T = 25°C unless otherwise noted) A θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W JA V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W JC Digital Input Voltage to GND Lead Temperature, Soldering (CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Digital Output Voltage to GND Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C (D ) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V OUT DD MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V REF DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W JA Analog Inputs θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W JC (V , V ) . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V IN+ IN– DD Lead Temperature, Soldering Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW *Stresses above those listed under Absolute Maximum Ratings may cause perma- θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W JA nent damage to the device. This is a stress rating only; functional operation of the θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W device at these or any other conditions above those listed in the operational JC sections of this specification is not implied. Exposure to absolute maximum rating Lead Temperature Soldering (10 sec) . . . . . . . . . . . 260°C conditions for extended periods may affect device reliability. ORDERING GUIDE Linearity Temperature Package Package Branding Model Error (LSB) Range Description Options Information AD7810YN ±1 LSB –40°C to +105°C Plastic DIP N-8 AD7810YR ±1 LSB –40°C to +105°C Small Outline IC (SOIC) SO-8 AD7810YRM ±1 LSB –40°C to +105°C microSOIC RM-8 C1Y I OL 200�A TO OUTPUT 1.6V PIN C L 50pF I OH 200�A Figure 1. Load Circuit for Digital Output Timing Specifications REV. B –3– AD7810 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion. A rising edge on the CONVST pin enables the serial port of the AD7810. This is useful in multi- package applications where a number of devices share the same serial bus. The state of this pin at the end of conversion also determines whether the part is powered down or not. See Operating Modes section of this data sheet. 2V Positive input of the pseudo differential analog input. IN+ 3V Negative input of the pseudo differential analog input. IN– 4 GND Ground reference for analog and digital circuitry. 5V External reference is connected here. REF 6D Serial data is shifted out on this pin. OUT 7 SCLK Serial Clock. An external serial clock is applied here. 8V Positive Supply Voltage 2.7 V to 5.5 V. DD PIN CONFIGURATION DIP/SOIC 1 8 V CONVST DD AD7810 V + 2 7 SCLK IN TOP VIEW 3 6 V – (Not to Scale) D IN OUT GND 4 5 V REF Typical Performance Characteristics 10 –15 2048 POINT FFT SAMPLING 357.142kSPS F = 30kHz IN –35 1 –55 0.1 –75 –95 –115 0.01 03 10 200 40 50 FREQUENCY BINS THROUGHPUT – kSPS Figure 2. Power vs. Throughput Figure 3. AD7810 SNR REV. B –4– POWER – mW dBs 1 23 45 67 89 111 133 155 177 199 221 243 265 287 309 331 353 375 397 419 441 463 485 507 529 551 573 595 617 639 661 683 705 727 749 771 793 815 837 859 881 903 925 947 969 991 1013 AD7810 TERMINOLOGY The AD7810 is tested using the CCIF standard where two Signal to (Noise + Distortion) Ratio input frequencies near the top end of the input bandwidth are This is the measured ratio of signal to (noise + distortion) at the used. In this case, the second and third order terms are of differ- output of the A/D converter. The signal is the rms amplitude of ent significance. The second order terms are usually distanced the fundamental. Noise is the rms sum of all nonfundamental in frequency from the original sine waves while the third order signals up to half the sampling frequency (f /2), excluding dc. terms are usually at a frequency close to the input frequencies. S The ratio is dependent upon the number of quantization levels in As a result, the second and third order terms are specified sepa- the digitization process; the more levels, the smaller the quantiza- rately. The calculation of the intermodulation distortion is as tion noise. The theoretical signal to (noise + distortion) ratio for per the THD specification where it is the ratio of the rms sum of an ideal N-bit converter with a sine wave input is given by: the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Signal to (Noise + Distortion) = (6.02N + 1.76) dB Relative Accuracy Thus for a 10-bit converter, this is 62 dB. Relative accuracy or endpoint nonlinearity is the maximum Total Harmonic Distortion deviation from a straight line passing through the endpoints of Total harmonic distortion (THD) is the ratio of the rms sum of the ADC transfer function. harmonics to the fundamental. For the AD7810 it is defined as: Differential Nonlinearity This is the difference between the measured and the ideal 2 2 2 2 V +V +V +V 2 3 4 5 1 LSB change between any two adjacent codes in the ADC. THD dB = 20 log () V 1 Offset Error where V is the rms amplitude of the fundamental and V , V , 1 2 3 This is the deviation of the first code transition (0000 . . . 000) 2 V , V and V are the rms amplitudes of the second through 4 5 6 to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB. the sixth harmonics. Gain Error Peak Harmonic or Spurious Noise This is the deviation of the last code transition (1111 . . . 110) Peak harmonic or spurious noise is defined as the ratio of the to (1111 . . . 111) from the ideal (i.e., V – 1 LSB) after the REF rms values of the next largest component in the ADC output offset error has been adjusted out. spectrum (up to f /2 and excluding dc) to the rms value of the S Track/Hold Acquisition Time fundamental. Normally, the value of this specification is deter- Track/hold acquisition time is the time required for the output of mined by the largest harmonic in the spectrum, but for parts the track/hold amplifier to reach its final value, within ±1/2 LSB, where the harmonics are buried in the noise floor, it will be a after the end of conversion (the point at which the track/hold noise peak. returns to track mode). It also applies to situations where there Intermodulation Distortion is a step input change on the input voltage applied to the V IN+ With inputs consisting of sine waves at two frequencies, fa and input of the AD7810. It means that the user must wait for the fb, any active device with nonlinearities will create distortion duration of the track/hold acquisition time, after the end of conver- products at sum and difference frequencies of mfa ± nfb where sion or after a step input change to V , before starting another IN+ m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which conversion to ensure that the part operates to specification. neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). REV. B –5– AD7810 SUPPLY CIRCUIT DESCRIPTION 2.7V TO 5.5V TWO WIRE 10�F 0.1�F Converter Operation SERIAL INTERFACE The AD7810 is a successive approximation analog-to-digital converter based around a charge redistribution DAC. The ADC V V DD REF 0V TO V REF V + SCLK can convert analog input signals in the range 0 V to V . Fig- IN DD INPUT ures 4 and 5 below show simplified schematics of the ADC. AD7810 �C/�P V – D IN OUT Figure 4 shows the ADC during its acquisition phase. SW2 is AGND CONVST closed and SW1 is in Position A; the comparator is held in a balanced condition; and the sampling capacitor acquires the . Figure 6. Typical Connection Diagram signal on V IN+ Analog Input CHARGE Figure 7 shows an equivalent circuit of the analog input struc- REDISTRIBUTION DAC ture of the AD7810. The two diodes, D1 and D2, provide ESD SAMPLING CAPACITOR protection for the analog inputs. Care must be taken to ensure A V + IN that the analog input signal never exceeds the supply rails by CONTROL SW1 LOGIC more than 200 mV. This will cause these diodes to become B ACQUISITION SW2 PHASE forward biased and start conducting current into the substrate. COMPARATOR CLOCK The maximum current these diodes can conduct without caus- V – V /3 IN OSC DD ing irreversible damage to the part is 20 mA. The capacitor C2 is typically about 4 pF and can be primarily attributed to pin Figure 4. ADC Acquisition Phase capacitance. The resistor R1 is a lumped component made up of When the ADC starts a conversion (see Figure 5), SW2 will the on resistance of a multiplexer and a switch. This resistor is open and SW1 will move to Position B, causing the comparator typically about 125 Ω. The capacitor C1 is the ADC sampling to become unbalanced. The control logic and the charge redis- capacitor and has a capacitance of 3.5 pF. tribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator V DD back into a balanced condition. When the comparator is rebal- anced, the conversion is complete. The control logic generates C1 R1 D1 3.5pF 125� the ADC output code. Figure 11 shows the ADC transfer function. V + V /3 IN DD C2 D2 4pF CHARGE CONVERT PHASE – SWITCH OPEN REDISTRIBUTION DAC ACQUISITION PHASE – SWITCH CLOSED SAMPLING CAPACITOR A Figure 7. Equivalent Analog Input Circuit V + IN CONTROL SW1 LOGIC The analog input of the AD7810 is made up of a pseudo differ- B CONVERSION SW2 PHASE ential pair. V pseudo differential with respect to V . The IN+ IN– COMPARATOR CLOCK signal is applied to V , but in the pseudo differential scheme IN+ – V V /3 IN DD OSC the sampling capacitor is connected to V during conversion IN– (see Figure 8). This input scheme can be used to remove offsets Figure 5. ADC Conversion Phase that exist in a system. For example, if a system had an offset of 0.5 V, the offset could be applied to V and the signal applied IN– TYPICAL CONNECTION DIAGRAM to V . This has the effect of offsetting the input span by 0.5 V. IN+ Figure 6 shows a typical connection diagram for the AD7810. The It is only possible to offset the input span when the reference serial interface is implemented using two wires; the rising edge voltage (V ) is less than V – V . REF DD OFFSET of CONVST enables the serial interface—see Serial Interface is connected to a well decoupled section for more details. V REF V pin to provide an analog input range of 0 V to V . When CHARGE DD DD REDISTRIBUTION V is first connected, the AD7810 powers up in a low current DD DAC mode, i.e., power-down. A rising edge on the CONVST input SAMPLING COMPARATOR CAPACITOR will cause the part to power up—see Operating Modes. If power V + IN CONTROL V (+) consumption is of concern, the automatic power-down at the IN LOGIC V CONVERSION OFFSET SW2 end of a conversion should be used to improve power perfor- PHASE mance. See Power vs. Throughput Rate section of the data sheet. V – IN CLOCK V /3 OSC DD V OFFSET Figure 8. Pseudo Differential Input Scheme REV. B –6– AD7810 When using the pseudo differential input scheme, the signal on For small values of source impedance, the settling time associated V must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition IN– sion process. If the signal on V varies during conversion, the time of the ADC. For example, with a source impedance (R2) IN– conversion result will be incorrect. For single-ended operation, of 10 Ω, the charge time for the sampling capacitor is approxi- V is always connected to AGND. Figure 9 shows the AD7810 mately 4 ns. The charge time becomes significant for source IN– pseudo differential input being used to make a unipolar dc cur- impedances of 2 kΩ and greater. rent measurement. A sense resistor is used to convert the current AC Acquisition Time to a voltage and the voltage, is applied to the differential input In ac applications it is recommended to always buffer analog as shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of V DD the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor- V + IN mance can generally be achieved by using an external 1 nF R AD7810 SENSE capacitor on V . IN+ V – IN R L ADC TRANSFER FUNCTION The output coding of the AD7810 is straight binary. The designed code transitions occur at successive integer LSB values Figure 9. DC Current Measurement Scheme (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V /1024. The REF ideal transfer characteristic for the AD7810 is shown in Figure DC Acquisition Time 11 below. The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling time associated with the 111...111 sampling circuit. This settling time lasts approximately 100 ns. 111...110 The analog signal on V is also being acquired during this IN+ settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 10 shows the equivalent charging circuit for the sampling 111...000 capacitor when the ADC is in its acquisition phase. R2 repre- 011...111 sents the source impedance of a buffer amplifier or resistive 1LSB = V /1024 REF network; R1 is an internal multiplexer resistance and C1 is the sampling capacitor. 000...010 R1 000...001 V + 125� R2 IN 000...000 C1 0V 1LSB +V –1LSB REF 3.5pF ANALOG INPUT Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (t ) is given by the fol- CHARGE lowing formula: t = 7.6 × (R2 + 125 Ω) × 3.5 pF CHARGE REV. B –7– ADC CODE AD7810 POWER-UP TIMES OPERATING MODES The AD7810 has a 1.5 µs power-up time. When V is first Mode 1 Operation (High Speed Sampling) DD connected, the AD7810 is in a low current mode of operation. When the AD7810 is used in this mode of operation, the part is In order to carry out a conversion, the AD7810 must first be not powered down between conversions. This mode of opera- powered up. The ADC is powered up by a rising edge on the tion allows high throughput rates to be achieved. The timing CONVST pin. A conversion is initiated on the falling edge of diagram in Figure 14 shows how this optimum throughput rate CONVST. Figure 12 shows how to power up the AD7810 when is achieved by bringing the CONVST signal high before the end V is first connected or after the AD7810 is powered down of the conversion. The AD7810 leaves its tracking mode and DD using the CONVST pin. goes into hold on the falling edge of CONVST. A conversion is also initiated at this time. The conversion takes 2.3 µs to complete. Care must be taken to ensure that the CONVST pin of the At this point, the result of the current conversion is latched into the AD7810 is logic low when V is first applied. DD serial shift register, and the state of the CONVST signal checked. The CONVST signal should be high at the end of the conversion MODE 1 (CONVST IDLES HIGH) to prevent the part from powering down. V DD t POWER-UP < 1�s 1.5�s t 1 CONVST CONVST MODE 2 (CONVST IDLES LOW) A B t 2 V DD t POWER-UP SCLK 1.5�s CONVST D CURRENT CONVERSION RESULT OUT Figure 12. Power-Up Times Figure 14. Mode 1 Operation Timing POWER VS. THROUGHPUT RATE The serial port on the AD7810 is enabled on the rising edge of By operating the AD7810 in Mode 2, the average power con- the CONVST signal (see Serial Interface section). As explained sumption of the AD7810 decreases at lower throughput rates. earlier, this rising edge should occur before the end of the con- Figure 13 shows how the automatic power-down is implemented version process if the part is not to be powered down. A serial using the CONVST signal to achieve the optimum power per- read can take place at any stage after the rising edge of CONVST. formance for the AD7810. As the throughput rate is reduced, the If a serial read is initiated before the end of the current con- device remains in its power-down state longer and the average version process (i.e., at time “A”), the result of the previous power consumption over time drops accordingly. conversion is shifted out on the D pin. It is possible to allow OUT the serial read to extend beyond the end of a conversion. In this t CONVERT case the new data will not be latched into the output shift regis- t 2.3�s POWER-UP 1.5�s POWER-DOWN ter until the read has finished. The dynamic performance of the AD7810 typically degrades by up to 3 dBs while reading during CONVST a conversion. If the user waits until the end of the conversion t CYCLE process, i.e., 2.3 µs after falling edge of CONVST (Point “B”), 100�s @ 10kSPS before initiating a read, the current conversion result is shifted out. Figure 13. Automatic Power-Down For example, if the AD7810 is operated in a continuous sampling mode with a throughput rate of 10 kSPS, the power consump- tion is calculated as follows. The power dissipation during normal operation is 9 mW, V = 3 V. If the power-up time is 1.5µs DD and the conversion time is 2.3 µs, the AD7810 can be said to dissipate 9 mW for 3.8 µs (worst case) during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissipated during each cycle is (3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of Power vs. Throughput. REV. B –8– AD7810 Mode 2 Operation (Automatic Power-Down) before initiating a serial read. The serial port of the AD7810 is When used in this mode of operation, the part automatically still functional even though the AD7810 has been powered down. powers down at the end of a conversion. This is achieved by NOTE: Serial read should not cross the next rising edge of leaving the CONVST signal low until the end of the conversion. CONVST. Because it takes approximately 1.5 µs for the part to power up Because it is possible to do a serial read from the part while it after it has been powered down, this mode of operation is in- is powered down, the AD7810 is powered up only to do the tended to be used in applications where slower throughput rates conversion and is immediately powered down at the end of a are required, i.e., in the order of 100 kSPS. The timing diagram conversion. This significantly improves the power consumption in Figure 15 shows how to operate the part in this mode. If the of the part at slower throughput rates—see Power vs. Through- AD7810 is powered down, the rising edge of the CONVST put Rate section. pulse causes the part to power up. When the part has powered up (≈ 1.5 µs after the rising edge of CONVST), the CONVST SERIAL INTERFACE signal is brought low, and a conversion is initiated on this falling The serial interface of the AD7810 consists of three wires, a edge of the CONVST signal. The conversion takes 2.3 µs and serial clock input SCLK, serial port enable CONVST and a after this time, the conversion result is latched into the serial serial data output D (see Figure 16). The serial interface OUT shift register and the part powers down. Therefore, when the is designed to allow easy interfacing to most microcontrollers, part is operated in Mode 2, the effective conversion time is e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any equal to the power-up time (1.5 µs) and the SAR conversion gluing logic. When interfacing to the 8051, the SCLK must be time (2.3 µs). inverted. The Microprocessor Interface section explains how to NOTE: Although the AD7810 takes 1.5 µs to power up after the interface to some popular microcontrollers. rising edge of CONVST, it is not necessary to leave CONVST Figure 16 shows the timing diagram for a serial read from the high for 1.5 µs after the rising edge before bringing it low to AD7810. The serial interface works with both a continuous and initiate a conversion. If the CONVST signal goes low before 1.5 µs a noncontinuous serial clock. The rising edge of the CONVST in time has elapsed, then the power-up time is timed out inter- signal resets a counter, which counts the number of serial clocks nally and a conversion is then initiated. Hence the AD7810 is to ensure the correct number of bits are shifted out of the serial guaranteed to have always powered up before a conversion is shift registers. The SCLK is ignored once the correct number of initiated—even if the CONVST pulsewidth is < 1.5 µs. If the bits have been shifted out. In order for another serial transfer to CONVST width is > 1.5 µs, then a conversion is initiated on take place, the counter must be reset by the falling edge of the the falling edge. 10th SCLK. Data is clocked out from the D line on the first OUT As in the case of Mode 1 operation, the rising edge of the rising SCLK edge after the rising edge of the CONVST signal CONVST pulse enables the serial port of the AD7810 (see and on subsequent SCLK rising edges. D enters its high OUT Serial Interface section). If a serial read is initiated soon after impedance state again on the falling edge of the 10th SCLK. this rising edge (Point “A”), i.e., before the end of the conver- In multipackage applications, the CONVST signal can be used sion, the result of the previous conversion is shifted out on pin as a chip select signal. The serial interface will not shift data out D . In order to read the result of the current conversion, the until it receives a rising edge on the CONVST pin. OUT user must wait at least 2.3 µs after the falling edge of CONVST t POWER-UP t 1 1.5�s CONVST SCLK B A D OUT CURRENT CONVERSION RESULT Figure 15. Mode 2 Operation Timing t 3 SCLK 12 3 4 5 6 78 9 10 t t 5 4 CONVST t t 7 t 8 6 D OUT DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Figure 16. AD7810 Serial Interface Timing REV. B –9– AD7810 MICROPROCESSOR INTERFACING AD7810 to 8051 The serial interface on the AD7810 allows the parts to be directly The AD7810 requires a clock synchronized to the serial data; connected to a range of many different microprocessors. This therefore, the 8051 serial interface must be operated in Mode section explains how to interface the AD7810 with some of the 0. In this mode serial data enters and exits through RXD, and a more common microcontroller serial interface protocols. serial clock is output on TXD (half duplex). Figure 19 shows how the 8051 is connected to the AD7810. However, because AD7810 to PIC16C6x/7x the AD7810 shifts data out on the rising edge of the serial The PIC16C6x Synchronous Serial Port (SSP) is configured clock, the serial clock must be inverted. as an SPI Master with the Clock Polarity Bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See PIC16/17 Microcontroller User Manual. Figure AD7810* 8051* 17 shows the hardware connections needed to interface to the SCLK TXD PIC16/PIC17. In this example I/O port RA1 is being used to D RXD OUT pulse CONVST and enable the serial port of the AD7810. This CONVST P1.1 microcontroller transfers only eight bits of data during each serial transfer operation, therefore, two consecutive read opera- *ADDITIONAL PINS OMITTED FOR CLARITY tions are needed. Figure 19. Interfacing to the 8051 Serial Port It is possible to implement a serial interface using the data ports PIC16C6x/7x* AD7810* on the 8051 (or any microcontroller). This would allow direct SCK/RC3 SCLK interfacing between the AD7810 and 8051 to be implemented. D SDO/RC5 OUT The technique involves “bit banging” an I/O port (e.g., P1.0) CONVST RA1 to generate a serial clock and using another I/O port (e.g., P1.1) to read in data, see Figure 20. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. Interfacing to the PIC16/PIC17 AD7810* 8051* AD7810 to MC68HC11 SCLK P1.0 The Serial Peripheral Interface (SPI) on the MC68HC11 is D P1.1 OUT configured for Master Mode (MSTR = 0), Clock Polarity Bit CONVST P1.2 (CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)—see *ADDITIONAL PINS OMITTED FOR CLARITY 68HC11 User Manual. A connection diagram is shown in Figure 20. Interfacing to the 8051 Using I/O Ports Figure 18. AD7810* MC68HC11* SCLK/PD4 SCLK D MISO/PD2 OUT CONVST PA0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 18. Interfacing to the MC68HC11 REV. B –10– AD7810 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 14 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) PIN 1 0.015 (0.38) 0.195 (4.95) 0.210 (5.33) 0.115 (2.93) MAX 0.130 0.160 (4.06) (3.30) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.100 0.022 (0.558) 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 8-Lead Small Outline (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.1574 (4.00) 0.2440 (6.20) 1 4 0.1497 (3.80) 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0098 (0.25) 0.0500 (1.27) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) 8-Lead microSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.199 (5.05) 0.187 (4.75) 0.114 (2.90) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.84) 0.112 (2.84) 0.043 (1.09) 0.006 (0.15) 0.037 (0.94) 0.002 (0.05) 33° 0.018 (0.46) 27° 0.028 (0.71) SEATING 0.011 (0.28) 0.008 (0.20) PLANE 0.003 (0.08) 0.016 (0.41) REV. B –11– C01311a–0–10/00 (rev. B) PRINTED IN U.S.A.