ANALOG DEVICES AD7809

a +3.3 V to +5 V Quad/Octal 10-Bit DACs AD7804/AD7805/AD7808/AD7809 FUNCTIONAL BLOCK DIAGRAMS FEATURES Four 10-Bit DACs in One Package AV DV AGND DGND DD DD Serial and Parallel Loading Facilities Available V F* OUT POWER ON REFOUT 1.23V REF RESET AD7804/ AD7804 Quad 10-Bit Serial Loading V E* OUT AD7808 REFIN AD7805 Quad 10-Bit Parallel Loading AV DD V BIAS DIVIDER AD7808 Octal 10-Bit Serial Loading MUX V D DAC D OUT COMP AD7809 Octal 10-Bit Parallel Loading CHANNEL D DATA DAC +3.3 V to +5 V Operation CONTROL REG REGISTER REGISTER Power-Down Mode V BIAS Power-On Reset MUX DAC C V C OUT Standby Mode (All DACs/Individual DACs) CHANNEL C DATA DAC Low Power All CMOS Construction CONTROL REG REGISTER REGISTER 10-Bit Resolution V BIAS MUX V B DAC B OUT Double Buffered DAC Registers Dual External Reference Capability CHANNEL B DATA DAC CONTROL REG REGISTER REGISTER APPLICATIONS V Optical Disk Drives BIAS MUX V A DAC A OUT Instrumentation and Communication Systems Process Control and Voltage Setpoint Control PD** CHANNEL A DATA DAC REGISTER REGISTER CONTROL REG Trim Potentiometer Replacement V H* SYSTEM OUT Automatic Calibration CONTROL REG V G* OUT FSIN INPUT SHIFT CLKIN REGISTER & GENERAL DESCRIPTION CONTROL LOGIC SDIN The AD7804/AD7808 are quad/octal 10-bit digital-to-analog **ONLY AD7804 SHOWN FOR CLARITY CLR LDAC **SHOWS ADDITIONAL CHANNELS ON THE AD7808 converters, with serial load capabilities, while the AD7805/AD7809 **PIN ON THE AD7808 ONLY are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3.3 V to +5 V AV DV DD DD AGND DGND (–10%) power supply and incorporates an on-chip reference. V F* OUT POWER ON REFOUT 1.23V REF RESET AD7805/ V . These DACs provide output signals in the form of V BIAS –SWING V E* OUT AD7809 REFIN is derived internally from V . On-chip control registers V SWING BIAS AV DD V BIAS DIVIDER V D include a system control register and channel control registers. MUX DAC D OUT COMP The system control register has control over all DACs in the CHANNEL D DATA DAC package. The channel control registers allow individual control CONTROL REG REGISTER REGISTER of DACs. The complete transfer function of each individual V BIAS V C MUX point using an on-chip DAC C OUT DAC can be shifted around the V BIAS Sub DAC. All DACs contain double buffered data inputs, CHANNEL C DATA DAC REGISTER which allow all analog outputs to be simultaneously updated CONTROL REG REGISTER using the asynchronous LDAC input. V BIAS V B MUX DAC B OUT Control Features Channels Controlled Main DAC Sub DAC DATA DAC CHANNEL B Hardware Clear All ˇˇ REGISTER REGISTER CONTROL REG System Control 1 V BIAS Power Down All ˇˇ V A MUX DAC A OUT 2 System Standby All ˇˇ System Clear All ˇ CHANNEL A DATA DAC CONTROL REG REGISTER REGISTER Input Coding All ˇˇ PD** Channel Control SYSTEM CONTROL REG V H* 2 OUT Channel Standby Selective ˇˇ INPUT CS CONTROL REGISTER V G* Channel Clear Selective ˇ WR LOGIC OUT V Selective ˇˇ BIAS MODE A0 A1 DB9 DB2 DB1 DB0 A2** CLR LDAC NOTES **ONLY AD7805 SHOWN FOR CLARITY 1 Power-down function powers down all internal circuitry including the reference. **SHOWS ADDITIONAL CHANNELS ON THE AD7809 2 **PIN ON THE AD7809 ONLY Standby functions power down all circuitry except for the reference. REV. A Index on Page 26. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7804/AD7805/AD7808/AD7809 AD7804/AD7805–SPECIFICATIONS (AV and DV = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; DD DD Reference = Internal Reference; C = 100 pF; R = 2 kV to GND. Sub DAC at Midscale. All specifications T to T unless otherwise noted.) L L MIN MAX 1 1 Parameter B Grade C Grade Units Comments STATIC PERFORMANCE MAIN DAC Resolution 10 10 Bits Relative Accuracy–3–3 LSB max Gain Error–3–3 % FSR max 2 Bias Offset Error –80/+40 –80/+40 mV max DAC Code = 0.5 Full Scale 3 Zero-Scale Error ±V ±V mV max DAC Code = 000H for Offset Binary BIAS BIAS / +40 / +40 16 16 Monotonicity 9 10 Bits and 200H for Twos Complement Coding Minimum Load Resistance 2 2 kW min SUB DAC Resolution 8 8 Bits Differential Nonlinearity–0.125–0.125 LSB typ Refers to an LSB of the Main DAC –0.5–0.5 LSB max OUTPUT CHARACTERISTICS 3 Output Voltage Range V – 15/16 · V V – 15/16 · V V Twos Complement Coding BIAS BIAS BIAS BIAS V /16 to 31/16 · V V /16 to 31/16 · V V Offset Binary Coding BIAS BIAS BIAS BIAS Voltage Output Settling Time to 10 Bits 4 4ms max Typically 1.5 ms Slew Rate 2.5 2.5 V/ms typ Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around the Major Carry Digital Feedthrough 0.5 0.5 nV-s typ Digital Crosstalk 0.5 0.5 nV-s typ Analog Crosstalk–0.2–0.2 LSB typ DC Output Impedance 2 2W typ Power Supply Rejection Ratio 0.002 0.002 %/% typDV – 10% DD DAC REFERENCE INPUTS REF IN Range 1.0 to V /2 1.0 to V /2 V min to V max DD DD REF IN Input Leakage–1–1mA max Typically –1 nA DIGITAL INPUTS Input High Voltage, V @ V = 5 V 2.4 2.4 V min IH DD Input High Voltage, V @ V = 3.3 V 2.1 2.1 V min IH DD Input Low Voltage, V @ V = 5 V 0.8 0.8 V max IL DD Input Low Voltage, V @ V = 3.3 V 0.6 0.6 V max IL DD Input Leakage Current–10mA max Input Capacitance 10 10 pF max Input Coding Twos Comp/Binary Twos Comp/Binary REFERENCE OUTPUT REF OUT Output Voltage 1.23 1.23 V nom REF OUT Error–8–8 % max REF OUT Temperature Coefficient –100 –100 ppm/°C typ REF OUT Output Impedance 5 5 kW nom POWER REQUIREMENTS V (AV and DV ) 3/5.5 3/5.5 V min to V max DD DD DD I (AI Plus DI ) Excluding Load Currents DD DD DD Normal Mode 12 12 mA max V = V , V = DGND IH DD IL System Standby (SSTBY) Mode 250 250mAV = V , V = DGND IH DD IL Power-Down (PD) Mode @ +25°C 0.8 0.8mA max V = V , V = DGND IH DD IL T –T 1.5 1.5mA max MIN MAX Power Dissipation Excluding Power Dissipated in Load Normal Mode 66 66 mW max System Standby (SSTBY) Mode 1.38 1.38 mW max Power-Down (PD) Mode @ +25°C 4.4 4.4mW max T –T 8.25 8.25mW max MIN MAX NOTES 1 Temperature range is –40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 V is the center of the output voltage swing and can be V /2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. BIAS DD Specifications subject to change without notice. –2– REV. A AD7804/AD7805/AD7808/AD7809 AD7808/AD7809–SPECIFICATIONS (AV and DV = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; DD DD Reference = Internal Reference; C = 100 pF; R = 2 kV to GND. Sub DAC at Midscale. All specifications T to T unless otherwise noted.) L L MIN MAX 1 Parameter B Grade Units Comments STATIC PERFORMANCE MAIN DAC Resolution 10 Bits Relative Accuracy–4 LSB max Gain Error–3 % FSR max 2 Bias Offset Error–60 mV max DAC Code = 0.5 Full Scale Zero-Scale Error–35 mV max DAC Code = 000H for Offset Binary Monotonicity 9 Bits and 200H for Twos Complement Minimum Load Resistance 2 kW min Coding SUB DAC Resolution 8 Bits Differential Nonlinearity–0.125 LSB typ Refers to an LSB of the Main DAC –0.5 LSB max OUTPUT CHARACTERISTICS 3 Output Voltage Range V – 15/16 · V V Twos Complement Coding BIAS BIAS V /16 to 31/16 · V V Offset Binary Coding BIAS BIAS Voltage Output Settling Time to 10 Bits 4ms max Typically 1.5 ms Slew Rate 2.5 V/ms typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around the Major Carry Digital Feedthrough 0.5 nV-s typ Digital Crosstalk 0.5 nV-s typ Analog Crosstalk–0.2 LSB typ DC Output Impedance 2W typ Power Supply Rejection Ratio 0.002 %/% typDV– 10% DD DAC REFERENCE INPUTS REF IN Range 1.0 to V /2 V min to V max DD REF IN Input Leakage–1mA max Typically –1 nA DIGITAL INPUTS Input High Voltage, V @ V = 5 V 2.4 V min IH DD Input High Voltage, V @ V = 3.3 V 2.1 V min IH DD Input Low Voltage, V @ V = 5 V 0.8 V max IL DD Input Low Voltage, V @ V = 3.3 V 0.6 V max IL DD Input Leakage Current–10mA max Input Capacitance 8 pF max Input Coding Twos Comp/Binary REFERENCE OUTPUT REF OUT Output Voltage 1.23 V nom REF OUT Error–8 % max REF OUT Temperature Coefficient –100 ppm/°C typ REF OUT Output Impedance 5 kW nom POWER REQUIREMENTS V (AV and DV ) 3/5.5 V min to V max DD DD DD I (AI Plus DI ) Excluding Load Currents DD DD DD Normal Mode 18 mA max V = V , V = DGND IH DD IL System Standby (SSTBY) Mode 250mA max V = V , V = DGND IH DD IL Power-Down (PD) Mode @ +25°C1mA max V = V , V = DGND IH DD IL T –T 3mA max MIN MAX Power Dissipation Excluding Power Dissipated in Load Normal Mode 99 mW max System Standby (SSTBY) Mode 1.38 mW max Power-Down (PD) Mode @ +25°C 5.5mW max T –T 16.5mW max MIN MAX NOTES 1 Temperature range is –40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 V is the center of the output voltage swing and can be V /2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. BIAS DD Specifications subject to change without notice. –3– REV. A AD7804/AD7805/AD7808/AD7809 1 (V = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference = AD7804/AD7808 TIMING CHARACTERISTICS DD Internal Reference. All specifications T to T unless otherwise noted.) MIN MAX Limit at T , T MIN MAX Parameter All Versions Units Description t 100 ns min CLKIN Cycle Time 1 t 40 ns min CLKIN High Time 2 t 40 ns min CLKIN Low Time 3 t 30 ns min FSIN Setup Time 4 t 30 ns min Data Setup Time 5 t 5 ns min Data Hold Time 6 t 6 ns min LDAC Hold Time 6A t 90 ns max FSIN Hold Time 7 20 ns min t 40 ns min LDAC, CLR Pulsewidth 8 t 100 ns min LDAC Setup Time 9 NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V + V )/2. IL IH Specifications subject to change without notice. t 1 CLKIN(I) t 2 t 3 t t 4 7 FSIN(I) t 5 t 6 SDIN(I) DB15 DB0 t 6A t 5 1 LDAC t 9 2 LDAC t 8 t 8 CLR 1 TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2 TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 1. Timing Diagram for AD7804 and AD7808 –4– REV. A AD7804/AD7805/AD7808/AD7809 1 AD7805/AD7809 TIMING CHARACTERISTICS (V = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference DD = Internal Reference. All specifications T to T unless otherwise noted.) MIN MAX Limit at T , T MIN MAX Parameter All Versions Unit Description 25 ns min Mode Valid to Write Setup Time t 1 4.5 ns min Mode Valid to Write Hold Time t 2 25 ns min Address Valid to Write Setup Time t 3 4.5 ns min Address Valid to Write Hold Time t 4 25 ns min Data Setup Time t 5 4.5 ns min Data Hold Time t 6 6 ns min LDAC Valid to Write Hold Time t 6A 40 ns min Chip Select to Write Setup Time t 7 0 ns min Chip Select to Write Hold Time t 8 40 ns min Write Pulsewidth t 9 100 ns min Time Between Successive Writes t 10 40 ns min LDAC, CLR Pulsewidth t 11 t 100 ns min Write to LDAC Setup Time 12 NOTE 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V + V )/2. IL IH Specifications subject to change without notice. t 1 t 2 MODE t 4 t 3 A0, A1, A2 t 8 t 7 CS t 10 t 9 WR t 6 t 5 DATA t 6A 1 LDAC t t 12 11 2 LDAC t 11 CLR 1 TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2 TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write REV. A –5– AD7804/AD7805/AD7808/AD7809 1 ABSOLUTE MAXIMUM RATINGS PDIP (N-24) Package, Power Dissipation . . . . . . . . . 670 mW (T = +25°C unless otherwise noted) Aq Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W JA Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD SOIC (R-28) Package, Power Dissipation . . . . . . . . . 875 mW AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V + 0.3 V Lead Temperature, Soldering Digital Input Voltage to DGND . . . . . –0.3 V to DV + 0.3 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Analog Input Voltage to AGND . . . . . –0.3 V to AV + 0.3 V DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C COMP to AGND . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD PDIP (N-28) Package, Power Dissipation . . . . . . . . . 875 mW REF OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to + AV DD q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA REF IN to AGND . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD 2 Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C V to AGND . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V OUT DD 3 SSOP (RS-28) Package, Power Dissipation . . . . . . . . 875 mW Input Current to Any Pin Except Supplies . . . . . . . . –10 mA q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W JA Operating Temperature Range Lead Temperature, Soldering AD7804/AD7805 Commercial Plastic Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C (B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C AD7808/AD7809 Commercial Plastic TQFP (SU-44) Package, Power Dissipation . . . . . .   450 mW (B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W JA Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C SOIC (R-16) Package, Power Dissipation . . . . . . . . . 450 mW Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA NOTES Lead Temperature, Soldering 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C nent damage to the device. This is a stress rating only; functional operation of the Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C device at these or any other conditions above those listed in the operational PDIP (N-16) Package, Power Dissipation . . . . . . . . . 670 mW sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W JA 2 The outputs may be shorted to voltages in this range provided the power dissipation Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C of the package is not exceeded. 3 SOIC (R-24) Package, Power Dissipation . . . . . . . . . 450 mW Transient currents of up to 100 mA will not cause SCR latch-up. q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ORDERING GUIDE Supply Temperature Relative Package Model Voltage Range Accuracy Package Descriptions Options AD7804BN 3.3 V to 5 V –40°C to +85°C–3 LSB 16-Lead Plastic DIP N-16 AD7804BR 3.3 V to 5 V –40°C to +85°C–3 LSB 16-Lead Small Outline IC R-16 AD7805BN 3.3 V to 5 V –40°C to +85°C–3 LSB 28-Lead Plastic DIP N-28 AD7805BR 3.3 V to 5 V –40°C to +85°C–3 LSB 28 Lead Small Outline IC R-28 AD7805BRS 3.3 V to 5 V –40°C to +85°C–3 LSB 28-Lead Shrink Small Outline Package RS-28 AD7805CR 3.3 V to 5 V –40°C to +85°C–3 LSB 28-Lead Small Outline IC R-28 AD7808BN 3.3 V to 5 V –40°C to +85°C–4 LSB 24-Lead Plastic DIP N-24 AD7808BR 3.3 V to 5 V –40°C to +85°C–4 LSB 24 Lead Small Outline IC R-24 AD7809BST 3.3 V to 5 V –40°C to +85°C–4 LSB 44-Lead Thin Plastic Quad Flatpack (TQFP) SU-44 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. A AD7804/AD7805/AD7808/AD7809 AD7804/AD7808 PIN FUNCTION DESCRIPTION AD7804 AD7808 Pin No. Pin No. Mnemonic Description 1 1, 6 AGND Ground reference point for analog circuitry. 2, 3 2, 3 V B, V A Analog output voltage from the DACs. OUT OUT 4 4 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V. 5 PD Active low input used to put the part into low power mode reducing current consumption to 1mA. 7, 8 V F, V E Analog output voltages from the DACs. OUT OUT 59 FSIN Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register and data is transferred on the falling edges of CLKIN. 610 LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the data registers. If LDAC is tied permanently low, or is low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic update will take place. 7 11 SDIN Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift register on the falling edge of CLKIN. 8 12 DGND Ground reference point for digital circuitry. 913 DV Digital Power Supply. DD 10 14 CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Duty Cycle should be between 40% and 60%. 11 15 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to V or to V /16 volts. All Sub DACs are also cleared and thus the BIAS BIAS transfer function of the Main DAC will remain centered around the V point. BIAS 16 NC No Connect. This pin should be left open circuit. 17, 18 V H, V G Analog output voltages from the DACs. OUT OUT 12 20 REFIN This is an external reference input for the DACs. When this reference is selected for a DAC in the control register, the analog output from the selected DAC swings around this point. 13 21 COMP Compensation Pin. This pin provides an output from the internal V /2 divider and is DD provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors to both AV and AGND. This pin can be overdriven with an external reference, thus DD giving the facility for two external references on the part. 14, 15 22, 23 V D, V C Analog output voltage from the DACs. OUT OUT 16 19, 24 AV Analog Power Supply. +3.3 V to +5 V. DD AD7808 PIN CONFIGURATION AD7804 PIN CONFIGURATION 1 24 AGND AV DD AGND 1 16 AV DD 2 23 V B V C OUT OUT V B 2 15 V C OUT OUT 3 22 V A V D OUT OUT V A 3 14 V D OUT OUT 4 21 REFOUT COMP REFOUT 4 AD7804 13 COMP 5 20 REFIN PD TOP VIEW AD7808 12 FSIN 5 REFIN (Not to Scale) 6 19 AGND AV DD TOP VIEW 6 11 LDAC CLR (Not to Scale) V F 7 18 V G OUT OUT 7 10 SDIN CLKIN 8 17 V E V H OUT OUT DGND 8 9 DV 9 16 NC DD FSIN 10 15 LDAC CLR 11 14 SDIN CLKIN 12 13 DGND DV DD NC = NO CONNECT REV. A –7– AD7804/AD7805/AD7808/AD7809 AD7805/AD7809 PIN FUNCTION DESCRIPTIONS AD7805 AD7809 Pin No. Pin No. Mnemonic Description 1, 11, 13, NC No Connect. These pins should be left open circuit. 20, 33 1 2, 5, 39, 40 AGND Ground reference point for analog circuitry. 2, 3 41, 42 V B, V A Analog output voltages from the DACs. OUT OUT 4 43 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V. 5–10, 3, 4, 6, 7, 9, DB9–DB2 Data Inputs. DB9 to DB2 are the 8 MSBs of the data word. 12, 13 10, 15, 23 19, 20 24, 26 DB1, DB0 DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but have other functions when BYTE loading structure is used. 8, 12 V F, V E Analog output voltages from the DACs. OUT OUT 11 14 LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is low during the rising edge of WR similar to data inputs, an automatic update will take place. 14 16 DGND Ground reference point for digital circuitry. 15 17 DV Digital Power Supply. DD 16 18 WR Write Input WR is an active low logic input which is used in conjunction with CS and the address pins to write data to the relevant registers. 17 21 CS Chip Select. Active low logic input. 18 19 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to V or to V /16 volts. All Sub DACs are also cleared and thus the BIAS BIAS transfer function of the MAIN DAC will remain centered around the V point. BIAS 22, 25 V H, V G Analog output voltages from the DACs. OUT OUT 21, 22 27, 29, 30 A2, A1, A0 DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to determine which DAC channel control register or DAC data register is loaded from the input register. These address bits are don’t cares when writing to the system control register. 23 31 MODE Logic Input. Logic high enables writing to the DAC data registers, a logic low enables writing to the control registers. 24 32 REFIN This is an external reference input for the DAC. When this reference is selected for the DAC in the control register, the analog output from the selected DAC swings around this point. 25 34 COMP Compensation Pin. This pin provides an output from the internal V /2 divider and is DD provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors and AGND. This pin can be overdriven with an external reference, thus to both AV DD giving the facility for two external references on the part. 26, 27 35, 36 V D, V C Analog output voltages from the DACs. OUT OUT 28 28, 37, 38 AV Analog Power Supply. DD 44 PD Active low input used to put the part into low power mode reducing current consump- tion to 1mA. AD7805 PIN CONFIGURATION AD7809 PIN CONFIGURATION AGND 1 28 AV DD V B 2 27 V C OUT OUT 44 43 42 41 40 39 38 37 36 35 34 V A 3 26 V D OUT OUT REFOUT 4 25 COMP NC 1 33 NC PIN 1 AGND 2 32 REFIN DB9 5 24 REFIN IDENTIFIER 3 31 DB9 MODE DB8 6 23 MODE AD7805 4 30 DB8 A0 DB7 7 22 A0 TOP VIEW 5 29 AGND A1 AD7809 (Not to Scale) DB6 8 21 A1 DB7 6 28 AV DD TOP VIEW DB5 9 20 DB0 DB6 7 (Not to Scale) 27 A2 V F 8 26 DB0 DB4 10 19 DB1 OUT 9 25 V G DB5 OUT 11 18 LDAC CLR 10 24 DB4 DB1 DB3 12 17 CS 11 NC 23 DB2 DB2 13 16 WR 12 13 14 15 16 17 18 19 20 21 22 DGND 14 15 DV DD NC = NO CONNECT –8– REV. A V E PD OUT NC REFOUT LDAC V A OUT DB3 V B OUT DGND AGND DV AGND DD AV WR DD AV CLR DD NC V C OUT V D CS OUT V H COMP OUT AD7804/AD7805/AD7808/AD7809 TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy Digital-to-analog glitch impulse is the impulse injected into the For the DACs, relative accuracy or endpoint nonlinearity is a analog output when the digital inputs change state with the measure of the maximum deviation, in LSBs, from a straight DAC selected and the LDAC used to update the DAC. It is line passing through the endpoints of the DAC transfer func- normally specified as the area of the glitch in nV-s and is mea- tion. Figures 32 and 33 show the linearity at 3 V and 5 V sured when the digital input code is changed by 1 LSB at the respectively. major carry transition. Regardless of whether offset binary or twos complement coding is used, the major carry transition occurs at Differential Nonlinearity the analog output voltage change of V to V – 1 LSB BIAS BIAS Differential nonlinearity is the difference between the measured or vice versa. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of –1 LSB maxi- Digital Feedthrough mum ensures monotonicity. Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same Bias Offset Error DAC but is measured when the DAC is not updated. It is speci- If the DACs are ideal, the output voltage of any DAC with fied in nV secs and is measured with a full-scale code change on midscale code loaded will be equal to V where V is se- BIAS BIAS the data bus, i.e., from all 0s to all 1s and vice versa. lected by MX1 and MX0 in the control register. The DAC bias offset error is the difference between the actual output voltage Digital Crosstalk and V , expressed in mV. BIAS Digital crosstalk is the glitch impulse transferred to the output of one converter due to a digital code change to another DAC. Gain Error It is specified in nV-s. The difference between the actual and ideal analog output range, expressed as a percent of full-scale range. It is the devia- Analog Crosstalk tion in slope of the DAC transfer characteristic from ideal. Analog crosstalk is a change in output of any DAC in response to a change in the output of one or more of the other DACs. It Zero-Scale Error is measured in LSBs. The zero-scale error is the actual output minus the ideal output from any DAC when zero code is loaded to the DAC. If offset Power Supply Rejection Ratio (PSRR) binary coding is used, the code loaded is 000Hex, and if twos This specification indicates how the output of the DAC is af- complement coding is used, a code of 200HEX is loaded to the fected by changes in the power supply voltage. Power-supply DAC to calculate the zero-scale error. Zero-scale error is ex- rejection ratio is quoted in terms of % change in output per % pressed in mV. change in V for full-scale output of the DAC. V is varied DD DD –10%. AD7804/AD7808 INTERFACE SECTION sequence for the channel control register write, and Figures 6 The AD7804 and AD7808 are serial input devices. Three lines and 7 show the sequence for loading data to the Main and Sub control the serial interface, FSIN, CLKIN and SDIN. The timing DAC data registers. Figure 3 shows the internal registers associ- diagram is shown in Figure 1. ated with the AD7804/AD7808 serial interface DACs. Only one DAC structure is shown for clarity. Two mode bits (MD1 and MD0) which are DB13 and DB14 of the serial word written to the AD7804/AD7808 are used to deter- FSIN mine whether writing is to the DAC data registers or the control 16-BIT CLKIN INPUT SHIFT REGISTER registers of the device. These parts contain a system control SDIN register for controlling the operation of all DACs in the package DECODER as well as a channel control register for controlling the operation of SYSTEM each individual DAC. Table I shows how to access these registers. CONTROL REGISTER Table I. Register Selection Table for the AD7804/AD7808 CHANNEL DATA REGISTER DATA REGISTER CONTROL TO ALL MD1 MD0 Function REGISTER CHANNELS 10 8 DAC REGISTER DAC REGISTER 0 0 Write enable to system control register. SINGLE CHANNEL 10 8 0 1 Write enable to channel control register. 10-BIT DAC 8-BIT DAC 1 X Write enable to DAC data registers. V OUT (MAIN DAC) (SUB DAC) INTERNAL V V REF BIAS When the FSIN input goes low, data appearing on the SDIN V /2 MUX DD REFIN line is clocked into the input register on each falling edge of CLKIN. Data to be transferred to the AD7804/AD7808 is Figure 3. AD7804/AD7808 Internal Registers loaded MSB first. Figure 4 shows the loading sequence for the AD7804/AD7808 system control register, Figure 5 shows the REV. A –9– AD7804/AD7805/AD7808/AD7809 MSB LSB X MD0 = 0 MD1 = 0 X XXXX0 BIN/COMP PD SSTBY SCLR 0 X X X = Don’t Care Figure 4. AD7804/AD7808 System Control Register Loading Sequence DB15 (MSB) DB0 (LSB) X MD0 = 1 MD1 = 0 A2* A1 A0 MX1 MX0 X X X STBY CLR 0 X X X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804. Figure 5. AD7804/AD7808 Channel Control Register Loading Sequence DB15 (MSB) DB0 (LSB) MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804. Figure 6. AD7804/AD7808 Main DAC Data Register Loading Sequence (MAIN/SUB = 0) DB15 (MSB) DB0 (LSB) MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804. Figure 7. AD7804/AD7808 Sub DAC Data Register Loading Sequence (MAIN/SUB = 1) AD7804/AD7808 SYSTEM CONTROL REGISTER (MD1 = 0, When the system control register is selected by writing zeros to MD0 = 0) the mode bits, MD1 and MD0 the address bits are ignored as The bits in this register allow control over all DACs in the the system control register controls all DACs in the package. package. The control bits include power down (PD), DAC input When MD1 = 0 and MD0 = 1, writing is to the channel control coding select (BIN/COMP), system standby (SSTBY) and a register. Only the DAC selected by the address bits will be af- system clear (SCLR). The function of these bits is as follows: fected by writing to this register. Each individual DAC has a channel control register. Power Down (PD) This bit in the control register is used to shut down the complete The DACs data registers are addressed by writing a one to device. With a 0 in this position, the reference and all DACs are MD1 (DB13); the condition of MD0 (DB14) does not matter put into low power mode. Writing a 1 to this bit puts the part in when writing to the data registers. DB15 determines whether the normal operating mode. When in power-down mode, the writing is to the Main DAC data register or to the Sub DAC contents of all registers are retained and are valid when the data register. The Main DAC is 10 bits wide and the Sub DAC device is put back into normal operation. is 8 bits wide. Thus when writing to the Sub DAC DB1 and DB0 become don’t cares. The Sub DAC is used to offset the Coding (BIN/COMP) complete transfer function of the Main DAC around its V BIAS This bit in the system control register allows the user to select point. The Sub DAC has 1/8 LSB resolution and will enable the one of two input coding schemes. The available schemes are transfer function of the Main DAC to be offset by – V /32. BIAS Twos complement coding and offset binary coding. All DACs will be configured with the same input coding scheme. Writing When the LDAC line goes low, all DAC registers in the device a zero to the control register selects twos complement coding, are simultaneously loaded with the contents of their respective while writing a 1 to this bit in the control register selects offset DAC data registers, and the outputs change accordingly. binary coding. Bringing the CLR line low resets the DAC data and DAC regis- With twos complement coding selected the output voltage from ters. This hardware clear affects both the Main and Sub DACs. the Main DAC is of the form : This operation sets the analog output of the Main DAC to V / BIAS 16 when offset binary coding is selected and the output is set to V = V–V OUT BIAS SWING V when twos complement coding is used. V is the output BIAS BIAS where of the internal multiplexer as shown in Figure 3. The output of 15 the Sub DAC is used to shift the transfer function of the Main V is·V SWING BIAS 16 DAC around the V point and the contribution from the Sub BIAS DAC is zero following an external hardware clear. Software With Offset Binary coding selected the output voltage from the clears affect the Main DACs only. Main DAC ranges from: V BIAS 31 V V = to V =·BIAS OUT OUT 16 16 –10– REV. A AD7804/AD7805/AD7808/AD7809 V can be the internal bandgap reference, the internal V /2 Standby (STBY) BIAS DD reference or the external REFIN as determined by MX1 and This bit allows the selected DAC in the package to be put into MX0 in the channel control register. A second external refer- low power mode. Writing a zero to the STBY bit in the channel ence can be used if required by overdriving the V /2 reference control register puts the selected DAC into standby mode. On DD which appears at the COMP pin. writing a zero to this bit all linear circuitry is switched off and the DAC output is connected through a high impedance to System Standby (SSTBY) ground. The DAC is returned to normal operation by writing a This bit allows all the DACs in the package to be put into low one to the STBY bit. power mode simultaneously but the reference is not affected. Writing a one to the SSTBY bit in the system control register Software Clear Function (CLR) puts all DACs into standby mode. On writing a one to this bit This function allows the user to clear the contents of the se- all linear circuitry is switched off and the DAC outputs are lected DAC’s data in software. Writing a one to the CLR bit in connected through a high impedance to ground. The DACs come the control register clears the DAC’s output. A zero in the CLR out of standby mode when a 0 is written to the SSTBY bit. bit position puts the DAC in normal operating mode. This software CLR operation clears only the Main DAC, the con- System Clear Function (SCLR) tents of the Sub DAC is unaffected by a CLR operation. The This function allows the user to clear the contents of all data output of the Main DAC can be cleared to one of two places and DAC registers in software. Writing a one to the SCLR bit depending on the input coding used. An LDAC pulse is re- in the control register clears the DAC’s outputs. A zero in this quired to activate the channel clear function and must be ap- bit position puts the DAC in normal operating mode. The out- plied after the bit in the channel control register is set or reset. If put of the Main DACs are cleared to one of two voltages de- twos complement coding is selected, then issuing a software pending on the input coding used. If twos complement coding clear will reset the output of the Main DAC to midscale (V ). BIAS is selected, then issuing a software clear will reset the output of If offset binary coding is selected, the Main DAC output will be the Main DAC to midscale (V ). If offset binary coding is BIAS reset to V /16 following the execution of a software clear. BIAS selected, the Main DAC output will be reset to V /16 follow- BIAS ing the execution of a software clear. This system clear function Multiplexer Selection (MX1, MX0) does not affect the Sub DAC; the Sub DAC data register retains These two bits are used to select the reference input for the its value during a system software clear (SCLR). selected DAC. Table III shows the options available. Table III. Multiplexer Output Selection AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0, MD0 = 1) MX1 MX0 V BIAS This register allows the user to have control over individual 00 V /2 DACs in the package. The control bits in this register include DD the address bits for the selected DAC, standby (STBY), indi- 0 1 INTERNAL V REF 1 0 REFIN vidual DAC clear (CLR) and multiplexer output selection 1 1 Undetermined (MX1 and MX0). The function of these bits follows. DAC Selection (A2, A1, A0) AD7804/AD7808 SUB DAC DATA REGISTER Bits A2, A1 and A0 in the input registers are used to address a Figure 7 shows the loading sequence for writing to the data specific DAC. Table IIa shows the selection table for the DACs registers of the DACs. DB15 determines whether writing is to of the AD7804. Table IIb shows the selection table for the the Main or Sub DAC’s data register. A one in this position DACs of the AD7808. selects the addressed Sub DAC’s data register. The Sub DAC is Table IIa. DAC Selection Table for the AD7804 8 bits wide and thus DB1 and DB0 of the 16-bit input word are don’t cares when writing to the Sub DAC. This Sub DAC al- A2 A1 A0 Function lows the complete transfer function of each individual DAC to X 0 0 DAC A Selected be offset around the V point. This is achieved by either BIAS X 0 1 DAC B Selected adding or subtracting to the output of the Main DAC. This Sub X 1 0 DAC C Selected DAC has a span of –V /32 with 1/8-bit resolution. The BIAS X 1 1 DAC D Selected coding scheme for the Sub DAC is the same as that for the Main DAC. With offset binary coding the transfer function for the Sub DAC is Table IIb. DAC Selection Table for the AD7808 V A2 A1 A0 Function (NB ±128) BIAS · 16 256 0 0 0 DAC A Selected where NB is the digital code written to the Sub DAC and varies 0 0 1 DAC B Selected from 0 to 255. 0 1 0 DAC C Selected 0 1 1 DAC D Selected With twos complement coding the transfer function for the Sub 1 0 0 DAC E Selected DAC is 1 0 1 DAC F Selected V BIAS NB · () 1 1 0 DAC G Selected 16 256 1 1 1 DAC H Selected where NB is the digital code written to the Sub DAC and varies can be either the internal bandgap from –128 to 127. V BIAS /2 reference or the external REFIN as reference, the internal V DD REV. A –11– AD7804/AD7805/AD7808/AD7809 determined by MX1 and MX0 in the channel control register as POWER-UP shown in Table III. The internal V /2 reference is provided at DD the COMP pin. This internal reference can be overdriven with WRITE TO SYSTEM SYSTEM CONTROL REGISTER CONFIGURATION an external reference thus providing the facility for two external references. WRITE TO CHANNEL CONTROL REGISTER CHANNEL CONFIGURATION AD7804/AD7808 POWER-UP CONDITIONS When power is applied to the device, the device will come up in N standby mode where all the linear circuitry excluding the refer- ALL CHANNELS CONFIGURED ence are switched off. Figure 8 shows the relevant default val- ues for the system control register. Since a write to the system Y control register is required to remove the standby condition the WRITE TO SELECTED only bits for which default conditions are applicable are PD and MAIN OR SUB DAC DATA REGISTERS SSTBY. Figure 9 details the relevant default conditions for the DATA WRITE Channel Control Register. N DATA LOADING COMPLETE PD SSTBY 11 Y CHANGE Figure 8. Default Conditions for System Control Register Y CHANNEL CONFIGURATION on Power-Up N STBY CLR MX1 MX0 CHANGE 1 1 0 0 Y SYSTEM CONFIGURATION Figure 9. Default Conditions for Channel Control Register N on Power-Up END After power has been applied to the device the following proce- dure should be followed to communicate and set up the device. Figure 10. Flowchart for Controlling the DAC Following First, a write to the system control register is required to clear Power-Up the SSTBY bit and change the input coding scheme if required. AD7805/AD7809 INTERFACE SECTION For example, to remove standby and set up offset binary input The AD7805 and AD7809 are parallel data input devices and coding 0060Hex should be written to the input register, if twos contain both control registers and data registers. The system complement coding is required 0020Hex should be written to control register has global control over all DACs in the package the input register. MD1 and MD0 are decoded in the input while the channel control register allows control over individual register and this allows the data to be written to the system DACs in the package. Two data registers are also available, one control register. for the 10-bit Main DAC and the second for the 8-bit Sub Step two requires writing to the channel control register, which DAC. In the parallel mode, CS and WR, in association with the allows individual control over each DAC in the package and address pins, control the loading of data. Data is transferred for the DAC to be selected as well as individual allows the V BIAS from the data register to the DAC register under the control of DAC standby and clear functions. For example, if channel A is the LDAC signal. Only data contained in the DAC register deter- to be configured for normal operation with internal reference mines the analog output of any DAC. The timing diagram for selected then 4110Hex should be written to the input register. 10-bit parallel loading is shown in Figure 2. The MODE pin on In the input register, the MD1 and MD0 bits are decoded in the device determines whether writing is to the data registers or association with the address bits to give access to the required to the control registers. When MODE is at a logic one, writing channel control register. The third and final step is to write data is to the data registers. In the next write to the data registers a to the selected DAC. To write half scale to channel A Main bit in the channel control register determines whether the Main DAC, 2200Hex should be written to the input register, the DAC or the Sub DAC is addressed. This means that to address MSB in the sixteen bit stream selects the Main DAC and the either the Main or the Sub DAC the Main/Sub bit in the control next three bits address the DAC and the final 10 bits contain register has to be set appropriately before the data register write. the data. To write half scale to channel A Sub DAC, then A200 A logic zero on the mode pin enables writing to the control should be written to the input register. The flowchart in Figure register. Bit MD0 determines whether writing is to the system 10 shows in graphic form the steps required in communicating control register or to the addressed channel control register. with the AD7804/AD7808. Bringing the CLR line low resets the DAC registers to one of two known conditions depending on the coding scheme se- lected. The hardware clear affects both the Main and Sub DAC registers. With offset binary coding a clear sets the output –12– REV. A AD7804/AD7805/AD7808/AD7809 DB9 DB0 of the Main DAC to the bottom of the transfer function, V /16. BIAS With twos complement coding the output of the DAC is cleared DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 to midscale which is V . A hardware clear always clears the BIAS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X output of the Sub DAC to midscale thus the output of the Sub DAC makes zero contribution to the output of the channel. X = Don’t Care Figure 14. AD7805/AD7809 Main DAC Data Register (Top) MODE ADDR D9 D2 D1 D0 and Sub DAC Data Register (Bottom) Configuration (MODE = 1, 10/8 = 0) CS CONTROL WR INPUT REGISTER LOGIC LDAC Figure 15 shows the bit allocations when 8-bit parallel operation DECODER is selected in the system control register. DB9 to DB2 are re- SYSTEM tained as data bits. DB1 acts as a high byte or low byte enable. CONTROL REGISTER When DB1 is low, the eight MSBs of the data word are loaded to the input register. When DB1 is high, the low byte consisting CHANNEL DATA REGISTER DATA REGISTER CONTROL of the two LSBs are loaded to the input register. DB0 is used to TO ALL REGISTER CHANNELS 10 8 select either the Main or Sub DAC when in the byte mode. DAC REGISTER DAC REGISTER SINGLE CHANNEL 10 8 DB9 DB2 DB1 DB0 10-BIT DAC 8-BIT DAC V DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 MAIN/SUB OUT (MAIN DAC) (SUB DAC) INTERNAL V V REF BIAS X X X X X XDB1 DB0 1 MAIN/SUB V /2 MUX DD X = Don’t Care REFIN Figure 15. AD7805/AD7809 Main DAC Data Register Con- Figure 11. AD7805/AD7809 Internal Registers figuration (MODE = 1, 10/8 = 1, MAIN/SUB = 0) Figure 16 shows the bit allocations for writing to the Sub DAC. AD7805/AD7809 CONTROL REGISTERS Access to the control registers of the AD7805/AD7809 is DB9 DB2 DB1 DB0 achieved by taking the mode pin to a logic low. The control register of these DACs are configured as in Figures 12 and 13. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X MAIN/SUB There are two control registers associated with the part. System X = Don’t Care control register which looks after the input coding, data format, Figure 16. AD7805/AD7809 Sub DAC Data Register Con- power down, system clear and system standby. The channel figuration (MODE = 1, MAIN/SUB = 1) control register contains bits that affect the operation of the selected DAC. The external address bits are used to select the Each DAC has a separate channel control register. The follow- DACs. These registers are eight bits wide and the last two bits ing is a brief discussion on the bits in each of the control registers. are control bits. The mode pin must be low to have access to the DAC Selection (A2, A1, A0) control registers. The external address pins in conjunction with CS, WR and MODE are used to address the various DAC data and control DB9 DB2 DB1 DB0 registers. Table IVa shows how these DAC registers can be XX 10/8 BIN/COMP PD SSTBY SCLR 0 X MD0 = 0 addressed on the AD7805. Table IVb shows how these registers are addressed on the AD7809. Refer to Figures 12 to 16 for infor- X = Don’t Care mation on the registers. Figure 12. AD7805/AD7809 System Control Register Con- figuration, (MODE = 0) Table IVa. AD7805 DAC Data/Control Register Selection Table DB9 DB2 DB1 DB0 MODE A1 A0 Function Selected MX1 MX0 MAIN/SUB X X STBY CLR 0 X MD0 = 1 X = Don’t Care 0 0 0 DAC A Control Registers 0 0 1 DAC B Control Registers Figure 13. AD7805/AD7809 Channel Control Register Con- 0 1 0 DAC C Control Registers figuration (MODE = 0) 0 1 1 DAC D Control Registers The external mode pin must be taken high to allow data to be 1 0 0 DAC A Data Registers written to the DAC data registers. Figure 14 shows the bit allo- 1 0 1 DAC B Data Registers cations when 10-bit parallel operation is selected in the system 1 1 0 DAC C Data Registers control register. 1 1 1 DAC D Data Registers REV. A –13– AD7804/AD7805/AD7808/AD7809 Table IVb. AD7809 DAC Data/Control Register System Clear Selection Table SCLR 0 Normal operation. MODE A2 A1 A0 Function Selected 1 All DACs in the package are cleared to a known state 0 0 0 0 DAC A Control Register depending on the coding scheme selected. The SCLR bit 0 0 0 1 DAC B Control Register clears the Main DACs only; the Sub DACs are unaf- 0 0 1 0 DAC C Control Register fected by the system clear function. The main DAC is 0 0 1 1 DAC D Control Register cleared to different levels depending on the coding 0 1 0 0 DAC E Control Register scheme. With offset binary coding the Main DAC output 0 1 0 1 DAC F Control Register is cleared to the bottom of the transfer function V /16. BIAS 0 1 1 0 DAC G Control Register With twos complement coding the Main DAC output is 0 1 1 1 DAC H Control Register cleared to midscale V . The channel output will be the BIAS 1 0 0 0 DAC A Data Register sum of the Main DAC and Sub DAC contributions. 1 0 0 1 DAC B Data Register AD7805/AD7809 CHANNEL CONTROL REGISTER 1 0 1 0 DAC C Data Register This register allows the user to have control over individual 1 0 1 1 DAC D Data Register DACs in the package. The control bits in this register include 1 1 0 0 DAC E Data Register multiplexer output selection (MX1 and MX0), Main or Sub 1 1 0 1 DAC F Data Register DAC selection (MAIN/SUB), standby (STBY) and individual 1 1 1 0 DAC G Data Register DAC clear (CLR). The function of these bits is as follows. 1 1 1 1 DAC H Data Register Multiplexer Selection (MX1, MX0) Table V shows the V selection using MX1 and MX0 bits in BIAS AD7805/AD7809 SYSTEM OR CHANNEL CONTROL the channel control register. REGISTER SELECTION Table V. V Selection Table BIAS MD0 0 This enables writing to the system control register. MX1 MX0 V BIAS The contents of this are shown in Figure 12. Mode 00 V /2 (Default on Power-Up) DD must be low to access this control register. 0 1 INTERNAL VREF 1 This enables writing to the channel control register. 1 0 REFIN The contents of this are shown in Figure 13. Mode 1 1 Undetermined must also be low to access this control register. Main DAC or Sub DAC Selection AD7805/AD7809 SYSTEM CONTROL REGISTER MAIN/SUB The bits in this register allow control over all DACs in the pack- 0 Writing a 0 to this bit means that the data in the next age. The control bits include data format (10/8), power down data register write is transferred to the selected Main (PD), DAC input coding select (BIN/COMP), system standby DAC. (SSTBY) and a system clear (SCLR). The function of these bits 1 Writing a 1 to this bit means that the data in the next is as follows: data register write is transferred to the selected Sub DAC. Data Format This applies to the 10-bit parallel load feature. In byte 10/8 load mode, (Figure 15) DB0 selects the Main or Sub 0 10-bit parallel loading structure. DAC data registers. 1 Byte loading structure. (8+2 loading). Standby STBY Input Coding BIN/COMP 0 Places the selected DAC and its associated linear cir- cuitry in Standby Mode. 0 Twos complement coding. 1 Normal operation (default on power-up). 1 Offset Binary Coding. Clear Power Down CLR PD 0 Normal operation. 0 Complete power-down of device. 1 Clears the output of the selected Main DAC to one 1 Normal operation (default on power-up). of two conditions depending on the input coding se- System Standby lected. With offset binary coding the Main DAC out- SSTBY put is cleared to the bottom of the transfer function, V /16 and with twos complement coding the Main BIAS 0 Normal operation. DAC output is cleared to midscale V . The Sub BIAS 1 All DACs in the package put in standby mode (default DAC is unaffected by a clear operation. An LDAC on power-up). signal has to be applied to the DAC for a channel clear to be implemented. –14– REV. A AD7804/AD7805/AD7808/AD7809 POWER-UP CONDITIONS (POWER-ON RESET) START When power is applied to the AD7805/AD7809 the device powers up in a known condition. The device powers up in sys- WRITE TO SYSTEM CONTROL REGISTER tem standby (SSTBY) mode where all DACs in the package are in low power mode, the reference is active and the outputs of Y the DACs are connected internally through a high impedance to WRITE TO MAIN DAC ground. Figure 17 show the default conditions for the system WRITE TO CHANNEL control register. Since a write to the system control register is CONTROL REGISTER N required to remove the standby condition, relevant default con- Y WRITE TO ditions are only applicable for PD and SSTBY in the system WRITE TO MAIN DAC SUB DAC DATA REGISTER control register. The following are the bits in the channel con- WRITE TO CHANNEL CONTROL REGISTER trol register for which default conditions are applicable, STBY, N CLR, MX1 and MX0. Figure 18 shows the default conditions WRITING Y COMPLETE WRITE TO SUB DAC RECONFIGURE for the channel control register. DATA REGISTER SYSTEM Y N PD SSTBY N WRITING COMPLETE END 11 Y Figure 17. Default Conditions for the AD7805/AD7809 System Control Register on Power-Up Figure 19. Flowchart for Controlling the AD7805/AD7809 DACs in 10-Bit Parallel Mode Following Power-Up STBY CLR MX1 MX0 mode as the selection can be made using the hardware bit DB0 and this will reduce the software overheads when accessing the DACs. 11 0 0 CLEAR FUNCTIONS Figure 18. Default Conditions for the AD7805/AD7809 There are three methods of clearing the output of the Main Channel Control Register on Power-Up DAC in these devices. The first is the external hardware clear. The flowchart in Figure 19 shows the steps necessary to control An active low logic signal applied to this pin clears all the DACs the AD7805/AD7809 following power-on. This flowchart de- in the package. The voltage to which the output is cleared will tails the necessary steps when using the AD7805/AD7809 in its depend on the input coding selected. The Main DAC outputs 10-bit parallel mode. The first step is to write to the system are cleared to midscale (V ) in twos complement format and BIAS control register to clear the SSTBY bit and to configure the part to the bottom of the transfer function (V /16) in offset binary BIAS for 10-bit parallel mode and select the required coding scheme. format. The second way of clearing the main DACs is a software The next step is to determine whether writing is to the Main or clear by asserting the SCLR bit in the system control register of Sub DAC. This is achieved by writing to the channel control the part. Writing a one to this bit clears all DACs in the pack- register. Other bits that need to be configured in the channel age. The third method of clearing a DAC is to write a one to the control register are MX1 and MX0 which determine the source CLR bit in the channel control register. This differs from that of of the V for the selected DAC and the channel STBY and BIAS the system control register in that only the selected DACs out- channel CLR bits need to be configured as desired. Once writ- put is cleared. The channel clear requires an LDAC pulse to ing to the channel control register is complete, data can now be activate it. written to the selected Main or Sub DAC. There is only one way of clearing the output of the Sub DAC Parallel data can also be written to the device in 8+2 format to and that is to use the external hardware clear. The output of the allow interface to 8-bit processors. Eight-bit mode is invoked by Sub DAC is cleared to midscale (0 V) regardless of the input writing a one to the 10/8 bit in the system control register. coding being used. Figure 20 shows a simplified diagram of the When in the 8-bit mode the two unused data bits (DB1 and implementation of the clear functions for a single DAC in the DB0) are used as hardware control bits and have the same tim- package. ing characteristics as the address inputs. DB1 is a don’t care bit when writing to both the system and channel control registers; EXT CLR DB0 acts as the mode select bit and must be low to enable writ- SYSTEM CLR CLR ing to the system control register and when high enables access SUB DAC CHANNEL CLR to the channel control register. LDAC When in the 8-bit data write mode, DB1 acts as a low byte and CLR A2 MAIN DAC high byte enable, when low data is written to the 8 MSBs of the ADDR A1 DECODER DAC and when high data is written to the two LSBs. DB0 acts A0 as a bit to select writing to the Main or Sub DAC. When DB0 is ALL OTHER CIRCUITRY OMITTED FOR CLARITY low, writing is to the Main DAC, and when high, writing is to the Sub DAC data register. In the 8+2 mode the channel con- Figure 20. CLR Functions for Main and Sub DACs trol register does not have to be accessed to switch between writing to the Main and Sub DACs as in the 10-bit parallel REV. A –15– AD7804/AD7805/AD7808/AD7809 POWER-DOWN AND STANDBY FUNCTIONS ANALOG OUTPUTS There are two distinct low power modes on the device, power- The AD7804 and AD7805 DACs contain four independent down mode and standby mode. When in power-down mode all voltage output Main DACs with 10-bit resolution. The AD7808 circuitry including the reference are put into low power mode and AD7809 contain eight independent voltage output main and power dissipation from the package is at its minimum. DACs with 10-bit resolution. Each Main DAC has an associ- ated Sub DAC with 8-bit resolution which can be used to offset SYSTEM PD the complete transfer function of the Main DAC around the STANDBY V point. These DACs produce an output voltage in the form SYSTEM STBY BIAS INT of V –V where V is 15/16 of V . REFERENCE BIAS SWING SWING BIAS CHANNEL STBY The digital input code to these DACs can be in twos comple- STANDBY ment or offset binary form. All DACs will be configured with A2 MAIN & SUB the same input coding scheme which is programmed through ADDR A1 DAC DECODER the system control register. The default condition on power-up A0 ONLY ONE DAC SHOWN FOR CLARITY is for offset binary coding. Figure 21. Implementation of Power-Down and Standby TWOS COMPLEMENT CODING Functions Table VI shows the twos complement transfer function for the Main DAC. The standby functions allow either the selected DAC or all DACs in the package to be put into low power mode. The reference is Table VI. Twos Complement Code Table for Main DAC not switched off when any of the standby functions are invoked. Digital Input Analog Output The PD bit in the system control register is used to shut down MSB... LSB the complete device. With a 0 in this position the reference and all DACs are put into low power mode. Writing a 1 to this bit puts the 0111111111 V (1+1.875 · 511/1024) BIAS part in the normal operating mode. When in power-down mode (1+1.875 · 510/1024) 0111111110 V BIAS the contents of all registers are retained and are valid when the (1+1.875 · 1/1024) 0000000001 V BIAS device is taken out of power down. The SSTBY bit which resides 0000000000 V BIAS in the system control register can be used to put all DACs and 1111111111 V (1–1.875 · 1/1024) their associated linear circuitry into standby mode, the SSTBY BIAS function does not power down the reference. The STBY bit in (1–1.875 · 511/1024) 1000000001 V BIAS the channel control register can be used to put a selected DAC 1000000000 V (1–1.875 · 512/1024) BIAS and its associated linear circuitry into standby mode. Figure 18 shows a simplified diagram of how the power-down and standby Figure 22 shows the Main DAC transfer function for twos functions are implemented for a single DAC in the package. complement coding. Any Main DAC output voltage can be expressed as: LDAC FUNCTION V ' = V + 1.875 · V · NA/1024 OUT BIAS BIAS LDAC input is a logic input that allows all DAC registers to be where NA is the decimal equivalent of the twos complement simultaneously updated with the contents of the DAC data input code. NA ranges from –512 to +511. registers. LDAC input has two operating modes, a synchronous mode and an asynchronous mode. The LDAC input condition is 31 sampled on the sixteenth falling edge on the AD7804/AD7808 and V 16 BIAS is sampled on the rising edge of write on the AD7805/AD7809. If LDAC is low on the sixteenth falling clock edge or on the rising edge of WR, an automatic or synchronous update will take place. LDAC input can be tied permanently low or have timing similar to that of the data inputs to operate in the synchronous mode. V BIAS If LDAC is high during the sample period, the AD7804/AD7805/ AD7808/AD7809 assumes an asynchronous update. When in the asynchronous mode, an LDAC setup time has to be allowed following the sixteenth falling clock edge or the rising edge of WR before the LDAC can be activated. V BIAS 16 DAC INPUT CODE 200 201 3FF 000 001 1FE 1FF Figure 22. Main DAC Output Voltage vs. DAC Input Codes (HEX) for Twos Complement Coding –16– REV. A DAC OUTPUT VOLTAGE AD7804/AD7805/AD7808/AD7809 Configuring the AD7805/AD7809 for Twos Complement Coding Table VII shows the twos complement transfer function for the Figure 24 shows a typical configuration for the AD7805/AD7809. Sub DAC. Figure 23 shows the Sub DAC transfer function for The circuit can be used for either 3.3 V or 5 V operation and uses twos complement coding. Any Sub DAC output voltage can be the internal V /2 as the reference for the part and 10-bit paral- DD expressed as: lel interfacing is used. The following are the steps required to V " = V /16 · (NB/256) OUT BIAS operate the Main DACs in this part. where NB is the decimal equivalent of the twos complement input code. NB ranges from –128 to +127. +3.3V/+5V Table VII. Twos Complement Code Table for Sub DAC 0.1mF 0.1mF 10mF Digital Input Analog Input MSB . . . LSB 0.01mF AV DV DD DD COMP REFIN 01111111 (V /16) · (127/256) 0.01mF BIAS /16) · (126/256) 01111111 (V BIAS REFOUT /16) · (1/256) 00000001 (V BIAS A2* AD7805/ A0 00000000 0 AD7809 V A A1 OUT /16) · (1/256) 11111111 (–V BIAS /16) · (127/256) D9 10000001 (–V BIAS DIGITAL V B OUT INTERFACE 10000000 (–V /16) · (128/256) D0 BIAS MODE V C OUT CS V 127 BIAS WR 3 256 16 V D DV CLR OUT DD LDAC DGND AGND *USED ON THE AD7809 ONLY 0 Figure 24. Typical Configuration for AD7805/AD7809 System Control Register Write: MODE = 0, address inputs (A2, A1, A0) are don’t cares. V 128 BIAS Write 020 Hex Configure part for 10-bit parallel, twos 3 256 16 complement coding, normal operation Channel Control Register Write: DAC INPUT CODE 80 81 FF 00 01 7E 7F MODE = 0, address inputs (A2, A1, A0) select desired channel. Figure 23. Sub DAC Output Voltage vs. DAC Input Codes Write 011 Hex Internal V /2 selected as V for DD BIAS (HEX) for Twos Complement Coding DAC, and any DAC data writes that The total output for a single channel when using twos comple- follow are to the Main DAC. ment coding is the sum of the voltage from the Main DAC and DAC Data Register Write: the Sub DAC. MODE = 1, address inputs (A2, A1, A0) select desired channel. V = V ' + V " OUT OUT OUT = V + 1.875 · V · (NA/1024) + V /16 · (NB/256) BIAS BIAS BIAS Write XXX Hex With MODE = 1 all data writes are to the selected DAC. XXX is the required = V · (1 + 1.875 · NA/1024 + NB/4096) BIAS data. 200 Hex will give zero scale and 1FF where NA ranges from –512 to +511 and NB ranges from –128 to Hex will give full scale from the DAC. +127. Figure 28 shows a pictorial view of the transfer function for any DAC. REV. A –17– DAC OUTPUT VOLTAGE AD7804/AD7805/AD7808/AD7809 Table VI and Figure 22 show the analog outputs available for OFFSET BINARY CODING the above configuration. The following is the procedure re- Table VIII shows the offset binary transfer function for the Main quired if the complete transfer function needs to be offset DAC. around the V point. Table VII and Figure 23 show the ana- BIAS Table VIII. Offset Binary Code Table for Main DAC log output variations available from the Sub DAC. Digital Inputs Analog Output System Control Register Write: MSB . . . LSB MODE = 0, address inputs (A2, A1, A0) are don’t cares. 1111111111 V +1.875 · V (1023–512)/1024 BIAS BIAS Write 020 Hex Configure part for 10-bit parallel, twos +1.875 · V (1022–512)/1024 1111111110 V BIAS BIAS complement coding, normal operation +1.875 · V /1024 1000000001 V BIAS BIAS Channel Control Register Write: 1000000000 V BIAS 0111111111 V +1.875 · V (511–512)/1024 MODE = 0, address inputs (A2, A1, A0) select desired channel. BIAS BIAS +1.875 · V (1–512)/1024 0000000001 V BIAS BIAS Write 091 Hex Internal V /2 selected as V for DD BIAS 0000000000 V /16 BIAS DAC, and any DAC data writes that NOTE: The span range is (30/16) · V = 1.875 · V follow are to the Sub DAC. BIAS BIAS DAC Data Register Write: 31 V BIAS 16 MODE = 1, address inputs (A2, A1, A0) select desired channel. Write XX Hex With MODE = 1 all data writes are to the selected DACs Sub DAC. XX is the required data. 7F Hex will give zero scale and 80 Hex will give full scale from the Sub DAC. V BIAS Channel Control Register Write: MODE = 0, address inputs (A2, A1, A0) select desired channel. Write 011 Hex Internal V /2 selected as V for DD BIAS DAC, and any DAC data writes that V BIAS 16 follow are to the Main DAC. DAC Data Register Write: DAC INPUT CODE 000 001 1FF 200 201 3FE 3FF MODE = 1, address inputs (A2, A1, A0) select desired channel. Figure 25. Main DAC Output Voltage vs. DAC Input Codes Write XXX Hex With MODE = 1 all data writes are to (HEX) for Offset Binary Coding the selected Main DAC. XXX is the required data. 1FF Hex will give zero Figure 25 shows the Main DAC transfer function when offset scale and 200 Hex will give full scale binary coding is used. With offset binary coding selected the from the DAC. output voltage can be calculated as follows: V ' = V + 1.875 · V · ((NA-512)/1024) OUT BIAS BIAS where NA is the decimal equivalent of the offset binary input code. NA ranges from 0 to 1023. Table IX shows the offset binary transfer function for the Sub DAC. Figure 26 shows the Sub DAC transfer function for offset binary coding. Any Sub DAC output voltage can be expressed as: V " = V /16 · [(NB-128)/256] OUT BIAS where NB is the decimal equivalent of the offset binary input code. NB ranges from 0 to 255. –18– REV. A DAC OUTPUT VOLTAGE AD7804/AD7805/AD7808/AD7809 Table IX. Offset Binary Code Table for Sub DAC +3.3V/+5V Digital Input Analog Output 0.1mF 10mF 0.1mF MSB . . . LSB 6.8kV 11111111 V /16 · 127/256 BIAS 0.01mF AV DV DD DD /16 · 126/256 11111110 V BIAS COMP REFIN 0.01mF /16 · 1/256 10000001 V BIAS AD589 AD7804/ 10000000 0 AD7808 /16 · 1/256 01111111 –V BIAS FSIN REFOUT /16 · 127/256 00000001 –V BIAS SERIAL SDIN V A INTERFACE OUT 00000000 –V /32 BIAS CLKIN V B OUT V C OUT V 127 BIAS 3 V D 128 32 DV CLR OUT DD LDAC DGND AGND 0 Figure 27. Typical Configuration for AD7804/AD7808 Using an AD589 1.23 V Reference for the AD7804/AD7808 System Control Register Serial Write: Write 0060 Hex Mode bits select system control register V and configure system for offset binary BIAS 32 coding and normal operation. Channel Control Register Serial Write: DAC INPUT CODE 00 01 7F 80 81 FE FF Write 4210 Hex Mode bits select channel control register, Figure 26. Sub DAC Output Voltage vs. DAC Input Codes channel A is configured for operation with (HEX) for Offset Binary Coding external reference. Configuring the AD7804/AD7808 for Offset Binary Coding Main DAC Data Register Serial Write: Figure 27 shows a typical configuration for the AD7804/AD7808. Write 23FF Hex This 16-bit write selects writing to channel This circuit can be used for both 3.3 V or 5 V operation and A and writes full scale to the Main DAC. uses an external AD589 as the reference for the part and serial Sub DAC Data Register Serial Write: interfacing with offset binary coding is used. The MX1 and MX0 bits in the system control register have to be set to enable Write A3FF Hex This 16-bit write selects writing to channel selection of the AD589 as the reference. The following are the A Sub DAC and writes full scale to the steps required to operate the DACs in this part. Figures 4 to 7 Sub DAC. show the contents of the registers on the AD7804/AD7808. Table VIII and Figure 25 show the analog outputs available for the above configuration when writing to the Main DAC only while Table IX and Figure 26 show the contributions from the Sub DAC to the overall transfer function. The total output for a single channel when using offset binary coding is the sum of that from the Main DAC and the Sub DAC. V = V ' + V " OUT OUT OUT = V + 1.875 · V · ((NA-512)/1024) + V /16 BIAS BIAS BIAS = · [(NB-128)/256] = V · (1 + 1.875 · ((NA-512)/1024) + (NB-128)/ BIAS 4096) where NA ranges from 0 to +1023 and NB ranges from 0 to +255. Figure 28 shows a pictorial view of the transfer function for any DAC channel. REV. A –19– DAC OUTPUT VOLTAGE AD7804/AD7805/AD7808/AD7809 MAIN DAC RANGE 2 32 62 V V V 32 32 32 BIAS BIAS BIAS 1 31 63 3 33 61 V V V V V V 32 BIAS BIAS 32 32 32 BIAS 32 BIAS 32 BIAS BIAS SUB DAC RANGE CHANNEL RANGE MIN CODE LOADED TO SUB DAC CHANNEL RANGE CENTER CODE LOADED TO SUB DAC CHANNEL RANGE MAX CODE LOADED TO SUB DAC Figure 28. Pictorial View of Transfer Function for Any DAC Channel Grounding and Layout Techniques should be shielded with analog ground. To reduce the noise on To obtain optimum performance from the AD7804/AD7805/ this reference it should be decoupled with a 0.01 mF capacitor to AD7808/AD7809 care should be taken with the layout. Causes analog ground, keeping the capacitor as close as possible to the for concern would be feedthrough from the interface bus onto device. The comp pin which is the output from the internal the analog circuitry particularly the reference pins and ground V /2 reference is located next to V D on the DAC and is DD OUT loops. The board should be designed such that the analog and sensitive to noise pickup and feedthrough from the DAC output digital sections are separated as much as possible. Ground plan- and thus should be shielded with analog ground to keep this ing and shielding should be used as much as possible. Digital reference point as quiet as possible. The comp pin should be and analog ground planes should only be joined in one place to decoupled both to AV and AGND with 1–10 nF ceramic DD avoid ground loops. The ideal place to join the ground planes is capacitors. The external REFIN pin should also be shielded at the analog and digital ground pins of the DAC. Alternatively with analog ground from the digital pins located next to it. a star ground should be established on the board to which all The same precautions should be taken with the reference pins other grounds are returned. Good decoupling is important in on the AD7804/AD7808 to reduce the risk of noise pickup and achieving optimum performance. All supplies, analog or digital, feedthrough. should be decoupled with 10 mF tantalum and 0.1 mF ceramic Reference Settling Time capacitors to their respective grounds, and should be as close as With the REFOUT on the AD7804/AD7805/AD7808/AD7809 possible to the pins of the device. The main aim of the bypass- decoupled with a 0.01 mF capacitor to AGND it takes the ing element is to maximize the charge stored in the bypass loop REFOUT approximately 2 ms to fully settle after taking the while simultaneously minimizing the inductance of this loop. device out of power down. When this capacitor is reduced to Inductance in the loop acts as an impedance to high frequency 1 nF the settling time reduces to 150 ms. The size of the capaci- transients and results in power supply spiking. By keeping the tor required on the REFOUT depends to a large extent on the decoupling as close as possible to the device, the loop area is kept layout, if the REFOUT is well shielded with AGND the size of to a minimum thus reducing the possibility of power supply spikes. the capacitor can be reduced thus reducing the settling time for On the AD7805 the REFOUT pin of the device is located next the reference. The internal V /2 reference provided at the DD to the DB9 of the data bus, to reduce the risk of digital feed- comp pin when decoupled with a 1 nF capacitor to both AV DD through and noise being coupled from the digital section onto and AGND has very fast settling time, typically less than 500 ns. the reference, the REFOUT pin and any trace connected to it –20– REV. A Typical Performance Characteristics–AD7804/AD7805/AD7808/AD7809 0.150000 2.0 MAIN DAC = ZERO SCALE AV = DV = 5V DD DD SUB DAC = MID SCALE 1.5 V = V /2 BIAS DD 0.125000 V = V /2 BIAS DD T = +258C A T = +258C A 1.0 SUB DAC LOADED WITH 1/2 SCALE 0.100000 V = 5.5V 0.5 DD 0.075000 0.0 –0.5 V = 3V DD 0.050000 –1.0 0.025000 –1.5 SOURCE CURRENT SINK CURRENT 0.000000 –2.0 –0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 100 200 300 400 500 600 700 800 900 1023 CURRENT – mA DAC CODE Figure 29. Sink and Source Current with Zero Scale Figure 32. Integral Linearity with 5 V Operation Loaded to DAC. V = 5 V and V = 3 V DD DD 5.200000 2.0 V = 5.5V DD AV = DV = 3V DD DD MAIN DAC = FULL SCALE 1.5 V = V /2 BIAS DD SUB DAC = MID SCALE 5.180000 T = +258C V = V /2 A BIAS DD 1.0 SUB DAC LOADED WITH T = +258C A 1/2 SCALE R = L 0.5 5.160000 0.0 R = 2kV L 5.140000 –0.5 –1.0 5.120000 –1.5 SOURCE CURRENT SINK CURRENT 5.100000 –2.0 –6.0 –4.0 –2.0 0.0 2.0 4.0 6.0 0 100 200 300 400 500 600 700 800 900 1023 CURRENT – mA DAC CODE Figure 30. Sink and Source Current at Full Scale with Figure 33. Integral Linearity with 3 V Operation V = 5 V DD 2.850000 1.225 V = 3V DD V = 3V DD MAIN DAC = FULL SCALE 1.224 R = 2kV||100pF L SUB DAC = MID SCALE V = V /2 CODE CHANGE 2.830000 BIAS DD 1.223 011111 1111 TO T = +258C A 100000 0000 T = +258C R = A L 1.222 2.810000 1.221 R = 2kV L 1.220 2.790000 1.219 1.218 2.770000 1.217 SOURCE CURRENT SINK CURRENT 2.750000 1.216 –6.0 –4.0 –2.0 0.0 2.0 4.0 6.0 0 20 40 60 80 100 120 140 160 180 200 CURRENT – mA ns Figure 31. Sink and Source Current at Full Scale with Figure 34. Digital-to-Analog Glitch Impulse V = 3 V DD REV. A –21– V – V V – V OUT V – V OUT OUT DAC OUTPUT INTEGRAL LINEARITY – LSBs INTEGRAL LINEARITY – LSBs AD7804/AD7805/AD7808/AD7809 MICROPROCESSOR INTERFACING AD7804*/ AD7804/AD7808–ADSP-2101/ADSP-2103 Interface 68HC11/68L11* AD7808 Figure 35 shows a serial interface between the AD7804/AD7808 PC5 CLR and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP- PC6 LDAC 2103 should be set up to operate in the SPORT Transmit Alter- nate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is FSIN PC7 programmed through the SPORT control register and should be SCK CLKIN configured as follows: Internal Clock Operation, Active Low MOSI SDIN Framing, 16-bit Word Length. Transmission is initiated by writing a word to the TX register after the SPORT has been *ADDITIONAL PINS OMITTED FOR CLARITY enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD7804/AD7808 on the falling edge Figure 36. AD7804/AD7808–68HC11/68L11 Interface of the SCLK. AD7804/AD7808–80C51/80L51 Interface Figure 37 shows a serial interface between the AD7804/AD7808 and the 80C51/80L51 microcontroller. The setup for the inter- AD7804*/ ADSP-2101/ +5V AD7808 face is as follows, TXD of the 80C51/80L51 drives CLKIN of ADSP-2103* the AD7804/AD7808 while RXD drives the serial data line of CLR the part. The FSIN signal is again derived from a bit program- FO LDAC mable pin on the port in this case port line P3.3 is used. When FSIN TFS data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 80C51/80L51 DT SDIN transmits data in eight bit bytes thus only eight falling clock CLKIN SCLK edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted and a *ADDITIONAL PINS OMITTED FOR CLARITY second write cycle is initiated to transmit the second byte of data, P3.3 is taken high following the completion of this cycle. Figure 35. ADSP-2101/ADSP-2103 Interface The 80C51/80L51 outputs the serial data in a format which has AD7804/AD7808–68HC11/68L11 Interface the LSB first. The AD7804/AD7808 requires its data with the Figure 36 shows a serial interface between the AD7804/AD7808 MSB as the first bit received. The 80C51/80L51 transmit rou- and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ tine should take this into account. In the diagram shown LDAC 68L11 drives the CLKIN of the AD7804/AD7808, while the and CLR are also controlled from the bit programmable lines of MOSI output drives the serial data line of the DAC. The FSIN the 80C51/80L51 port. The user can bring LDAC low after signal is derived from a port line (PC7). The setup conditions every two bytes have been transmitted to update that particular for correct operation of this interface are as follows: the DAC which has been programmed or alternatively it is possible 68HC11/68L11 should be configured so that its CPOL bit is a 0 to wait until all the input registers have been loaded before and its CPHA bit is a 1. When data is being transmitted to the updating takes place. DAC the FSIN line is taken low (PC7). When the 68HC11/ 68L11 is configured as above, data appearing on the MOSI AD7804*/ output is valid on the falling edge of SCK. Serial data from the 80C51/80L51* AD7808 68HC11/68L11 is transmitted in 8-bit bytes with only eight P3.5 CLR falling clock edges occurring in the transmit cycle. Data is trans- mitted MSB first. In order to load data to the AD7804/AD7808, P3.4 LDAC PC7 is left low after the first eight bits are transferred and a P3.3 FSIN second serial write operation is performed to the DAC and then TXD SCLK PC7 is taken high at the end of this procedure. In the diagram shown LDAC and CLR are also controlled from the bit pro- RXD SDIN grammable lines of the 68HC11/68L11. The user can bring LDAC low after every two bytes have been transmitted to up- *ADDITIONAL PINS OMITTED FOR CLARITY date that particular DAC which has been programmed or alter- Figure 37. AD7804/AD7808–80C51/80L51 Interface natively it is possible to wait until all the input registers have been loaded before updating takes place. –22– REV. A AD7804/AD7805/AD7808/AD7809 Again fast interface timing allows the AD7805/AD7809 inter- AD7805/AD7809–ADSP-2101 Interface face directly to the processor. Data is loaded to the AD7805/ Figure 38 shows a parallel interface between the AD7805/AD7809 AD7809 input latch using the following instruction: and the ADSP-2101/ADSP-2103 digital signal processor. OUT DAC, D. Fast interface timing allows the AD7805/AD7809 interface directly to the DSP. In this interface an external timer is used to DAC = Decoded DAC Address. update the DACs. D = Data Memory Address. Certain applications may require that the updating of the DAC TIMER latch be controlled by the microprocessor rather than the exter- DMA14 nal timer. One option as shown in the TMS32020 interface is to ADDRESS BUS decode the LDAC from the address bus so that a write opera- DMA0 tion to the DAC latch (at a separate address to the input latch) A0 A1 A2** ADDR updates the output. DECODE LDAC MODE DMS EN AD7805/AD7809–8051/8088 Interface CS AD7805*/ Figure 40 shows a parallel interface between the AD7805/ ADSP-2101*/ ADSP-2103* AD7809 AD7809 and the 8051/8088 processors. WR WR DB9 A15 ADDRESS BUS DB0 A8 A0 A1 A2** DMD15 ADDR DATA BUS DECODE CS MODE DMD0 PSEN OR DEN EN LDAC **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY WR WR Figure 38. AD7805/AD7809–ADSP-2101/ADSP-2103 AD7805*/ 8051/8088 AD7809 Interface OCTAL ALE DB9 LATCH Data is loaded to the AD7805/AD7809 input register using the DB0 following instruction: DM(DAC) = MR0, AD7 ADDRESS/DATA BUS AD0 MR0 = ADSP-2101 MR0 Register. **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY DAC = Decoded DAC Address. Figure 40. AD7805/AD7809–8051/8088 Interface AD7805/AD7809–TMS32020 Interface Figure 39 shows a parallel interface between the AD7805/AD7809 and the TMS32020 processor. A15 ADDRESS BUS A0 A0 A1 A2** ADDR CS DECODE IS EN AD7805*/ AD7809 TMS32020 LDAC STRB WR R/W DB9 DB0 D15 DATA BUS D0 **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY Figure 39. AD7805/AD7809–TMS32020 Interface REV. A –23– AD7804/AD7805/AD7808/AD7809 APPLICATIONS AD7808 CLKIN Opto-Isolated Interface for Process Control Applications FSIN The AD7804/AD7808 has a versatile serial three-wire serial SDIN SDIN interface making it ideal for generating accurate voltages in V process control and industrial applications. Due to noise, safety CLKIN DD LDAC requirements, or distance, it may be necessary to isolate the V CC AD7804/AD7808 from the controller. This can easily be 1Y0 AD7808 achieved by using opto-isolators which will provide isolation in 1G ENABLE 1Y1 FSIN excess of 3 kV. The serial loading structure of the AD7804/ 1A SDIN AD7808 makes it ideally suited for use in opto-isolated appli- 1Y2 CODED CLKIN cations. Figure 41 shows an opto-isolated interface to the 1B ADDRESS LDAC AD7804/AD7808 where SDIN, CLKIN and FSIN are driven 1Y3 from optocouplers. LDAC is hardwired low to reduce the number 74HC139 AD7808 of interface lines and this ensures that each DAC is updated follow- DGND FSIN ing the sixteenth serial clock of a write cycle. SDIN CLKIN +5V LDAC REGULATOR POWER 10mF 0.1mF AD7808 V DD FSIN AV DV DD DD 10kV SDIN REFOUT CLKIN CLKIN CLKIN LDAC 1 TO 10nF REFIN V AD7804/ DD AD7808 10kV V A OUT Figure 42. Decoding Multiple AD7808s Using the FSIN Pin FSIN FSIN AD7805 As a Digitally Programmable Window Detector V B OUT V DD A digitally programmable upper/lower limit detector using two DACs in the AD7805 is shown in Figure 43. The upper and 10kV V C OUT lower limits for the test are loaded to DACs A and B that in DATA SDIN turn set the limits on the CMP04. If a signal at the V input is IN V D OUT V 1 CLR DD not within the programmed window an LED will indicate the LDAC fail condition. Only one limit detector is shown below but can DGND AGND easily be adapted for a dual channel system by using the extra DACs on the AD7805 and the two unused comparators on the CMP04. Figure 41. AD7804/AD7808 Opto-Isolated Interface +5V 0.1mF 10mF Decoding Multiple AD7808s 1kV 1kV FAIL PASS The FSIN pin on the AD7808s can be used in applications to V IN 0.01mF decode a number of DACs. In this application all DACs in the 1/2 AV DV system receive the same serial clock and serial data, but only the DD DD CMP04 COMP FSIN to one of the DACs will be active at any one time allowing V A 0.01mF OUT access to eight channels in this thirty-two channel system. The PASS/ 74HC139 is used as a 2- to 4-line decoder to address any of the AD7805 FAIL D9 DACs in the system. To prevent timing errors from occurring D0 V B OUT the enable input should be brought to its inactive state while the MODE coded address inputs are changing state. Figure 42 shows a 1/6 V C OUT CS 74HC05 system decoding multiple AD7808s in a multichannel system. WR V D OUT DV CLR DD LDAC DGND AGND Figure 43. Digitally Programmable Window Detector –24– REV. A AD7804/AD7805/AD7808/AD7809 Low Cost, Two-Channel Mixer Using AD7805, SSM2164 and Dual External Reference Input Capability OP275 It is possible to operate the AD7804/AD7805/AD7808/AD7809 The SSM2164 is a quad voltage controlled amplifier (VCA) with two externally applied references. Figure 45 shows the with 120 dB of gain control range. Each VCA in the package is connections for the AD7804. Reference one, the AD589, is a current in, current out device with a –33 mV/dB voltage con- connected to the REFIN pin of the part; the second reference, trol input port. Figure 44 shows a basic application circuit the AD780, is used to overdrive the internal VDD/2 reference which can be used to implement a low cost stereo, two channel which is provided at the COMP pin of the device. With the mixer. A 30 kW resistor converts the input voltage to an input circuit shown in Figure 45 it is possible to configure two of the current for the VCA. The 500 W resistor and 560 pF capacitor channels for operation with the AD780 2.5 V reference and the on the input are added to ensure stable operation of the other two with the AD589 1.23 V reference. The channel con- SSM2164. The I pin of the SSM2164 should be maintained trol register allows the user to select the reference for the indi- OUT at virtual ground and thus the OP275 is operated in its inverting vidual channels. mode. Its wide bandwidth, high slew rate and low power make it +5V ideal for a current to voltage converter. A 30 kW feedback resis- tor is chosen to match the input resistor and thus give unity gain 10mF 0.1mF 0.1mF for a zero volt control voltage input. The 100 pF capacitors reduce high frequency noise and can be increased to reduce the 6.8kV V IN AV DV DD DD low pass cutoff frequency for further noise reduction. The V O COMP REFIN AD780 AD7805 in the circuit is used to control the attenuation of the 0.01mF AD589 GND VCA, this application circuit only gives attenuation. The voltage AD7804 output from the AD7805 provides a low impedance drive to the FSIN REFOUT SSM2164 so attenuation can be controlled accurately. With a SERIAL SDIN V A INTERFACE 5 V V and a V of V /2 the AD7805 has an LSB size of OUT DD BIAS DD CLKIN V B approximately 4.5 mV. Therefore, the attenuation can be con- OUT trolled with a resolution of 0.136 dB/bit and thus 750 codes are DV CLR V C DD OUT required to provide the full 100 dB of attenuation. LDAC V D OUT DGND AGND Figure 45. Two Externally Applied References +5V V 2 V 1 IN IN 0.1mF 10mF 30kV 30kV 100pF +15V 500V 500V 30kV 0.01mF AV DV DD DD 560pF 560pF +15V COMP +V 1/2 0.01mF IN 1 OP275 AD7805 V 1 V A C OUT V A OUT IN D9 2 –15V D0 V 2 C V B OUT 100pF IN MODE 3 V 3 CS 30kV C V C OUT WR IN 4 +15V 1/2 DV CLR V 4 DD C OP275 V D OUT LDAC SSM2164 V B OUT DGND AGND –V 500V 500V –15V 560pF 560pF –15V 30kV 30kV V 3V 4 IN IN Figure 44. Low Cost, Two-Channel Mixer REV. A –25– AD7804/AD7805/AD7808/AD7809 PAGE INDEX PAGE INDEX (AD7804/AD7808 SERIAL INTERFACE PART) (AD7805/AD7809 PARALLEL INTERFACE PART) Topic Page No. Topic Page No. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Timing Information Timing Information Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Terminology Terminology Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . 9 Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . 9 Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 14 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 11 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . 14 SUB DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down and Standby Functions . . . . . . . . . . . . . . . . 16 Power-Down and Standby Functions . . . . . . . . . . . . . . . . . 16 LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer Functions Transfer Functions Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . 16 Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . . 16 Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . 17 Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . . 17 Complete Channel Transfer Function . . . . . . . . . . . . . . 17 Complete Channel Transfer Function . . . . . . . . . . . . . . . 17 Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . 18 Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . . 18 Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . 19 Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . . 19 Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . 20 Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . . 20 Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical Performance Characteristics . . . . . . . . . . . . . . . . . 21 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 21 Microprocessor Interfacing Microprocessor Interfacing ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . 23 ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . . 22 TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 68HC11/68L11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8051/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 80C51/80L51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications Applications Programmable Window Detector . . . . . . . . . . . . . . . . . . 24 Opto-Isolated Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Low Cost Two-Channel Mixer . . . . . . . . . . . . . . . . . . . 25 Decoding Multiple ICs . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dual External Reference Input Capability . . . . . . . . . . . 25 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28 –26– REV. A AD7804/AD7805/AD7808/AD7809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-28) Plastic DIP (N-16) 0.840 (21.33) 28 15 0.745 (18.93) 0.580 (14.73) 16 9 0.280 (7.11) 0.485 (12.32) PIN 1 0.240 (6.10) 18 1 14 0.325 (8.25) 0.195 (4.95) 0.060 (1.52) 0.300 (7.62) 1.565 (39.70) PIN 1 0.115 (2.93) 0.015 (0.38) 1.380 (35.10) 0.060 (1.52) 0.250 0.015 (0.38) 0.210 (5.33) (6.35) MAX 0.130 MAX 0.150 (3.30) 0.160 (4.06) 0.200 (5.05) (3.81) MIN 0.125 (3.18) MIN 0.115 (2.93) 0.015 (0.381) 0.100 0.070 (1.77) SEATING 0.022 (0.558) 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.204) SEATING PLANE (2.54) MAX (2.54) 0.014 (0.356) 0.045 (1.15) 0.014 (0.356) PLANE BSC BSC 0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18) SOIC (R-16) 0.015 (0.381) 0.008 (0.204) 0.4133 (10.50) 0.3977 (10.00) SOIC (R-28) 16 9 28 15 1 8 0.2992 (7.60) 0.2914 (7.40) 0.1043 (2.65) 0.4193 (10.65) PIN 1 0.0291 (0.74) PIN 1 x 45° 0.3937 (10.00) 0.0118 (0.30) 0.0926 (2.35) 0.0098 (0.25) 1 14 0.0040 (0.10) 0.0500 (1.27) 8° 0.1043 (2.65) 0.7125 (18.10) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40) 0.0926 (2.35) SEATING 0.0125 (0.32) (1.27) 0.6969 (17.70) 0.0291 (0.74) 0.0138 (0.35) PLANE x 45° BSC 0.0091 (0.23) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0157 (0.40) 0.0118 (0.30) 0° 0.0192 (0.49) 0.0500 (1.27) 0.0125 (0.32) 0.0040 (0.10) BSC 0.0138 (0.35) 0.0091 (0.23) SSOP (RS-28) 28 15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) PIN 1 1 14 0.07 (1.78) 0.407 (10.34) 0.066 (1.67) 0.397 (10.08) 8° 0.03 (0.762) 0° 0.022 (0.558) 0.008 (0.203) 0.0256 (0.65) 0.015 (0.38) 0.009 (0.229) BSC 0.010 (0.25) 0.002 (0.050) 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS REV. A –27– 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) AD7804/AD7805/AD7808/AD7809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TQFP (SU-44) Plastic DIP (N-24) 0.047 (1.20) MAX 13 0.472 (12.00) SQ 24 0.280 (7.11) 0.030 (0.75) PIN 1 0.240 (6.10) 0.018 (0.45) 33 23 1 12 34 22 SEATING 1.275 (32.30) 0.325 (8.25) 1.125 (28.60) 0.015 0.300 (7.62) PLANE (0.38) 0.210 MIN 0.195 (4.95) 0.394 (5.33) 0.115 (2.93) TOP VIEW MAX (10.0) (PINS DOWN) 0.130 SQ 0.160 (4.06) (3.30) 0.115 (2.92) MIN 0.015 (0.381) 0.008 (0.203) 0.022 (0.558) 0.070 (1.77) 0.100 (2.54) SEATING 44 12 0.014 (0.356) BSC 0.045 (1.15) PLANE 1 11 0.006 (0.15) 0.002 (0.05) 0.018 (0.45) 0.031 (0.80) 0.04134 (1.05) BSC 0.012 (0.30) 0.0374 (0.95) SOIC (R-24) 0.614 (15.6) 0.598 (15.2) 24 13 0.299 (7.6) 0.419 (10.65) 0.291 (7.4) 0.394 (10.00) 1 12 PIN 1 0.104 (2.65) 0.03 (0.75) 0.093 (2.35) 0.01 (0.25) 88 0.012 (0.3) 0.0500 (1.27) 0.019 (0.49) 08 SEATING 0.0500 (1.27) 0.013 (0.32) BSC PLANE 0.004 (0.1) 0.014 (0.35) 0.0157 (0.40) 0.009 (0.25) –28– REV. A PRINTED IN U.S.A. C2107A–1–12/98