ANALOG DEVICES AD7801

+2.7 V to +5.5 V, Parallel Input, a Voltage Output 8-Bit DAC AD7801 FUNCTIONAL BLOCK DIAGRAM FEATURES Single 8-Bit DAC 20-Pin SOIC/TSSOP Package +2.7 V to +5.5 V Operation D7 INPUT DAC V I DAC I/V OUT Internal and External Reference Capability REGISTER REGISTER D0 DAC Power-Down Function Parallel Interface POWER-ON MUX RESET WR On-Chip Output Buffer Rail-to-Rail Operation CONTROL LOGIC CS Low Power Operation 1.75 mA max @ 3.3 V‚2 AGND AD7801 Power-Down to 1 mA max @ 258C REFIN V DGND PD CLR LDAC APPLICATIONS DD Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7801 is a single, 8-bit, voltage out DAC that operates 1. Low Power, Single Supply operation. This part operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output from a single +2.7 V to +5.5 V supply and consumes typically 5 mW at 3 V, making it ideal for battery powered applications. buffer allows the DAC output to swing rail to rail. The AD7801 has a parallel microprocessor and DSP compatible interface with 2. The on-chip output buffer amplifier allows the output of the high speed registers and double buffered interface logic. Data is DAC to swing rail to rail with a settling time of typically 1.2 μs. loaded to the input register on the rising edge of CS or WR. 3. Internal or external reference capability. Reference selection for the AD7801 can be either an internal 4. High speed parallel interface. reference derived from the V or an external reference applied DD 5. Power-down capability. When powered down the DAC at the REFIN pin. The output of the DAC can be cleared by consumes less than 1 μA at 25°C. using the asynchronous CLR input. 6. Packaged in 20-lead SOIC and TSSOP packages. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consump- tion is less than 5 mW at 3.3 V, reducing to less than 3 μW in power-down mode. The AD7801 is available in a 20-lead SOIC and a 20-lead TSSOP package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1997 (V = +2.7 V to +5.5 V, Internal Reference; C = 100 pF, R = 10 kV to V and GND. DD L L DD All specifications T to T unless otherwise noted.) AD7801–SPECIFICATIONS MIN MAX 1 Parameter B Versions Units Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits 2 Relative Accuracy ±1 LSB max Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Zero-Code Error @ +25°C 3 LSB typ All Zeros Loaded to DAC Register Full-Scale Error –0.75 LSB typ All Ones Loaded to DAC Register Zero-Code Error Drift 100 μV/°C typ 3 Gain Error ±1 % FSR typ DAC REFERENCE INPUT REFIN Input Range 1 to V /2 V min/V max DD REFIN Input Impedance 10 MΩ typ OUTPUT CHARACTERISTICS Output Voltage Range 0 to V V min/V max DD Output Voltage Settling Time 2 μs max Typically 1.2 μs Slew Rate 7.5 V/μs typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry Digital Feedthrough 0.2 nV-s typ DC Output Impedance 40 Ω typ Short Circuit Current 14 mA typ 4 Power Supply Rejection Ratio 0.0003 %/% max ΔV = ±10% DD LOGIC INPUTS Input Current ±10 μA max V , Input Low Voltage 0.8 V max V = +5 V INL DD V , Input Low Voltage 0.6 V max V = +3 V INL DD V , Input High Voltage 2.4 V min V = +5 V INH DD V , Input High Voltage 2.1 V min V = +3 V INH DD Pin Capacitance 7 pF max POWER REQUIREMENTS 2.7/5.5 V min/V max V DD I (Normal Mode) DAC Active and Excluding Load Current DD = 3.3 V V = V and V = GND V DD IH DD IL @ 25°C 1.55 mA max See Figure 6 to T 1.75 mA max T MIN MAX V = 5.5 V DD @ 25°C 2.35 mA max T to T 2.5 mA max MIN MAX (Power-Down) I DD @ 25°C1 μA max V = V and V = GND IH DD IL T to T 2 μA max See Figure 18 MIN MAX NOTES 1 Temperature ranges are as follows: B Version: –40°C to +105°C 2 Relative Accuracy is calculated using a reduced code range of 15 to 245. 3 Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4 Guaranteed by characterization at product release, not production tested. Specifications subject to change without notice. t t 1 2 CS t 3 WR t t 4 5 D7-D0 t t 6 7 LDAC t 8 CLR Figure 1. Timing Diagram for Parallel Data Write REV. 0 –2– AD7801 (V = +2.7 V to +5.5 V; GND = 0 V; Internal V /2 Reference. All specifications T to T DD DD MIN MAX 1, 2 TIMING CHARACTERISTICS unless otherwise noted.) Limit at T , T MIN MAX Parameter (B Version) Units Conditions/Comments t 0 ns min Chip Select to Write Setup Time 1 t 0 ns min Chip Select to Write Hold Time 2 t 20 ns min Write Pulse Width 3 t 15 ns min Data Setup Time 4 t 4.5 ns min Data Hold Time 5 t 20 ns min Write to LDAC Setup Time 6 t 20 ns min LDAC Pulse Width 7 t 20 ns min CLR Pulse Width 8 NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of DD (V + V )/2. tr and tf should not exceed 1 μs on any digital input. IL IH 2 See Figure 1. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (T = +25°C unless otherwise noted) A Temperature Package V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Model Range Option* Reference Input Voltage to AGND . . . .–0.3 V to V + 0.3 V DD Digital Input Voltage to DGND . . . . . .–0.3 V to V + 0.3 V AD7801BR –40°C to +105°C R-20 DD AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AD7801BRU –40°C to +105°C RU-20 V to AGND . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT DD *R = Small Outline; RU = Thin Shrink Small Outline. Operating Temperature Range Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7801 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– AD7801 PIN CONFIGURATION (MSB) DB7 1 20 DGND DB6 2 19 V OUT DB5 3 18 NC DB4 4 17 AGND DB3 5 16 REFIN AD7801 TOP VIEW DB2 6 15 V DD (Not to Scale) DB1 7 14 CLR (LSB) DB0 8 13 LDAC CS 9 12 PD WR 10 11 DGND NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1–8 D7–D0 Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR. 9 CS Chip Select. Active low logic input. 10 WR Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register. 11 DGND Digital Ground 12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 μA. 13 LDAC Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR. 14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all zeroes and the DAC output is cleared to zero volts. 15 V Power Supply Input. This part can be operated from +2.7 V to +5.5 V and should be decoupled to GND. DD 16 REFIN External Reference Input. This can be used as the reference for the DAC. The range on this reference input is 1 V to V /2. If REFIN is tied directly to V the internal V /2 reference is selected. DD DD DD 17 AGND Analog Ground reference point and return point for all analog current on the part. 18 NC No Connect Pin. 19 V Analog Output Voltage from the DAC. The output amplifier can swing rail to rail on its output. OUT 20 DGND Digital Ground reference point and return point for all digital current on the part. REV. 0 –4– Typical Performance Characteristics–AD7801 5 800 3.5 V = 5V AND 3V 4.92 720 DD 3.25 INTERNAL REFERENCE 640 T = +25 C 4.84 A 3.0 DAC LOADED WITH 00HEX 560 4.76 2.75 480 4.68 2.5 400 4.6 2.25 320 4.52 2.0 V = 5V DD 4.44 V = 3V 240 1.75 DD INTERNAL REFERENCE INTERNAL REFERENCE DAC REGISTER LOADED 160 4.36 1.5 DAC REGISTER LOADED WITH FFHEX WITH FFHex T = +25°C A 80 4.28 1.25 T = +25°C A 0 4.2 1.0 08 24 6 02 46 8 01 23 4567 8 SINK CURRENT – mA SOURCE CURRENT – mA SOURCE CURRENT – mA Figure 2. Output Sink Current Capa- Figure 3. Output Source Current Figure 4. Output Source Current bility with V = 3 V and V = 5 V Capability with V = 5 V DD DD DD Capability with V = 3 V DD 0.5 4.0 4.0 INTERNAL REFERENCE DAC ACTIVE V = 5V 0.45 DD LOGIC INPUTS = V OR GND DD INTERNAL REFERENCE 3.5 T = +25 C A DAC ACTIVE T = +25°C A 0.4 3.0 3.0 LOGIC INPUTS = V OR V 0.35 IH IL 2.5 0.3 INL ERROR 0.25 V = 5.5V 2.0 DD 2.0 0.2 1.5 0.15 V = 3.3V LOGIC INPUTS = V OR GND DD DD 1.0 DNL ERROR 1.0 0.1 0.5 0.05 0 0 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 –50 –25 0 255075 100 125 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE – Volts TEMPERATURE – C V – Volts DD Figure 5. Relative Accuracy vs. Figure 6. Typical Supply Current Figure 7. Typical Supply Current External Reference vs. Temperature vs. Supply Voltage 10 5 WR T 0 1‹ –5 PD 2‹–10 2‹ –15 V OUT ‹–20 V OUT –25 V = 3V DD V OUT V = 5V DD INTERNAL VOLTAGE‹–30 1 EXTERNAL SINEWAVE REFERENCE AD7801 POWER-UP TIME REFERENCE DAC REGISTER LOADED WITH FFHEX –35 FULL SCALE CODE V = 5V DD T = +25°C A CHANGE 00H-FFH INTERNAL REFERENCE 3‹–40 T = +25°C DAC IN POWER-DOWN INITIALLY A 1 10 100 1k 10k FREQUENCY – Hz CH1 = 2V/div, CH2 = 5V/Div, CH1 5V, CH2 1V, CH3 20mV TIME BASE = 2 ms/Div TIME BASE = 200 ns/Div Figure 10. Exiting Power-Down (Full Figure 9. Full-Scale Settling Time Figure 8. Large Scale Signal Power-Down) Frequency Response REV. 0 –5– ERROR – LSBs ATTENUATION – dB V – mV OUT I – mA DD V – Volts OUT V – Volts I – mA OUT DD AD7801–Typical Performance Characteristics 10 9 T WR V 8 DD V = 5V DD 1‹1 INTERNAL VOLTAGE 7 REFERENCE VDD = 2.7 TO 5.5V 10 LSB STEP CHANGE 6 DAC LOADED WITH ALL ZEROES T = +258C A INTERNAL REFERENCE T 5 2 V V OUT OUT 4 3 2 1 2‹ 0 CH1 5.00V, CH2 50.0mV, M 250ns CH1 M20.0ms 5.00V CH2 5.00V CH1 –50 –25 0 25 50 75 100 125 TEMPERATURE – C Figure 11. Power-On—Reset Figure 12. Zero Code Error vs. Figure 13. Small-Scale Settling Time Temperature 0.5 0.5 0.5 V = 5V DD 0.4 0.4 0.4 INTERNAL REFERENCE 5kΩ 100pF LOAD 0.3 0.3 0.3 LIMITED CODE RANGE (15–245) T = +25°C 0.2 A 0.2 0.2 V = 5V DD INTERNAL REFERENCE 0.1 V = 5V 0.1 0.1 DD INTERNAL REFERENCE 0 0 0 –0.1 –0.1 –0.1 –0.2 –0.2 –0.2 –0.3 –0.3 –0.3 –0.4 –0.4 –0.4 –0.5 –0.5 –0.5 0 32 64 96 128 160 192 224 256 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 INPUT CODE (15 to 245) TEMPERATURE – C TEMPERATURE – C Figure 14. Integral Linearity Plot Figure 15. Typical INL vs. Temperature Figure 16. Typical DNL vs. Temperature 1000 1.0 V = 5V DD 900 V = 5V DD LOGIC INPUTS = V OR GND DD 800 0.8 700 600 0.6 500 400 0.4 300 200 0.2 100 0 0 255075 100 150 0 –50 –25 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – C TEMPERATURE – C Figure 17. Typical Internal Reference Figure 18. Power-Down Current vs. Error vs. Temperature Temperature REV. 0 –6– INL ERROR – LSB INT REFERENCE ERROR – % INL ERROR – LSB ZERO CODE ERROR – LSB POWER DOWN CURRENT – nA DNL ERROR – LSB AD7801 TERMINOLOGY Integral Nonlinearity AD7801 REFERENCE V DD 11.7kΩ For the DAC, Relative Accuracy or End-Point nonlinearity is a AMPLIFIER measure of the maximum deviation, in LSBs, from a straight 30kΩ CURRENT line passing through the endpoints of the DAC transfer DAC REFIN I/V V OUT function. A graphical representation of the transfer curve is 11.7kΩ shown in Figure 14. 30kΩ Differential Nonlinearity Differential Nonlinearity is the difference between the mea- sured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB Figure 19. DAC Architecture maximum ensures monotonicity. The DAC output is internally buffered and has rail-to-rail Zero-Code Error output characteristics. The output amplifier is capable of driving Zero-Code Error is the measured output voltage from V of OUT a load of 100 pF and 10 kΩ to both V and ground. The DD the DAC when zero code (all zeros) is loaded to the DAC reference selection for the DAC can be either internally gener- latch. It is due to a combination of the offset errors in the DAC ated from V or externally applied through the REFIN pin. A DD and output amplifier. Zero-code error is expressed in LSBs. comparator on the REFIN pin detects whether the required Gain Error reference is the internally generated reference or the externally This is a measure of the span error of the DAC. It is the applied voltage to the REFIN pin. If REFIN is connected to deviation in slope of the DAC transfer characteristic from ideal V , the reference selected is the internally generated V /2 DD DD expressed as a percent of the full-scale value. It includes full- reference. When an externally applied voltage is more than one scale errors but not offset errors. volt below V , the comparator selection switches to the externally DD applied voltage on the REFIN pin. The range on the external Digital-to-Analog Glitch Impulse reference input is from 1.0 V to V /2 V. The output voltage DD Digital-to-Analog Glitch Impulse is the impulse injected into from the DAC is given by: the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC. It   N V = 2V × O REF is normally specified as the area of the glitch in nV-secs and   256   measured when the digital input code is changed by 1 LSB at the major carry transition. where V is the voltage applied to the external REFIN pin or REF V /2 when the internal reference is selected. N is the decimal DD Digital Feedthrough equivalent of the code loaded to the DAC register and ranges Digital Feedthrough is a measure of the impulse injected into from 0 to 255. the analog output of a DAC from the digital inputs of the same DAC, but is measured when the DAC is not updated. It is specified in nV-secs and measured with a full-scale code change V DD on the data bus, i.e., from all 0s to all 1s and vice versa. VTH Power Supply Rejection Ratio (PSRR) PMOS This specification indicates how the output of the DAC is affected COMPARATOR INT REF by changes in the power supply voltage. Power supply rejection REF IN ratio is quoted in terms of % change in output per % change in V for full-scale output of the DAC. V is varied ±10%. EXT REF DD DD MUX INT GENERAL DESCRIPTION REF D/A Section The AD7801 is an 8-bit voltage output digital-to-analog con- SELECTED REFERENCE verter. The architecture consists of a reference amplifier and a OUTPUT current source DAC followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the DAC. Figure 19 shows a block diagram of the basic DAC Figure 20. Reference Selection Circuitry architecture. REV. 0 –7– AD7801 Automatic Update Mode Reference In this mode of operation the LDAC signal is permanently tied The AD7801 has the ability to use either an external reference low. The state of the LDAC is sampled on the rising edge of applied through the REFIN pin or an internal reference generated WR. LDAC being low allows the DAC register to be automati- from V . Figure 20 shows the reference input arrangement DD cally updated on the rising edge of WR. The output update where either the internal V /2 or the externally applied reference DD occurs on the rising edge of WR. Figure 23 shows the timing can be selected. associated with the automatic update mode of operation and The internal reference is selected by tying the REFIN pin to also the status of the various registers during this frame. V . If an external reference is to be used, this can be directly DD applied to the REFIN pin and if this is 1 V below V , the DD internal circuitry will select this externally applied reference as CS the reference source for the DAC. WR Digital Interface The AD7801 contains a fast parallel interface allowing this D7-D0 DAC to interface to industry standard microprocessors, microcontrollers and DSP machines. There are two modes in LDAC = 0 which this parallel interface can be configured to update the TRACK I/P REG (MLE) HOLD HOLD DAC output. The synchronous update mode allows synchro- nous updating of the DAC output; the automatic update mode DAC REG (SLE) TRACK HOLD TRACK allows the DAC to be updated individually following a write cycle. Figure 21 shows the internal logic associated with the V OUT digital interface. The PON STRB signal is internally generated from the power-on reset circuitry and is low during the power- Figure 23. Timing and Register Arrangement for Auto- on reset phase of the power up procedure. matic Update Mode CLR Synchronous Update Mode CLR In this mode of operation the LDAC signal is used to update the PON STRB DAC output to synchronize with other updates in the system. CLEAR MLE The state of the LDAC is sampled on the rising edge of WR. If SET SLE LDAC LDAC is high, the automatic update mode is disabled and the DAC CONTROL LDAC SLE LOGIC DAC latch is updated at any time after the write by taking ENABLE LDAC low. The output update occurs on the falling edge of CS LDAC. LDAC must be taken back high again before the next WR data transfer takes place. Figure 24 shows the timing associated with the synchronous update mode of operation and also the Figure 21. Logic Interface status of the various registers during this frame. The AD7801 has a double buffered interface, which allows for synchronous updating of the DAC output. Figure 22 shows a CS block diagram of the register arrangement within the AD7801. WR 4 15 15 30 D7-D0 DB7-DB0 8 UPPER NIBBLE LDAC I/P REG (MLE) HOLD TRACK HOLD 4 15 15 30 DAC REG (SLE) HOLD TRACK HOLD LOWER NIBBLE V OUT MLE SLE Figure 24. Timing and Register Arrangement for Synchro- CS WR nous Update Mode CONTROL LOGIC LDAC CLR Figure 22. Register Arrangement REV. 0 –8– INPUT REGISTER 4 TO 15 4 TO 15 DECODER DECODER DAC DAC REGISTER REGISTER DRIVERS DRIVERS AD7801 POWER-ON RESET   N V = 2×V The AD7801 has a power-on reset circuit designed to allow O REF   UT 256   output stability during power up. This circuit holds the DAC in where: a reset state until a write takes place to the DAC. In the reset state all zeros are latched into the input register of the DAC and N is the decimal equivalent of the binary input the DAC register is in transparent mode thus the output of the code. N ranges from 0 to 255. DAC is held at ground potential until a write takes place to the V is the voltage applied to the external REFIN pin REF DAC. The power-on reset circuitry generates a PON STRB when the external reference is selected and is V /2 DD signal which is a gating signal used within the logic to identify if the internal reference is used. a power-on condition. Table I. Output Voltage for Selected Input Codes POWER-DOWN FEATURES The AD7801 has a power-down feature implemented by Digital Analog Output exercising the external PD pin. An active low signal puts the MSB . . . LSB complete DAC into power-down mode. When in power-down, the current consumption of the device is reduced to less than 255 1111 1111 2 × ×V V 1 μA max at +25°C or 2 μA max over temperature, making the REF 256 device suitable for use in portable battery powered equipment. 254 The internal reference resistors, the reference bias servo loop, 1111 1110 2 × ×V V REF 256 the output amplifier and associated linear circuitry are all shut down when the power-down is activated. The output terminal 129 1000 0001 2 × ×V V REF sees a load of ≈ 23 kΩ to GND when in power-down mode as 256 shown in Figure 25. The contents of the data register are 1000 0000 V V REF unaffected when in power-down mode. The device typically 127 comes out of power-down in 13 μs (see Figure 10). 0111 1111 2 × ×V V REF 256 11.7kΩ V REF 0000 0001 2 × V V DD 256 0000 0000 0 V I DAC 2V REF 11.7kΩ V REF V REF Figure 25. Output Stage During Power-Down Analog Outputs The AD7801 contains a voltage output DAC with 8-bit resolution and rail-to-rail operation. The output buffer provides a gain of two at the output. Figures 2, 3 and 4 show the source and sink 0 capabilities of the output amplifier. The slew rate of the output amplifier is typically 7.5 V/μs and has a full-scale settling to eight bits with a 100 pF capacitive load in typically 1.2 μs. DAC INPUT CODE 00 01 7F 80 81 FE FF The input coding to the DAC is straight binary. Table I shows the binary transfer function for the AD7801. Figure 26 shows Figure 26. DAC Transfer Function the DAC transfer function for binary coding. Any DAC output voltage can be expressed as: REV. 0 –9– DAC OUTPUT VOLTAGE AD7801 Figure 27 shows a typical setup for the AD7801 when using its MICROPROCESSOR INTERFACING internal reference. The internal reference is selected by tying the AD7801–ADSP-2101/ADSP-2103 Interface REFIN pin to V . Internally in the reference section there is a Figure 29 shows an interface between the AD7801 and the ADSP- DD reference detect circuit that will select the internal V /2 based 2101/ADSP-2103. The fast interface timing associated with the DD on the voltage connected to the REFIN pin. If REFIN is within AD7801 allows easy interface to the ADSP-2101/ADSP-2103. a threshold voltage of a PMOS device (approximately 1 V) of LDAC is permanently tied low in this circuit so the DAC V the internal reference is selected. When the REFIN voltage DD output is updated on the rising edge of the WR signal. is more than 1 V below V , the externally applied voltage at DD Data is loaded to the AD7801 input register using the following this pin is used as the reference for the DAC. The internal ADSP-21xx instruction. reference on the AD7801 is V /2, the output current to DD voltage converter within the AD7801 provides a gain of two. DM(DAC) = MR0 Thus the output range of the DAC is from 0 V to V , based on DD MR0 = ADSP-21xx MR0 Register. Table I. DAC = Decoded DAC Address. V = 3V TO 5V DD DMA14 ADDRESS BUS 0.1mF 10mF DMA0 AD7801* ADDR DMS EN V AGND DGND CS DD DECODE REF IN ADSP-2101*/ V OUT LDAC ADSP-2103* AD7801 V OUT CLR WR WR PD CS WR LDAC D7-D0 DB7 V DD DB0 DATA BUS CONTROL DMD15 INPUTS DATA BUS DMD0 Figure 27. Typical Configuration Selecting the Internal *ADDITIONAL CIRCUITRY OMITTED FOR CLARITY. Reference Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface Figure 28 shows a typical setup for the AD7801 when using an external reference. The reference range for the AD7801 is from AD7801–TMS320C20 Interface 1 V to V /2 V. Higher values of reference can be incorporated DD Figure 30 shows an interface between the AD7801 and the but will saturate the output at both the top and bottom end of TMS320C20. Data is loaded to the AD7801 using the following the transfer function. There is a gain of two from input to output instruction: on the AD7801. Suitable references for 5 V operation are the OUT DAC, D AD780 and REF192. For 3 V operation a suitable external DAC = Decoded DAC Address. reference would be the AD589 a 1.23 V bandgap reference. D = Data Memory Address. V = 3V TO 5V DD A15 ADDRESS BUS 0.1mF 10mF A0 V IN AD7801* V AGND DGND DD EXT REF V OUT REF IN ADDR IS EN CS DECODE V 0.1mF OUT GND TMS320C20 AD7801 V OUT CLR LDAC STRB PD AD780/REF192 WITH V = 5V DD WR CS LDAC D7-D0 WR OR V DD R/W AD589 WITH V = 3V DD DB7 DB0 DATA BUS CONTROL INPUTS D15 DATA BUS Figure 28. Typical Configuration Using An External D0 Reference *ADDITIONAL CIRCUITRY OMITTED FOR CLARITY. Figure 30. AD7801–TMS320C20 Interface REV. 0 –10– AD7801 In the circuit shown the LDAC is hardwired low thus the DAC V = 3V TO 5V DD R4 output is updated on the rising edge of WR. Some applications 20kW may require synchronous updating of the DAC in the AD7801. 0.1mF 10mF R3 +5V 10kWIn this case the LDAC signal can be driven from an external V timer or can be controlled by the microprocessor. One option IN AD820/ V AGND DGND DD OP295 for synchronous updating is to decode the LDAC from the ad- EXT REF V–5V OUT REF IN V OUT dress bus so a write operation at this address will synchronously 0.1mF GND –5V AD7801 update the DAC output. A simple OR gate with one input CLR R1 10kW PD driven from the decoded address and the second input from the AD780/REF192 CS D7-D0 WR LDAC WR signal will implement this function. WITH V = 5V DD R2 V DD OR 20kW AD589 WITH V = 3V AD7801–8051/8088 Interface DD Figure 31 shows a serial interface between the AD7801 and the DATA CONTROL BUS INPUTS 8051/8088 processors. Figure 32. Bipolar Operation Using the AD7801 A15 Decoding Multiple AD7801s in a System ADDRESS BUS A8 The CS pin on the AD7801 can be used in applications to decode a number of DACs. In this application, all DACs in the AD7801* system receive the same input data, but only the CS to one of ADDR PSEN OR DEN EN CS DECODE the DACs will be active at any one time allowing access to one channel in the system. The 74HC139 is used as a two-to-four WR WR line decoder to address any of the DACs in the system. To LDAC 8051/8088* prevent timing errors from occurring, the Enable input on the OCTAL ALE DB7 74HC139 should be brought to its inactive state while the LATCH Coded Address inputs are changing state. Figure 33 shows a DB0 diagram of a typical setup for decoding multiple AD7801 AD7 devices in a system. The built-in power-on reset circuit on the DATA BUS AD7801 ensures that the outputs of all DACs in the system AD0 power up with zero volts on their outputs. *ADDITIONAL CIRCUITRY OMITTED FOR CLARITY. Figure 31. AD7801–8051/8088 Interface DATA BUS AD7801 APPLICATIONS CS V OUT WR Bipolar Operation Using the AD7801 WR The AD7801 has been designed for unipolar operation but D0 D7 LDAC V DD bipolar operation is possible using the circuit in Figure 32. The circuit shown is configured for an output voltage range of –5 V V CC to +5 V. Rail-to-rail operation at the amplifier output is achievable 1G AD7801 1Y0 ENABLE by using an AD820 or OP295 as the output amplifier. 1A CS V 1Y1 OUT 1B WR The output voltage for any input code can be calculated as 1Y2 CODED ADDRESS D0 follows: 74HC139 D7 LDAC 1Y3   DGND       R4 2V D R4 REF V = R 1+ / R1+ R2× −V   O 2 () REF       R3 256 R3         AD7801   CS V OUT Where D is the decimal equivalent of the code loaded to the WR DAC and V is the reference voltage input. REF D0 D7 LDAC With V = 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20 kΩ and REF V = 5 V. DD AD7801   10D V = ±5 O   256 CS V   OUT WR D0 D7 LDAC Figure 33. Decoding Multiple AD7801s REV. 0 –11– AD7801 V = 5V DD AD7801 as a Digitally Programmable Indicator A digitally programmable upper limit detector using the DAC is V SOURCE 0.1µF 10µF shown in Figure 34. The upper limit for the test is loaded to the DAC, which in turn sets the limit for the CMP04. If a signal at LOAD V IN the V input is not below the programmed value, an LED will IN V +5V DD EXT REF V indicate the Fail condition. OUT REF IN V OUT 0.1µF GND 2N3904/ AD820/ AD7801 OP295 BC107 +5V AD780/ REF192 AGND DGND 0.1 F 10 F V WITH V = 5V IN DD 1kΩ 1kΩ FAIL PASS 4.7kΩ V REFIN DD 470Ω AD7801 V OUT D7 PASS/ Figure 35. Programmable Current Source D0 Coarse and Fine Adjustment using two AD7801s The two DACs can be paired together to form a coarse and fine adjustment function for a setpoint as shown in Figure 36. In this 1/4 1/6 CMP-04 74HC05 DV circuit, the first DAC is used to provide the coarse adjustment DD and the second DAC is used to provide the fine adjustment. Varying the ratio of R1 and R2 will vary the relative effect of the DGND AGND coarse and fine tune elements in the circuit. For the resistor values shown, the second DAC has a resolution of 148 μV giving a fine tune range of 38 mV (approximately 2 LSB) for operation with a V of 5 V and a reference of 2.5 V. The DD Figure 34. Digitally Programmable Indicator amplifier shown allows a rail-to-rail output voltage to be achieved on the output. A typical application for the circuit Programmable Current Source would be in a setpoint controller. Figure 35 shows the AD7801 used as the control element of a programmable current source. In this circuit the full-scale V = 5V DD current is set to 1 mA. The output voltage from the DAC is R3 R4 51.2kΩ 390Ω applied across the current setting resistor of 4.7 kΩ in series with 0.1µF 10µF the full-scale setting resistor of 470 Ω. Suitable transistors to +5V place in the feedback loop of the amplifier include the BC107 V V IN O R1 and the 2N3904, which enable the current source to operate V AD820/ DD EXT REF V 390Ω OP295 OUT REF IN from a minimum V of 6 V. The operating range is SOURCE V OUT 0.1µF GND AD7801 determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both of AGND DGND AD780/ REF192 which have rail-to-rail operation on their outputs. The current WITH V = 5V DD for any digital input code can be calculated as follows: OR AD589 WITH V = 3V DD 2V D () REF V DD I = REF IN 256 (5 kΩ) V OUT () 0.1µF AD7801 R2 51.2kΩ AGND DGND Figure 36. Coarse and Fine Adjustment REV. 0 –12– AD7801 Power Supply Bypassing and Grounding The power supply lines of the AD7801 should use as large a In any circuit where accuracy is important, careful consideration trace as possible to provide low impedance paths and reduce the of the power supply and ground return layout helps to ensure effects of glitches on the supply line. Fast switching signals like the rated performance. The printed circuit board on which the clocks should be shielded with digital ground to avoid radiating AD7801 is mounted should be designed so that the analog and noise to other parts of the board and should never be run near digital sections are separated and confined to certain areas of the reference inputs. Avoid crossover of digital and analog signals. board. If the AD7801 is in a system where multiple devices Traces on opposite sides of the board should run at right angles require an AGND to DGND connection, the connection should to each other. This reduces the effect of feedthrough through be made at one point only, a star ground point which should be the board. A microstrip technique is by far the best, but not established as closely as possible to the AD7801. The AD7801 always possible with a double-sided board. In this technique, the should have ample supply bypassing of 10 μF in parallel with component side of the board is dedicated to the ground plane 0.1 μF located as close to the package as possible, ideally right while signal traces are placed on the solder side. up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. REV. 0 –13– AD7801 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Wide Body SOIC (R-20) 0.5118 (13.00) 0.4961 (12.60) 20 11 1 10 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 20-Lead TSSOP (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 1 10 0.006 (0.15) PIN 1 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0256 (0.65) 0.0118 (0.30) 0° 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) REV. 0 –14– 0.177 (4.50) 0.169 (4.30) 0.2992 (7.60) 0.256 (6.50) 0.2914 (7.40) 0.246 (6.25) 0.4193 (10.65) 0.3937 (10.00) –15– –16– PRINTED IN U.S.A. C2995–12–4/97