ANALOG DEVICES AD7795

6-Channel, Low Noise, Low Power, 24-/16-Bit ∑-Δ ADC with On-Chip In-Amp and Reference AD7794/AD7795 FEATURES Industrial process control Instrumentation Up to 23 effective bits Blood analysis RMS noise: 40 nV @ 4.17 Hz, 85 nV @ 16.7 Hz Smart transmitters Current: 400 μA typical Liquid/gas chromatography Power-down: 1 μA maximum 6-digit DVM Low noise, programmable gain, instrumentation amp Band gap reference with 4 ppm/°C drift typical GENERAL DESCRIPTION Update rate: 4.17 Hz to 470 Hz The AD7794/AD7795 are low power, low noise, complete Six differential analog inputs analog front ends for high precision measurement applications. Internal clock oscillator They contain a low noise, 24-/16-bit ∑-Δ ADC with six Simultaneous 50 Hz/60 Hz rejection differential inputs. The on-chip low noise instrumentation Reference detect amplifier means that signals of small amplitude can be Programmable current sources interfaced directly to the ADC. On-chip bias voltage generator Each device contains a precision, low noise, low drift internal Burnout currents band gap reference, and can also accept up to two external Low-side power switch differential references. Other on-chip features include Power supply: 2.7 V to 5.25 V Temperature range: programmable excitation current sources, burnout currents, B grade: –40°C to +105°C and a bias voltage generator that is used to set the common- C grade: –40°C to +125°C mode voltage of a channel to AVDD/2. The low-side power Independent interface power supply switch can be used to power down bridge sensors between 24-lead TSSOP conversions, minimizing the system’s power consumption. The 3-wire serial interface AD7794/AD7795 can operate with either an internal clock or SPI®, QSPI™, MICROWIRE™, and DSP compatible an external clock. The output data rate from each part can vary Schmitt trigger on SCLK from 4.17 Hz to 470 Hz. Both parts operate with a power supply from 2.7 V to 5.25 V. APPLICATIONS The B-grade parts (AD7794 and AD7795) are specified for a Temperature measurement temperature range of −40°C to +105°C while the C-grade part Pressure measurement (AD7794) is specified for a temperature range of −40°C to Weigh scales +125°C. They consume a current of 400 μA typical and are Strain gage transducers housed in a 24-lead TSSOP. Gas analysis FUNCTIONAL BLOCK DIAGRAM GND AV AIN4(+)/REFIN2(+) REFIN1(+) AIN4(–)/REFIN2(–) REFIN1(–) DD REFERENCE V BIAS BAND GAP DETECT REFERENCE V DD GND AIN1(+) DOUT/RDY AIN1(–) SERIAL INTERFACE DIN Σ-Δ AIN2(+) BUF IN-AMP AND ADC SCLK AIN2(–) LOGIC CONTROL AIN3(+) CS MUX AIN3(–) AIN5(+)/IOUT2 GND AIN5(–)/IOUT1 AIN6(+)/P1 TEMP INTERNAL DV SENSOR CLOCK DD AIN6(–)/P2 V AD7794/AD7795 DD PSW AD7794: 24-BIT ADC AD7795: 16-BIT ADC GND CLK Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04854-001 AD7794/AD7795 TABLE OF CONTENTS Features .............................................................................................. 1 Full-Scale Register...................................................................... 25 Applications....................................................................................... 1 ADC Circuit Information.............................................................. 26 General Description ......................................................................... 1 Overview ..................................................................................... 26 Functional Block Diagram .............................................................. 1 Digital Interface.......................................................................... 28 Revision History ............................................................................... 2 Circuit Description......................................................................... 31 Specifications..................................................................................... 3 Analog Input Channel ............................................................... 31 Timing Characteristics..................................................................... 8 Instrumentation Amplifier........................................................ 31 Timing Diagrams.............................................................................. 9 Bipolar/Unipolar Configuration .............................................. 31 Absolute Maximum Ratings.......................................................... 10 Data Output Coding .................................................................. 32 ESD Caution................................................................................ 10 Burnout Currents ....................................................................... 32 Pin Configuration and Function Descriptions........................... 11 Excitation Currents .................................................................... 32 RMS Noise and Resolution Specifications .................................. 13 Bias Voltage Generator .............................................................. 32 Chop Enabled.............................................................................. 13 Reference ..................................................................................... 32 Chop Disabled ............................................................................ 15 Reference Detect......................................................................... 33 Typical Performance Characteristics ........................................... 16 Reset ............................................................................................. 33 On-Chip Registers.......................................................................... 17 AV Monitor ............................................................................. 33 DD Communications Register......................................................... 17 Calibration................................................................................... 33 Status Register............................................................................. 18 Grounding and Layout .............................................................. 34 Mode Register ............................................................................. 19 Applications Information .............................................................. 35 Configuration Register .............................................................. 22 Flowmeter.................................................................................... 35 Data Register ............................................................................... 24 Outline Dimensions ....................................................................... 36 ID Register................................................................................... 24 Ordering Guide .......................................................................... 36 IO Register................................................................................... 24 Offset Register............................................................................. 25 REVISION HISTORY 3/07—Rev. C to Rev. D 4/05—Rev. 0 to Rev. A Changes to Specifications Endnote 1............................................. 7 Changes to Absolute Maximum Ratings........................................9 Changes to Status Register Section .............................................. 18 Changes to Figure 21...................................................................... 25 Changes to Ordering Guide .......................................................... 36 Changes to Data Output Coding Section.................................... 28 Changes to Calibration Section .................................................... 30 10/06—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 33 Updated Format..................................................................Universal Added AD7794 C-Grade Part...........................................Universal 10/04—Revision 0: Initial Version Changes to Specifications................................................................ 3 Changes to Ordering Guide .......................................................... 36 6/06—Rev. A to Rev. B Added AD7795 ...................................................................Universal Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to RMS Noise and Resolution Specifications Section..................................................................... 12 Changes to Table 19........................................................................ 20 Changes to ADC Circuit Information Section ........................... 25 Changes to Ordering Guide .......................................................... 35 Rev. D | Page 2 of 36 AD7794/AD7795 SPECIFICATIONS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter AD7794/AD7795 Unit Test Conditions/Comments CHOP ENABLED Output Update Rate 4.17 to 470 Hz nom Settling time = 2/output update rate 2 No Missing Codes AD7794 24 Bits min f ≤ 242 Hz ADC AD7795 16 Bits min Resolution See the RMS Noise and Resolution Specifications section RMS Noise and Update Rates See the RMS Noise and Resolution Specifications section Integral Nonlinearity ±15 ppm of FSR max 3 Offset Error ±1 μV typ 4 Offset Error Drift vs. Temperature ±10 nV/°C typ 3, 5 Full-Scale Error ±10 μV typ 4 Gain Drift vs. Temperature ±1 ppm/°C typ Gain = 1 to 16, external reference ±3 ppm/°C typ Gain = 32 to 128, external reference Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference ANALOG INPUTS Differential Input Voltage Ranges ±VREF/gain V nom V = REFIN(+) − REFIN(−), or internal reference, REF gain = 1 to 128 2 Absolute AIN Voltage Limits Unbuffered Mode GND − 30 mV V min Gain = 1 or 2 AVDD + 30 mV V max Buffered Mode GND + 100 mV V min Gain = 1 or 2 AV − 100 mV V max DD In-Amp Active GND + 300 mV V min Gain = 4 to 128 AVDD − 1.1 V max Common-Mode Voltage, VCM 0.5 V min VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 Analog Input Current Buffered Mode or In-Amp Active 2 Average Input Current AD7794B/AD7795B ±1 nA max Gain = 1 or 2, update rate < 100 Hz ±250 pA max Gain = 4 to 128, update rate < 100 Hz ±1 nA max AIN6(+)/AIN6(−) AD7794C ±3 nA max Gain = 1 or 2, update rate < 100 Hz ±2 nA max Gain = 4 to 128, update rate < 100 Hz ±3 nA max AIN6(+)/AIN6(−) Average Input Current Drift ±2 pA/°C typ Unbuffered Mode Gain = 1 or 2 Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typ 2, 6 Normal Mode Rejection Internal Clock @ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 @ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 External Clock @ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 @ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 @ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 Rev. D | Page 3 of 36 AD7794/AD7795 1 Parameter AD7794/AD7795 Unit Test Conditions/Comments Common-Mode Rejection AD7794B/AD7795B @ DC 100 dB min AIN = 1 V/gain, gain ≥ 4 2 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 2 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 AD7794C @ DC 97 dB min AIN = 1 V/gain, gain ≥ 4 2 @ 50 Hz, 60 Hz 97 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 2 @ 50 Hz, 60 Hz 97 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 CHOP DISABLED Output Update Rate 4.17 to 470 Hz nom Settling time = 1/output update rate 2 No Missing Codes AD7794 24 Bits min fADC ≤ 123 Hz AD7795 16 Bits min Resolution See the RMS Noise and Resolution Specifications section RMS Noise and Update Rates See the RMS Noise and Resolution Specifications section Integral Nonlinearity ±15 ppm of FSR max 3 Offset Error ±100/gain μV typ Without calibration 4 Offset Error Drift vs. Temperature ±100/gain nV/°C typ Gain = 1 to 16 10 nV/°C typ Gain = 32 to 128 3, 5 Full-Scale Error ±10 μV typ 4 Gain Drift vs. Temperature ±1 ppm/°C typ Gain = 1 to 16, external reference ±3 ppm/°C typ Gain = 32 to 128, external reference Power Supply Rejection 100 dB typ AIN = 1 V/gain, gain ≥ 4, external reference ANALOG INPUTS Differential Input Voltage Ranges ±VREF/gain V nom VREF = REFIN(+) − REFIN(−), or internal reference, gain = 1 to 128 2 Absolute AIN Voltage Limits Unbuffered Mode GND − 30 mV V min Gain = 1 or 2 AVDD + 30 mV V max Buffered Mode GND + 100 mV V min Gain = 1 or 2 AVDD − 100 mV V max In-Amp Active GND + 300 mV V min Gain = 4 to 128 AV − 1.1 V max DD Common-Mode Voltage, V CM 0.2 + (gain/2 × (AIN(+) − V min AMP − CM = 1, VCM = (AIN(+) + AIN(–))/2, gain = 4 to 128 AIN(−))) AVDD − 0.2 − (gain/2 × V max (AIN(+) − AIN(−))) Analog Input Current Buffered Mode or In-Amp Active 2 Average Input Current AD7794B/AD7795B ±1 nA max Gain = 1 or 2 ±250 pA max Gain = 4 to 128 ±1 nA max AIN6(+)/AIN6(−) AD7794C ±3 nA max Gain = 1 or 2 ±2 nA max Gain = 4 to 128 ±3 nA max AIN6(+)/AIN6(−) Average Input Current Drift ±2 pA/°C typ Unbuffered Mode Gain = 1 or 2 Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typ Rev. D | Page 4 of 36 AD7794/AD7795 1 Parameter AD7794/AD7795 Unit Test Conditions/Comments 2, 6 Normal Mode Rejection Internal Clock @ 50 Hz, 60 Hz 60 dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 @ 50 Hz 78 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 @ 60 Hz 86 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 External Clock @ 50 Hz, 60 Hz 60 dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 @ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 @ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 Common-Mode Rejection AD7794B/AD7795B @ DC 100 dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1 2 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 2 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 AD7794C @ DC 97 dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1 2 @ 50 Hz, 60 Hz 97 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 2 @ 50 Hz, 60 Hz 97 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 CHOP ENABLED or DISABLED REFERENCE INPUT Internal Reference Internal Reference Initial 1.17 ± 0.01% V min/max AVDD = 4 V, TA = 25°C Accuracy 2 Internal Reference Drift 4 ppm/°C typ 15 ppm/°C max Power Supply Rejection 85 dB typ External Reference External REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−) 2 Reference Voltage Range 0.1 V min AVDD V max When VREF = AVDD, the differential input must be limited to 0.9 × V /gain if the in-amp is active REF 2 Absolute REFIN Voltage Limits GND − 30 mV V min AV + 30 mV V max DD Average Reference Input 400 nA/V typ Current Average Reference Input ±0.03 nA/V/°C typ Current Drift 2 Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB typ Reference Detect Levels 0.3 V min 0.65 V max NOXREF bit active if VREF < 0.3 V EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current 10/210/1000 μA nom Initial Tolerance at 25°C ±5 % typ Drift 200 ppm/°C typ Current Matching ±0.5 % typ Matching between IEXC1 and IEXC2, V = 0 V OUT Drift Matching 50 ppm/°C typ Line Regulation (AVDD) 2 %/V typ AVDD = 5 V ± 5% Load Regulation 0.2 %/V typ Output Compliance AVDD − 0.65 V max Current sources programmed to 10 μA or 210 μA AVDD − 1.1 V max Current sources programmed to 1 mA GND − 30 mV V min Rev. D | Page 5 of 36 AD7794/AD7795 1 Parameter AD7794/AD7795 Unit Test Conditions/Comments BIAS VOLTAGE GENERATOR VBIAS AVDD/2 V nom VBIAS Generator Start-Up Time ms/nF typ Dependent on the capacitance connected to AIN; See Figure 11 TEMPERATURE SENSOR Accuracy ±2 °C typ Applies if user calibrates the temperature sensor Sensitivity 0.81 mV/°C typ LOW-SIDE POWER SWITCH RON 7 Ω max AVDD = 5 V 9 Ω max AV = 3 V DD 2 Allowable Current 30 mA max Continuous current DIGITAL OUTPUTS (P1 and P2) 2 V , Output High Voltage AV − 0.6 V min AV = 3 V, I = 100 μA OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max AV = 3 V, I = 100 μA OL DD SINK 2 VOH, Output High Voltage 4 V min AVDD = 5 V, ISOURCE = 200 μA 2 VOL, Output Low Voltage 0.4 V max AVDD = 5 V, ISINK = 800 μA INTERNAL/EXTERNAL CLOCK Internal Clock 2 Frequency 64 ± 3% kHz min/max Duty Cycle 50:50 % typ External Clock Frequency 64 kHz nom A 128 kHz external clock can be used if the divide-by-2 function is used (Bit CLK1 = CLK0 = 1) Duty Cycle 45:55 to 55:45 % typ Applies for external 64 kHz clock, a 128 kHz clock can have a less stringent duty cycle LOGIC INPUTS 2 CS V , Input Low Voltage 0.8 V max DV = 5 V INL DD 0.4 V max DV = 3 V DD V , Input High Voltage 2.0 V min DV = 3 V or 5 V INH DD SCLK (Schmitt-Triggered Input), 2 CLK, and DIN AD7794B/AD7795B V (+) 1.4/2 V min/max DV = 5 V T DD V (−) 0.8/1.7 V min/max DV = 5 V T DD VT(+) to VT(−) 0.1/0.17 V min/max DVDD = 5 V VT(+) 0.9/2 V min/max DVDD = 3 V VT(−) 0.4/1.35 V min/max DVDD = 3 V V (+) to V (−) 0.06/0.13 V min/max DV = 3 V T T DD AD7794C V (+) 1.35/2.05 V min/max DV = 5 V T DD VT(−) 0.8/1.9 V min/max DVDD = 5 V VT(+) to VT(−) 0.1/0.19 V min/max DVDD = 5 V VT(+) 0.9/2 V min/max DVDD = 3 V V(−) 0.4/1.35 V min/max DV = 3 V T DD V (+) to V(−) 0.06/0.15 V min/max DV = 3 V T T DD Input Currents ±10 μA max VIN = DVDD or GND Input Capacitance 10 pF typ All digital inputs Rev. D | Page 6 of 36 AD7794/AD7795 1 Parameter AD7794/AD7795 Unit Test Conditions/Comments LOGIC OUTPUT (INCLUDING CLK) 2 VOH, Output High Voltage DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA 2 VOL, Output Low Voltage 0.4 V max DVDD = 3 V, ISINK = 100 μA 2 V , Output High Voltage 4 V min DV = 5 V, I = 200 μA OH DD SOURCE 2 V , Output Low Voltage 0.4 V max DV = 5 V, I = 1.6 mA (DOUT/RDY), 800 μA (CLK) OL DD SINK Floating-State Leakage Current ±10 μA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset binary 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max 7 POWER REQUIREMENTS Power Supply Voltage AV to GND 2.7/5.25 V min/max DD DV to GND 2.7/5.25 V min/max DD Power Supply Currents IDD Current 140 μA max 110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V, unbuffered mode, external reference 185 μA max 130 μA typ @ AV = 3 V, 165 μA typ @ AV = 5 V, DD DD buffered mode, gain = 1 or 2, external reference 400 μA max 300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V, gain = 4 to 128, external reference 500 μA max 400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V, gain = 4 to 128, internal reference I (Power-Down Mode) 1 μA max AD7794B, AD7795B DD 2 μA max AD7794C 1 Temperature range: B Grade: −40°C to +105°C, C Grade: −40°C to +125°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common- mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AVDD – 1.6 V typically. In addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AVDD − 1.6 V. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale, and applies at the factory calibration conditions (AV = 4 V, gain = 1, T = 25°C). DD A 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DV or GND with excitation currents and bias voltage generator disabled. DD Rev. D | Page 7 of 36 AD7794/AD7795 TIMING CHARACTERISTICS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. 1, 2 Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments t 100 ns min SCLK high pulse width 3 t 100 ns min SCLK low pulse width 4 Read Operation t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DV = 2.7 V to 3.6 V DD 3 4 t 0 ns min SCLK active edge to data valid delay 2 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V 5, 6 t5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 Write Operation 4 t8 0 ns min CS falling edge to SCLK active edge setup time t9 30 ns min Data valid to SCLK edge setup time t 25 ns min Data valid to SCLK edge hold time 10 t 0 ns min CS rising edge to SCLK edge hold time 11 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. R F DD 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, therefore, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. I (1.6mA WITH DV =5V, SINK DD 100µA WITH DV =3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH DV =5V, SOURCE DD 100µA WITH DV =3V) DD Figure 2. Load Circuit for Timing Characterization Rev. D | Page 8 of 36 04854-002 AD7794/AD7795 TIMING DIAGRAMS CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 I= INPUT, O= OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 11 8 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. D | Page 9 of 36 04854-004 04854-003 AD7794/AD7795 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those listed in the operational sections AV to GND −0.3 V to +7 V DD of this specification is not implied. Exposure to absolute DV to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V device reliability. Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V Digital Output Voltage to GND −0.3 V to DV + 0.3 V DD ESD CAUTION AIN/Digital Input Current 10 mA Operating Temperature Range B Grade −40°C to +105°C C Grade −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 97.9°C/W θJC Thermal Impedance 14°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. D | Page 10 of 36 AD7794/AD7795 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 24 DIN CLK 2 23 DOUT/RDY CS 3 22 DV DD NC 4 21 AV DD AD7794/ AIN6(+)/P1 5 20 GND AD7795 AIN6(–)/P2 6 19 PSW TOP VIEW AIN1(+) 7 18 AIN4(–)/REFIN2(–) (Not to Scale) AIN1(–) 8 17 AIN4(+)/REFIN2(+) AIN2(+) 9 16 AIN5(–)/IOUT1 AIN2(–) 10 15 AIN5(+)/IOUT2 AIN3(+) 11 14 REFIN1(–) AIN3(–) 12 13 REFIN1(+) NC = NO CONNECT Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CLK Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 4 NC No Connect. 5 AIN6(+)/P1 Analog Input/Digital Output Pin. AIN6(+) is the positive terminal of the differential analog input pair, AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AVDD and GND. 6 AIN6(−)/P2 Analog Input/Digital Output Pin. AIN6(−) is the negative terminal of the differential analog input pair, AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AV and GND. DD 7 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair, AIN1(+)/AIN1(−). 8 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair, AIN1(+)/AIN1(−). 9 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair, AIN2(+)/AIN2(−). 10 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair, AIN2(+)/AIN2(−). 11 AIN3(+) Analog Input. AIN3(+) is the positive terminal of the differential analog input pair, AIN3(+)/AIN3(−). 12 AIN3(−) Analog Input. AIN3(−) is the negative terminal of the differential analog input pair, AIN3(+)/AIN3(−). 13 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. 14 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AV − 0.1 V. DD 15 AIN5(+)/IOUT2 Analog Input/Output of Internal Excitation Current Source. AIN5(+) is the positive terminal of the differential analog input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 16 AIN5(−)/IOUT1 Analog Input/Output of Internal Excitation Current Source. AIN5(−) is the negative terminal of the differential analog input pair, AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 17 AIN4(+)/REFIN2(+) Analog Input/Positive Reference Input. AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as a positive reference input for REFIN2. REFIN2(+) can lie anywhere between AV and GND + 0.1 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the part DD functions with a reference from 0.1 V to AV . DD Rev. D | Page 11 of 36 04854-005 AD7794/AD7795 Pin No. Mnemonic Description 18 AIN4(−)/REFIN2(−) Analog Input/Negative Reference Input. AIN4(−) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere between GND and AVDD − 0.1 V. 19 PSW Low-Side Power Switch to GND. 20 GND Ground Reference Point. 21 AV Supply Voltage, 2.7 V to 5.25 V. DD 22 DVDD Serial Interface Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, the serial interface operates at 3 V with AVDD at 5 V or vice versa. 23 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC with the register selection bits of the communications register identifying the appropriate register. Rev. D | Page 12 of 36 AD7794/AD7795 RMS NOISE AND RESOLUTION SPECIFICATIONS CHOP ENABLED The AD7794/AD7795 can be operated with chop enabled or External Reference chop disabled, allowing the ADC to be optimized for switching time or drift performance. With chop enabled, the settling time Table 5 shows the AD7794/AD7795 rms noise for some update is two times the conversion time. However, the offset is rates and gain settings. The numbers given are for the bipolar continuously removed by the ADC leading to low offset and low input range with an external 2.5 V reference. These numbers are offset drift. With chop disabled, the allowable update rates are typical and are generated with a differential input voltage of 0 V. the same as in chop enable mode. However, the settling time Table 6 and Table 7 show the effective resolution, while the now equals the conversion time. With chop disabled, the offset output peak-to-peak (p-p) resolution is listed in brackets. It is is not removed by the ADC, so periodic offset calibrations can important to note that the effective resolution is calculated be required to remove offset due to drift. using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest LSB. Table 5. RMS Noise (μV) vs. Gain and Output Update Rate Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 0.64 0.6 0.29 0.22 0.1 0.065 0.039 0.041 8.33 1.04 0.96 0.38 0.26 0.13 0.078 0.057 0.055 16.7 1.55 1.45 0.54 0.36 0.18 0.11 0.087 0.086 33.2 2.3 2.13 0.74 0.5 0.23 0.17 0.124 0.118 62 2.95 2.85 0.92 0.58 0.29 0.2 0.153 0.144 123 4.89 4.74 1.49 1 0.48 0.32 0.265 0.283 242 11.76 9.5 4.02 1.96 0.88 0.45 0.379 0.397 470 11.33 9.44 3.07 1.79 0.99 0.63 0.568 0.593 Table 6. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 23 (20.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 8.33 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 16.7 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19 (16.5) 33.2 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20.5 (18) 20 (17.5) 19 (16.5) 18.5 (16) 62 20.5 (18) 19.5 (17) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 123 20 (17.5) 19 (16.5) 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 18 (15.5) 17 (14.5) 242 18.5 (16) 18 (15.5) 18 (15.5) 18 (15.5) 18.5 (16) 18.5 (16) 17.5 (15) 16.5 (14) 470 18.5 (16) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17 (14.5) 16 (13.5) Table 7. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 123 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 242 16 (16) 16 (15.5) 16 (15.5) 16 (15.5) 16 (16) 16 (16) 16 (15) 16 (14) 470 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (14.5) 16 (13.5) Rev. D | Page 13 of 36 AD7794/AD7795 Internal Reference It is important to note that the effective resolution is calculated Table 8 shows the AD7794/AD7795 rms noise for some of the using the rms noise while the p-p resolution is calculated based update rates and gain settings. The numbers given are for the on peak-to-peak noise. The p-p resolution represents the bipolar input range with the internal 1.17 V reference. These resolution for which there is no code flicker. These numbers are numbers are typical and are generated with a differential input typical and rounded to the nearest LSB. voltage of 0 V. Table 9 and Table 10 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. Table 8. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 0.81 0.67 0.32 0.2 0.13 0.065 0.04 0.039 8.33 1.18 1.11 0.41 0.25 0.16 0.078 0.058 0.059 16.7 1.96 1.72 0.55 0.36 0.25 0.11 0.088 0.088 33.2 2.99 2.48 0.83 0.48 0.33 0.17 0.13 0.12 62 3.6 3.25 1.03 0.65 0.46 0.2 0.15 0.15 123 5.83 5.01 1.69 0.96 0.67 0.32 0.25 0.26 242 11.22 8.64 2.69 1.9 1.04 0.45 0.35 0.34 470 12.46 10.58 4.58 2 1.27 0.63 0.50 0.49 Table 9. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 8.33 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 18 (15.5) 16.7 20 (17.5) 19.5 (17) 20 (17.5) 19.5 (17) 19 (16.5) 19.5 (17) 18.5 (16) 17.5 (15) 33.2 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 62 19.5 (17) 18.5 (16) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 18 (15.5) 17 (14.5) 123 18.5 (16) 18 (15.5) 18.5 (16) 18 (15.5) 17.5 (15) 18 (15.5) 17 (14.5) 16 (13.5) 242 17.5 (15) 17 (14.5) 17.5 (15) 17 (14.5) 17 (14.5) 17.5 (15) 16.5 (14) 15.5 (13) 470 17.5 (15) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 16 (13.5) 15 (12.5) Table 10. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 123 16 (16) 16 (15.5) 16 (16) 16 (15.5) 16 (15) 16 (15.5) 16 (14.5) 16 (13.5) 242 16 (15) 16 (14.5) 16 (15) 16 (14.5) 16 (14.5) 16 (15) 16 (14) 15.5 (13) 470 16 (15) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 16 (13.5) 15 (12.5) Rev. D | Page 14 of 36 AD7794/AD7795 CHOP DISABLED With chop disabled, the switching time or settling time is The numbers given are for the bipolar input range with the reduced by a factor of two. However, periodic offset calibrations internal 1.17 V reference. These numbers are typical and are may now be required to remove offset and offset drift. When generated with a differential input voltage of 0 V. chop is disabled, the AMP-CM bit in the mode register should Table 12 and Table 13 show the effective resolution while the be set to 1. This limits the allowable common-mode voltage that output peak-to-peak (p-p) resolution is listed in brackets. It is can be used. However, the common-mode rejection degrades if important to note that the effective resolution is calculated the bit is not set. using the rms noise, while the p-p resolution is calculated based Table 11 shows the rms noise of the AD7794/AD7795 for some on peak-to-peak noise. The p-p resolution represents the of the update rates and gain settings with chop disabled. resolution for which there is no code flicker. These numbers are typical and rounded to the nearest LSB. Table 11. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 1.22 0.98 0.33 0.18 0.13 0.062 0.053 0.051 8.33 1.74 1.53 0.49 0.29 0.21 0.1 0.079 0.07 16.7 2.64 2.44 0.79 0.48 0.33 0.16 0.13 0.12 33.2 4.55 3.52 1.11 0.66 0.46 0.21 0.17 0.16 62 5.03 4.45 1.47 0.81 0.58 0.27 0.2 0.22 123 8.13 7.24 2.27 1.33 0.96 0.48 0.36 0.37 242 15.12 13.18 3.77 2.09 1.45 0.64 0.5 0.47 470 17.18 14.63 8.86 2.96 1.92 0.89 0.69 0.7 Table 12. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 21 (18.5) 20 (17.5) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 8.33 20.5 (18) 19.5 (17) 20 (17.5) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 16.7 20 (17.5) 19 (16.5) 19.5 (17) 19 (16.5) 19 (16.5) 19 (16.5) 18 (15.5) 17 (14.5) 33.2 19 (16.5) 18.5 (16) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 17.5 (15) 17 (14.5) 62 19 (16.5) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17.5 (15) 16.5 (14) 123 18 (15.5) 17.5 (15) 18 (15.5) 17.5 (15) 17 (14.5) 17 (14.5) 16.5 (14) 15.5 (13) 242 17 (14.5) 16.5 (14) 17 (14.5) 17 (14.5) 16.5 (14) 17 (14.5) 16 (13.5) 15 (12.5) 470 17 (14.5) 16.5 (14) 16 (13.5) 16.5 (14) 16 (13.5) 16.5 (14) 15.5 (13) 14.5 (12) Table 13. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5) 62 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (15) 16 (14) 123 16 (15.5) 16 (15) 16 (15.5) 16 (15) 16 (14.5) 16 (14.5) 16 (14) 15.5 (13) 242 16 (14.5) 16 (14) 16 (14.5) 16 (14.5) 16 (14) 16 (14.5) 16 (13.5) 15 (12.5) 470 16 (14.5) 16 (14) 16 (13.5) 16 (14) 16 (13.5) 16 (14) 15.5 (13) 14.5 (12) Rev. D | Page 15 of 36 AD7794/AD7795 TYPICAL PERFORMANCE CHARACTERISTICS 8388800 14 8388750 12 8388700 10 8388650 8 8388600 6 8388550 4 8388500 2 8388450 0 8388068 8388100 8388150 8388200 8388250 8388300 8388350 8388396 0 200 400 600 800 1000 CODE READING NUMBER Figure 6. Typical Noise Plot for the AD7794 (Internal Reference, Figure 9. Noise Distribution Histogram for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, Chop Enabled) Gain = 64, Update Rate = 16.7 Hz, Chop Disabled, AMP-CM = 1) 16 14 20 12 10 8 10 6 4 2 0 0 8388482 8388520 8388560 8388600 8388640 8388680 8388720 8388750 –2.0 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 CODE MATCHING (%) Figure 7. Noise Distribution Histogram for the AD7794 (Internal Reference, Figure 10. Excitation Current Matching (210 μA) at Ambient Temperature Gain = 64, Update Rate = 16.7 Hz, Chop Enabled) 8388450 90 8388400 80 70 8388350 60 8388300 50 8388250 BOOST = 0 40 8388200 30 8388150 20 8388100 10 BOOST = 1 8388050 0 0 200 400 600 800 1000 0 200 400 600 800 1000 READING NUMBER LOAD CAPACITANCE (nF) Figure 8. Typical Noise Plot for the AD7794 (Internal Reference, Figure 11. Bias Voltage Generator Power-Up Time vs. Load Capacitance Gain = 64, Update Rate = 16.7 Hz, AMP-CM = 1, Chop Disabled) Rev. D | Page 16 of 36 CODE READ CODE READ OCCURRENCE 04854-007 04854-008 04854-006 POWER-UP TIME (ms) (%) OCCURRENCE 04854-011 04854-010 04854-009 AD7794/AD7795 ON-CHIP REGISTERS returns to where it expects a write operation to the The ADC is controlled and configured via a number of on-chip communications register. This is the default state of the registers that are described in the following sections. In the interface and, on power-up or after a reset, the ADC is in this following descriptions, set implies a Logic 1 state and cleared default state waiting for a write operation to the communications implies a Logic 0 state, unless otherwise noted. register. In situations where the interface sequence is lost, a COMMUNICATIONS REGISTER write operation of at least 32 serial clock cycles with DIN high RS2, RS1, RS0 = 0, 0, 0 returns the ADC to this default state by resetting the entire part. Table 14 outlines the bit designations for the communications The communications register is an 8-bit write-only register. All register. CR0 through CR7 indicate the bit location, with CR communications to the part must start with a write operation to denoting the bits are in the communications register. CR7 the communications register. The data written to the communi- denotes the first bit of the data stream. The number in brackets cations register determines whether the next operation is a read indicates the power-on/reset default status of that bit. or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 14. Communications Register Bit Designations Bit No. Mnemonic Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR5 to RS2 to RS0 Register Address Bits. These address bits are used to select which registers of the ADC are being selected during CR3 this serial interface communication. See Table 15. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be read continuously, that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is written to the device. CR1 to 0 These bits must be programmed to Logic 0 for correct operation. CR0 Table 15. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications Register During a Write Operation 8-bit 0 0 0 Status Register During a Read Operation 8-bit 0 0 1 Mode Register 16-bit 0 1 0 Configuration Register 16-bit 0 1 1 Data Register 24-bit (AD7794)/16-Bit (AD7795) 1 0 0 ID Register 8-bit 1 0 1 IO Register 8-bit 1 1 0 Offset Register 24-bit (AD7794)/16-Bit (AD7795) 1 1 1 Full-Scale Register 24-bit (AD7794)/16-Bit (AD7795) Rev. D | Page 17 of 36 AD7794/AD7795 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7795)/0x88 (AD7794) Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, with SR denoting that The status register is an 8-bit read-only register. To access the the bits are in the status register. SR7 denotes the first bit of the ADC status register, the user must write to the communications data stream. The number in brackets indicates the power- register, select the next operation to be read, and load Bit RS2, on/reset default status of that bit. Bit RS1, and Bit RS0 with 0. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) NOXREF(0) 0(0) 0/1 CH2(0) CH1(0) CH0(0) Table 16. Status Register Bit Designations Bit No. Mnemonic Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. Cleared by a write operation to start a conversion. SR5 NOXREF No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. Cleared to indicate that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid. SR4 0 This bit is automatically cleared. SR3 0/1 This bit is automatically cleared on the AD7795 and is automatically set on the AD7794. SR2 to CH2 to CH0 These bits indicate which channel is being converted by the ADC. SR0 Rev. D | Page 18 of 36 AD7794/AD7795 MODE REGISTER denoting that the bits are in the mode register. MR15 is the first RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A bit of the data stream. The number in parentheses indicates the The mode register is a 16-bit read/write register that is used to power-on/reset default status of that bit. Any write to the setup select the operating mode, the update rate, and the clock source. RDY register resets the modulator and filter, and sets the bit. Table 17 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations with MR MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MD2(0) MD1(0) MD0(0) PSW(0) 0(0) 0(0) AMP-CM(0) 0(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 CLK1(0) CLK0(0) 0(0) CHOP-DIS(0) FS3(1) FS2(0) FS1(1) FS0(0) Table 17. Mode Register Bit Designations Bit No. Mnemonic Description MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operating mode of the AD7794/AD7795 (see Table 18). MR12 PSW Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode, the power switch is opened. MR11 to MR10 0 These bits must be programmed with a Logic 0 for correct operation. MR9 AMP-CM Instrumentation Amplifier Common-Mode Bit. This bit is used in conjunction with the CHOP-DIS bit. With chop disabled, the user can operate with a wider range of common-mode voltages when AMP-CM is cleared. However, the dc common-mode rejection degrades. With AMP-CM set, the span for the common- mode voltage is reduced (see the Specifications section). However, the dc common-mode rejection is significantly better. MR8 0 This bit must be programmed with a Logic 0 for correct operation. MR7 to MR6 CLK1 to CLK0 These bits are used to select the clock source for the AD7794/AD7795. Either the on-chip 64 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7794/AD7795 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7794/AD7795. CLK1 CLK0 ADC Clock Source 0 0 Internal 64 kHz clock. Internal clock is not available at the CLK pin. 0 1 Internal 64 kHz clock. This clock is made available at the CLK pin. 1 0 External 64 kHz. The external clock can have a 45:55 duty cycle (see the Specifications section for the external clock). 1 1 External clock. The external clock is divided by 2 within the AD7794/AD7795. MR5 0 This bit must be programmed with a Logic 0 for correct operation. MR4 CHOP-DIS This bit is used to enable or disable chop. On power-up or following a reset, CHOP-DIS is cleared so chop is enabled. When CHOP-DIS is set, chop is disabled. This bit is used in conjunction with the AMP-CM bit. When chop is disabled, the AMP-CM bit should be set. This limits the common-mode voltage that can be used by the ADC, but the dc common-mode rejection does not degrade. MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 19). Rev. D | Page 19 of 36 AD7794/AD7795 Table 18. Operating Modes MD2 MD1 MD0 Mode 0 0 0 Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communica- tions register. After power-on, the first conversion is available after a period of 2/fADC when chop is enabled or 1/fADC when chop is disabled. Subsequent conversions are available at a frequency of fADC with chop either enabled or disabled. 0 0 1 Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/fADC when chop is enabled, or 1/fADC when chop is disabled. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. 0 1 0 Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 1 Power-Down Mode. In power-down mode, all the AD7794/AD7795 circuitry is powered down including the current sources, power switch, burnout currents, bias voltage generator, and clock circuitry. 1 0 0 Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration. When the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled and 2 conversion cycles when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. 1 1 0 System Zero-Scale Calibration. User should connect the system zero-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and CH0 bit. A system offset calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coeffi- cient is placed in the offset register of the selected channel. 1 1 1 System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and CH0 bit. A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. Rev. D | Page 20 of 36 AD7794/AD7795 1 Table 19. Update Rates Available (Chop Enabled) FS3 FS2 FS1 FS0 f (Hz) T (ms) Rejection @ 50 Hz/60 Hz (Internal Clock) ADC SETTLE 0 0 0 0 x x 0 0 0 1 470 4 0 0 1 0 242 8 0 0 1 1 123 16 0 1 0 0 62 32 0 1 0 1 50 40 0 1 1 0 39 48 0 1 1 1 33.2 60 1 0 0 0 19.6 101 90 dB (60 Hz only) 1 0 0 1 16.7 120 80 dB (50 Hz only) 1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz) 1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz) 1 1 0 0 10 200 69 dB (50 Hz and 60 Hz) 1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz) 1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz) 1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz) 1 With chop disabled, the update rates remain unchanged, but the settling time for each update rate is reduced by a factor of 2. The rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB. Rev. D | Page 21 of 36 AD7794/AD7795 CONFIGURATION REGISTER Table 20 outlines the bit designations for the filter register. RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 CON0 through CON15 indicate the bit locations. CON denotes The configuration register is a 16-bit read/write register that is that the bits are in the configuration register. CON15 is the first used to configure the ADC for unipolar or bipolar mode, enable bit of the data stream. The number in parentheses indicates the or disable the buffer, enable or disable the burnout currents, power-on/reset default status of that bit. select the gain, and select the analog input channel. CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 VBIAS1(0) VBIAS0(0) BO(0) U/B(0) BOOST(0) G2(1) G1(1) G0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 REFSEL1(0) REFSEL0(0) REF_DET(0) BUF(1) CH3(0) CH2(0) CH1(0) CH0(0) Table 20. Configuration Register Bit Designations Bit No. Mnemonic Description CON15 to VBIAS1 to VBIAS0 Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AVDD/2. CON14 These bits are used in conjunction with the BOOST bit. VBIAS1 VBIAS0 Bias Voltage 0 0 Bias voltage generator disabled 0 1 Bias voltage generator connected to AIN1(−) 1 0 Bias voltage generator connected to AIN2(−) 1 1 Bias voltage generator connected to AIN3(−) CON13 BO Burnout Current Enable Bit. This bit must be programmed with a Logic 0 for correct operation. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active. CON12 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding, that is, zero differential input results in 0x000000 output and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and positive full-scale differential input results in an output code of 0xFFFFFF. CON11 BOOST This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias voltage generator is increased, which reduces its power-up time. CON10 to G2 to G0 Gain Select Bits. CON8 Written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (2.5 V Reference) 0 0 0 1 (in-amp not 2.5 V used) 0 0 1 1.25 V 2 (in-amp not used) 0 1 0 4 625 mV 0 1 1 8 312.5 mV 1 0 0 16 156.2 mV 1 0 1 32 78.125 mV 1 1 0 64 39.06 mV 1 1 1 128 19.53 mV CON7 to REFSEL1/REFSEL0 Reference Select Bits. CON6 The reference source for the ADC is selected using these bits. REFSEL1 REFSEL0 Reference Source 0 0 External reference applied between REFIN1(+) and REFIN1(−) 0 1 External reference applied between REFIN2(+) and REFIN2(−) 1 0 Internal 1.17 V reference 1 1 Reserved Rev. D | Page 22 of 36 AD7794/AD7795 Bit No. Mnemonic Description CON5 REF_DET Enables the reference detect function. When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the reference detect function is disabled. CON4 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is automatically enabled. With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above AV . When the buffer is enabled, it requires some headroom so the voltage DD on any input pin must be limited to 100 mV within the power supply rails. CON3 to CH3 to CH0 Channel Select Bits. CON0 Written by the user to select the active analog input channel to the ADC. CH3 CH2 CH1 CH0 Channel Calibration Pair 0 0 0 0 AIN1(+)/AIN1(−) 0 0 0 0 1 AIN2(+)/AIN2(−) 1 0 0 1 0 AIN3(+)/AIN3(−) 2 0 0 1 1 AIN4(+)/AIN4(−) 3 0 1 0 0 AIN5(+)/AIN5(−) 3 0 1 0 1 AIN6(+)/AIN6(−) 3 0 1 1 0 Temp Sensor Automatically selects the internal 1.17 V reference and sets the gain to 1 0 1 1 1 AV Monitor DD Automatically selects the internal 1.17 V reference and sets the gain to 1/6 1 0 0 0 AIN1(−)/AIN1(−) 0 1 0 0 1 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Rev. D | Page 23 of 36 AD7794/AD7795 DATA REGISTER IO REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 0x0000(AD7795), 0x000000 (AD7794) The IO register is an 8-bit read/write register that is used The conversion result from the ADC is stored in this data to enable the excitation currents and select the value of the register. This is a read-only register. On completion of a read excitation currents. operation from this register, the RDY bit/pin is set. Table 21 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations. IO denotes that the bits ID REGISTER are in the IO register. IO7 denotes the first bit of the data RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXF stream. The number in brackets indicates the power-on/reset The identification number for the AD7794/AD7795 is stored in default status of that bit. the ID register. This is a read-only register. IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0(0) IOEN(0) IO2DAT(0) IO1DAT(0) IEXCDIR1(0) IEXCDIR0(0) IEXCEN1(0) IEXCEN0(0) Table 21. IO Register Bit Designations Bit No. Mnemonic Description IO7 0 This bit must be programmed with a Logic 0 for correct operation. IO6 IOEN Configures Pin AIN6(+)/P1 and Pin AIN6(−)/P2 as analog input pins or digital output pins. When this bit is set, the pins are configured as Digital Output Pin P1 and Digital Output Pin P2. When this bit is cleared, these pins are configured as Analog Input Pin AIN6(+) and Analog Input Pin AIN6(−). IO5 to IO4 IO2DAT/IO1DAT P2/P1 Data. When IOEN is set, the data for Digital Output Pin P1 and Digital Output Pin P2 is written to Bit IO2DAT and Bit IO1DAT. IO3 to IO2 IEXCDIR1 to IEXCDIR0 Direction of Current Sources Select Bits. IEXCDIR1 IEXCDIR0 Current Source Direction 0 0 Current Source IEXC1 connected to Pin IOUT1. Current Source IEXC2 connected to Pin IOUT2. 0 1 Current Source IEXC1 connected to Pin IOUT2. Current Source IEXC2 connected to Pin IOUT1. 1 0 Both current sources connected to Pin IOUT1. Permitted only when the current sources are set to 10 μA or 210 μA. 1 1 Both current sources connected to Pin IOUT2. Permitted only when the current sources are set to 10 μA or 210 μA. IO3 to IO2 IEXCEN1 to IEXCEN0 These bits are used to enable and disable the current sources. They also select the value of the excitation currents. IEXCEN1 IEXCEN0 Current Source Value 0 0 Excitation currents disabled 0 1 10 μA 1 0 210 μA 1 1 1 mA Rev. D | Page 24 of 36 AD7794/AD7795 OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7795), 0x800000 (AD7794)) (AD7795), 0x5XXX00 (AD7794) The offset register is a 16-bit register on the AD7795 and a 24-bit The full-scale register is a 16-bit register on the AD7795 and a register on the AD7794. The offset register holds the offset 24-bit register on the AD7794. The full-scale register holds the calibration coefficient for the ADC and its power-on reset value full-scale calibration coefficient for the ADC. The AD7794/ is 0x8000/0x800000, for the AD7794/AD7795, respectively. The AD7795 each have four full-scale registers. The AIN1, AIN2, AD7794/AD7795 each have four offset registers. Channel AIN1 and AIN3 channels have dedicated full-scale registers, while the to Channel AIN3 have dedicated offset registers while the AIN4, AIN5, and AIN6 channels share a register. The full-scale AIN4, AIN5, and AIN6 channels share an offset register. Each registers are read/write registers. However, when writing to the of these registers is a read/write register. The register is used in full-scale registers, the ADC must be placed in power-down conjunction with its associated full-scale register to form a mode or idle mode. These registers are configured on power-on register pair. The power-on reset value is automatically with factory calibrated full-scale calibration coefficients, the overwritten if an internal or system zero-scale calibration is calibration being performed at gain = 1. Therefore, every device initiated by the user. The AD7794/AD7795 must be placed in has different default coefficients. The coefficients are different, power-down mode or idle mode when writing to the offset depending on whether the internal reference or an external register. reference is selected. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or the full-scale register is written to. Rev. D | Page 25 of 36 AD7794/AD7795 ADC CIRCUIT INFORMATION 50 Hz and 60 Hz rejection is optimized when the update rate OVERVIEW equals 16.7 Hz or less, as notches are placed at both 50 Hz and The AD7794/AD7795 are low power ADCs that incorporate a 60 Hz with these update rates (see Figure 14). ∑-Δ modulator, buffer, reference, in-amp, and on-chip digital The AD7794/AD7795 use slightly different filter types, filtering, which are intended for the measurement of wide depending on the output update rate, so that the rejection of dynamic range, low frequency signals (such as those in pressure quantization noise and device noise is optimized. When the transducers), weigh scales, and temperature measurement update rate is 4.17 Hz to 12.5 Hz, a Sinc3 filter along with an applications. averaging filter is used. When the update rate is 16.7 Hz to Each part has six differential inputs that can be buffered or 39 Hz, a modified Sinc3 filter is used. This filter gives unbuffered. The devices operate with an internal 1.17 V refer- simultaneous 50 Hz/60 Hz rejection when the update rate ence or by using an external reference. Figure 12 shows the equals 16.7 Hz. A Sinc4 filter is used when the update rate is basic connections required to operate the parts. 50 Hz to 242 Hz. Finally, an integrate-only filter is used when The output rate of the AD7794/AD7795 (f ) is user pro- ADC the update rate equals 470 Hz. Figure 13 to Figure 16 show the grammable. The allowable update rates, along with the frequency response of the different filter types for some of the corresponding settling times, are listed in Table 19 for chop update rates when chop is enabled. In this mode, the settling enabled. With chop disabled, the allowable update rates remain time equals twice the update rate. Figure 17 to Figure 20 show unchanged, but the settling time equals 1/fADC. Normal mode the filter response with chop disabled. rejection is the major function of the digital filter. Simultaneous V DD REFIN1(+) GND AV DD IN+ OUT– OUT+ AIN1(+) AD7794/AD7795 AIN1(–) IN+ V IN– DD OUT– OUT+ AIN2(+) DOUT/RDY SERIAL AIN2(–) DIN INTERFACE Σ-Δ MUX BUF IN-AMP AND IN– ADC AIN3(+) SCLK LOGIC CONTROL CS AIN3(–) GND REFIN2(+) V R DD CM REFIN2(–) DV IOUT1 INTERNAL DD CLOCK REFIN1(–) PSW GND CLK Figure 12. Basic Connection Diagram Rev. D | Page 26 of 36 04854-012 AD7794/AD7795 0 0 –10 –20 –20 –40 –30 –60 –40 –80 –50 –100 –60 01 20 40 60 80 10020 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Filter Response with Update Rate = 4.17 Hz (Chop Enabled) Figure 16. Filter Response with Update Rate = 470 Hz (Chop Enabled) 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 20 40 60 80 100 120 140 160 18000 01 20 40 60 80 10020 FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Filter Response with Update Rate = 16.7 Hz (Chop Enabled) Figure 17. Filter Response with Update Rate = 4.17 Hz (Chop Disabled) 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 500 1000 1500 2000 2500 3000 02 20 40 60 80 100 120 140 160 18000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Filter Response with Update Rate = 242 Hz (Chop Enabled) Figure 18. Filter Response with Update Rate = 16.7 Hz (Chop Disabled) Rev. D | Page 27 of 36 (dB) (dB) (dB) 04854-019 04854-018 04854-017 (dB) (dB) (dB) 04854-022 04854-021 04854-020 AD7794/AD7795 RDY 0 to transfer data into the on-chip registers, while DOUT/ is used for accessing data from the on-chip registers. SCLK is the serial clock input for the devices, and all data transfers (either –20 on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also operates as a data ready signal; the –40 line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data –60 register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is –80 CS being updated. is used to select a device. It can be used to decode the AD7794/AD7795 in systems where several –100 components are connected to the serial bus. 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) Figure 3 and Figure 4 show timing diagrams for interfacing to the Figure 19. Filter Response at 242 Hz Update Rate (Chop Disabled) CS AD7794/AD7795 with , which is being used to decode the parts. Figure 3 shows the timing for a read operation from the output 0 shift register of the AD7794/AD7795, while Figure 4 shows the timing for a write operation to the input shift register. It is –10 possible to read the same word from the data register several times, even though the DOUT/RDY line returns high after the –20 first read operation. However, care must be taken to ensure that the read operations have been completed before the next output –30 update occurs. In continuous read mode, the data register can be read only once. –40 CS The serial interface can operate in 3-wire mode by tying low. RDY In this case, the SCLK, DIN, and DOUT/ lines are used to –50 communicate with the AD7794/AD7795. The end of the –60 conversion can be monitored using the RDY bit in the status 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 register. This scheme is suitable for interfacing to micro- FREQUENCY (Hz) CS controllers. If is required as a decoding signal, it can be Figure 20. Filter Response at 470 Hz Update Rate (Chop Disabled) generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. DIGITAL INTERFACE CS The AD7794/AD7795 can be operated with being used as a As previously outlined in the On-Chip Registers section, the frame synchronization signal. This scheme is useful for DSP programmable functions of the AD7794/AD7795 are controlled interfaces. In this case, the first bit (MSB) is effectively clocked using a set of on-chip registers. Data is written to these registers out by CS, because CS normally occurs after the falling edge of via the serial interface. Read access to the on-chip registers is SCLK in DSPs. The SCLK can continue to run between data also provided by this interface. All communications with the transfers, provided the timing numbers are obeyed. parts must start with a write to the communications register. The serial interface can be reset by writing a series of 1s on the After power-on or reset, each device expects a write to its DIN input. If a Logic 1 is written to the AD7794/AD7795 line communications register. The data written to this register for at least 32 serial clock cycles, the serial interface is reset. determines whether the next operation is a read operation or a This ensures that the interface can be reset to a known state if write operation, and determines to which register this read or the interface gets lost due to a software error or some glitch in write operation occurs. Therefore, write access to any of the the system. Reset returns the interface to the state in which it is other registers on the parts begins with a write operation to the expecting a write to the communications register. This communications register, followed by a write to the selected operation resets the contents of all registers to their power-on register. A read operation from any other register (except when values. Following a reset, the user should allow a period of continuous read mode is selected) starts with a write to the 500 μs before addressing the serial interface. communications register, followed by a read operation from the The AD7794/AD7795 can be configured to continuously convert selected register. or perform a single conversion (see Figure 21 through Figure 23). The serial interface of the AD7794/AD7795 consists of four CS RDY signals: , DIN, SCLK, and DOUT/ . The DIN line is used Rev. D | Page 28 of 36 (dB) (dB) 04854-024 04854-023 AD7794/AD7795 CS 0x08 0x200A 0x58 DIN DATA DOUT/RDY SCLK Figure 21. Single Conversion CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK Figure 22. Continuous Conversion CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK Figure 23. Continuous Read Rev. D | Page 29 of 36 04854-016 04854-015 04854-014 AD7794/AD7795 Continuous Read Single Conversion Mode Rather than write to the communications register each time a In single conversion mode, the AD7794/AD7795 are placed in conversion is complete to access the data, the AD7794/AD7795 shutdown mode between conversions. When a single can be configured so that the conversions are placed on the conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 DOUT/RDY line automatically. By writing 01011100 to the to 1 in the mode register, the AD7794/AD7795 power up, communications register, the user need only apply the perform a single conversion, and then return to shutdown appropriate number of SCLK cycles to the ADC. The 24-bit mode. The on-chip oscillator requires 1 ms to power up. A RDY word is automatically placed on the DOUT/ line when a RDY conversion requires a time period of 2 × tADC. DOUT/ goes conversion is complete. The ADC should be configured for low to indicate the completion of a conversion. When the data- continuous conversion mode. word has been read from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY remains high until another When DOUT/RDY goes low to indicate the end of a conversion, conversion is initiated and completed. The data register can be sufficient SCLK cycles must be applied to the ADC, and the read several times, if required, even when DOUT/RDY has RDY data conversion is placed on the DOUT/ line. When the gone high. RDY conversion is read, DOUT/ returns high until the next conversion is available. Continuous Conversion Mode In this mode, the data can be read only once. Also, the user must This is the default power-up mode. The AD7794/AD7795 ensure that the data-word is read before the next conversion is continuously convert with the RDY pin in the status register complete. If the user has not read the conversion before the going low each time a conversion is complete. If CS is low, the completion of the next conversion, or if insufficient serial clocks are RDY DOUT/ line also goes low when a conversion is complete. applied to the AD7794/AD7795 to read the word, the serial To read a conversion, the user writes to the communications output register is reset when the next conversion is complete. register, indicating that the next operation is a read of the data The new conversion is then placed in the output serial register. RDY register. The digital conversion is placed on the DOUT/ To exit the continuous read mode, the instruction 01011000 pin as soon as SCLK pulses are applied to the ADC. DOUT/RDY RDY must be written to the communications register while the returns high when the conversion is read. The user can read this pin is low. While in the continuous read mode, the ADC register additional times, if required. However, the user must monitors activity on the DIN line so that it can receive the ensure that the data register is not being accessed at the completion instruction to exit the continuous read mode. Additionally, a of the next conversion, or else the new conversion word is lost. reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. Rev. D | Page 30 of 36 AD7794/AD7795 CIRCUIT DESCRIPTION INSTRUMENTATION AMPLIFIER ANALOG INPUT CHANNEL Amplifying the analog input signal by a gain of 1 or 2 is The AD7794/AD7795 have six differential analog input performed digitally within the AD7794/AD7795. However, channels. These are connected to the on-chip buffer amplifier when the gain equals 4 or higher, the output from the buffer is when the devices are operated in buffered mode. When in applied to the input of the on-chip instrumentation amplifier. unbuffered mode, the channels connect directly to the This low noise in-amp means that signals of small amplitude modulator. In buffered mode (the BUF bit in the configuration can be gained within the AD7794/AD7795 while still register is set to 1), the input channel feeds into a high maintaining excellent noise performance. For example, when impedance input stage of the buffer amplifier. Therefore, the the gain is set to 64, the rms noise is 40 nV typically, which is input can tolerate significant source impedances and is tailored equivalent to 21 bits effective resolution or 18.5 bits peak-to- for direct connection to external resistive-type sensors such as peak resolution. strain gages or resistance temperature detectors (RTDs). Each AD7794/AD7795 can be programmed to have a gain of 1, When BUF = 0, the parts operate in unbuffered mode. This 2, 4, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the results in a higher analog input current. Note that this configuration register. Therefore, with an external 2.5 V unbuffered input path provides a dynamic load to the driving reference, the unipolar ranges are from 0 mV to 20 mV to 0 V source. Therefore, resistor/capacitor combinations on the input to 2.5 V and the bipolar ranges are from ±20 mV to ±2.5 V. pins can cause gain errors, depending on the output impedance When the in-amp is active (gain ≥ 4), the common-mode of the source that is driving the ADC input. Table 22 shows the voltage ((AIN(+) + AIN(−))/2) must be greater than or equal to allowable external resistance/capacitance values for unbuffered 0.5 V when chop is enabled. With chop disabled, and with the mode so that no gain error at the 20-bit level is introduced. AMP-CM bit set to 1 to prevent degradation in the common- Table 22. External R-C Combination for 20-Bit No Gain Error mode rejection, the allowable common-mode voltage is limited Capacitance (pF) Resistance (Ω) to between 50 9 k 0.2 + (Gain/2 × (AIN(+) − AIN(−))) 100 6 k and 500 1.5 k AV − 0.2 − (Gain/2 × (AIN(+) − AIN(−))) 1000 900 DD 5000 200 If the AD7794/AD7795 are operated with an external reference that has a value equal to AV , for correct operation, the analog The AD7794/AD7795 can be operated in unbuffered mode DD only when the gain equals 1 or 2. At higher gains, the buffer input signal must be limited to 90% of VREF/gain when the in- amp is active. is automatically enabled. The absolute input voltage range in buffered mode is restricted to a range between GND + 100 mV BIPOLAR/UNIPOLAR CONFIGURATION and AVDD − 100 mV. When the gain is set to 4 or higher, the The analog input to the AD7794/AD7795 can accept either in-amp is enabled. The absolute input voltage range when the in- unipolar or bipolar input voltage ranges. A bipolar input range amp is active is restricted to a range between GND + 300 mV and does not imply that the parts can tolerate negative voltages with AV − 1.1 V. Care must be taken in setting up the common- DD respect to system GND. Unipolar and bipolar signals on the mode voltage so that these limits are not exceeded. Otherwise, AIN(+) input are referenced to the voltage on the AIN(−) input. there is degradation in linearity and noise performance. For example, if AIN(−) is 2.5 V and the ADC is configured for The absolute input voltage in unbuffered mode includes the unipolar mode with a gain of 1, the input voltage range on the range between GND − 30 mV and AVDD + 30 mV as a result of AIN(+) pin is 2.5 V to 5 V. being unbuffered. The negative absolute input voltage limit does If the ADC is configured for bipolar mode, the analog input allow the possibility of monitoring small, true bipolar signals range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar with respect to GND. option is chosen by programming the U/B bit in the configuration register. Rev. D | Page 31 of 36 AD7794/AD7795 DATA OUTPUT CODING EXCITATION CURRENTS When the ADC is configured for unipolar operation, the output The AD7794/AD7795 also contain two matched, software code is natural (straight) binary with a zero differential input configurable, constant current sources that can be programmed voltage resulting in a code of 00...00, a miscalled voltage to equal 10 μA, 210 μA, or 1 mA. Both source currents from resulting in a code of 100...000, and a full-scale input voltage AV are directed to either the IOUT1 or IOUT2 pin of the DD resulting in a code of 111...111. The output code for any analog device. These current sources are controlled via bits in the IO input voltage can be represented as register. The configuration bits enable the current sources and N direct the current sources to IOUT1 or IOUT2, along with Code = (2 × AIN × GAIN)/VREF selecting the value of the current. These current sources can be When the ADC is configured for bipolar operation, the output used to excite external resistive bridge or RTD sensors. code is offset binary with a negative full-scale voltage resulting BIAS VOLTAGE GENERATOR in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage A bias voltage generator is included on the AD7794/AD7795. It resulting in a code of 111...111. The output code for any analog biases the negative terminal of the selected input channel to input voltage can be represented as AVDD/2. This function is available on inputs AIN1(−) to N – 1 AIN3(−). It is useful in thermocouple applications, as the Code = 2 × [(AIN × GAIN/VREF) + 1] voltage generated by the thermocouple must be biased about where: some dc voltage if the gain is greater than 2. This is necessary AIN is the analog input voltage. because the instrumentation amplifier requires headroom. If GAIN is the in-amp setting (1 to 128). there is no headroom, signals close to GND or AV do not DD N = 24. convert accurately. BURNOUT CURRENTS The bias voltage generator is controlled using the VBIAS1 and VBIAS0 bits in conjunction with the BOOST bit in the The AD7794/AD7795 contain two 100 nA constant current configuration register. The power-up time of the bias voltage generators, one sourcing current from AVDD to AIN(+), and one generator is dependent on the load capacitance. To accommodate sinking current from AIN(−) to GND. The currents are higher load capacitances, each AD7794/AD7795 has a BOOST switched to the selected analog input pair. Both currents are bit. When this bit is set to 1, the current consumed by the bias either on or off, depending on the burnout current enable (BO) voltage generator is increased so that power-up time is reduced bit in the configuration register. These currents can be used to considerably. Figure 11 shows the power-up times when verify that an external transducer is still operational before BOOST equals 0 and BOOST equals 1 for different load attempting to take measurements on that channel. Once the capacitances. The current consumption of the AD7794/AD7795 burnout currents are turned on, they flow in the external increases by 40 μA when the bias voltage generator is enabled, transducer circuit, and a measurement of the input voltage on and BOOST equals 0. With the BOOST function enabled, the the analog input channel can be taken. If the resulting voltage current consumption increases by 250 μA. measured is full scale, the user needs to verify why this is the case. A full-scale reading could mean that the front-end sensor REFERENCE is open circuit. It could also mean that the front-end sensor is The AD7794/AD7795 have embedded 1.17 V references. These overloaded and is justified in outputting full scale, or that the references can be used to supply the ADC or external references reference may be absent and the NOXREF bit is set, thus can be applied. The embedded references are low noise, low clamping the data to all 1s. drift references with 4 ppm/°C drift typically. For external When reading all 1s from the output, the user needs to check references, the ADC has a fully differential input capability for these three cases before making a judgment. If the voltage the channel. In addition, the user has the option of selecting one measured is 0 V, it may indicate that the transducer has short of two external reference options (REFIN1 or REFIN2). The circuited. For normal operation, these burnout currents are reference source for the AD7794/AD7795 is selected using the turned off by writing a 0 to the BO bit in the configuration REFSEL1 and REFSEL0 bits in the configuration register. When register. The current sources work over the normal absolute the internal reference is selected, it is internally connected to input voltage range specifications with buffers on. the modulator (it is not available on the REFIN pins). The common-mode range for these differential inputs is from GND to AVDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V nominal, but the AD7794/AD7795 are functional with reference voltages from 0.1 V to AV . In applications where the DD excitation (voltage or current) for the transducer on the analog Rev. D | Page 32 of 36 AD7794/AD7795 input also drives the reference voltage for the parts, the effect of the on-chip registers. A reset is useful if the serial interface the low frequency noise in the excitation source is removed, becomes asynchronous due to noise on the SCLK line. because the application is ratiometric. If the AD7794/AD7795 AV MONITOR DD are used in nonratiometric applications, a low noise reference Along with converting external voltages, the ADC can be should be used. used to monitor the voltage on the AV pin. When Bit CH2 DD Recommended 2.5 V reference voltage sources for the to Bit CH0 equals 1, the voltage on the AV pin is internally DD AD7794/AD7795 include the ADR381 and ADR391, which are attenuated by 6, and the resulting voltage is applied to the low noise, low power references. Also, note that the reference ∑-Δ modulator using an internal 1.17 V reference for analog- inputs provide a high impedance, dynamic load. Because the to-digital conversion. This is useful because variations in the input impedance of each reference input is dynamic, resis- power supply voltage can be monitored. tor/capacitor combinations on these inputs can cause dc gain CALIBRATION errors, depending on the output impedance of the source driving the reference inputs. The AD7794/AD7795 provide four calibration modes that can be programmed via the mode bits in the mode register. These Reference voltage sources (for example, the ADR391) typically are internal zero-scale calibration, internal full-scale calibration, have low output impedances and are, therefore, tolerant to system zero-scale calibration, and system full-scale calibration, having decoupling capacitors on REFIN(+) without introducing which effectively reduce the offset error and full-scale error to gain errors in the system. Deriving the reference input voltage the order of the noise. After each conversion, the ADC across an external resistor means that the reference input sees a conversion result is scaled using the ADC calibration registers significant external source impedance. External decoupling on before being written to the data register. The offset calibration the REFIN pins is not recommended in this type of circuit coefficient is subtracted from the result prior to multiplication configuration. by the full-scale coefficient. REFERENCE DETECT To start a calibration, write the relevant value to the MD2 to The AD7794/AD7795 include on-chip circuitry to detect if they MD0 bits in the mode register. After the calibration is have a valid reference for conversions or calibrations when the completed, the contents of the corresponding calibration user selects an external reference as the reference source. This RDY registers are updated, the bit in the status register is set, feature is enabled when the REF_DET bit in the configuration RDY CS the DOUT/ pin goes low (if is low), and the register is set to 1. If the voltage between the selected REFIN(+) AD7794/AD7795 revert to idle mode. and REFIN(–) pins goes below 0.3 V, or either the REFIN(+) or During an internal zero-scale or full-scale calibration, the REFIN(–) inputs are open circuit, the AD7794/AD7795 detect respective zero input and full-scale input are automatically that they no longer have valid references. In this case, the connected internally to the ADC input pins. A system calibration, NOXREF bit of the status register is set to 1. If the AD7794/ however, expects the system zero-scale and system full-scale AD7795 are performing normal conversions and the NOXREF voltages to be applied to the ADC pins before initiating the bit becomes active, the conversion results revert to all 1s. calibration mode. In this way, external ADC errors are removed. Therefore, it is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only From an operational point of view, a calibration should be necessary to verify its status if the conversion result read from treated like another ADC conversion. A zero-scale calibration, the ADC data register is all 1s. If the AD7794/AD7795 are if required, should always be performed before a full-scale performing either offset or full-scale calibrations and the calibration. System software should monitor the RDY bit in the NOXREF bit becomes active, the updating of the respective RDY status register or the DOUT/ pin to determine the end of calibration registers is inhibited to avoid loading incorrect calibration via a polling sequence or an interrupt-driven routine. coefficients to these registers, and the ERR bit in the status With chop enabled, both an internal offset calibration and register is set. If the user is concerned about verifying that a a system offset calibration take two conversion cycles. With valid reference is in place every time a calibration is performed, chop enabled, an internal offset calibration is not needed the status of the ERR bit should be checked at the end of the because the ADC itself removes the offset continuously. With calibration cycle. chop disabled, an internal offset calibration or system offset RESET calibration takes one conversion cycle to complete. Internal The circuitry and serial interface of the AD7794/AD7795 can offset calibrations are required with chop disabled and should be reset by writing 32 consecutive 1s to the device. This resets occur before the full-scale calibration. the logic, the digital filter, and the analog modulator, and all on- To perform an internal full-scale calibration, a full-scale input chip registers are reset to their default values. A reset is voltage is automatically connected to the selected analog input automatically performed on power-up. When a reset is initiated, for this calibration. When the gain equals 1, a calibration takes the user must allow a period of 500 μs before accessing any of two conversion cycles to complete when chop is enabled and Rev. D | Page 33 of 36 AD7794/AD7795 one conversion cycle when chop is disabled. For higher gains, levels from the AD7794/AD7795 are so low, care must be taken four conversion cycles are required to perform the full-scale with regard to grounding and layout. calibration when chop is enabled, and two conversion cycles The printed circuit board that houses the AD7794/AD7795 when chop is disabled. DOUT/RDY goes high when the should be designed so that the analog and digital sections are calibration is initiated and returns low when the calibration is separated and confined to certain areas of the board. A minimum complete. The ADC is placed in idle mode following a cali- etch technique is generally best for ground planes because it bration. The measured full-scale coefficient is placed in the full- gives the best shielding. scale register of the selected channel. Internal full-scale It is recommended that the GND pin of the AD7794/AD7795 calibrations cannot be performed when the gain equals 128. be tied to the AGND plane of the system. In any layout, it is With this gain setting, a system full-scale calibration can be important that the user keep in mind the flow of currents in the performed. A full-scale calibration is required each time the system, ensuring that the return paths for all currents are as gain of a channel is changed to minimize the full-scale error. close as possible to the paths the currents took to reach their An internal full-scale calibration can be performed at specified destinations. Avoid forcing digital currents to flow through the update rates only. For gains of 1, 2, and 4, an internal full-scale AGND sections of the layout. calibration can be performed at any update rate. However, for The ground plane of the AD7794/AD7795 should be allowed to higher gains, internal full-scale calibrations can be performed run under the AD7794/AD7795 to prevent noise coupling. The only when the update rate is less than or equal to 16.7 Hz, 33.3 Hz, power supply lines to the AD7794/AD7795 should use as wide a and 50 Hz. However, the full-scale error does not vary with trace as possible to provide low impedance paths and reduce the update rate, so a calibration at one update is valid for all update effects of glitches on the power supply line. Fast switching rates (assuming the gain or reference source is not changed). signals, such as clocks, should be shielded with digital ground A system full-scale calibration takes two conversion cycles to to avoid radiating noise to other sections of the board. In complete, irrespective of the gain setting when chop is enabled addition, clock signals should never be run near the analog and one conversion cycle when chop is disabled. A system full- inputs. Avoid crossover of digital and analog signals. Traces on scale calibration can be performed at all gains and all update opposite sides of the board should run at right angles to each rates. With chop disabled, the offset calibration (internal or other. This reduces the effects of feedthrough through the system offset) should be performed before the system full-scale board. A microstrip technique is the best, but it is not always calibration is initiated. possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, GROUNDING AND LAYOUT while signals are placed on the solder side. Because the analog inputs and reference inputs of the ADC are Good decoupling is important when using high resolution differential, most of the voltages in the analog modulator are ADCs. AV should be decoupled with 10 μF tantalum in DD common-mode voltages. The excellent common-mode parallel with 0.1 μF capacitors to GND. DV should be DD rejection of the part removes common-mode noise on these decoupled with 10 μF tantalum in parallel with 0.1 μF inputs. The digital filter provides rejection of broadband noise capacitors to the system’s DGND plane, with the system’s on the power supply, except at integer multiples of the AGND to DGND connection being close to the modulator sampling frequency. The digital filter also removes AD7794/AD7795. To achieve the best from these decoupling noise from the analog and reference inputs, provided that these components, they should be placed as close as possible to the noise sources do not saturate the analog modulator. As a result, device, ideally right up against the device. All logic chips should the AD7794/AD7795 are more immune to noise interference be decoupled with 0.1 μF ceramic capacitors to DGND. than conventional high resolution converters. However, because the resolution of the AD7794/AD7795 is so high, and the noise Rev. D | Page 34 of 36 AD7794/AD7795 APPLICATIONS INFORMATION The AD7794/AD7795 offer low cost, high resolution analog-to- A second advantage of using the AD7794/AD7795 in transducer- digital functions. Because the analog-to-digital function is based applications is that the low-side power switch can be fully provided by a ∑-Δ architecture, it makes the parts more immune utilized in low power applications. The low-side power switch is to noisy environments, making them ideal for use in sensor connected in series with the cold side of the bridges. In normal measurement, and industrial and process control applications. operation, the switch is closed and measurements can be taken. In applications where power is of concern, the AD7794/AD7795 FLOWMETER can be placed in standby mode, thus significantly reducing the Figure 24 shows the AD7794/AD7795 being used in a power consumed in the application. In addition, the low-side flowmeter application that consists of two pressure transducers, power switch can be opened while in standby mode, thus with the rate of flow being equal to the pressure difference. The avoiding unnecessary power consumption by the front-end pressure transducers shown are the BP01 from Sensym. The transducers. When the parts are taken out of standby mode, and pressure transducers are arranged in a bridge network and give the low-side power switch is closed, the user should ensure that a differential output voltage between its OUT+ and OUT– the front-end circuitry is fully settled before attempting a read terminals. With rated full-scale pressure (in this case from the AD7794/AD7795. 300 mmHg) on the transducer, the differential output voltage is In the diagram, temperature compensation is performed using a 3 mV/V of the input voltage (that is, the voltage between the thermistor. The on-chip excitation current supplies the thermistor. IN(+) and IN(–) terminals). In addition, the reference voltage for the temperature measurement Assuming a 5 V excitation voltage, the full-scale output range is derived from a precision resistor in series with the thermistor. from the transducer is 15 mV. The excitation voltage for the This allows a ratiometric measurement so that variation of the bridge can be used to directly provide the reference for the excitation current has no effect on the measurement (it is the ADC, as the reference input range includes the supply voltage. ratio of the precision reference resistance to the thermistor resistance that is measured). V DD REFIN1(+) GND AV DD IN+ OUT– OUT+ AIN1(+) AD7794/AD7795 AIN1(–) IN+ V DD IN– OUT– OUT+ AIN2(+) DOUT/RDY SERIAL AIN2(–) DIN INTERFACE Σ-Δ MUX BUF IN-AMP AND IN– ADC AIN3(+) SCLK LOGIC CONTROL CS AIN3(–) GND REFIN2(+) V R DD CM REFIN2(–) DV INTERNAL DD IOUT1 CLOCK REFIN1(–) PSW GND CLK Figure 24. Typical Application (Flowmeter) Rev. D | Page 35 of 36 04854-025 AD7794/AD7795 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0° 0.30 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 25. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7794BRU –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7794BRU-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7794BRUZ –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7794BRUZ-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7794CRUZ –40°C to +125°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7794CRUZ-REEL –40°C to +125°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7795BRUZ –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7795BRUZ-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 EVAL-AD7794EB Evaluation Board EVAL-AD7795EB Evaluation Board 1 Z = RoHS Compliant Part. ©2004-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04854-0-3/07(D) Rev. D | Page 36 of 36