ANALOG DEVICES AD7792

3-Channel, Low Noise, Low Power, 16-/24-Bit ∑-Δ ADC with On-Chip In-Amp and Reference AD7792/AD7793 FEATURES FUNCTIONAL BLOCK DIAGRAM GND AV REFIN(+)/AIN3(+) REFIN(–)/AIN3(–) DD Up to 23 bits effective resolution RMS noise 40 nV @ 4.17 Hz V BIAS BAND GAP REFERENCE 85 nV @ 16.7 Hz GND AV DD Current: 400 μA typical AIN1(+) DOUT/RDY AIN1(–) SERIAL MUX Power-down: 1 μA maximum DIN INTERFACE AIN2(+) Σ-Δ BUF IN-AMP AND ADC AIN2(–) SCLK Low noise programmable gain instrumentation amp CONTROL LOGIC CS Band gap reference with 4 ppm/°C drift typical AV DD GND DV DD Update rate: 4.17 Hz to 470 Hz IOUT1 INTERNAL AD7792: 16-BIT CLOCK AD7793: 24-BIT 3 differential inputs IOUT2 Internal clock oscillator CLK Simultaneous 50 Hz/60 Hz rejection Figure 1. Programmable current sources GENERAL DESCRIPTION On-chip bias voltage generator The AD7792/AD7793 are low power, low noise, complete Burnout currents analog front ends for high precision measurement applications. Power supply: 2.7 V to 5.25 V The AD7792/AD7793 contain a low noise 16-/24-bit ∑-Δ ADC –40°C to +105°C temperature range with three differential analog inputs. The on-chip, low noise Independent interface power supply instrumentation amplifier means that signals of small ampli- 16-lead TSSOP package tude can be interfaced directly to the ADC. With a gain Interface setting of 64, the rms noise is 40 nV when the update rate 3-wire serial equals 4.17 Hz. SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK The devices contain a precision low noise, low drift internal band gap reference and can accept an external differential APPLICATIONS reference. Other on-chip features include programmable Thermocouple measurements excitation current sources, burnout currents, and a bias voltage RTD measurements generator. The bias voltage generator sets the common-mode Thermistor measurements voltage of a channel to AVDD/2. Gas analysis The devices can be operated with either the internal clock or an Industrial process control external clock. The output data rate from the parts is software- Instrumentation programmable and can be varied from 4.17 Hz to 470 Hz. Portable instrumentation Blood analysis The parts operate with a power supply from 2.7 V to 5.25 V. Smart transmitters They consume a current of 400 μA typical and are housed in a Liquid/gas chromatography 16-lead TSSOP package. 6-digit DVM Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04855-001 AD7792/AD7793 TABLE OF CONTENTS Features .............................................................................................. 1 Offset Register ............................................................................ 19 Applications....................................................................................... 1 Full-Scale Register...................................................................... 19 Functional Block Diagram .............................................................. 1 ADC Circuit Information.............................................................. 20 General Description ......................................................................... 1 Overview ..................................................................................... 20 Revision History ............................................................................... 2 Digital Interface.......................................................................... 21 Specifications..................................................................................... 3 Circuit Description......................................................................... 24 Timing Characteristics..................................................................... 6 Analog Input Channel ............................................................... 24 Timing Diagrams.......................................................................... 7 Instrumentation Amplifier........................................................ 24 Absolute Maximum Ratings............................................................ 8 Bipolar/Unipolar Configuration .............................................. 24 ESD Caution.................................................................................. 8 Data Output Coding .................................................................. 24 Pin Configuration and Function Descriptions............................. 9 Burnout Currents ....................................................................... 25 Output Noise and Resolution Specifications .............................. 11 Excitation Currents .................................................................... 25 External Reference...................................................................... 11 Bias Voltage Generator .............................................................. 25 Internal Reference ...................................................................... 12 Reference ..................................................................................... 25 Typical Performance Characteristics ........................................... 13 Reset ............................................................................................. 25 On-Chip Registers.......................................................................... 14 AV Monitor ............................................................................. 26 DD Communications Register......................................................... 14 Calibration................................................................................... 26 Status Register............................................................................. 15 Grounding and Layout .............................................................. 26 Mode Register ............................................................................. 15 Applications Information .............................................................. 28 Configuration Register .............................................................. 17 Temperature Measurement using a Thermocouple............... 28 Data Register ............................................................................... 18 Temperature Measurement using an RTD.............................. 29 ID Register................................................................................... 18 Outline Dimensions....................................................................... 30 IO Register................................................................................... 18 Ordering Guide .......................................................................... 30 REVISION HISTORY 3/07—Rev. A to Rev. B Updated Format..................................................................Universal 4/05—Rev. 0 to Rev. A Change to Functional Block Diagram ........................................... 1 Changes to Absolute Maximum Ratings........................................8 Changes to Specifications Section.................................................. 3 Changes to Figure 17.......................................................................22 Changes to Specifications Endnote 1............................................. 5 Changes to Data Output Coding Section.....................................24 Changes to Table 5, Table 6, and Table 7 ..................................... 11 Changes to Calibration Section .....................................................26 Changes to Table 8, Table 9, and Table 10 ................................... 12 Changes to Ordering Guide ...........................................................30 Changes to Table 16........................................................................ 16 10/04—Revision 0: Initial Version Changes to Overview Section ....................................................... 20 Renamed Applications Section to Applications Information... 29 Changes to Ordering Guide .......................................................... 30 Rev. B | Page 2 of 32 AD7792/AD7793 SPECIFICATIONS AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter AD7792B/AD7793B Unit Test Conditions/Comments ADC CHANNEL Output Update Rate 4.17 to 470 Hz nom 2 No Missing Codes 24 Bits min fADC < 242 Hz, AD7793 16 Bits min AD7792 Resolution See Output Noise and Resolution Specifications Output Noise and Update Rates See Output Noise and Resolution Specifications Integral Nonlinearity ±15 ppm of FSR max 3 Offset Error ±1 μV typ 4 Offset Error Drift vs. Temperature±10 nV/°C typ 3, 5 Full-Scale Error ±10 μV typ 4 Gain Drift vs. Temperature ±1 ppm/°C typ Gain = 1 to 16, external reference ±3 ppm/°C typ Gain = 32 to 128, external reference Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference ANALOG INPUTS Differential Input Voltage Ranges ±V /Gain V nom REF VREF = REFIN(+) − REFIN(−) or internal reference, gain = 1 to 128 2 Absolute AIN Voltage Limits Unbuffered Mode GND – 30 mV V min Gain = 1 or 2 AV + 30 mV V max DD Buffered Mode GND + 100 mV V min Gain = 1 or 2 AVDD – 100 mV V max In-Amp Active GND + 300 mV V min Gain = 4 to 128 AVDD – 1.1 V max Common-Mode Voltage, V 0.5 V min CM VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 Analog Input Current Buffered Mode or In-Amp Active 2 Average Input Current ±1 nA max Gain = 1 or 2, update rate < 100 Hz ±250 pA max Gain = 4 to 128, update rate < 100 Hz Average Input Current Drift ±2 pA/°C typ Unbuffered Mode Gain = 1 or 2. Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typ 2 Normal Mode Rejection Internal Clock 6 @ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 6 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 6 @ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 External Clock 6 @ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 6 @ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 6 @ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 Common-Mode Rejection @ DC 100 dB min AIN = 1 V/gain, gain ≥ 4 2 6 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 2 6 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz (FS[3:0] = 1001) , 60 ± 1 Hz 6 (FS[3:0] = 1000) Rev. B | Page 3 of 32 AD7792/AD7793 1 Parameter AD7792B/AD7793B Unit Test Conditions/Comments REFERENCE Internal Reference Internal Reference Initial Accuracy 1.17 ± 0.01% V min/max AVDD = 4 V, TA = 25°C 2 Internal Reference Drift 4 ppm/°C typ 15 ppm/°C max Power Supply Rejection 85 dB typ External Reference External REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−) 2 Reference Voltage Range 0.1 V min AVDD V max When VREF = AVDD, the differential input must be limited to 0.9 × VREF /gain if the in-amp is active 2 Absolute REFIN Voltage Limits GND − 30 mV V min AV + 30 mV V max DD Average Reference Input Current 400 nA/V typ Average Reference Input Current ±0.03 nA/V/°C typ Drift Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB typ EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current 10/210/1000 μA nom Initial Tolerance at 25°C ±5 % typ Drift 200 ppm/°C typ Current Matching ±0.5 % typ Matching between IEXC1 and IEXC2; VOUT = 0 V Drift Matching 50 ppm/°C typ Line Regulation (V) 2 %/V typ AV = 5 V ± 5% DD DD Load Regulation 0.2 %/V typ Output Compliance AVDD − 0.65 V max 10 μA or 210 μA currents selected AV − 1.1 V max 1 mA currents selected DD GND − 30 mV V min TEMPERATURE SENSOR Accuracy ±2 °C typ Applies if user calibrates the temperature Sensitivity 0.81 mV/°C typ sensor BIAS VOLTAGE GENERATOR V AV/2 V nom BIAS DD VBIAS Generator Start-Up Time See Figure 10 ms/nF typ Dependent on the capacitance on the AIN pin INTERNAL/EXTERNAL CLOCK Internal Clock 2 Frequency 64 ± 3% kHz min/max Duty Cycle 50:50 % typ External Clock Frequency 64 kHz nom A 128 kHz external clock can be used if the divide-by-2 function is used (Bit CLK1 = CLK0 = 1) Duty Cycle 45:55 to 55:45 % typ Applies for external 64 kHz clock; a 128 kHz clock can have a less stringent duty cycle LOGIC INPUTS 2 CS VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V min DVDD = 3 V or 5 V Rev. B | Page 4 of 32 AD7792/AD7793 1 Parameter AD7792B/AD7793B Unit Test Conditions/Comments SCLK, CLK, and DIN (Schmitt- 2 Triggered Input) VT(+) 1.4/2 V min/V max DVDD = 5 V V (–) 0.8/1.7 V min/V max DV = 5 V T DD 0.1/0.17 V min/V max DV = 5 V VT(+) − VT(−) DD VT(+) 0.9/2 V min/V max DVDD = 3 V VT(–) 0.4/1.35 V min/V max DVDD = 3 V V (+) − V (−) 0.06/0.13 V min/V max DV = 3 V T T DD Input Currents ±10 μA max VIN = DVDD or GND Input Capacitance 10 pF typ All digital inputs LOGIC OUTPUTS (INCLUDING CLK) 2 V , Output High Voltage V min DV = 3 V, I = 100 μA OH DVDD − 0.6 DD SOURCE 2 VOL, Output Low Voltage 0.4 V max DVDD = 3 V, ISINK = 100 μA 2 VOH, Output High Voltage 4 V min DVDD = 5 V, ISOURCE = 200 μA 2 V , Output Low Voltage 0.4 V max DV = 5 V, I = 1.6 mA (DOUT/RDY)/800 μA OL DD SINK (CLK) Floating-State Leakage Current ±10 μA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset binary 2 SYSTEM CALIBRATION Full-Scale Calibration Limit +1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max 7 POWER REQUIREMENTS Power Supply Voltage AVDD to GND 2.7/5.25 V min/max DV to GND 2.7/5.25 V min/max DD Power Supply Currents IDD Current 140 μA max 110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V, unbuffered mode, external reference 185 μA max 130 μA typ @ AV = 3 V, 165 μA typ @ AV = 5 V, DD DD buffered mode, gain = 1 or 2, external reference 400 μA max 300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V, gain = 4 to 128, external reference 500 μA max 400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V, gain = 4 to 128, internal reference I (Power-Down Mode) 1 μA max DD 1 Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AVDD − 16 V typically. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AVDD − 1.6 V. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DV or GND with excitation currents and bias voltage generator disabled. DD Rev. B | Page 5 of 32 AD7792/AD7793 TIMING CHARACTERISTICS AV = 2.7 V to 5.25 V, DV = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV , unless otherwise noted. DD DD DD Table 2. 1, 2 Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments t 100 ns min SCLK high pulse width 3 t 100 ns min SCLK low pulse width 4 Read Operation t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DV = 2.7 V to 3.6 V DD 3 4 t 0 ns min SCLK active edge to data valid delay 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DVDD = 2.7 V to 3.6 V 5, 6 t5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 Write Operation 4 t8 0 ns min CS falling edge to SCLK active edge setup time t9 30 ns min Data valid to SCLK edge setup time t 25 ns min Data valid to SCLK edge hold time 10 t 0 ns min CS rising edge to SCLK edge hold time 11 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. R F DD 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. I (1.6mA WITH DV = 5V, SINK DD 100µA WITH DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH DV = 5V, SOURCE DD 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Rev. B | Page 6 of 32 04855-002 AD7792/AD7793 TIMING DIAGRAMS CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 NOTES 1. I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 11 8 SCLK (I) t 9 t 10 DIN (I) MSB LSB NOTES 1. I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. B | Page 7 of 32 04855-004 04855-003 AD7792/AD7793 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Ratings other conditions above those listed in the operational sections AV to GND DD −0.3 V to +7 V of this specification is not implied. Exposure to absolute DVDD to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V device reliability. Reference Input Voltage to GND −0.3 V to AV + 0.3 V DD ESD CAUTION Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V Digital Output Voltage to GND −0.3 V to DV + 0.3 V DD AIN/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 128°C/W θJC Thermal Impedance 14°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. B | Page 8 of 32 AD7792/AD7793 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 16 SCLK DIN 2 15 CLK DOUT/RDY 3 14 CS DV DD AD7792/ IOUT1 4 13 AV AD7793 DD TOP VIEW AIN1(+) 5 12 GND (Not to Scale) AIN1(–) 6 11 IOUT2 AIN2(+) 7 10 REFIN(–)/AIN3(–) 8 AIN2(–) 9 REFIN(+)/AIN3(+) Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CLK Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 4 IOUT1 Output of Internal Excitation Current Source. The internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−). 8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−). 9 REFIN(+)/AIN3(+) Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage REFIN(+) − REFIN(−) is 2.5 V, but the part functions with a reference from 0.1 V to AV . Alternatively, this pin DD can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−). 10 REFIN(−)/AIN3(−) Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere between GND and AVDD − 0.1 V. This pin also functions as AIN3(−), which is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−). 11 IOUT2 Output of Internal Excitation Current Source. The internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 12 GND Ground Reference Point. 13 AV Supply Voltage, 2.7 V to 5.25 V. DD 14 DV Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which DD is between 2.7 V and 5.25 V. The DVDD voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V with DVDD at 3 V or vice versa. Rev. B | Page 9 of 32 04855-005 AD7792/AD7793 Pin No. Mnemonic Description 15 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 16 DIN Serial Data Input. This serial data input is to the input shift register on the ADC. Data in this shift register is transferred to the control registers within the ADC; the register selection bits of the communications register identify the appropriate register. Rev. B | Page 10 of 32 AD7792/AD7793 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS EXTERNAL REFERENCE Table 5 shows the output rms noise of the AD7792/AD7793 for shown in parentheses for the AD7793 and AD7792, respectively. some of the update rates and gain settings. The numbers given It is important to note that the effective resolution is calculated are for the bipolar input range with an external 2.5 V reference. using the rms noise, while the p-p resolution is based on the p-p These numbers are typical and are generated with a differential noise. The p-p resolution represents the resolution for which input voltage of 0 V. Table 6 and Table 7 show the effective there is no code flicker. These numbers are typical and are resolution, with the output peak-to-peak (p-p) resolution rounded to the nearest LSB. Table 5. Output RMS Noise (μV) vs. Gain and Output Update Rate for the AD7792 and AD7793 Using an External 2.5 V Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 0.64 0.6 0.29 0.22 0.1 0.065 0.039 0.041 8.33 1.04 0.96 0.38 0.26 0.13 0.078 0.057 0.055 16.7 1.55 1.45 0.54 0.36 0.18 0.11 0.087 0.086 33.2 2.3 2.13 0.74 0.5 0.23 0.17 0.124 0.118 62 2.95 2.85 0.92 0.58 0.29 0.2 0.153 0.144 123 4.89 4.74 1.49 1 0.48 0.32 0.265 0.283 242 11.76 9.5 4.02 1.96 0.88 0.45 0.379 0.397 470 11.33 9.44 3.07 1.79 0.99 0.63 0.568 0.593 Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7793 Using an External 2.5 V Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 23 (20.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 8.33 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 16.7 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19 (16.5) 33.2 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20.5 (18) 20 (17.5) 19 (16.5) 18.5 (16) 62 20.5 (18) 19.5 (17) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 123 20 (17.5) 19 (16.5) 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 18 (15.5) 17 (14.5) 242 18.5 (16) 18 (15.5) 18 (15.5) 18 (15.5) 18.5 (16) 18.5 (16) 17.5 (15) 16.5 (14) 470 18.5 (16) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17 (14.5) 16 (13.5) Table 7. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7792 Using an External 2.5 V Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 123 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 165 (15.5) 16 (14.5) 242 16 (16) 16 (15.5) 16 (15.5) 16 (15.5) 16 (16) 16 (16) 16 (15) 16 (14) 470 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (14.5) 15.5 (13.5) Rev. B | Page 11 of 32 AD7792/AD7793 INTERNAL REFERENCE Table 8 shows the output rms noise of the AD7792/AD7793 for resolution given in parentheses for the AD7793 and AD7792, some of the update rates and gain settings. The numbers given respectively. It is important to note that the effective resolution are for the bipolar input range with the internal 1.17 V is calculated using the rms noise, while the p-p resolution is reference. These numbers are typical and are generated with a calculated based on p-p noise. The p-p resolution represents the differential input voltage of 0 V. Table 9 and Table 10 show the resolution for which there is no code flicker. These numbers are effective resolution, with the output peak-to-peak (p-p) typical and are rounded to the nearest LSB. Table 8. Output RMS Noise (μV) vs. Gain and Output Update Rate for the AD7792 and AD7793 Using the Internal Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 0.81 0.67 0.32 0.2 0.13 0.065 0.04 0.039 8.33 1.18 1.11 0.41 0.25 0.16 0.078 0.058 0.059 16.7 1.96 1.72 0.55 0.36 0.25 0.11 0.088 0.088 33.2 2.99 2.48 0.83 0.48 0.33 0.17 0.13 0.12 62 3.6 3.25 1.03 0.65 0.46 0.2 0.15 0.15 123 5.83 5.01 1.69 0.96 0.67 0.32 0.25 0.26 242 11.22 8.64 2.69 1.9 1.04 0.45 0.35 0.34 470 12.46 10.58 4.58 2 1.27 0.63 0.50 0.49 Table 9. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7793 Using the Internal Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 8.33 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 18 (15.5) 16.7 20 (17.5) 19.5 (17) 20 (17.5) 19.5 (17) 19 (16.5) 19.5 (17) 18.5 (16) 17.5 (15) 33.2 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 62 19.5 (17) 18.5 (16) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 18 (15.5) 17 (14.5) 123 18.5 (16) 18 (15.5) 18.5 (16) 18 (15.5) 17.5 (15) 18 (15.5) 17 (14.5) 16 (13.5) 242 17.5 (15) 17 (14.5) 17.5 (15) 17 (14.5) 17 (14.5) 17.5 (15) 16.5 (14) 15.5 (13) 470 17.5 (15) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 16 (13.5) 15 (12.5) Table 10. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7792 Using the Internal Reference Update Rate (Hz) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 123 16 (16) 16 (15.5) 16 (16) 16 (15.5) 16 (15) 16 (15.5) 16 (14.5) 15.5 (13.5) 242 16 (15) 16 (14.5) 16 (15) 16 (14.5) 16 (14.5) 16 (15) 16 (14) 15 (13) 470 16 (15) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 15.5 (13.5) 14.5 (12.5) Rev. B | Page 12 of 32 AD7792/AD7793 TYPICAL PERFORMANCE CHARACTERISTICS 8388800 8388750 20 8388700 8388650 8388600 10 8388550 8388500 0 8388450 –1.75 –1.05 –0.70 –0.35 0 0.35 0.70 1.05 1.40 1.75 0 200 400 600 800 1000 MATCHING (%) READING NUMBER Figure 9. Excitation Current Matching (1 mA) at Ambient Temperature Figure 6. Typical Noise Plot (Internal Reference, Gain = 64, Update Rate = 16.7 Hz) for AD7793 16 90 80 14 70 12 60 10 50 8 40 6 30 4 20 2 10 0 0 8388482 8388520 8388560 8388600 8388640 8388680 8388720 8388750 0 200 400 600 800 1000 CODE LOAD CAPACITANCE (nF) Figure 10. Bias Voltage Generator Power-Up Time vs. Load Capacitance Figure 7. Noise Distribution Histogram for AD7793 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz) 3.0 V = 5V DD UPDATE RATE = 16.6Hz T = 25°C A 2.5 20 2.0 1.5 10 1.0 0.5 0 0 –2.0 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MATCHING (%) REFERENCE VOLTAGE (V) Figure 8. Excitation Current Matching (210 μA) at Ambient Figure 11. RMS Noise vs. Reference Voltage (Gain = 1) Temperature Rev. B | Page 13 of 32 CODE READ OCCURRENCE (%) OCCURRENCE 04855-008 04855-007 04855-006 RMS NOISE (µV) POWER-UP TIME (ms) OCCURRENCE (%) 04855-011 04855-010 04855-009 AD7792/AD7793 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip complete, the interface returns to where it expects a write registers, which are described on the following pages. In the operation to the communications register. This is the default following descriptions, set implies a Logic 1 state and cleared state of the interface and, on power-up or after a reset, the ADC implies a Logic 0 state, unless otherwise stated. is in this default state waiting for a write operation to the communications register. In situations where the interface COMMUNICATIONS REGISTER sequence is lost, a write operation of at least 32 serial clock RS2, RS1, RS0 = 0, 0, 0 cycles with DIN high returns the ADC to this default state by The communications register is an 8-bit write-only register. All resetting the entire part. Table 11 outlines the bit designations communications to the part must start with a write operation to for the communications register. CR0 through CR7 indicate the the communications register. The data written to the bit location, CR denoting the bits are in the communications communications register determines whether the next register. CR7 denotes the first bit of the data stream. The operation is a read or write operation, and to which register this number in parentheses indicates the power-on/reset default operation takes place. For read or write operations, once the status of that bit. subsequent read or write operation to the selected register is CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 11. Communications Register Bit Designations Bit Location Bit Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected RS0 during this serial interface communication. See Table 12. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read. For example, the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation. Table 12. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications Register During a Write Operation 8-bit 0 0 0 Status Register During a Read Operation 8-bit 0 0 1 Mode Register 16-bit 0 1 0 Configuration Register 16-bit 0 1 1 Data Register 16-/24-bit 1 0 0 ID Register 8-bit 1 0 1 IO Register 8-bit 1 1 0 Offset Register 16-bit (AD7792)/24-bit (AD7793) 1 1 1 Full-Scale Register 16-bit (AD7792)/24-bit (AD7793) Rev. B | Page 14 of 32 AD7792/AD7793 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 13 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, and SR denotes that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) 0(0) 0(0) 0/1 CH2(0) CH1(0) CH0(0) Table 13. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange. Cleared by a write operation to start a conversion. SR5 to SR4 0 These bits are automatically cleared. SR3 0/1 This bit is automatically cleared on the AD7792 and is automatically set on the AD7793. SR2 to SR0 CH2 to CH0 These bits indicate which channel is being converted by the ADC. MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, update rate, and clock source. Table 14 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses RDY indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the bit. MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MD2(0) MD1(0) MD0(0) 0(0) 0(0) 0(0) 0(0) 0(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 CLK1(0) CLK0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0) Table 14. Mode Register Bit Designations Bit Location Bit Name Description Mode Select Bits. These bits select the operational mode of the AD7792/AD7793 (see Table 15). MR15 to MD2 to MR13 MD0 MR12 to MR8 0 These bits must be programmed with a Logic 0 for correct operation. MR7 to MR6 CLK1 to These bits are used to select the clock source for the AD7792/AD7793. Either an on-chip 64 kHz clock can be CLK0 used, or an external clock can be used. The ability to override using an external clock allows several AD7792/AD7793 devices to be synchronized. In addition, 50 Hz/60 Hz is improved when an accurate external clock drives the AD7792/AD7793. CLK1 CLK0 ADC Clock Source 0 0 Internal 64 kHz Clock. Internal clock is not available at the CLK pin. 0 1 Internal 64 kHz Clock. This clock is made available at the CLK pin. 1 0 External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection. See specifications for external clock. 1 1 External Clock Used. The external clock is divided by 2 within the AD7792/AD7793. MR5 to MR4 0 These bits must be programmed with a Logic 0 for correct operation. MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 16). Rev. B | Page 15 of 32 AD7792/AD7793 Table 15. Operating Modes MD2 MD1 MD0 Mode 0 0 0 Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode, whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, a channel change, or a write to the mode, configuration, or IO registers, the first conversion is available after a period of 2/fADC. Subsequent conversions are available at a frequency of fADC. 0 0 1 Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f . The ADC conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register, and RDY remains active low until the data is read or another conversion is performed. 0 1 0 Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are still provided. 0 1 1 Power-Down Mode. In power-down mode, all the AD7792/AD7793 circuitry is powered down, including the current sources, burnout currents, bias voltage generator, and CLKOUT circuitry. 1 0 0 Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration. When the gain equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles are required to perform the full-scale calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full- scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. 1 1 0 System Zero-Scale Calibration. User should connect the system zero-scale input to the channel input pins as selected by the CH2 to CH0 bits. A system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 1 1 System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins as selected by the CH2 to CH0 bits. A calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. Table 16. Update Rates Available FS3 FS2 FS1 FS0 f (Hz) t (ms) Rejection @ 50 Hz/60 Hz (Internal Clock) ADC SETTLE 0 0 0 0 x x 0 0 0 1 470 4 0 0 1 0 242 8 0 0 1 1 123 16 0 1 0 0 62 32 0 1 0 1 50 40 0 1 1 0 39 48 0 1 1 1 33.2 60 1 0 0 0 19.6 101 90 dB (60 Hz only) Rev. B | Page 16 of 32 AD7792/AD7793 FS3 FS2 FS1 FS0 fADC (Hz) tSETTLE (ms) Rejection @ 50 Hz/60 Hz (Internal Clock) 1 0 0 1 16.7 120 80 dB (50 Hz only) 1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz) 1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz) 1 1 0 0 10 200 69 dB (50 Hz and 60 Hz) 1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz) 1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz) 1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz) CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to con- figure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. Table 17 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations; CON denotes that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 VBIAS1(0) VBIAS0(0) BO(0) U/B(0) BOOST(0) G2(1) G1(1) G0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 REFSEL(0) 0(0) 0(0) BUF(1) 0(0) CH2(0) CH1(0) CH0(0) Table 17. Configuration Register Bit Designations Bit Location Bit Name Description CON15 to VBIAS1 to Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AVDD/2. These CON14 VBIAS0 bits are used in conjunction with the boost bit. VBIAS1 VBIAS0 Bias Voltage 0 0 Bias voltage generator disabled 0 1 Bias voltage connected to AIN1(−) 1 0 Bias voltage connected to AIN2(−) 1 1 Reserved CON13 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active. CON12 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding; that is, zero differential input results in 0x000000 output, and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and a positive full-scale differential input results in an output code of 0xFFFFFF. CON11 BOOST This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias voltage generator is increased. This reduces its power-up time. CON10 to G2 to G0 Gain Select Bits. CON8 Written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (2.5 V Reference) 0 0 0 1 (In-amp not used) 2.5 V 0 0 1 2 (In-amp not used) 1.25 V 0 1 0 4 625 mV 0 1 1 8 312.5 mV 1 0 0 16 156.2 mV 1 0 1 32 78.125 mV 1 1 0 64 39.06 mV 1 1 1 128 19.53 mV Rev. B | Page 17 of 32 AD7792/AD7793 Bit Location Bit Name Description CON7 REFSEL Reference Select Bit. The reference source for the ADC is selected using this bit. REFSEL Reference Source 0 External Reference Applied between REFIN(+) and REFIN(–). 1 Internal Reference Selected. CON6 to 0 These bits must be programmed with a Logic 0 for correct operation. CON5 CON4 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. The buffer can be disabled when the gain equals 1 or 2. For higher gains, the buffer is automatically enabled. With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above AV . When the buffer is enabled, it requires some headroom, so the voltage on any input pin must be limited DD to 100 mV within the power supply rails. CON3 0 This bit must be programmed with a Logic 0 for correct operation. CON2 to CH2 to Channel Select Bits. Written by the user to select the active analog input channel to the ADC. CON0 CH0 CH2 CH1 CH0 Channel Calibration Pair 0 0 0 AIN1(+) – AIN1(–) 0 0 0 1 AIN2(+) – AIN2(–) 1 0 1 0 AIN3(+) – AIN3(–) 2 0 1 1 AIN1(–) – AIN1(–) 0 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Temp Sensor Automatically selects gain = 1 and internal reference 1 1 1 AVDD Monitor Automatically selects gain = 1/6 and 1.17 V reference DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXA (AD7792)/0xXB (AD7793) The identification number for the AD7792/AD7793 is stored in the ID register. This is a read-only register. IO REGISTER RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable and select the value of the excitation currents. Table 18 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations; IO denotes that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in parentheses indicates the power- on/reset default status of that bit. IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0(0) 0(0) 0(0) 0(0) IEXCDIR1(0) IEXCDIR0(0) IEXCEN1(0) IEXCEN0(0) Rev. B | Page 18 of 32 AD7792/AD7793 Table 18. IO Register Bit Designations Bit Location Bit Name Description IO7 to IO4 0 These bits must be programmed with a Logic 0 for correct operation. IO3 to IO2 IEXCDIR1 to Direction of current sources select bits. IEXCDIR0 IEXCDIR1 IEXCDIR0 Current Source Direction 0 0 Current Source IEXC1 connected to Pin IOUT1, Current Source IEXC2 connected to Pin IOUT2. 0 1 Current Source IEXC1 connected to Pin IOUT2, Current Source IEXC2 connected to Pin IOUT1. 1 0 Both current sources connected to Pin IOUT1. Permitted when the current sources are set to 10 μA or 210 μA only. 1 1 Both current sources connected to Pin IOUT2. Permitted when the current sources are set to 10 μA or 210 μA only. IO1 to IO0 IEXCEN1 to These bits are used to enable and disable the current sources along with selecting the value of the IEXCEN0 excitation currents. IEXCEN1 IEXCEN0 Current Source Value 0 0 Excitation Current Disabled. 0 1 10 μA 1 0 210 μA 1 1 1 mA FULL-SCALE REGISTER OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7792)/0x5XXX00 (AD7793) (AD7792)/0x800000 (AD7793) The full-scale register is a 16-bit register on the AD7792 and a Each analog input channel has a dedicated offset register that 24-bit register on the AD7793. The full-scale register holds the holds the offset calibration coefficient for the channel. This full-scale calibration coefficient for the ADC. The register is 16 bits wide on the AD7792 and 24 bits wide on the AD7792/AD7793 have 3 full-scale registers, each channel AD7793, and its power-on/reset value is 0x8000(00). The offset having a dedicated full-scale register. The full-scale registers are register is used in conjunction with its associated full-scale read/write registers; however, when writing to the full-scale register to form a register pair. The power-on-reset value is registers, the ADC must be placed in power-down mode or idle automatically overwritten if an internal or system zero-scale mode. These registers are configured on power-on with factory- calibration is initiated by the user. The offset register is a calibrated full-scale calibration coefficients, the calibration read/write register. However, the AD7792/AD7793 must be being performed at gain = 1. Therefore, every device has in idle mode or power-down mode when writing to the different default coefficients. The coefficients are different offset register. depending on whether the internal reference or an external reference is selected. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user, or the full-scale register is written to. Rev. B | Page 19 of 32 AD7792/AD7793 ADC CIRCUIT INFORMATION 0 OVERVIEW The AD7792/AD7793 are low power ADCs that incorporate a –20 ∑-Δ modulator, a buffer, reference, in-amp, and an on-chip digital filter intended for the measurement of wide dynamic –40 range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications. –60 The part has three differential inputs that can be buffered or unbuffered. The device can be operated with the internal 1.17 V –80 reference, or an external reference can be used. Figure 12 shows the basic connections required to operate the part. –100 GND AV DD 0 20 40 60 80 100 120 V BIAS REFIN(+) REFIN(–) FREQUENCY (Hz) THERMOCOUPLE BAND GAP JUNCTION R REFERENCE AIN1(+) Figure 13. Filter Profile with Update Rate = 4.17 Hz GND AIN1(–) AV DD R C 0 DOUT/RDY MUX AIN2(+) SERIAL INTERFACE DIN Σ-Δ BUF IN-AMP AIN2(–) AND ADC SCLK CONTROL LOGIC CS REFIN(+) –20 R REF GND DV DD INTERNAL AV REFIN(–) DD CLOCK AD7792/AD7793 IOUT2 –40 CLK Figure 12. Basic Connection Diagram –60 The output rate of the AD7792/AD7793 (fADC) is user-program- mable. The allowable update rates, along with their corresponding settling times, are listed in Table 16. Normal mode rejection is –80 the major function of the digital filter. Simultaneous 50 Hz and 60 Hz rejection is optimized when the update rate equals –100 16.7 Hz or less as notches are placed at both 50 Hz and 60 Hz 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) with these update rates. See Figure 14. Figure 14. Filter Profile with Update Rate = 16.7 Hz The AD7792/AD7793 use slightly different filter types, 0 depending on the output update rate so that the rejection of quantization noise and device noise is optimized. When the update rate is from 4.17 Hz to 12.5 Hz, a Sinc3 filter, along with –20 an averaging filter, is used. When the update rate is from 16.7 Hz to 39 Hz, a modified Sinc3 filter is used. This filter –40 provides simultaneous 50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A Sinc4 filter is used when the update rate –60 is from 50 Hz to 242 Hz. Finally, an integrate-only filter is used when the update rate equals 470 Hz. –80 Figure 13 to Figure 16 show the frequency response of the different filter types for several update rates. –100 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) Figure 15. Filter Profile with Update Rate = 242 Hz Rev. B | Page 20 of 32 04855-012 (dB) (dB) (dB) 04855-020 04855-019 04855-018 AD7792/AD7793 0 Figure 3 and Figure 4 show timing diagrams for interfacing to CS the AD7792/AD7793 with being used to decode the part. –10 Figure 3 shows the timing for a read operation from the AD7792/AD7793 output shift register, and Figure 4 shows the –20 timing for a write operation to the input shift register. It is possible to read the same word from the data register several –30 times, even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that –40 the read operations have been completed before the next output update occurs. In continuous read mode, the data register can –50 be read only once. –60 The serial interface can operate in 3-wire mode by tying CS low. 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 In this case, the SCLK, DIN, and DOUT/RDY lines are used FREQUENCY (Hz) to communicate with the AD7792/AD7793. The end of the Figure 16. Filter Response at 470 Hz Update Rate RDY conversion can be monitored using the bit in the status DIGITAL INTERFACE register. This scheme is suitable for interfacing to microcon- The programmable functions of the AD7792/AD7793 are CS trollers. If is required as a decoding signal, it can be controlled using a set of on-chip registers. Data is written to generated from a port pin. For microcontroller interfaces, it is these registers via the serial interface of the device; read access recommended that SCLK idle high between data transfers. to the on-chip registers is also provided by this interface. All The AD7792/AD7793 can be operated with CS being used as a communications with the device must start with a write to the frame synchronization signal. This scheme is useful for DSP communications register. After power-on or reset, the device interfaces. In this case, the first bit (MSB) is effectively clocked expects a write to its communications register. The data written CS CS out by , because would normally occur after the falling to this register determines whether the next operation is a read edge of SCLK in DSPs. The SCLK can continue to run between operation or a write operation and determines to which register data transfers, provided the timing numbers are obeyed. this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write The serial interface can be reset by writing a series of 1s on the operation to the communications register followed by a write to DIN input. If a Logic 1 is written to the AD7792/AD7793 line the selected register. A read operation from any other register for at least 32 serial clock cycles, the serial interface is reset. (except when continuous read mode is selected) starts with a This ensures that the interface can be reset to a known state if write to the communications register followed by a read the interface gets lost due to a software error or some glitch in operation from the selected register. the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This opera- The serial interfaces of the AD7792/AD7793 consist of four tion resets the contents of all registers to their power-on values. signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used Following a reset, the user should allow a period of 500 μs to transfer data into the on-chip registers, and DOUT/RDY is before addressing the serial interface. used for accessing from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN The AD7792/AD7793 can be configured to continuously RDY convert or to perform a single conversion. See Figure 17 or DOUT/ ) occur with respect to the SCLK signal. The through Figure 19. RDY DOUT/ pin operates as a data-ready signal also, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is CS being updated. is used to select a device. It can be used to decode the AD7792/AD7793 in systems where several components are connected to the serial bus. Rev. B | Page 21 of 32 (dB) 04855-021 AD7792/AD7793 Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7792/AD7793 are placed in This is the default power-up mode. The AD7792/AD7793 shutdown mode between conversions. When a single conver- continuously converts, the RDY pin in the status register going sion is initiated by setting MD2, MD1, MD0 to 0, 0, 1 in the low each time a conversion is completed. If CS is low, the mode register, the AD7792/AD7793 power up, perform a single DOUT/ RDY line also goes low when a conversion is complete. conversion, and then return to shutdown mode. The on-chip To read a conversion, the user writes to the communications oscillator requires 1 ms to power up. A conversion requires a register indicating that the next operation is a read of the data RDY time period of 2 × tADC. DOUT/ goes low to indicate the RDY register. The digital conversion is placed on the DOUT/ completion of a conversion. When the data-word has been read pin as soon as SCLK pulses are applied to the ADC. from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY returns high when the conversion is read. The DOUT/RDY remains high until another conversion is initiated user can read this register additional times, if required. and completed. The data register can be read several times, if However, the user must ensure that the data register is not being required, even when DOUT/RDY has gone high. accessed at the completion of the next conversion, otherwise the new conversion word is lost. CS 0x08 0x200A 0x58 DIN DATA DOUT/RDY SCLK Figure 17. Single Conversion CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK Figure 18. Continuous Conversion Rev. B | Page 22 of 32 04855-016 04855-015 AD7792/AD7793 Continuous Read read before the next conversion is complete. If the user has not read the conversion before the completion of the next Rather than write to the communications register each time a conversion, or if insufficient serial clocks are applied to the conversion is complete to access the data, the AD7792/AD7793 AD7792/AD7793 to read the word, the serial output register is can be configured so that the conversions are placed on the reset when the next conversion is completed, and the new DOUT/RDY line automatically. By writing 01011100 to the conversion is placed in the output serial register. communications register, the user needs only to apply the appropriate number of SCLK cycles to the ADC, and the 16/24- To exit the continuous read mode, the instruction 01011000 RDY must be written to the communications register while the bit word is automatically placed on the DOUT/ line when a RDY conversion is complete. The ADC should be configured for DOUT/ pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the continuous conversion mode. instruction to exit the continuous read mode. Additionally, a When DOUT/RDY goes low to indicate the end of a conver- reset occurs if 32 consecutive 1s are seen on DIN. Therefore, sion, sufficient SCLK cycles must be applied to the ADC, and DIN should be held low in continuous read mode until an RDY the data conversion is placed on the DOUT/ line. When instruction is written to the device. RDY the conversion is read, DOUT/ returns high until the next conversion is available. In this mode, the data can be read only once. In addition, the user must ensure that the data-word is CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK Figure 19. Continuous Read Rev. B | Page 23 of 32 04855-017 AD7792/AD7793 CIRCUIT DESCRIPTION For example, when the gain is set to 64, the rms noise is 40 nV ANALOG INPUT CHANNEL typically, which is equivalent to 21 bits effective resolution or The AD7792/AD7793 have three differential analog input 18.5 bits peak-to-peak resolution. channels. These are connected to the on-chip buffer amplifier The AD7792/AD7793 can be programmed to have a gain of 1, when the device is operated in buffered mode and directly to 2, 4, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configu- the modulator when the device is operated in unbuffered mode. ration register. Therefore, with an external 2.5 V reference, the In buffered mode (the BUF bit in the mode register is set to 1), unipolar ranges are from 0 mV to 20 mV to 0 V to 2.5 V while the input channel feeds into a high impedance input stage of the the bipolar ranges are from ±20 mV to ±2.5 V. When the buffer amplifier. Therefore, the input can tolerate significant in-amp is active (gain ≥ 4), the common-mode voltage (AIN(+) source impedances and is tailored for direct connection to + AIN(–))/2 must be greater than or equal to 0.5 V. external resistive-type sensors, such as strain gauges or resistance temperature detectors (RTDs). If the AD7792/AD7793 are operated with an external reference that has a value equal to AVDD, the analog input signal must be When BUF = 0, the part is operated in unbuffered mode. limited to 90% of V /gain when the in-amp is active, for REF This results in a higher analog input current. Note that this correct operation. unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input BIPOLAR/UNIPOLAR CONFIGURATION pins can cause gain errors, depending on the output impedance The analog input to the AD7792/AD7793 can accept either of the source that is driving the ADC input. Table 19 shows the unipolar or bipolar input voltage ranges. A bipolar input range allowable external resistance/capacitance values for unbuffered does not imply that the part can tolerate negative voltages with mode such that no gain error at the 20-bit level is introduced. respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(–) input. Table 19. External R-C Combination for No 20-Bit Gain Error For example, if AIN(−) is 2.5 V, and the ADC is configured for C (pF) R (Ω) unipolar mode and a gain of 1, the input voltage range on the 50 9 k AIN(+) pin is 2.5 V to 5 V. 100 6 k If the ADC is configured for bipolar mode, the analog input 500 1.5 k range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar 1000 900 B 5000 200 option is chosen by programming the U/ bit in the configura- tion register. The AD7792/AD7793 can be operated in unbuffered mode only when the gain equals 1 or 2. At higher gains, the buffer is auto- DATA OUTPUT CODING matically enabled. The absolute input voltage range in buffered When the ADC is configured for unipolar operation, the output mode is restricted to a range between GND + 100 mV and code is natural (straight) binary with a zero differential input AV – 100 mV. When the gain is set to 4 or higher, the in-amp DD voltage resulting in a code of 00...00, a midscale voltage is enabled. The absolute input voltage range when the in-amp is resulting in a code of 100...000, and a full-scale input voltage active is restricted to a range between GND + 300 mV and resulting in a code of 111...111. The output code for any analog AVDD − 1.1 V. Take care in setting up the common-mode input voltage can be represented as voltage so that these limits are not exceeded to avoid N Code = (2 × AIN × GAIN)/VREF degradation in linearity and noise performance. When the ADC is configured for bipolar operation, the output The absolute input voltage in unbuffered mode includes the code is offset binary with a negative full-scale voltage resulting range between GND – 30 mV and AV + 30 mV as a result of DD in a code of 000...000, a zero differential input voltage resulting being unbuffered. The negative absolute input voltage limit does in a code of 100...000, and a positive full-scale input voltage allow the possibility of monitoring small true bipolar signals resulting in a code of 111...111. The output code for any analog with respect to GND. input voltage can be represented as INSTRUMENTATION AMPLIFIER N – 1 Code = 2 × [(AIN × GAIN /VREF) + 1] Amplifying the analog input signal by a gain of 1 or 2 is where AIN is the analog input voltage, GAIN is the in-amp performed digitally within the AD7792/AD7793. However, setting (1 to 128), and N = 16 for the AD7792 and N = 24 for when the gain equals 4 or higher, the output from the buffer is the AD7793. applied to the input of the on-chip instrumentation amplifier. This low noise in-amp means that signals of small amplitude can be gained within the AD7792/AD7793 while still maintaining excellent noise performance. Rev. B | Page 24 of 32 AD7792/AD7793 The current consumption of the AD7792/AD7793 increases by BURNOUT CURRENTS 40 μA when the bias voltage generator is enabled, and boost The AD7792/AD7793 contain two 100 nA constant current equals 0. With the boost function enabled, the current generators, one sourcing current from AVDD to AIN(+) and one consumption increases by 250 μA. sinking current from AIN(–) to GND. The currents are switched to the selected analog input pair. Both currents are REFERENCE either on or off, depending on the burnout current enable (BO) The AD7792/AD7793 have an embedded 1.17 V reference that bit in the configuration register. These currents can be used to can be used to supply the ADC, or an external reference can be verify that an external transducer is still operational before applied. The embedded reference is a low noise, low drift attempting to take measurements on that channel. Once the reference, the drift being 4 ppm/°C typically. For external burnout currents are turned on, they flow in the external references, the ADC has a fully differential input capability for transducer circuit, and a measurement of the input voltage on the channel. The reference source for the AD7792/AD7793 is the analog input channel can be taken. If the resultant voltage selected using the REFSEL bit in the configuration register. measured is full scale, the user needs to verify why this is the When the internal reference is selected, it is internally con- case. A full-scale reading could mean that the front-end sensor nected to the modulator. It is not available on the REFIN pins. is open circuit. It could also mean that the front-end sensor is The common-mode range for these differential inputs is from overloaded and is justified in outputting full scale, or the GND to AVDD. The reference input is unbuffered; therefore, reference may be absent, thus clamping the data to all 1s. excessive R-C source impedances introduce gain errors. The When reading all 1s from the output, the user needs to check reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V these three cases before making a judgment. If the voltage nominal, but the AD7792/AD7793 are functional with reference measured is 0 V, it may indicate that the transducer has short voltages from 0.1 V to AV . In applications where the exci- DD circuited. For normal operation, these burnout currents are tation (voltage or current) for the transducer on the analog turned off by writing a 0 to the BO bit in the configuration input also drives the reference voltage for the part, the effect register. The current sources work over the normal absolute of the low frequency noise in the excitation source is removed input voltage range specifications with buffers on. because the application is ratiometric. If the AD7792/AD7793 are used in a nonratiometric application, a low noise reference EXCITATION CURRENTS should be used. The AD7792/AD7793 also contain two matched, software Recommended 2.5 V reference voltage sources for the AD7792/ configurable, constant current sources that can be programmed AD7793 include the ADR381 and ADR391, which are low noise, to equal 10 μA, 210 μA, or 1 mA. Both source currents from the low power references. Also note that the reference inputs AVDD are directed to either the IOUT1 or IOUT2 pin of the provide a high impedance, dynamic load. Because the input device. These current sources are controlled via bits in the IO register. The configuration bits enable the current sources, impedance of each reference input is dynamic, resistor/capacitor direct the current sources to IOUT1 or IOUT2, and select the combinations on these inputs can cause dc gain errors, depending value of the current. These current sources can be used to excite on the output impedance of the source that is driving the external resistive bridge or RTD sensors. reference inputs. Reference voltage sources like those recommended above (such BIAS VOLTAGE GENERATOR as ADR391) typically have low output impedances and are, A bias voltage generator is included on the AD7792/AD7793. therefore, tolerant to having decoupling capacitors on REFIN(+) This biases the negative terminal of the selected input channel without introducing gain errors in the system. Deriving the to AV /2. It is useful in thermocouple applications, because the DD reference input voltage across an external resistor means that voltage generated by the thermocouple must be biased about the reference input sees a significant external source impedance. some dc voltage if the gain is greater than 2. This is necessary External decoupling on the REFIN pins is not recommended in because the instrumentation amplifier requires headroom to this type of circuit configuration. ensure that signals close to GND or AVDD are converted accurately. RESET The bias voltage generator is controlled using the VBIAS1 and The circuitry and serial interface of the AD7792/AD7793 can VBIAS0 bits in conjunction with the boost bit in the configura- be reset by writing 32 consecutive 1s to the device. This resets tion register. The power-up time of the bias voltage generator is the logic, the digital filter, and the analog modulator while all dependent on the load capacitance. To accommodate higher on-chip registers are reset to their default values. A reset is load capacitances, the AD7792/AD7793 have a boost bit. When automatically performed on power-up. When a reset is initiated, this bit is set to 1, the current consumed by the bias voltage the user must allow a period of 500 μs before accessing any of generator increases, so that the power-up time is considerably the on-chip registers. A reset is useful if the serial interface reduced. Figure 10 shows the power-up time when boost equals becomes asynchronous due to noise on the SCLK line. 0 and 1 for different load capacitances. Rev. B | Page 25 of 32 AD7792/AD7793 The ADC is placed in idle mode following a calibration. The AV MONITOR DD measured full-scale coefficient is placed in the full-scale register Along with converting external voltages, the ADC can be used of the selected channel. Internal full-scale calibrations cannot be to monitor the voltage on the AVDD pin. When Bit CH2 to performed when the gain equals 128. With this gain setting, a Bit CH0 equal 1, the voltage on the AVDD pin is internally system full-scale calibration can be performed. A full-scale attenuated by 6, and the resultant voltage is applied to the ∑-Δ calibration is required each time the gain of a channel is modulator using an internal 1.17 V reference for analog-to- changed to minimize the full-scale error. digital conversion. This is useful, because variations in the power supply voltage can be monitored. An internal full-scale calibration can be performed at specified update rates only. For gains of 1, 2, and 4, an internal full-scale CALIBRATION calibration can be performed at any update rate. However, for The AD7792/AD7793 provide four calibration modes that can higher gains, internal full-scale calibrations can be performed be programmed via the mode bits in the mode register. These when the update rate is less than or equal to 16.7 Hz, 33.2 Hz, are internal zero-scale calibration, internal full-scale calibration, and 50 Hz only. However, the full-scale error does not vary with system zero-scale calibration, and system full-scale calibration, update rate, so a calibration at one update rate is valid for all which effectively reduces the offset error and full-scale error to update rates (assuming the gain or reference source is not the order of the noise. After each conversion, the ADC con- changed). version result is scaled using the ADC calibration registers A system full-scale calibration takes 2 conversion cycles to before being written to the data register. The offset calibration complete, irrespective of the gain setting. A system full-scale coefficient is subtracted from the result prior to multiplication calibration can be performed at all gains and all update rates. If by the full-scale coefficient. system offset calibrations are being performed along with To start a calibration, write the relevant value to the MD2 to system full-scale calibrations, the offset calibration should be MD0 bits in the mode register. After the calibration is complete, performed before the system full-scale calibration is initiated. the contents of the corresponding calibration registers are GROUNDING AND LAYOUT RDY updated, the bit in the status register is set, the DOUT/ Because the analog inputs and reference inputs of the ADC are RDY CS pin goes low (if is low), and the AD7792/AD7793 differential, most of the voltages in the analog modulator are revert to idle mode. common-mode voltages. The excellent common-mode reject- During an internal zero-scale or full-scale calibration, the ion of the part removes common-mode noise on these inputs. respective zero input and full-scale input are automatically The digital filter provides rejection of broadband noise on the connected internally to the ADC input pins. A system power supply, except at integer multiples of the modulator calibration, however, expects the system zero-scale and system sampling frequency. The digital filter also removes noise from full-scale voltages to be applied to the ADC pins before the the analog and reference inputs, provided that these noise calibration mode is initiated. In this way, external ADC errors sources do not saturate the analog modulator. As a result, the are removed. AD7792/AD7793 are more immune to noise interference than a From an operational point of view, a calibration should be conventional high resolution converter. However, because the treated like another ADC conversion. A zero-scale calibration resolution of the AD7792/AD7793 is so high, and the noise (if required) should always be performed before a full-scale levels from the AD7792/AD7793 are so low, care must be taken calibration. System software should monitor the RDY bit in with regard to grounding and layout. the status register or the DOUT/RDY pin to determine the The printed circuit board that houses the AD7792/AD7793 end of calibration via a polling sequence or an interrupt-driven should be designed such that the analog and digital sections are routine. separated and confined to certain areas of the board. A mini- Both an internal offset calibration and a system offset mum etch technique is generally best for ground planes because calibration take two conversion cycles. An internal offset it provides the best shielding. calibration is not needed, as the ADC itself removes the offset It is recommended that the GND pins of the AD7792/AD7793 continuously. be tied to the AGND plane of the system. In any layout, it is important to keep in mind the flow of currents in the system, To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input ensuring that the return paths for all currents are as close as for this calibration. When the gain equals 1, a calibration takes possible to the paths the currents took to reach their destinations. 2 conversion cycles to complete. For higher gains, 4 conversion Avoid forcing digital currents to flow through the AGND cycles are required to perform the full-scale calibration. sections of the layout. RDY DOUT/ goes high when the calibration is initiated and returns low when the calibration is complete. Rev. B | Page 26 of 32 AD7792/AD7793 The ground planes of the AD7792/AD7793 should be allowed Good decoupling is important when using high resolution to run under the AD7792/AD7793 to prevent noise coupling. ADCs. AV should be decoupled with 10 μF tantalum in DD The power supply lines to the AD7792/AD7793 should use as parallel with 0.1 μF capacitors to GND. DV should be DD wide a trace as possible to provide low impedance paths and decoupled with 10 μF tantalum in parallel with 0.1 μF reduce the effects of glitches on the power supply line. Fast capacitors to the system’s DGND plane, with the system’s switching signals such as clocks should be shielded with digital AGND to DGND connection being close to the ground to avoid radiating noise to other sections of the board, AD7792/AD7793. and clock signals should never be run near the analog inputs. To achieve the best from these decoupling components, they Avoid crossover of digital and analog signals. Traces on should be placed as close as possible to the device, ideally right opposite sides of the board should run at right angles to each up against the device. All logic chips should be decoupled with other. This reduces the effects of feedthrough through the 0.1 μF ceramic capacitors to DGND. board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Rev. B | Page 27 of 32 AD7792/AD7793 APPLICATIONS INFORMATION The AD7792/AD7793 provide a low cost, high resolution amplify the signal from the thermocouple. As the input channel analog-to-digital function. Because the analog-to-digital is buffered, large decoupling capacitors can be placed on the function is provided by a ∑-Δ architecture, the parts are more front end to eliminate any noise pickup that may be present in immune to noisy environments, making them ideal for use in the thermocouple leads. The AD7792/AD7793 have a reduced sensor measurement and industrial and process control common-mode range with the in-amp enabled, so the bias applications. voltage generator provides a common-mode voltage so that the voltage generated by the thermocouple is biased up to AV /2. DD TEMPERATURE MEASUREMENT USING A The cold junction compensation is performed using a thermis- THERMOCOUPLE tor in the diagram. The on-chip excitation current supplies the Figure 20 outlines a connection from a thermocouple to the thermistor. In addition, the reference voltage for the cold AD7792/AD7793. In a thermocouple application, the voltage junction measurement is derived from a precision resistor in generated by the thermocouple is measured with respect to an series with the thermistor. This allows a ratiometric measure- absolute reference, so the internal reference is used for this ment so that variation of the excitation current has no effect on conversion. The cold junction measurement uses a ratiometric the measurement (it is the ratio of the precision reference configuration, so the reference is provided externally. resistance to the thermistor resistance that is measured). Because the signal from the thermocouple is small, the AD7792/AD7793 are operated with the in-amp enabled to GND AV DD V BIAS REFIN(+) REFIN(–) THERMOCOUPLE BAND GAP JUNCTION REFERENCE R AIN1(+) GND AIN1(–) AV DD R C DOUT/RDY MUX AIN2(+) SERIAL DIN INTERFACE Σ-Δ BUF IN-AMP AND AIN2(–) ADC SCLK CONTROL LOGIC CS REFIN(+) R REF GND DV DD INTERNAL AV REFIN(–) DD CLOCK AD7792/AD7793 IOUT2 CLK Figure 20. Thermocouple Measurement Using the AD7792/AD7793 Rev. B | Page 28 of 32 04855-012 AD7792/AD7793 material and of equal length), and IOUT1 and IOUT2 match, TEMPERATURE MEASUREMENT USING AN RTD the error voltage across RL2 equals the error voltage across RL1, To optimize a 3-wire RTD configuration, two identically and no error voltage is developed between AIN1(+) and matched current sources are required. The AD7792/AD7793, AIN1(–). Twice the voltage is developed across RL3 but, which contain two well-matched current sources, are ideally because this is a common-mode voltage, it does not introduce suited to these applications. One possible 3-wire configuration errors. The reference voltage for the AD7792/AD7793 is also is shown in Figure 21. In this 3-wire configuration, the lead generated using one of these matched current sources. It is resistances result in errors if only one current is used, as the developed using a precision resistor and applied to the excitation current flows through RL1, developing a voltage error differential reference pins of the ADC. This scheme ensures that between AIN1(+) and AIN1(–). In the scheme outlined, the the analog input voltage span remains ratiometric to the second RTD current source is used to compensate for the error reference voltage. Any errors in the analog input voltage due to introduced by the excitation current flowing through RL1. The the temperature drift of the excitation current are compensated second RTD current flows through RL2. Assuming RL1 and by the variation of the reference voltage. RL2 are equal (the leads would normally be of the same GND AV DD REFIN(+) REFIN(–) BAND GAP IOUT1 REFERENCE GND AV DD RL1 AIN1(+) DOUT/RDY RTD AIN1(–) SERIAL DIN INTERFACE Σ-Δ RL2 BUF IN-AMP AND IOUT2 ADC SCLK CONTROL LOGIC CS RL3 REFIN(+) GND DV R DD REF INTERNAL AD7792/AD7793 CLOCK REFIN(–) CLK Figure 21. RTD Application Using the AD7792/AD7793 Rev. B | Page 29 of 32 04855-013 AD7792/AD7793 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7792BRU –40°C to +105°C 16-Lead TSSOP RU-16 AD7792BRU-REEL –40°C to +105°C 16-Lead TSSOP RU-16 1 AD7792BRUZ –40°C to +105°C 16-Lead TSSOP RU-16 1 AD7792BRUZ-REEL –40°C to +105°C 16-Lead TSSOP RU-16 AD7793BRU –40°C to +105°C 16-Lead TSSOP RU-16 AD7793BRU-REEL –40°C to +105°C 16-Lead TSSOP RU-16 1 AD7793BRUZ –40°C to +105°C 16-Lead TSSOP RU-16 1 AD7793BRUZ-REEL –40°C to +105°C 16-Lead TSSOP RU-16 1 EVAL-AD7792EBZ Evaluation Board 1 EVAL-AD7793EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 30 of 32 AD7792/AD7793 NOTES Rev. B | Page 31 of 32 AD7792/AD7793 NOTES ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04855-0-3/07(B) Rev. B | Page 32 of 32