ANALOG DEVICES AD7790

Low Power, 16-Bit Buffered Sigma-Delta ADC AD7790 FUNCTIONAL BLOCK DIAGRAM FEATURES Power GND V REFIN DD Supply: 2.5 V to 5.25 V operation Normal: 75 µA maximum V DD INTERNAL CLOCK Power-down: 1 µA maximum RMS noise: 1.1 µV at 9.5 Hz update rate 16-BIT SERIAL 16-bit p-p resolution DIGITAL BUF AIN ADC INTERFACE PGA Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection AD7790 GND Internal clock oscillator 03538-0-001 Programmable gain amplifier Rail-to-rail input buffer Figure 1. V monitor channel DD Temperature range: –40°C to +105°C GENERAL DESCRIPTION 10-lead MSOP The AD7790 is a low power, complete analog front end for low frequency measurement applications. It contains a low INTERFACE noise 16-bit ∑-∆ ADC with one differential input that can be 3-wire serial buffered or unbuffered along with a digital PGA, which allows SPI®, QSPI™, MICROWIRE™, and DSP compatible gains of 1, 2, 4, and 8. Schmitt trigger on SCLK The device operates from an internal clock. Therefore, the user APPLICATIONS does not have to supply a clock source to the device. The output Smart transmitters data rate from the part is software programmable and can be Battery applications varied from 9.5 Hz to 120 Hz, with the rms noise equal to Portable instrumentation 1.1 µV at the lower update rate. The internal clock frequency Sensor measurement can be divided by a factor of 2, 4, or 8, which leads to a reduc- Temperature measurement tion in the current consumption. The update rate, cutoff Pressure measurement frequency, and settling time will scale with the clock frequency. Weigh scales The part operates with a power supply from 2.5 V to 5.25 V. 4 to 20 mA loops When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7790 TABLE OF CONTENTS AD7790—Specifications.................................................................. 3 ADC Circuit Information.............................................................. 13 Timing Characteristics..................................................................... 5 Overview ..................................................................................... 13 Absolute Maximum Ratings............................................................ 7 Noise Performance..................................................................... 13 Pin Configuration and Function Descriptions............................. 8 Reduced Current Modes ........................................................... 13 Typical Performance Characteristics ............................................. 9 Digital Interface.......................................................................... 14 On-Chip Registers.......................................................................... 10 Single Conversion Mode ....................................................... 15 Communications Register Continuous Conversion Mode............................................. 15 (RS1, RS0 = 0, 0) ......................................................................... 10 Continuous Read Mode ........................................................ 16 Status Register Circuit Description......................................................................... 17 (RS1, RS0 = 0, 0; Power-on/Reset = 0x88)............................... 11 Analog Input Channel ............................................................... 17 Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 11 Programmable Gain Amplifier................................................. 17 Filter Register Bipolar Configuration................................................................ 17 (RS1, RS0 = 1, 0; Power-on/Reset = 0x04)............................... 12 Data Output Coding .................................................................. 17 Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) .......................... 12 Reference Input........................................................................... 17 VDD Monitor ................................................................................ 18 Grounding and Layout .............................................................. 18 Outline Dimensions ....................................................................... 19 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD7790 1 AD7790—SPECIFICATIONS Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V; all specifications T to T , unless otherwise noted.) MIN MAX Parameter AD7790B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATION Output Update Rate 9.5 Hz min nom 120 Hz max nom ADC CHANNEL 2 No Missing Codes 16 Bits min ±V Range, Update Rate ≤ 20 Hz REF Resolution 16 Bits p-p 9.5 Hz Update Rate Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typ 3 Full-Scale Error ±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min Input Range = ±REFIN, 100 dB typ ANALOG INPUTS Differential Input Voltage Ranges ±REFIN/GAIN V nom REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8 2 Absolute AIN Voltage Limits GND + 100 mV V min Buffered Mode of Operation V – 100 mV V max DD Analog Input Current Buffered Mode of Operation 2 Average Input Current ±1 nA max Average Input Current Drift ±5 pA/°C typ 2 Absolute AIN Voltage Limits GND – 30 mV V min Unbuffered Mode of Operation VDD + 30 mV V max Analog Input Current Unbuffered Mode of Operation Input current varies with input voltage. Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ 2 Normal Mode Rejection 4 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 4 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101 4 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011 Common Mode Rejection Input Range = ±REFIN, AIN = 1 V 4 @ DC 90 dB min 100 dB typ (FS[2:0] = 100 ) 2 4 4 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz (FS[2:0] = 101 ), 60 ± 1 Hz (FS[2:0] = 011 ) REFERENCE INPUT REFIN = REFIN(+) – REFIN(–) REFIN Voltage 2.5 V nom 2 Reference Voltage Range 0.1 V min V V max DD 2 Absolute REFIN Voltage Limits GND – 30 mV V min V + 30 mV V max DD Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ 1 Temperature Range –40°C to +105°C. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (V = 4 V). DD 4 FS[2:0] are the three bits used in the filter register to select the output word rate. Rev. 0 | Page 3 of 20 AD7790 1 SPECIFICATIONS (continued) Parameter AD7790B Unit Test Conditions/Comments REFERENCE INPUT (continued) 2 Normal Mode Rejection 4 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 4 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101 4 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011 Common Mode Rejection Input Range = ±2.5 V, AIN = 1 V 4 @ DC 100 dB typ FS[2:0] = 100 4 4 @ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 101 ), 60 ± 1 Hz (FS[2:0] = 011 ) LOGIC INPUTS 2 All Inputs Except SCLK VINL, Input Low Voltage 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V V , Input High Voltage 2.0 V min V = 3 V or 5 V INH DD 2 SCLK Only (Schmitt-Triggered Input) V (+) 1.4/2 V min/V max V = 5 V T DD VT(–) 0.8/1.4 V min/V max VDD = 5 V VT(+) – VT(–) 0.3/0.85 V min/V max VDD = 5 V VT(+) 0.9/2 V min/V max VDD = 3 V V (–) 0.4/1.1 V min/V max V = 3 V T DD V (+) - V (–) 0.3/0.85 V min/V max V = 3 V T T DD Input Currents ±1 µA max VIN = VDD or GND Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS 2 VOH, Output High Voltage VDD – 0.6 V min VDD = 3 V, ISOURCE = 100 µA 2 VOL, Output Low Voltage 0.4 V max VDD = 3 V, ISINK = 100 µA 2 VOH, Output High Voltage 4 V min VDD = 5 V, ISOURCE = 200 µA 2 V , Output Low Voltage 0.4 V max V = 5 V, I = 1.6 mA OL DD SINK Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary 5 POWER REQUIREMENTS Power Supply Voltage VDD – GND 2.5/5.25 V min/max Power Supply Currents 6 I Current 75 µA max 65 µA typ, V = 3.6 V, Unbuffered Mode DD DD 145 µA max 130 µA typ, V = 3.6 V, Buffered Mode DD 80 µA max 73 µA typ, V = 5.25 V, Unbuffered Mode DD 160 µA max 145 µA typ, VDD = 5.25 V, Buffered Mode IDD (Power-Down Mode) 1 µA max 5 Digital inputs equal to V or GND. DD 6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15). Rev. 0 | Page 4 of 20 AD7790 1, 2 TIMING CHARACTERISTICS Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = V , unless otherwise noted.) DD Limit at T , T MIN MAX Parameter (B Version) Unit Conditions/Comments t3 100 ns min SCLK High Pulsewidth t 100 ns min SCLK Low Pulsewidth 4 Read Operation t1 0 ns min CS Falling Edge to DOUT/RDY Active Time 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V 3 4 t 0 ns min SCLK Active Edge to Data Valid Delay 2 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD 5, 6 t5 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t 100 ns max SCLK Inactive Edge to CS Inactive Edge 6 t 10 ns min SCLK Inactive Edge to DOUT/RDY High 7 Write Operation 4 t8 0 ns min CS Falling Edge to SCLK Active Edge Setup Time t9 30 ns min Data Valid to SCLK Edge Setup Time t10 25 ns min Data Valid to SCLK Edge Hold Time t 0 ns min CS Rising Edge to SCLK Edge Hold Time 11 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. Rev. 0 | Page 5 of 20 AD7790 I (1.6mA WITH V = 5V, SINK DD 100µA WITH V = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH V = 5V, SOURCE DD 100µA WITH V = 3V) DD 03538-0-002 Figure 2. Load Circuit for Timing Characterization CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 03538-0-003 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 8 11 SCLK (I) t 9 t 10 DIN (I) MSB LSB 03538-0-004 I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. 0 | Page 6 of 20 AD7790 ABSOLUTE MAXIMUM RATINGS Table 3. (TA= 25°C, unless otherwise noted.) Parameter Rating Stresses above those listed under Absolute Maximum Ratings VDD to GND –0.3 V to +7 V may cause permanent damage to the device. This is a stress Analog Input Voltage to GND –0.3 V to VDD + 0.3 V rating only; functional operation of the device at these or any Reference Input Voltage to GND –0.3 V to VDD + 0.3 V other conditions above those listed in the operational sections Total AIN/REFIN Current (Indefinite) 30 mA of this specification is not implied. Exposure to absolute Digital Input Voltage to GND –0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Digital Output Voltage to GND –0.3 V to V + 0.3 V DD device reliability. Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C Maximum Junction Temperature 150°C MSOP θ Thermal Impedance 206°C/W JA θJC Thermal Impedance 44°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C Rev. 0 | Page 7 of 20 AD7790 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN Pin CS 2 9 DOUT/RDY AD7790 No. Mnemonic Function AIN(+) 3 8 V TOP VIEW DD 6 REFIN(–) Negative Reference Input. This reference (Not to Scale) AIN(–) 4 7 GND input can lie anywhere between GND and 5 6 REF(+) REF(–) VDD – 0.1 V. 03538-0-005 7 GND Ground Reference Point. Figure 5. Pin Configuration 8 VDD Supply Voltage, 2.5 V to 5.25 V. 9 DOUT/RDY Serial Data Output/Data Ready Output. Table 4. Pin Function Descriptions DOUT/RDY serves a dual purpose. It functions Pin as a serial data output pin to access the out- No. Mnemonic Function put shift register of the ADC. The output shift register can contain data from any of the on- 1 SCLK Serial Clock Input for Data Transfers to and chip data or control registers. In addition, from the ADC. The SCLK has a Schmitt- DOUT/RDY operates as a data ready pin, triggered input, making the interface going low to indicate the completion of a suitable for opto-isolated applications. The conversion. If the data is not read after the serial clock can be continuous with all data conversion, the pin will go high before the transmitted in a continuous train of pulses. next update occurs. Alternatively, it can be a noncontinuous clock with the information being trans- The DOUT/RDY falling edge can be used as an mitted to or from the ADC in smaller interrupt to a processor, indicating that valid batches of data. data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be With CS low, the data/control word informa- used to select the ADC in systems with tion is placed on the DOUT/RDY pin on the more than one device on the serial bus or as SCLK falling edge and is valid on the SCLK a frame synchronization signal in communi- rising edge. cating with the device. CS can be hardwired The end of a conversion is also indicated by low, allowing the ADC to operate in 3-wire the RDY bit in the status register. When CS is mode with SCLK, DIN, and DOUT used to high, the DOUT/RDY pin is three-stated but interface with the device. the RDY bit remains active. 3 AIN(+) Analog Input. AIN(+) is the positive terminal 10 DIN Serial Data Input to the Input Shift Register of the fully differential analog input. on the ADC. Data in this shift register is 4 AIN(–) Analog Input. AIN(–) is the negative termi- transferred to the control registers within nal of the fully differential analog input. the ADC, the register selection bits of the 5 REFIN(+) Positive Reference Input. REFIN(+) can lie communications register identifying the anywhere between VDD and GND + 0.1 V. appropriate register. The nominal reference voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 0.1 V to V . DD Rev. 0 | Page 8 of 20 AD7790 TYPICAL PERFORMANCE CHARACTERISTICS 0 3.0 V = 5V DD UPDATE RATE = 16.6Hz –10 T = 25°C A –20 2.5 –30 –40 2.0 –50 1.5 –60 –70 1.0 –80 –90 0.5 –100 –110 0 –120 04 200 6080 100 120 140 160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (Hz) V (V) REF 03538-0-007 03538-0-013 Figure 6. Frequency Response for a 16.6 Hz Update Rate Figure 7. RMS Noise vs. Reference Voltage Rev. 0 | Page 9 of 20 dB RMS NOISE (µV) AD7790 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com- munications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis- ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi- cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) 0(0) RS1(0) RS0(0) R/W(0) CREAD(0) CH1(0) CH0(0) Table 5. Communications Register Bit Designations Bit Location Bit Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. CR6 0 This bit must be programmed to Logic 0 for correct operation. CR5–CR4 RS1–RS0 Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected during this serial interface communication. See Table 6. CR3 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu- nications register does not have to be written to for data reads. To enable continuous read mode, the instruction 001111XX must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. CR1–CR0 CH1–CH0 These bits are used to select the analog input channel. The differential channel can be selected (AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to digital conversion. Any change in channel resets the filter and a new conversion is started. Table 6. Register Selection Table 7. Channel Selection RS1 RS0 Register Register Size CH1 CH0 Channel 0 0 Communications Register 8-Bit 0 0 AIN(+) – AIN(–) during a Write Operation 0 1 Reserved 0 0 Status Register during a 8-Bit 1 0 AIN(–) – AIN(–) Read Operation 1 1 VDD Monitor 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register 16-Bit Rev. 0 | Page 10 of 20 AD7790 STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) 0(0) 0(0) 1(1) WL(0) CH1(0) CH0(0) Table 8. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in powe-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write operation to start a conversion. SR5 0 This bit is automatically cleared. SR4 0 This bit is automatically cleared. SR3 1 This bit is automatically set. SR2 0 This bit is automatically cleared if the device is an AD7790. It can be used to distinguish between the AD7790 and AD7791, in which the bit is set. SR1–SR0 CH1–CH0 These bits indicate which channel is being converted by the ADC. MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02) The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for range, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit. MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD1(0) MD0(0) G1(0) G0(0) BO(0) 0(0) BUF(1) 0(0) Table 9. Mode Register Bit Designations Bit Location Bit Name Description MR7–MR6 MD1–MD0 Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/ f while subsequent conversions are available at a frequency of f . In single ADC ADC conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. See Table 10. MR5–MR4 G1–G0 Range Bits. The AD7790 can be operated with four analog input ranges (see Table 11). MR3 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active. Rev. 0 | Page 11 of 20 AD7790 Bit Location Bit Name Description MR2 0 This bit must be programmed with a Logic 0 for correct operation. MR1 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR0 0 This bit must be programmed with a Logic 0 for correct operation. Table 10. Operating Modes Table 11. Analog Input Ranges MD1 MD0 Mode AD7790 LSB Size with VREF = +2.5 V G1 G0 Range (µV) 0 0 Continuous Conversion Mode (Default) 0 0 ±VREF 76.3 0 1 Reserved 0 1 ±V /2 38.14 REF 1 0 Single Conversion Mode 1 0 ±V /4 19.07 REF 1 1 Power-Down Mode 1 1 ±V /8 9.54 REF FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04) The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word rate. Table 12 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 0(0) 0(0) CDIV1(0) CDIV0(0) 0(0) FS2(1) FS1(0) FS0(0) Table 12. Filter Register Bit Designations Bit Location Bit Name Description FR7–FR6 0 These bits must be programmed with a Logic 0 for correct operation. FR5–FR4 CLKDIV1– These bits are used to operate the AD7790 in the lower power modes. The clock is internally divided and CDIV0 the power is reduced. 00 Normal Mode 01 Clock Divided by 2 10 Clock Divided by 4 11 Clock Divided by 8 FR3 0 This bit must be programmed with a Logic 0 for correct operation. FR2–FR0 FS2–FS0 These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and noise. The noise is the same for all gain settings. See Table 13 for the allowable update rates in full power mode. In the low power modes, the update rates will be reduced. (See Reduced Current Modes.) Table 13. Update Rates FS2 FS1 FS0 f (Hz) f3dB (Hz) RMS Noise (µV) Rejection ADC 0 0 0 120 28 40 25 dB @ 60 Hz 0 0 1 100 24 25 25 dB @ 50 Hz 0 1 0 33.3 8 3.36 0 1 1 20 4.7 1.6 80 dB @ 60 Hz 1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting) 1 0 1 16.7 4 1.5 80 dB @ 50 Hz 1 1 0 13.3 3.2 1.2 1 1 1 9.5 2.3 1.1 62 dB @ 50/60 Hz DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the bit/pin is set. RDY Rev. 0 | Page 12 of 20 AD7790 ADC CIRCUIT INFORMATION numbers given are with a reference of 2.5 V. The numbers are OVERVIEW typical and generated with a differential input voltage of 0 V. The AD7790 is a low power ADC that incorporates a ∑-∆ The peak-to-peak resolution figures represent the resolution for modulator, a buffer, a PGA, and on-chip digital filtering intend- which there will be no code flicker within a six-sigma limit. The ed for the measurement of wide dynamic range, low frequency output noise comes from two sources. The first is the electrical signals such as those in pressure transducers, weigh scales, and noise in the semiconductor devices (device noise) used in the temperature measurement applications. implementation of the modulator. The second is quantization noise, which is added when the analog input is converted into The part has one differential input that can be buffered or the digital domain. The device noise is at a low level and is unbuffered. Buffering the input channel means that the part can independent of frequency. The quantization noise starts at an accommodate significant source impedances on the analog even lower level but rises rapidly with increasing frequency to input and that R, C filtering (for noise rejection or RFI reduc- become the dominant noise source. tion) can be placed on the analog input, if required. The device requires an external reference of 2.5 nominal. Figure 7 shows Table 14. Typical Peak-to-Peak Resolution (Effective the basic connections required to operate the part. Resolution) vs. Update Rate and Input Range Input Range POWER SUPPLY Update Rate ±0.3125 ±0.625 ±1.25 ±2.5 0.1µF 10µF 9.5 16 (16) 16 (16) 16 (16) 16 (16) 13.3 16 (16) 16 (16) 16 (16) 16 (16) 16.7 16 (16) 16 (16) 16 (16) 16 (16) V DD REFIN(+) 16.6 16 (16) 16 (16) 16 (16) 16 (16) IN+ 20 15.5 (16) 16 (16) 16 (16) 16 (16) AD7790 33.3 14.5 (16) 15.5 (16) 16 (16) 16 (16) OUT– OUT+ CS AIN(+) 100 11.5 (14) 12.5 (15) 13.5 (16) 14.5 (16) DOUT/RDY MICROCONTROLLER AIN(–) 120 11 (13.5) 12 (14.5) 13 (15.5) 14 (16) IN– SCLK REFIN(–) GND REDUCED CURRENT MODES 03538-0-006 The AD7790 has a current consumption of 160 µA maximum Figure 7. Basic Connection Diagram when operated with the buffer enabled and with a 5 V power supply. The power can be reduced further by setting bits CDIV1 and CDIV0 in the filter register appropriately (see Table 15). The output rate of the AD7790 (f ) is user programmable ADC with the settling time equal to 2 × tADC. Normal mode rejection By setting these bits, the internal clock is divided by 2, 4, or 8 is the major function of the digital filter. Table 13 lists the avail- before being applied to the modulator and filter, resulting in a able output rates from the AD7790. Simultaneous 50 Hz and reduction in the digital current. 60 Hz rejection is optimized when the update rate equals 16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this When the internal clock is reduced, the update rate will also be update rate (see Figure 6). reduced. For example, if the filter bits are set to give an update rate of 16.6 Hz when the AD7790 is operated in full clock mode, NOISE PERFORMANCE the update rate will equal 8.3 Hz in divide by 2 mode. In these Table 14 shows the output rms noise, rms resolution, and peak- low power modes, there may be some degradation in the ADC to-peak resolution (rounded to the nearest 0.5 LSB) for the performance. different update rates and input ranges for the AD7790. The Table 15. Low Power Mode Selection CDIV[1:0] Clock Typ Current, Buffered (µA) Typ Current, Unbuffered (µA) 50 Hz/60 Hz Rejection (dB) 00 1 146 75 70 10 1/2 87 45 72 10 1/4 56 30 88 11 1/8 41 25 89 Rev. 0 | Page 13 of 20 AD7790 DIGITAL INTERFACE shift register while Figure 4 shows the timing for a write opera- tion to the input shift register. In all modes except continuous As previously outlined, the AD7790’s programmable functions read mode, it is possible to read the same word from the data are controlled using a set of on-chip registers. Data is written to register several times even though the DOUT/ line returns these registers via the part’s serial interface and read access to RDY the on-chip registers is also provided by this interface. All com- high after the first read operation. However, care must be taken munications with the part must start with a write to the to ensure that the read operations have been completed before communications register. After power-on or reset, the device the next output update occurs. In continuous read mode, the expects a write to its communications register. The data written data register can be read only once. to this register determines whether the next operation is a read low. The serial interface can operate in 3-wire mode by tying CS operation or a write operation and also determines to which In this case, the SCLK, DIN, and DOUT/RDY lines are used to register this read or write operation occurs. Therefore, write communicate with the AD7790. The end of the conversion can access to any of the other registers on the part begins with a write operation to the communications register followed by a be monitored using the RDY bit in the status register. This write to the selected register. A read operation from any other scheme is suitable for interfacing to microcontrollers. If CS is register (except when continuous read mode is selected) starts required as a decoding signal, it can be generated from a port with a write to the communications register followed by a read pin. For microcontroller interfaces, it is recommended that operation from the selected register. SCLK idles high between data transfers. The AD7790’s serial interface consists of four signals: CS, DIN, The AD7790 can be operated with CS being used as a frame SCLK, and DOUT/ . The DIN line is used to transfer data RDY synchronization signal. This scheme is useful for DSP interfaces. into the on-chip registers while DOUT/RDY is used for access- In this case, the first bit (MSB) is effectively clocked out by CS ing from the on-chip registers. SCLK is the serial clock input for since CS would normally occur after the falling edge of SCLK in the device and all data transfers (either on DIN or DOUT/ ) RDY DSPs. The SCLK can continue to run between data transfers, occur with respect to the SCLK signal. The DOUT/ RDY pin provided the timing numbers are obeyed. operates as a Data Ready signal also, the line going low when a The serial interface can be reset by writing a series of 1s on the new data-word is available in the output register. It is reset high DIN input. If a Logic 1 is written to the AD7790 line for at least when a read operation from the data register is complete. It also 32 serial clock cycles, the serial interface is reset. This ensures goes high prior to the updating of the data register to indicate that in 3-wire systems, the interface can be reset to a known when not to read from the device to ensure that a data read is state if the interface gets lost due to a software error or some not attempted while the register is being updated. CS is used to glitch in the system. Reset returns the interface to the state in select a device. It can be used to decode the AD7790 in systems which it is expecting a write to the communications register. where several components are connected to the serial bus. This operation resets the contents of all registers to their power- on values. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7790 with CS being used to decode the part. Figure 3 The AD7790 can be configured to continuously convert or to shows the timing for a read operation from the AD7790’s output perform a single conversion. See Figure 8 through Figure 10. Rev. 0 | Page 14 of 20 AD7790 Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7790 is placed in shutdown This is the default power-up mode. The AD7790 will continu- mode between conversions. When a single conversion is initi- ously convert, the RDY pin in the status register going low each ated by setting MD1 to 1 and MD0 to 0 in the mode register, the time a conversion is complete. If is low, the DOUT/RDY line CS AD7790 powers up, performs a single conversion, and then will also go low when a conversion is complete. To read a con- returns to shutdown mode. A conversion will require a time version, the user can write to the communications register, period of 2 × t . DOUT/ goes low to indicate the com- ADC RDY indicating that the next operation is a read of the data register. pletion of a conversion. When the data-word has been read The digital conversion will be placed on the DOUT/RDY pin as from the data register, DOUT/RDY will go high. If CS is low, soon as SCLK pulses are applied to the ADC. DOUT/ will RDY DOUT/ will remain high until another conversion is initi- RDY return high when the conversion is read. The user can read this ated and completed. The data register can be read several times, register additional times, if required. However, the user must if required, even when DOUT/ RDY has gone high. ensure that the data register is not being accessed at the comple- tion of the next conversion or else the new conversion word will be lost. CS 0x10 0x82 0x10 0x82 DIN DATA DATA DOUT/RDY SCLK 03538-0-010 Figure 8. Single Conversion CS 0x38 0x38 DIN DATA DATA DOUT/RDY SCLK 03538-0-012 Figure 9. Continuous Conversion Rev. 0 | Page 15 of 20 AD7790 Continuous Read Mode before the next conversion is complete. If the user has not read Rather than write to the communications register each time a the conversion before the completion of the next conversion or conversion is complete to access the data, the AD7790 can be if insufficient serial clocks are applied to the AD7790 to read the placed in continuous read mode. By writing 001111XX to the word, the serial output register is reset when the next conver- communications register, the user only needs to apply the sion is complete and the new conversion is placed in the output appropriate number of SCLK cycles to the ADC and the 16-bit serial register. word will automatically be placed on the DOUT/ line RDY To exit the continuous read mode, the instruction 001110XX when a conversion is complete. must be written to the communications register while the RDY When DOUT/RDY goes low to indicate the end of a conver- pin is low. While in the continuous read mode, the ADC sion, sufficient SCLK cycles must be applied to the ADC and the monitors activity on the DIN line so that it can receive the data conversion will be placed on the DOUT/ line. When instruction to exit the continuous read mode. Additionally, a RDY reset will occur if 32 consecutive 1s are seen on DIN. Therefore, the conversion is read, DOUT/RDY will return high until the DIN should be held low in continuous read mode until an next conversion is available. In this mode, the data can be read instruction is to be written to the device. only once. Also, the user must ensure that the data-word is read CS 0x3C DIN DATA DATA DATA DOUT/RDY SCLK 03538-0-011 Figure 10. Continuous Read Rev. 0 | Page 16 of 20 AD7790 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION The AD7790 has one differential analog input channel. This is The analog input to the AD7790 accepts a bipolar input voltage connected to the on-chip buffer amplifier when the device is range. A bipolar input range does not imply that the part can operated in buffered mode and directly to the modulator when tolerate negative voltages with respect to system GND. Bipolar the device is operated in unbuffered mode. In buffered mode signals on the AIN(+) input are referenced to the voltage on the (the BUF bit in the mode register is set to 1), the input channel AIN(–) input. For example, if AIN(–) is 2.5 V and the ADC is feeds into a high impedance input stage of the buffer amplifier. configured for a gain of 1, the analog input range on the AIN(+) Therefore, the input can tolerate significant source impedances input is 0 V to 5 V. and is tailored for direct connection to external resistive-type DATA OUTPUT CODING sensors such as strain gauges or resistance temperature detec- tors (RTDs). The output code is offset binary with a negative full-scale volt- age resulting in a code of 000...000, a zero differential input When BUF = 0, the part is operated in unbuffered mode. voltage resulting in a code of 100...000, and a positive full-scale This results in a higher analog input current. Note that this input voltage resulting in a code of 111...111. The output code unbuffered input path provides a dynamic load to the driving for any analog input voltage can be represented as source. Therefore, resistor/capacitor combinations on the N – 1 Code = 2 × [(AIN × GAIN/V ) + 1] input pins can cause dc gain errors, depending on the output REF impedance of the source that is driving the ADC input. Table 16 where AIN is the analog input voltage, GAIN is the PGA gain, shows the allowable external resistance/capacitance values for and N = 16. unbuffered mode such that no gain error at the 16-bit level is introduced. REFERENCE INPUT The AD7790 has a fully differential input capability for the Table 16. External R-C Combination for No 16-Bit Gain Error channel. The common-mode range for these differential inputs C (pF) R (Ω) is from GND to VDD. The reference input is unbuffered and, 50 22.8K therefore, excessive R-C source impedances will introduce gain 100 13.1K errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) is 500 3.3K 2.5 V nominal for specified operation, but the AD7790 is func- 1000 1.8K tional with reference voltages from 0.1 V to V . In applications DD 5000 360 where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, The absolute input voltage range in buffered mode is restricted the effect of the low frequency noise in the excitation source to a range between GND + 100 mV and VDD – 100 mV. Care will be removed because the application is ratiometric. If the must be taken in setting up the common-mode voltage so that AD7790 is used in a nonratiometric application, a low noise these limits are not exceeded. Otherwise, there will be degrada- reference should be used. tion in linearity and noise performance. Recommended 2.5 V reference voltage sources for the AD7790 The absolute input voltage in unbuffered mode includes the include the ADR381 and ADR391 because these are low noise, range between GND – 30 mV and V + 30 mV as a result of DD low power references. If the complete analog section is driven being unbuffered. The negative absolute input voltage limit does from a 2.5 V power supply, the reference voltage source will allow the possibility of monitoring small true bipolar signals require some headroom. In this case, a 2.048 V reference such as with respect to GND. the ADR390 or ADR380 is recommended, again low noise, low power references. Also note that the reference inputs provide a PROGRAMMABLE GAIN AMPLIFIER high impedance, dynamic load. Because the input impedance of The output from the buffer on the ADC is applied to the input each reference input is dynamic, resistor/capacitor combina- of the on-chip programmable gain amplifier (PGA). The PGA tions on these inputs can cause dc gain errors, depending on the gain range is programmed via the gain bits G1 and G0 in the output impedance of the source that is driving the reference mode register. With an external 2.5 V reference applied, the inputs. Reference voltage sources like those recommended PGA can be programmed to have a bipolar range of ±2.5 V, above (e.g., ADR391) will typically have low output impedances ±1.25 V, ±625 mV, or ±312.5 mV. These are the ranges that and are, therefore, tolerant to having decoupling capacitors on should appear at the input to the on-chip PGA. Rev. 0 | Page 17 of 20 AD7790 and confined to certain areas of the board. A minimum etch REFIN(+) without introducing gain errors in the system. Deriv- technique is generally best for ground planes because it gives ing the reference input voltage across an external resistor will the best shielding. mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not It is recommended that the AD7790’s GND pin be tied to the be recommended in this type of circuit configuration. AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, ensur- V MONITOR DD ing that the return paths for all currents are as close as possible Along with converting external voltages, the analog input chan- to the paths the currents took to reach their destinations. Avoid nel can be used to monitor the voltage on the VDD pin. When the forcing digital currents to flow through the AGND sections of CH1 and CH0 bits in the communications register are set to 1, the layout. the voltage on the VDD pin is internally attenuated by 5 and the resultant voltage is applied to the ∑-∆ modulator using an inter- The AD7790’s ground plane should be allowed to run under the nal 1.17 V reference for analog to digital conversion. This is AD7790 to prevent noise coupling. The power supply lines to useful because variations in the power supply voltage can be the AD7790 should use as wide a trace as possible to provide monitored. low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should GROUNDING AND LAYOUT be shielded with digital ground to avoid radiating noise to other Since the analog inputs and reference inputs of the ADC are sections of the board, and clock signals should never be run differential, most of the voltages in the analog modulator are near the analog inputs. Avoid crossover of digital and analog common-mode voltages. The excellent common-mode rejec- signals. Traces on opposite sides of the board should run at tion of the part will remove common-mode noise on these right angles to each other. This will reduce the effects of inputs. The digital filter will provide rejection of broadband feedthrough through the board. A microstrip technique is by far noise on the power supply, except at integer multiples of the the best, but it is not always possible with a double-sided board. modulator sampling frequency. The digital filter also removes In this technique, the component side of the board is dedicated noise from the analog and reference inputs, provided that these to ground planes, while signals are placed on the solder side. noise sources do not saturate the analog modulator. As a result, Good decoupling is important when using high resolution the AD7790 is more immune to noise interference than a con- ADCs. V should be decoupled with 10 µF tantalum in parallel DD ventional high resolution converter. However, because the with 0.1 µF capacitors to GND. To achieve the best from these resolution of the AD7790 is so high, and the noise levels from decoupling components, they should be placed as close as the AD7790 are so low, care must be taken with regard to possible to the device, ideally right up against the device. All grounding and layout. logic chips should be decoupled with 0.1 µF ceramic capacitors The printed circuit board that houses the AD7790 should be to DGND. designed such that the analog and digital sections are separated Rev. 0 | Page 18 of 20 AD7790 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.27 0.60 SEATING 0.23 0° 0.00 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 11. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 17. Ordering Guide Model Temperature Range Package Description Package Option Branding AD7790BRM –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COS AD7790BRM-REEL –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COS Rev. 0 | Page 19 of 20 AD7790 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C03538-0-8/03(0) Rev. 0 | Page 20 of 20